ISL22446 ® Quad Digitally Controlled Potentiometer (XDCP™) Data Sheet September 9, 2009 FN6181.2 Low Noise, Low Power, SPI™ Bus, 128 Taps Features The ISL22446 integrates four digitally controlled potentiometers (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. • Four potentiometers in one package • 128 resistor taps The digitally controlled potentiometers are implemented with a combination of resistor elements and CMOS switches. The position of the wipers are controlled by the user through the SPI serial interface. Each potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up the device recalls the contents of the DCP’s IVR to the corresponding WR. The DCPs can be used as three-terminal potentiometers or as two-terminal variable resistors in a wide variety of applications including control, parameter adjustments, and signal processing. • SPI serial interface • Non-volatile storage of wiper position • Wiper resistance: 70Ω typical @ VCC = 3.3V • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V • 50kΩ or 10kΩ total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T < +55°C • 20 Ld TSSOP and 20 Ld TQFN package • Pb-free (RoHS compliant) Pinouts 19 RL0 3 18 RH0 NC 4 17 SHDN SCK SDO 16 5 6 15 O VCC SDI GND 7 14 CS RW2 8 13 RH1 RL2 9 12 RL1 RH2 10 11 RW1 CS SDI SHDN 20 19 18 17 16 RL0 1 15 RH1 RW0 2 14 RL1 RH3 3 13 RW1 RL3 4 12 RH2 RW3 5 11 RL2 6 7 8 9 10 RW2 2 GND RL3 RW3 SCK RW0 SDO 20 RH0 1 NC RH3 VCC ISL22446 (20 LD TQFN) TOP VIEW ISL22446 (20 LD TSSOP) TOP VIEW Ordering Information PART NUMBER (Note) PART MARKING RESISTANCE OPTION (kΩ) TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL22446UFV20Z* 22446 UFVZ 50 -40 to +125 20 Ld TSSOP M20.173 ISL22446UFRT20Z* 224 46UFZ 50 -40 to +125 20 Ld 4x4 TQFN L20.4x4A ISL22446WFV20Z* 22446 WFVZ 10 -40 to +125 20 Ld TSSOP M20.173 ISL22446WFRT20Z* 224 46WFZ 10 -40 to +125 20 Ld 4x4 TQFN L20.4x4A *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22446 Block Diagram VCC RH3 WR3 SCK SDI POWER UP INTERFACE, CONTROL AND STATUS LOGIC SPI INTERFACE SDO CS RW3 RL3 RH2 WR2 RW2 RL2 RH1 WR1 NONVOLATILE REGISTERS SHDN RW1 RL1 RH0 WR0 RW0 RL0 GND Pin Descriptions TSSOP PIN NUMBER TQFN PIN NUMBER SYMBOL 1 3 RH3 “High” terminal of DCP3 2 4 RL3 “Low” terminal of DCP3 3 5 RW3 “Wiper” terminal of DCP3 4 6 NC 5 7 SCK SPI clock input 6 8 SDO SPI Open drain Data Output 7 9 GND Device ground pin 8 10 RW2 “Wiper” terminal of DCP2 9 11 RL2 “Low” terminal of DCP2 10 12 RH2 “High” terminal of DCP2 11 13 RW1 “Wiper” terminal of DCP1 12 14 RL1 “Low” terminal of DCP1 13 15 RH1 “High” terminal of DCP1 14 16 CS SPI Chip Select active low input 15 17 SDI SPI Data Input 16 18 VCC Power supply pin 17 19 SHDN 18 20 RH0 “High” terminal of DCP0 19 1 RL0 “Low” terminal of DCP0 20 2 RW0 “Wiper” terminal of DCP0 EPAD* DESCRIPTION No connect Shutdown active low input Exposed Die Pad internally connected to GND *NOTE: PCB thermal land for QFN EPAD should be connected to GND plane or left floating. For more information refer to http://www.intersil.com/data/tb/TB389.pdf 2 FN6181.2 September 9, 2009 ISL22446 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . -0.3V to VCC + 0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP Pin with Respect to GND. . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD Ratings Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV Machine Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .350V Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 20 Lead TSSOP (Note 1) . . . . . . . . . . . 95 N/A 20 Lead TQFN (Notes 2, 3) . . . . . . . . . 40 3.0 Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15mW Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -0.8V for all pins. Analog Specifications SYMBOL RTOTAL VRH, VRL RW CH/CL/CW (Note 21) ILkgDCP Over recommended operating conditions, unless otherwise stated. PARAMETER RH to RL Resistance TEST CONDITIONS MIN (Note 22) TYP (Note 5) MAX (Note 22) UNIT W option 10 kΩ U option 50 kΩ RH to RL ResistanceTolerance W and U option End-to-End Temperature Coefficient W option ±50 ppm/°C (Note 21) U option ±80 ppm/°C (Note 21) VRH and VRL Terminal Voltages VRH and VRL to GND Wiper Resistance VCC = 3.3V, wiper current = VCC/RTOTAL -20 0 70 Voltage at pin from GND to VCC 0.1 % VCC V 200 Ω 10/10/25 Potentiometer Capacitance Leakage on DCP Pins +20 pF 1 µA VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0, 1, 2 or 3) INL (Note 10) Integral Non-linearity Monotonic over all tap positions, W and U options -1 1 LSB (Note 6) DNL (Note 9) Differential Non-linearity Monotonic over all tap positions, W and U options -0.5 0.5 LSB (Note 6) ZSerror (Note 7) Zero-scale Error W option 0 1 5 LSB (Note 6) U option 0 0.5 2 LSB (Note 6) 3 FN6181.2 September 9, 2009 ISL22446 Analog Specifications SYMBOL FSerror (Note 8) Over recommended operating conditions, unless otherwise stated. (Continued) MIN (Note 22) TYP (Note 5) MAX (Note 22) W option -5 -1 0 LSB (Note 6) U option -2 -1 0 LSB (Note 6) -2 2 LSB (Note 6) PARAMETER Full-scale Error TEST CONDITIONS VMATCH (Note 11) DCP to DCP Matching Any two DCPs at same tap position, same voltage at all RH terminals, and same voltage at all RL terminals TCV (Note 12) Ratiometric Temperature Coefficient DCP register set to 40 hex ±4 UNIT ppm/°C RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected; i = 0, 1, 2 or 3) RINL (Note 16) Integral Non-linearity DCP register set between 10h and 7Fh; monotonic over all tap positions -1 1 MI (Note 13) RDNL (Note 15) Differential Non-linearity DCP register set between 10h and 7Fh; monotonic over all tap positions, W option -1 1 MI (Note 13) DCP register set between 10h and 7Fh; monotonic over all tap positions, U option -0.5 0.5 MI (Note 13) Roffset (Note 14) RMATCH (Note 17) Offset DCP to DCP Matching W option 0 1 7 MI (Note 13) U option 0 0.5 2 MI (Note 13) Any two DCPs at the same tap position with the same terminal voltages -2 2 MI (Note 13) Operating Specifications Over the recommended operating conditions, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 22) TYP (Note 5) MAX (Note 22) UNIT ICC1 VCC Supply Current (Volatile Write/Read) fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) 0.5 mA ICC2 VCC Supply Current (Non-volatile Write/Read) fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) 3 mA VCC Current (Standby) VCC = +5.5V @ +85°C, SPI interface in standby state 5 µA VCC = +5.5V @ +125°C, SPI interface in standby state 7 µA VCC = +3.6V @ +85°C, SPI interface in standby state 3 µA VCC = +3.6V @ +125°C, SPI interface in standby state 5 µA VCC = +5.5V @ +85°C, SPI interface in standby state 3 µA VCC = +5.5V @ +125°C, SPI interface in standby state 5 µA VCC = +3.6V @ +85°C, SPI interface in standby state 2 µA VCC = +3.6V @ +125°C, SPI interface in standby state 4 µA ISB ISD VCC Current (Shutdown) 4 FN6181.2 September 9, 2009 ISL22446 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL ILkgDig PARAMETER Leakage Current at Pins SHDN, SCK, Voltage at pin from GND to VCC SDI, SDO and CS tWRT (Note 21) Wiper Response Time after SPI Write to WR Register tShdnRec (Note 21) DCP Recall Time from Shutdown Mode Vpor TEST CONDITIONS Power-on Recall Voltage VccRamp VCC Ramp Rate tD Power-up Delay MIN (Note 22) TYP (Note 5) -1 MAX (Note 22) UNIT 1 µA 1.5 µs From rising edge of SHDN signal to wiper stored position and RH connection 1.5 µs SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs Minimum VCC at which memory recall occurs 2.0 2.6 0.2 V V/ms 3 VCC above Vpor, to DCP Initial Value Register recall completed, and SPI Interface in standby state ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 19) Temperature T < +55°C 1,000,000 Cycles 50 Years Non-volatile Write Cycle Time 12 20 ms SERIAL INTERFACE SPECIFICATIONS VIL SHDN, SCK, SDI, and CS Input Buffer LOW Voltage -0.3 0.3*VCC V VIH SHDN, SCK, SDI, and CS Input Buffer HIGH Voltage 0.7*VCC VCC + 0.3 V Hysteresis SHDN, SCK, SDI, and CS Input Buffer Hysteresis 0.05*VCC SDO Output Buffer LOW Voltage IOL = 4mA Rpu (Note 20) SDO pull-up resistor off-chip Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz Cpin (Note 21) SHDN, SCK, SDI, SDO and CS Pin Capacitance VOL V 0 0.4 V 2 kΩ 10 pF fSCK SPI Frequency tCYC SPI Clock Cycle Time 200 ns tWH SPI Clock High Time 100 ns tWL SPI Clock Low Time 100 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SDI, SCK and CS Input Setup Time 50 ns tH SDI, SCK and CS Input Hold Time 50 ns tRI SDI, SCK and CS Input Rise Time 10 ns tFI SDI, SCK and CS Input Fall Time 10 20 ns SDO Output Disable Time 0 100 ns 350 ns tDIS tV 5 SDO Output Valid Time 5 MHz FN6181.2 September 9, 2009 ISL22446 Operating Specifications Over the recommended operating conditions, unless otherwise specified. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 22) TYP (Note 5) MAX (Note 22) UNIT tHO SDO Output Hold Time 0 ns tRO SDO Output Rise Time Rpu = 2k, Cb = 30pF 60 ns tFO SDO Output Fall Time Rpu = 2k, Cb = 30pF 60 ns tCS CS Deselect Time 2 µs NOTES: 5. Typical values are for TA = +25°C and 3.3V supply voltage. 6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 7. ZS error = V(RW)0/LSB. 8. FS error = [V(RW)127 – VCC]/LSB. 9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 10. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 127 11. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 12. TC = --------------------------------------------------------------------------------------------- × -------------------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper V [ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 13. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 14. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 15. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 127. 16. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 127. 17. RMATCH = (RWi,x – RWi,y)/MI, for i = 1 to 127, x = 0 to 3 and y = 0 to 3. 6 for i = 16 to 112, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is [ Max ( Ri ) – Min ( Ri ) ] 10 TC R = ---------------------------------------------------------------- × --------------------- the minimum value of the resistance over the temperature range. [ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 +165°C 19. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 18. 20. Rpu is specified for the highest data rate transfer for the device. Higher value pullup can be used at lower data rates. 21. Limits should be considered typical and are not production tested. 22. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 6 FN6181.2 September 9, 2009 ISL22446 Timing Diagrams Input Timing tCS CS tCYC tLEAD SCK tLAG ... tSU tH tWL tRI tFI tWH ... SDI MSB SDO HIGH IMPEDANCE LSB Output Timing CS SCK ... tV tDIS ... MSB SDO SDI tHO LSB ADDR XDCP Timing (for All Load Instructions) CS SCK ... tWRT SDI MSB ... LSB VW SDO HIGH IMPEDANCE 7 FN6181.2 September 9, 2009 ISL22446 Typical Performance Curves 100 WIPER RESISITANCE (Ω) 1.4 VCC = 3.3V, T = +125°C 90 1.2 80 1.0 60 0.8 ISB (µA) 70 50 40 30 T = +125°C 0.6 0.4 T = +25°C VCC = 3.3V, T = -40°C VCC = 3.3V, T = +20°C 20 0.2 10 0 2.7 0 0 20 40 60 80 100 120 3.2 3.7 TAP POSITION (DECIMAL) 4.2 4.7 5.2 VCC (V) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W) FIGURE 2. STANDBY ICC vs VCC 0.2 0.2 T = +25°C T = +25°C VCC = 2.7V 0.1 INL (LSB) DNL (LSB) 0.1 0 -0.1 VCC = 2.7V 0 -0.1 VCC = 5.5V VCC = 5.5V -0.2 0 20 40 60 80 100 -0.2 120 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 0.0 1.3 10k 1.1 -0.3 ZSERROR (LSB) ZSERROR (LSB) 0.9 0.7 0.5 VCC = 2.7V VCC = 5.5V 0.3 0.1 -0.3 -40 -20 0 20 VCC = 5.5V 50k -0.6 -0.9 10k -1.2 50k -0.1 VCC = 2.7V 40 60 80 TEMPERATURE (°C) FIGURE 5. ZSERROR vs TEMPERATURE 8 100 120 -1.5 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (ºC) FIGURE 6. FSERROR vs TEMPERATURE FN6181.2 September 9, 2009 ISL22446 Typical Performance Curves (Continued) 0.4 0.4 T = +25°C T = +25°C VCC = 5.5V DNL (LSB) 0.2 VCC = 5.5V 0.2 INL (LSB) 0 -0.2 -0.4 0 -0.2 -0.4 VCC = 2.7V -0.6 16 36 VCC = 2.7V 56 76 96 -0.6 16 116 36 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 116 FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 1.0 105 90 0.5 75 VCC = 2.7V TCv (ppm/°C) END TO END RTOTAL CHANGE (%) 56 76 96 TAP POSITION (DECIMAL) 50k 0.0 VCC = 5.5V 10k -0.5 60 45 50k 30 10k 15 -1.0 -40 0 -20 0 20 40 60 80 100 120 16 36 TEMPERATURE (ºC) 56 76 96 TAP POSITION (DECIMAL) FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm INPUT OUTPUT 300 TCr (ppm/°C) 250 200 150 50k 10k 100 WIPER AT MID POINT (POSITION 40h) RTOTAL = 9.5kΩ 50 0 16 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm 9 FIGURE 12. FREQUENCY RESPONSE (2.6MHz) FN6181.2 September 9, 2009 ISL22446 Typical Performance Curves (Continued) SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h FIGURE 14. LARGE SIGNAL SETTLING TIME Pin Description Bus Interface Pins Potentiometers Pins SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. RHI AND RLI (i = 0, 1, 2, 3) The high (RHi) and low (RLi) terminals of the ISL22446 are equivalent to the fixed terminals of a mechanical potentiometer. RHi and RLi are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WRi set to 127 decimal, the wiper will be closest to RHi, and with the WRi set to 0, the wiper is closest to RLi. SERIAL DATA OUTPUT (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low. SDO requires an external pull-up resistor for proper operation. SERIAL DATA INPUT (SDI) RWI (i = 0, 1, 2, 3) RWi is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WRi register. SHDN The SHDN pin forces the resistor to end-to-end open circuit condition on RHi and shorts RWi to RLi. When SHDN is returned to logic high, the previous latch settings put RWi at the same resistance setting prior to shutdown. This pin is logically ANDed with SHDN bit in ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. CHIP SELECT (CS) CS LOW enables the ISL22446, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power-up. When CS is HIGH, the ISL22446 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. RHi Principles of Operation RWi RLi FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE 10 The ISL22446 is an integrated circuit incorporating four DCPs with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometers and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. FN6181.2 September 9, 2009 ISL22446 The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVRi will be maintained in the non-volatile memory. When power is restored, the contents of the IVRi is recalled and loaded into the corresponding WRi to set the wiper to the initial value. DCP Description Each DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of each DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by volatile Wiper Register (WR). Each DCP has its own WR. When the WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR[6:0]= 7Fh), its wiper terminal (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22446 is being powered up, all four WRs are reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, all WRs will be reload with the value stored in corresponding non-volatile Initial Value Registers (IVRs). The WRs can be read or written to directly using the SPI serial interface as described in the following sections. The SPI interface register address bits have to be set to 0000b, 0001b, 0010b or 0011b to access the WR of DCP0, DCP1, DCP2 or DCP3 respectively. The WRi and IVRi can be read or written to directly using the SPI serial interface as described in the following sections. Memory Description The ISL22446 contains seven non-volatile and five volatile 8-bit registers. The memory map of ISL22446 is shown in Table 1. The four non-volatile registers (IVRi) at address 0, 1, 2 and 3, contain initial wiper value and volatile registers (WRi) contain current wiper position. In addition, three non-volatile General Purpose registers from address 4 to address 6 are available. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 8 — ACR 7 Reserved 11 TABLE 1. MEMORY MAP (Continued) ADDRESS NON-VOLATILE VOLATILE 6 5 4 General Purpose General Purpose General Purpose Not Available Not Available Not Available 3 2 1 0 IVR3 IVR2 IVR1 IVR0 WR3 WR2 WR1 WR0 The non-volatile IVRi and volatile WRi registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit (ACR[7]) determines whether the access is to wiper registers WR or initial value registers IVR. TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 6 5 4 3 2 1 0 Bit Name VOL SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR[6]) disables or enables Shutdown mode. This bit is logically ANDed with SHDN pin. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR[5]) is read only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write to the IVRi, WRi or ACR while WIP bit is 1. Shutdown Mode The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3. TABLE 3. SHDN pin SHDN bit Mode High 1 Normal operation Low 1 Shutdown High 0 Shutdown Low 0 Shutdown SPI Serial Interface The ISL22446 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22446. SCK and CS lines are controlled by the host or master. The ISL22446 operates only as a slave device. FN6181.2 September 9, 2009 ISL22446 All communication over the SPI interface is conducted by sending the MSB of each byte of data first. volatile or both volatile and non-volatile registers. Refer to “Memory Description” on page 11 and Figure 16. Protocol Conventions Device can receive more than one byte of data by auto incrementing the address after each received byte. Note after reaching the address 0110b, the internal pointer “rolls over” to address 0000b. The first byte sent to the ISL22446 from the SPI host is the Identification Byte. A valid Identification Byte contains 0101 as the four MSBs, with the following four bits set to 0. The internal non-volatile write cycle starts after rising edge of CS and takes up to 20ms. Thus, non-volatile registers must be written individually. TABLE 4. IDENTIFICATION BYTE FORMAT 0 1 0 1 0 0 0 0 (MSB) (LSB) Read Operation A read operation to the ISL22446 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte following by “dummy” Data Byte is sent to SDI pin. The SPI host reads the data from SDO pin on falling edge of SCK. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 17). The next byte sent to the ISL22446 contains the instruction and register pointer information. The four MSBs are the instruction and four LSBs are register address (see Table 5). TABLE 5. IDENTIFICATION BYTE FORMAT 7 6 5 4 3 2 1 0 I3 I2 I1 I0 R3 R2 R1 R0 The ISL22446 will provide the Data Bytes to the SDO pin as long as SCK is provided by the host from the registers indicated by an internal pointer. This pointer initial value is determined by the register address in the Read operation instruction, and increments by one during transmission of each Data Byte. After reaching the memory location 0110b, the pointer “rolls over” to 0000b, and the device continues to output the data for each received SCK clock. There are only two valid instruction sets: 1011(binary) - is a Read operation 1100(binary) - is a Write operation Write Operation A Write operation to the ISL22446 is a three-byte operation. It first requires the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte followed by Data Byte is sent to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. For a write to addresses 0000b to 0011b, the MSB at address 8 (ACR[7]) determines if the Data Byte is to be written to In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. CS SCK SDI 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0 0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 FIGURE 16. THREE BYTE WRITE SEQUENCE CS SCK SDI DON’T CARE 0 1 0 1 0 0 0 0 0 I3 I2 I1 I0 R3 R2 R1 R0 SDO 0 D6 D5 D4 D3 FIGURE 17. THREE BYTE READ SEQUENCE 12 FN6181.2 September 9, 2009 ISL22446 Applications Information B. Reading from the WR This sequence will read the value from the WR3 (volatile): Communicating with ISL22446 Communication with ISL22446 proceeds using SPI interface through the ACR (address 1000b), IVRi (addresses 0000b, 0001b, 0010b and 0011b) and WRi (addresses 0000b, 0001b, 0010b and 0011b) registers. The wiper of the potentiometer is controlled by the WRi register. Writes and reads can be made directly to these registers to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 1000b to 1. The non-volatile IVRi stores the power up value of the wiper. IVRs are accessible when MSB bit at address 1000b is set to 0. Writing a new value to the IVRi register will set a new power up position for the wiper. Also, writing to this register will load the same value into the corresponding WRi as the IVRi. Reading from the IVRi will not change the WRi, if its contents are different. Write to ACR first to access the WRs Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 1 1 0 0 0 0 0 0 (Sent to SDI) Read the data from WR3 (Addr 0011b) Send the ID byte, Instruction Byte, then Read the Data byte 0 1 0 1 0 0 0 0 1 0 1 1 0 0 1 1 x x x x x x x x (Out on SDO) Examples A. Writing to the IVR This sequence will write a new value (77h) to the IVR2 (non-volatile): Set the ACR (Addr 1000b) for NV write (40h) Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 (Sent to SDI) Set the IVR0 (Addr 0000b) to 77h Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 1 1 0 1 1 1 (Sent to SDI) 13 FN6181.2 September 9, 2009 ISL22446 Thin Quad Flat No-Lead Plastic Package (TQFN) Thin Micro Lead FramePlastic Package (TMLFP) L20.4x4A 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220WGGD-1 ISSUE I) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - 0.02 0.05 - A2 - 0.55 0.80 9 A3 b 0.20 REF 0.18 D 0.30 5, 8 4.00 BSC D1 D2 0.25 9 - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.50 BSC - k 0.20 - - - L 0.35 0.60 0.75 8 N 20 2 Nd 5 3 Ne 5 3 P - - 0.60 θ - - 12 9 9 Rev. 0 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 14 FN6181.2 September 9, 2009 ISL22446 Thin Shrink Small Outline Plastic Packages (TSSOP) N INDEX AREA E 0.25(0.010) M E1 2 INCHES SYMBOL 3 0.05(0.002) -A- 20 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE GAUGE PLANE -B1 M20.173 B M 0.25 0.010 SEATING PLANE L A D -C- α e A1 b A2 c 0.10(0.004) 0.10(0.004) M C A M B S NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AC, Issue E. MIN MAX MILLIMETERS MIN MAX NOTES A - 0.047 - 1.20 - A1 0.002 0.006 0.05 0.15 - A2 0.031 0.051 0.80 1.05 - b 0.0075 0.0118 0.19 0.30 9 c 0.0035 0.0079 0.09 0.20 - D 0.252 0.260 6.40 6.60 3 E1 0.169 0.177 4.30 4.50 4 e 0.026 BSC 0.65 BSC - E 0.246 0.256 6.25 6.50 - L 0.0177 0.0295 0.45 0.75 6 8o 0o N α 20 0o 20 7 8o 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. Rev. 1 6/98 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees) All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 15 FN6181.2 September 9, 2009