DATASHEET

DATASHEET
Precision Single and Dual Low Noise Operational
Amplifiers
ISL28127, ISL28227, ISL28227SEH
The ISL28127, ISL28227 and ISL28227SEH are very high
precision amplifiers featuring very low noise, low offset
voltage, low input bias current and low temperature drift
making them the ideal choice for applications requiring both
high DC accuracy and AC performance. The combination of
precision, low noise and small footprint provides the user with
outstanding value and flexibility relative to similar competitive
parts.
Applications for these amplifiers include precision active
filters, medical and analytical instrumentation, precision
power supply controls and industrial controls.
The ISL28127 single and ISL28227 dual are available in 8 Ld
SOIC, TDFN and MSOP packages. All devices are offered in
standard pin configurations and operate over the extended
temperature range to -40°C to +125°C.
The ISL28227SEH is available in a 10 Ld hermetic ceramic
Flatpack package. The device is offered in an industry
standard pin configuration and operates over the extended
temperature range from -55°C to +125°C.
Features
• Low input offset voltage . . . . . . . . . . . . . . . . . . . . ±70µV, max
ISL28227SEH ±75µV, max
• Superb offset voltage TC . . . . . . . . . . . . . . . . . .0.5µV/°C, max
ISL28227SEH 1µV/°C, max
• Wide supply range . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 40V
ISL28227SEH 4.5V to 36V
• Very low voltage noise . . . . . . . . . . . . . . . . . . . . . . . . .2.5nV/Hz
• Input bias current. . . . . . . . . . . . . . . . . . . . . . . . . . ±10nA, max
• Gain-bandwidth product . . . . . . . . . .10MHz Unity gain stable
• No phase reversal
• Operating temperature range. . . . . . . . . . . .-40°C to +125°C
ISL28227SEH -55°C to +125°C
Applications
• Precision instruments
Related Literature
• Medical instrumentation
• AN1508, ISL281x7SOICEVAL1Z Evaluation Board User’s
Guide
• Active filter blocks
• AN1509, ISL282x7SOICEVAL1Z Evaluation Board User’s
Guide
• Industrial controls
• Data acquisition
• Power supply control
• AN1556, Building an Accurate SPICE Model for Low Noise,
Low Power Precision Amplifiers
• AN1690, Electronics Meets the Challenges of Patient
Monitors
C1
1.5nF
V+
VIN
R1
R2
95.3
232
OUTPUT
+
68.3nF
C2
V-
Sallen-Key Low Pass Filter (1MHz)
FIGURE 1. TYPICAL APPLICATION
April 1, 2016
FN6633.8
1
INPUT NOISE VOLTAGE (nV√Hz)
100
VS = ±19V
AV = 1
10
1
0.1
1
10
100
1k
10k
100k
FREQUENCY (Hz)
FIGURE 2. INPUT NOISE VOLTAGE SPECTRAL DENSITY
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2009-2010, 2015,2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL28127, ISL28227, ISL28227SEH
Table of Contents
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications ISL28127, ISL28227 (VS ±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical Specifications ISL28127, ISL28227 (VS ±5V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Electrical Specifications ISL28227SEH (VS ±15V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications ISL28227SEH (VS ±5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Applications Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input ESD Diode Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Phase Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Unused Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ISL28127, ISL28227 SPICE Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19
19
19
19
19
19
19
19
20
Characterization vs Simulation Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8.15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
L8.3x3K. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M8.118B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
K10.A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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2
30
30
31
32
33
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Ordering Information
VOS (MAX)
(µV)
PART
MARKING
PART NUMBER
ISL28127FBZ (No longer available,
recommended replacement:
ISL28127FRTZ-T13) (Notes 1, 4, 6)
28127 FBZ
ISL28127FRTBZ (No longer available,
recommended replacement:
ISL28127FRTZ-T13) (Notes 1, 4, 6)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
70
8 Ld SOIC
M8.15E
8127
75 (B Grade)
8 Ld TDFN
L8.3x3K
ISL28127FRTZ (Notes 1, 4, 6)
-C 8127
150 (C Grade)
8 Ld TDFN
L8.3x3K
ISL28127FUBZ (No longer available,
recommended replacement:
ISL28127FRTZ-T13) (Notes 1, 4, 6)
8127Z
70 (B Grade)
8 Ld MSOP
M8.118B
ISL28127FUZ (No longer available,
recommended replacement:
ISL28127FRTZ-T13) (Notes 1, 4, 6)
8127Z -C
150 (C Grade)
8 Ld MSOP
M8.118B
ISL28227FBZ (Notes 2, 4, 6)
28227 FBZ
75
8 Ld SOIC
M8.15E
ISL28227FRTBZ (Notes 2, 4, 6)
8227
75 (B Grade)
8 Ld TDFN
L8.3x3K
ISL28227FRTZ (Notes 1, 4, 6)
-C 8227
150 (C Grade)
8 Ld TDFN
L8.3x3K
ISL28227FUBZ (Notes 3, 4, 6)
8227Z
75 (B Grade)
8 Ld MSOP
M8.118B
ISL28227FUZ (Notes 3, 4, 6)
8227Z -C
150 (C Grade)
8 Ld MSOP
M8.118B
ISL28227SEHMF (Note 5)
ISL28227SEHMF
75 (B Grade)
10 Ld FLATPACK
K10.A
ISL28227SEHF/PROTO (Note 5)
ISL28227 SEHF/PROTO
75 (B Grade)
10 Ld FLATPACK
K10.A
ISL28227SEHMX (Note 5)
75 (B Grade)
DIE
ISL28227SEHX/SAMPLE (Note 5)
75 (B Grade)
DIE
ISL28127SOICEVAL1Z
Evaluation Board
ISL28127MSOPEVAL1Z
Evaluation Board
ISL28227SOICEVAL2Z
Evaluation Board
ISL70227MHEVAL1Z
Evaluation Board
1. Add “-T13” suffix for 6k unit, -T7” suffix for 1k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
2. Add “-T13” suffix for 2.5k unit, -T7” suffix for 1k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
3. Add “-T13” suffix for 2.5k unit, -T7” suffix for 1.5k,“-T7A” suffix for 250 unit Tape and Reel options. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products
are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. These Intersil Pb-free Hermetic packaged products employ 100% Au plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb
and Pb-free soldering operations.
6. For Moisture Sensitivity Level (MSL), please see device information page for ISL28127, ISL28227. For more information on MSL please see techbrief
TB363.
TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS
PART NUMBER
NUMBER OF DEVICES
OPERATING TEMPERATURE RANGE
ISL28127
1
-40°C to +125°C
ISL28227
2
-40°C to +125°C
ISL28227SEH
2
-55°C to +125°C
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3
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Pin Configurations
ISL28227
(8 LD SOIC, MSOP)
TOP VIEW
ISL28127
(8 LD SOIC, MSOP)
TOP VIEW
NC
1
-IN_A
2
+IN_A
3
NO
L
AI
V - 4 AV
R
E
NG
LO
ED
RT NC
8
O
PP
SU 7 V+
- +OR
LE
B
6 VOUTA
A
5
NC
VOUTA
1
-IN_A
2
+IN_A
3
V-
4
NC 1
- +
+IN 3
PD
V- 4
+ -
V+
7
VOUTB
6
-IN_B
5
+IN_B
ISL28227
(8 LD TDFN)
TOP VIEW
ISL28127
(8 LD TDFN)
TOP VIEW
-IN 2
- +
8
8 NC
VOUTA 1
7 V+
-IN_A 2
6 VOUT
+IN_A 3
V- 4
5 NC
8 V+
7 VOUTB
- +
PD
+ -
6 -IN_B
5 +IN_B
ISL28227SEH
(10 LD FLATPACK)
TOP VIEW
VOUTA
1
-IN A
2
+IN A
3
NC
4
V-
5
10
- +
+ -
V+
9
VOUTB
8
-IN B
7
+IN B
6
NC
Pin Descriptions
ISL28127
(8 Ld SOIC,
8 Ld MSOP)
(NO LONGER
AVAILABLE)
ISL28227
(8 Ld SOIC,
8 Ld MSOP)
ISL28127
(8 Ld TDFN)
ISL28227
(8 Ld TDFN)
ISL28227SEH
(10 Ld Flatpack)
3
3
4
4
+IN
Circuit 1
Amplifier noninverting input
DESCRIPTION
3
3
+IN_A
Circuit 1
Amplifier A noninverting input
4
4
5
V-
Circuit 3
Negative power supply
5
5
7
+IN_B
Circuit 1
Amplifier B noninverting input
-IN
Circuit 1
Amplifier inverting input
-IN_B
Circuit 1
Amplifier B inverting input
6
4
EQUIVALENT
CIRCUIT
3
2
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PIN
NAME
6
8
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Pin Descriptions (Continued)
ISL28127
(8 Ld SOIC,
8 Ld MSOP)
(NO LONGER
AVAILABLE)
ISL28227
(8 Ld SOIC,
8 Ld MSOP)
ISL28127
(8 Ld TDFN)
ISL28227
(8 Ld TDFN)
ISL28227SEH
(10 Ld Flatpack)
6
PIN
NAME
EQUIVALENT
CIRCUIT
VOUT
Circuit 2
Amplifier output
DESCRIPTION
7
7
9
VOUTB
Circuit 2
Amplifier B output
8
8
10
V+
Circuit 3
Positive power supply
6
1
1
1
VOUTA
Circuit 2
Amplifier A output
2
2
2
2
-IN_A
Circuit 1
Amplifier A inverting input
4, 6
NC
-
Not Connected – This pin is not
electrically connected internally.
PD
-
Thermal Pad. Pad should be
connected to lowest potential
source in the circuit.
7
1, 5, 8
7
1, 5, 8
PD
V+
IN-
V+
V-
V-
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CIRCUIT 2
5
CAPACITIVELY T
RIGGERED ESD
CLAMP
OUT
IN+
CIRCUIT 1
V+
VCIRCUIT 3
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Absolute Maximum Ratings
Thermal Information
Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2V
Maximum Supply Voltage ISL28227SEH (Note 12) . . . . . . . . . . . . . . . . 36V
Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA
Maximum Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.5V
Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . V- - 0.5V to V+ + 0.5V
Max/Min Input Current for
Input Voltage >V+ or <V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA
Output Short-Circuit Duration
(1 Output at a Time) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite
ESD Tolerance ISL28127, ISL28227
Human Body Model (Tested per JESD22-A114F)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5kV
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6.0kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 500V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . .1.5kV
ESD Tolerance ISL28227SEH
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per EIA/JESD22-A115-A) . . . . . . . . . . . . . . 300V
Charged Device Model (Tested per JESD22-C101D) . . . . . . . . . . . . 750V
Thermal Resistance (Typical)
JA (°C/W) JC (°C/W)
8 Ld SOIC (Notes 8, 11)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . .
120
60
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . .
110
55
8 Ld TDFN (Notes 7, 10)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . .
48
7
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . .
47
6
8 Ld MSOP (Notes 8, 11)
ISL28127. . . . . . . . . . . . . . . . . . . . . . . . . .
155
50
ISL28227. . . . . . . . . . . . . . . . . . . . . . . . . .
150
45
10 Ld Ceramic Flatpack (Notes 9, 10). . . .
130
20
Pb-Free Reflow Profile (None-Hermetic Packages Only) . . . . see TB493
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Recommended Operating Conditions
Ambient Operating Temperature Range
ISL28127, ISL28227 . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
ISL28227SEH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C
Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
7. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
8. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
9. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
10. For JC, the “case temp” location is the center of the package underside.
11. For JC, the “case temp” location is taken at the package top center.
12. No destructive single-event effects at effective LET of 86.4MeV•cm2/mg up to a supply of ±18V. Reference manufacturers SEE report.
Electrical Specifications ISL28127, ISL28227 (VS ±15V)
noted. Boldface limits apply across the operating temperature range, -40°C to +125°C.
PARAMETER
VOS
DESCRIPTION
Offset Voltage;
SOIC Package
TEST CONDITIONS
ISL28127
ISL28227
Offset Voltage;
MSOP Grade B Package
ISL28127
Offset Voltage;
TDFN Grade B Package
ISL28127
Offset Voltage;
MSOP, TDFN Grade B Package
ISL28227
Offset Voltage;
MSOP, TDFN Grade C Package
ISL28127
ISL28227
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6
VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
-70
10
70
µV
-120
-
120
µV
-75
10
75
µV
-150
-
150
µV
-70
-10
70
µV
-150
-
150
µV
-75
-10
75
µV
-160
-
160
µV
-75
-10
75
µV
-150
-
150
µV
-150
-10
150
µV
-250
-
250
µV
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Electrical Specifications ISL28127, ISL28227 (VS ±15V) VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise
noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
TCVOS
IOS
IB
VCM
CMRR
PSRR
DESCRIPTION
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
Offset Voltage Drift;
SOIC Package
ISL28127
-0.5
0.1
0.5
µV/°C
ISL28227
-0.75
0.10
0.75
µV/°C
Offset Voltage Drift;
MSOP, Grade B
ISL28127
-0.80
0.10
0.80
µV/°C
Offset Voltage Drift;
TDFN, Grade B
ISL28127
-0.90
0.10
0.90
µV/°C
Offset Voltage Drift;
MSOP, TDFN, Grade B
ISL28227
-0.75
0.10
0.75
µV/°C
Offset Voltage Drift;
MSOP, TDFN, Grade C
ISL28127
ISL28227
-1
0.1
1
µV/°C
-10
1
10
nA
-12
-
12
nA
-10
1
10
nA
-12
-
12
nA
-13
-
13
V
-12
-
12
V
VCM = -13V to +13V
115
120
-
dB
VCM = -12V to +12V
115
-
-
dB
Power Supply Rejection Ratio
ISL28127
VS = ±2.25V to ±20V
115
125
-
dB
VS = ±3V to ± 20V
115
-
-
dB
Power Supply Rejection Ratio ISL28227
VS = ±2.25V to ±20V
110
117
-
dB
VS = ±3V to ± 20V
110
-
-
dB
Input Offset Current
Input Bias Current
Input Voltage Range
Common-Mode Rejection Ratio
Guaranteed by CMRR
AVOL
Open-Loop Gain
VO = -13V to +13V
RL = 10kΩ to ground
1000
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
13.50
13.65
-
V
13.2
-
-
V
13.4
13.5
-
V
13.1
-
-
V
-
-13.65
-13.50
V
-
-
-13.2
V
-
-13.5
-13.4
V
-
-
-13.1
V
-
2.2
2.8
mA
-
-
3.7
mA
-
±45
-
mA
±2.25
-
±20
V
RL = 2kΩ to ground
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
IS
ISC
VSUPPLY
Supply Current/Amplifier
Short-Circuit
RL = 0Ωto ground
Supply Voltage Range
Guaranteed by PSRR
Submit Document Feedback
7
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Electrical Specifications ISL28127, ISL28227 (VS ±15V) VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise
noted. Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
-
10
-
MHz
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
enp-p
Voltage Noise
0.1Hz to 10Hz
-
85
-
nVP-P
Voltage Noise Density
f = 10Hz
-
3
-
nV/Hz
f = 100Hz
-
2.8
-
nV/Hz
f = 1kHz
-
2.5
-
nV/Hz
f = 10kHz
-
2.5
-
nV/Hz
Current Noise Density
f = 10kHz
-
0.4
-
pA/Hz
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 3.5VRMS,
RL = 2kΩ
-
0.00022
-
%
Slew Rate
AV = 10, RL = 2kΩVO = 4VP-P
-
±3.6
-
V/µs
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
36
-
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
38
-
ns
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1 VOUT = 10VP-P,
Rg = Rf =10k, RL = 2kΩ to VCM
-
3.4
-
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P,
RL = 2kΩ to VCM
-
3.8
-
µs
Output Overload Recovery Time
AV = 100, VIN = 0.2V
RL = 2kΩ to VCM
-
1.7
-
µs
en
in
THD + N
TRANSIENT RESPONSE
SR
tr, tf, Small Signal
ts
tOL
Electrical Specifications ISL28127, ISL28227 (VS ±5V)
VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted.
Boldface limits apply across the operating temperature range, -40°C to +125°C.
PARAMETER
VOS
DESCRIPTION
Offset Voltage; SOIC Package
TEST CONDITIONS
ISL28127
ISL28227
Offset Voltage;
MSOP Grade B Package
ISL28127
Offset Voltage;
TDFN Grade B Package
ISL28127
Offset Voltage;
MSOP, TDFN Grade B Package
ISL28227
Offset Voltage;
MSOP, TDFN Grade C Package
ISL28127
ISL28227
Submit Document Feedback
8
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
-70
10
70
µV
-120
-
120
µV
-75
10
75
µV
-150
-
150
µV
-70
-10
70
µV
-150
-
150
µV
-75
-10
75
µV
-160
-
160
µV
-75
-10
75
µV
-150
-
150
µV
-150
-10
150
µV
-250
-
250
µV
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Electrical Specifications ISL28127, ISL28227 (VS ±5V)
VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
TCVOS
IOS
IB
VCM
CMRR
PSRR
DESCRIPTION
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
Offset Voltage Drift;
SOIC Package
ISL28127
-0.5
0.1
0.5
µV/°C
ISL28227
-0.75
0.1
0.75
µV/°C
Offset Voltage Drift;
MSOP, Grade B
ISL28127
-0.80
0.1
0.80
µV/°C
Offset Voltage Drift;
TDFN, Grade B
ISL28127
-0.90
0.1
0.90
µV/°C
Offset Voltage Drift;
MSOP, TDFN, Grade B
ISL28227
-0.75
0.1
0.75
µV/°C
Offset Voltage Drift;
MSOP, TDFN, Grade C
ISL28127
ISL28227
-1
0.1
1
µV/°C
-10
1
10
nA
-12
-
12
nA
10
1
10
nA
-12
-
12
nA
-3
-
3
V
-2
-
2
V
VCM = -3V to +3V
115
120
-
dB
VCM = -2V to +2V
115
-
-
dB
VS = ±2.25V to ±5V
115
125
-
dB
VS = ±3V to ±5V
115
-
-
dB
Input Offset Current
Input Bias Current
Common-Mode Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
Guaranteed by CMRR
AVOL
Open-Loop Gain
VO = -3V to +3V
RL = 10kΩ to ground
1000
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
3.50
3.65
-
V
3.2
-
-
V
3.4
3.5
-
3.1
-
-
V
-
-3.65
-3.50
V
-
-
-3.2
V
-
-3.5
-3.4
-
-
-3.1
V
-
2.2
2.8
mA
-
-
3.7
mA
-
±45
-
mA
-
10
-
MHz
1kHz, G = 1, Vo = 2.5VRMS,
RL = 2kΩ
-
0.0034
-
%
AV = 10, RL = 2kΩ
-
±3.6
-
V/µs
RL = 2kΩ to ground
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
IS
ISC
Supply Current/Amplifier
Short-Circuit
AC SPECIFICATIONS
GBW
THD + N
Gain Bandwidth Product
Total Harmonic Distortion + Noise
TRANSIENT RESPONSE
SR
Slew Rate
Submit Document Feedback
9
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Electrical Specifications ISL28127, ISL28227 (VS ±5V)
VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
tr, tf, Small
Signal
ts
DESCRIPTION
TEST CONDITIONS
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
36
-
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
38
-
ns
Settling Time to 0.1%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
1.6
-
µs
Settling Time to 0.01%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩto VCM
-
4.2
-
µs
Electrical Specifications ISL28227SEH (VS ±15V)
VCM = 0, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted.
Boldface limits apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance
following 60Co irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance.
PARAMETER
VOS
DESCRIPTION
Offset Voltage Drift
IOS
Input Offset Current
VCM
CMRR
PSRR
TYP
MAX
(Note 13)
UNIT
-75
-10
75
µV
-100
-
100
µV
-1
0.1
1
µV/°C
TA = +25°C
-10
1
10
nA
TA = -55°C, +125°C
-12
-
12
nA
TA = +25°C, post radiation
-25
25
nA
TA = +25°C
-10
1
10
nA
TA = -55°C, +125°C
-12
-
12
nA
TA = +25°C, post radiation
-25
25
nA
Guaranteed by CMRR
-13
-
13
V
-12
-
12
V
VCM = -13V to +13V
115
120
-
dB
VCM = -12V to +12V
115
-
-
dB
VS = ±2.25V to ±5V
110
117
-
dB
VS = ±3V to ±15V
110
-
-
dB
Offset Voltage
TCVOS
IB
MIN
(Note 13)
TEST CONDITIONS
Input Bias Current
Input Voltage Range
Common-Mode Rejection Ratio
Power Supply Rejection Ratio
AVOL
Open-Loop Gain
VO = -13V to +13V
RL = 10kΩ to ground
1000
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
13.5
13.65
-
V
13.2
-
-
V
13.4
13.5
-
V
13.1
-
-
V
-
-13.65
-13.5
V
-
-
-13.2
V
-
-13.5
-13.4
V
-
-
-13.1
V
-
2.2
2.8
mA
-
-
3.7
mA
-
±45
-
mA
RL = 2kΩ to ground
VOL
Output Voltage Low
RL = 10kΩ to ground
RL = 2kΩ to ground
IS
ISC
Supply Current/Amplifier
Short-Circuit
Submit Document Feedback
RL = 0Ωto ground
10
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Electrical Specifications ISL28227SEH (VS ±15V)
VCM = 0, VO = 0V, RL = Open, TA = +25°C, unless otherwise noted.
Boldface limits apply across the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance
following 60Co irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued)
PARAMETER
VSUPPLY
DESCRIPTION
Supply Voltage Range
TEST CONDITIONS
Guaranteed by PSRR
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
±2.25
-
±15
V
-
10
-
MHz
AC SPECIFICATIONS
GBW
Gain Bandwidth Product
enp-p
Voltage Noise
0.1Hz to 10Hz
-
85
-
nVP-P
Voltage Noise Density
f = 10Hz
-
3
-
nV/Hz
f = 100Hz
-
2.8
-
nV/Hz
f = 1kHz
-
2.5
-
nV/Hz
f = 10kHz
-
2.5
-
nV/Hz
Current Noise Density
f = 10kHz
-
0.4
-
pA/Hz
Total Harmonic Distortion + Noise
1kHz, G = 1, VO = 3.5VRMS,
RL = 2kΩ
-
0.00022
-
%
Slew Rate
AV = 10, RL = 2kΩVO = 4VP-P
-
±3.6
-
V/µs
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
36
-
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
38
-
ns
Settling Time to 0.1%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P,
Rg = Rf = 10k, RL = 2kΩ to VCM
-
3.4
-
µs
Settling Time to 0.01%
10V Step; 10% to VOUT
AV = -1, VOUT = 10VP-P,
RL = 2kΩ to VCM
-
3.8
-
µs
Output Overload Recovery Time
AV = 100, VIN = 0.2V,
RL = 2kΩ to VCM
-
1.7
-
µs
en
in
THD + N
TRANSIENT RESPONSE
SR
tr, tf, Small
Signal
ts
tOL
Electrical Specifications ISL28227SEH (VS ±5V)
VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits
apply over the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following 60Co
irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance.
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
Offset Voltage
-
-10
-
µV
TCVOS
Offset Voltage Drift
-
.1
-
µV/°C
IOS
Input Offset Current
-
1
-
nA
IB
Input Bias Current
-
1
-
nA
PARAMETER
VOS
DESCRIPTION
TEST CONDITIONS
CMRR
Common-Mode Rejection Ratio
VCM = -3V to +3V
-
120
-
dB
PSRR
Power Supply Rejection Ratio
VS = ±2.25V to ±5V
-
125
-
dB
AVOL
Open-Loop Gain
VO = -3V to +3V
RL = 10kΩ to ground
-
1500
-
V/mV
VOH
Output Voltage High
RL = 10kΩ to ground
-
3.65
-
V
RL = 2kΩ to ground
-
3.5
-
RL = 10kΩ to ground
-
-3.65
-
RL = 2kΩ to ground
-
-3.5
-
-
2.2
-
VOL
IS
Output Voltage Low
Supply Current/Amplifier
Submit Document Feedback
11
V
mA
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Electrical Specifications ISL28227SEH (VS ±5V)
VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits
apply over the -55°C to +125°C operating temperature range. The limits also define room temperature post-irradiation performance following 60Co
irradiation at 0.01rad(Si)/s to a total dose of 50krad(Si) wafer-by-wafer acceptance. (Continued)
PARAMETER
ISC
DESCRIPTION
TEST CONDITIONS
Short-Circuit
MIN
(Note 13)
TYP
MAX
(Note 13)
UNIT
-
±45
-
mA
-
10
-
MHz
-
0.0034
-
%
AC SPECIFICATIONS
GBW
THD + N
Gain Bandwidth Product
Total Harmonic Distortion + Noise
1kHz, G = 1, Vo = 2.5VRMS,
RL = 2kΩ
TRANSIENT RESPONSE
SR
tr, tf, Small
Signal
ts
Slew Rate
AV = 10, RL = 2kΩ
-
±3.6
-
V/µs
Rise Time
10% to 90% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
36
-
ns
Fall Time
90% to 10% of VOUT
AV = -1, VOUT = 100mVP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
38
-
ns
Settling Time to 0.1%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
1.6
-
µs
Settling Time to 0.01%
AV = -1, VOUT = 4VP-P,
Rf = Rg = 2kΩ, RL = 2kΩ to VCM
-
4.2
-
µs
NOTE:
13. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
Submit Document Feedback
12
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified.
100
INPUT NOISE VOLTAGE (nV/√Hz)
INPUT NOISE VOLTAGE (nV)
100
80
60
40
20
0
-20
V+ = 38V
RL = 10k
CL = 3.5pF
Rg = 10, Rf = 100k
AV = 10,000
-40
-60
-80
-100
0
1
2
3
4
5
6
7
8
9
VS = ±19V
AV = 1
10
1
0.1
10
1
10
TIME (s)
FIGURE 3. INPUT NOISE VOLTAGE 0.1Hz to 10Hz
10
PSRR (dB )
INPUT NOISE CURRENT (pA/ÖHz)
VS = ±19V
AV = 1
1
1
10
100
1k
10k
100k
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
100k
RL = INF
CL = 5.25pF
AV = +1
VS = 1VP-P
PSRR+ AND PSRR- VS = ±15V
10
100
1k
10k
100k
10M
1M
FREQUENCY (Hz)
FIGURE 6. PSRR vs FREQUENCY, VS = ±5V, ±15V
FIGURE 5. INPUT NOISE CURRENT SPECTRAL DENSITY
100
VS = ±5V
VS = ±2.25V
50
VS = ±15V
VOS (µV)
CMRR (dB)
10k
PSRR+ AND PSRR- VS = ±5V
FREQUENCY (Hz)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
1k
FIGURE 4. INPUT NOISE VOLTAGE SPECTRAL DENSITY
100
0.1
0.1
100
FREQUENCY (Hz)
RL = INF
CL = 5.25pF
AV = +1
VCM = 1VP-P
100
VS = ±5
0
VS = ±15
-50
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 7. CMRR vs FREQUENCY, VS = ±2.25, ±5V, ±15V
Submit Document Feedback
13
-100
-50
0
50
TEMPERATURE (°C)
100
150
FIGURE 8. VOS vs TEMPERATURE vs VSUPPLY
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
5000
5000
4000
4000
3000
3000
2000
2000
1000
1000
0
IB- (pA)
IB+ (pA)
Typical Performance Curves
VS = ±15
-1000
-2000
-2000
VS = ±5
-3000
-4000
-5000
-50
0
50
100
TEMPERATURE (°C)
-5000
-50
150
-25
5000
29 UNITS
100
125
150
AVERAGE
40
3000
2000
20
0
VOS (µV)
VS = ±15
1000
VS = ±5
-1000
+25°C
0
+125°C
-20
-2000
-3000
-40°C
-40
-4000
-25
0
25
50
75
100
125
-60
150
-15
-10
-5
0
5
10
15
INPUT COMMON-MODE VOLTAGE
TEMPERATURE (°C)
FIGURE 11. IOS vs TEMPERATURE vs SUPPLY VOLTAGE
600
FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON-MODE
VOLTAGE, VS = ±15V
600
VS = ±15V
VS = ±5V
500
500
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
25
50
75
TEMPERATURE (°C)
60
4000
400
300
200
100
0
-70
0
FIGURE 10. IB- vs TEMPERATURE vs SUPPLY VOLTAGE
FIGURE 9. IB+ vs TEMPERATURE vs SUPPLY VOLTAGE
IOS (pA)
VS = ±5
-3000
-4000
-5000
-50
VS = ±15
0
-1000
-55
-40
-25
-10
5
20
35
50
65
VOS (µV)
FIGURE 13. INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±15V
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14
400
300
200
100
0
-70
-55
-40
-25
-10
5
20
35
50
65
VOS (µV)
FIGURE 14. INPUT OFFSET VOLTAGE DISTRIBUTION, VS = ±5V
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
30
30
Vs = ±5V
25
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
Vs = ±15V
20
15
10
5
0
-0.7
-0.5
-0.3
-0.1
0.1
0.3
VOS TC (µV/°C)
0.5
5
-0.7
-0.5
-0.3
-0.1
0.1
VOS TC (µV/°C)
0.3
30
25
20
15
10
5
-22.5
-15
-7.5
0
7.5
IB+ TC (pA/°C)
15
45
Vs = ±5V
25
20
15
10
5
0
-27
-18
-9
0
9
IB- TC (pA/°C)
18
27
FIGURE 19. IB- INPUT BIAS CURRENT DRIFT DISTRIBUTION,
VS = ±15V
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15
20
15
10
5
-25
-20
-15
-10
0
-5
5
IB+ TC (pA/°C)
10
35
NUMBER OF AMPLIFIERS
35
30
25
15
20
25
FIGURE 18. IB+ INPUT BIAS CURRENT DRIFT DISTRIBUTION,
VS = ±5V
Vs = ±15V
40
0.7
30
0
22.5
FIGURE 17. IB+ INPUT BIAS CURRENT DRIFT DISTRIBUTION,
VS = ±15V
0.5
FIGURE 16. OFFSET VOLTAGE DRIFT DISTRIBUTION, VS = ±5V
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
10
Vs = ±15V
35
NUMBER OF AMPLIFIERS
15
35
40
0
20
0
0.7
FIGURE 15. OFFSET VOLTAGE DRIFT DISTRIBUTION, VS = ±15V
25
Vs = ±5V
30
25
20
15
10
5
0
-30
-24
-18
-12
0
-6
6
IB- TC (pA/°C)
12
18
24
30
FIGURE 20. IB- INPUT BIAS CURRENT DRIFT DISTRIBUTION,
VS = ±5V
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Typical Performance Curves
50
VS = ±15V
50
40
30
20
10
0
-27
-18
-9
0
9
IOS TC (pA/°C)
18
30
25
20
15
10
-30
-18
-24
-12
-6
0
6
IOS TC (pA/°C)
12
18
24
30
FIGURE 22. INPUT OFFSET CURRENT DISTRIBUTION, VS = ±5V
-13.1
14.1
-13.2
MEDIAN
50 UNITS
14.0
-13.4
VOUT (V)
13.8
RL = 100k
13.7
13.6
RL = 2k
13.5
-13.6
-13.7
-13.9
-14.0
-14.1
0
20
40
60
80
100
-14.2
120
FIGURE 25. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ
CL = 10pF
16
-20
0
20
40
60
80
100
120
FIGURE 24. VOL vs TEMPERATURE, VS = ±15V
OPEN LOOP GAIN (dB)/PHASE(°)
FIGURE 23. VOH vs TEMPERATURE, VS = ±15V
200
180
160
140
PHASE
120
100
80
60
40
GAIN
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
-80 SIMULATION
-100
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
-40
TEMPERATURE (°C)
TEMPERATURE (°C)
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RL = 100k
-13.8
13.3
-20
RL = 2k
-13.5
13.4
-40
MEDIAN
50 UNITS
-13.3
13.9
VOUT (V)
35
0
27
14.2
OPEN LOOP GAIN (dB)/PHASE (°)
40
5
FIGURE 21. INPUT OFFSET CURRENT DISTRIBUTION, VS = ±15V
13.2
VS = ±5V
45
60
NUMBER OF AMPLIFIERS
NUMBER OF AMPLIFIERS
70
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
200
180
160
140
PHASE
120
100
80
60
40
GAIN
20
0
-20 R = 10k
L
-40
CL = 100pF
-60
SIMULATION
-80
-100
0.1m 1m 10m 100m 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz)
FIGURE 26. OPEN-LOOP GAIN, PHASE vs FREQUENCY, RL = 10kΩ
CL = 100pF
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
70
GAIN (dB)
50
40
30
20
10
0
15
AV = 1000
Rg = 100, Rf = 100k
Rg = 1k, Rf = 100k
AV = 100
VS = ±15V
CL = 3.5pF
RL = INF
VOUT = 100mVP-P
AV = 10
Rg = 10k, Rf = 100k
AV = 1
-10
100
Rg = OPEN, Rf = 0
1k
10k
100k
1M
FREQUENCY (Hz)
10M
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 499
RL = 100
RL = 49.9
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
-4
-5
1k
10k
3 VS = ±15V
RL = 10k
1
CL = 3.5pF
-1 A = +2
V
-3 VOUT = 100mVP-P
5
4
100k
100k
1M
FREQUENCY (Hz)
1M
10M
100M
CL = 1000pF
CL = 220pF
CL = 100pF
2
CL = 25.5pF
1
0
-1
CL = 3.5pF
-2
10M
-3
100M
10k
1k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 30. GAIN vs FREQUENCY vs CL
6
5
VS = ±2.25V
4
0
VS = ±5V
-1
VS = ±15V
CL = 3.5pF
RL = 10k
AV = +1
VOUT = 100mVP-P
-2
-3
LARGE SIGNAL (V)
NORMALIZED GAIN (dB)
10k
1k
3
FIGURE 29. GAIN vs FREQUENCY vs RL
1
Rf = Rg = 100
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
6
0
VS = ±15V
5
7
RL = 1k
-3
7
FIGURE 28. FREQUENCY RESPONSE vs FEEDBACK RESISTANCE
Rf/Rg
RL = 10k
-2
Rf = Rg = 1k
9
FREQUENCY (Hz)
2
-1
Rf = Rg = 10k
11
-5
100M
FIGURE 27. FREQUENCY RESPONSE vs CLOSED LOOP GAIN
1
Rf = Rg = 100k
13
NORMALIZED GAIN (dB)
60
1k
10k
2
1
0
1
RL = 2k
-2
-3
RL = 10k
-4
-5
100k
1M
10M
FREQUENCY (Hz)
FIGURE 31. GAIN vs FREQUENCY vs SUPPLY VOLTAGE
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VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0 Rg = inf
VOUT = 10VP-P
3
17
100M
-6
0
5
10
15
TIME (µs)
20
25
30
FIGURE 32. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Typical Performance Curves
VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued)
80
2.4
60
VS = ±15V, RL = 2k, 10k
0.8
0.4
0
-0.4
VS = ±5V, RL = 2k, 10k
-0.8
-1.2
CL = 3.5pF
AV = 1
VOUT = 4VP-P
-1.6
-2.0
-2.4
0
5
10
15
30
35
-0.26
VS = ±15V
RL = 10k
CL = 3.5pF
AV = 100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
5
10
15
20
25
TIME (µs)
30
13
0.22
11
0.08
9
7
5
OUTPUT
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
0.26
35
INPUT (V)
INPUT (V)
-0.02
-0.20
0
FIGURE 34. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V,
±15V
OUTPUT (V)
INPUT
-0.18
RL = 2k
CL = 3.5pF
AV = 1
VOUT = 100mVP-P
40
80
15
-0.14
20
TIME (ms)
0.06
-0.10
VS = ±5V, ±15V
0
40
FIGURE 33. LARGE SIGNAL TRANSIENT RESPONSE vs RL VS = ±5V,
±15V
-0.06
20
60
20
25
TIME (µs)
0.02
40
2
OUTPUT
0.04
0.10
0.06
3
0.02
1
-0.02
FIGURE 35. POSITIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
VS = ±15V
RL = 10k
CL = 3.5pF
AV = 100
Rf = 100k, Rg = 1k
VIN = 200mVP-P
-2
INPUT
-10
-4
-6
-8
-12
-0.06
0
-1
40
0
OUTPUT (V)
1.6
1.2
SMALL SIGNAL (mV)
LARGE SIGNAL (V)
2.0
5
10
15
20
25
TIME (µs)
30
35
-14
40
FIGURE 36. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME,
VS = ±15V
90
80
OVERSHOOT (%)
70
60
50
40
VS = ±15V
RL = 10k
AV = 1
VOUT = 100mVP-P
E
OV
30
20
O
HO
RS
OT
HO
RS
VE
+
OT
-
10
0
10
100
1000
CAPACITANCE (pF)
10000
FIGURE 37. % OVERSHOOT vs LOAD CAPACITANCE, VS = ±15V
Submit Document Feedback
18
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Applications Information
needed at each input terminal (see Figure 39 RIN+, RIN-) to limit
current through the power supply ESD diodes to 20mA.
Functional Description
The ISL28127, ISL28227 and ISL28227SEH are single and dual,
low noise 10MHz BW precision op amps. All devices are
fabricated in a new precision 40V complementary bipolar DI
process. A super-beta NPN input stage with input bias current
cancellation provides low input bias current (1nA typical), low
input offset voltage (10µV typical), low input noise voltage
(3nV/Hz) and low 1/f noise corner frequency (5Hz). These
amplifiers also feature high open loop gain (1500V/mV) for
excellent CMRR (120dB) and THD+N performance (0.0002% at
3.5VRMS, 1kHz into 2kΩ). A complimentary bipolar output stage
enables high capacitive load drive without external
compensation.
V+
VINVIN+
RIN-
-
RIN+
+
VOUT
RL
V-
FIGURE 39. INPUT ESD DIODE CURRENT LIMITING DIFFERENTIAL
INPUT
Operating Voltage Range
Output Current Limiting
The devices are designed to operate over the 4.5V (±2.25V) to
40V (±20V) range and are fully characterized at 10V (±5V) and
30V (±15V). Parameter variation with operating voltage is shown
in the “Typical Performance Curves” beginning on page 13.
The output current is internally limited to approximately ±45mA
at +25°C and can withstand short-circuit to either rail as long as
the power dissipation limits are not exceeded. This applies to
only 1 amplifier at a time for the dual op amp. Continuous
operation under these conditions may degrade long term
reliability.
Input ESD Diode Protection
The input terminals (IN+ and IN-) have internal ESD protection
diodes to the positive and negative supply rails and an additional
anti-parallel diode pair across the inputs (see Figures 38 and 39).
V+
VIN
RIN
VOUT
+
RL
V-
FIGURE 38. INPUT ESD DIODE CURRENT LIMITING - UNITY GAIN
For unity gain applications (see Figure 38) where the output is
connected directly to the non-inverting input a current limiting
resistor (RIN) will be needed under the following conditions to
protect the anti-parallel differential input protection diodes.
Output Phase Reversal
Output phase reversal is a change of polarity in the amplifier
transfer function when the input voltage exceeds the supply
voltage. The ISL28127, ISL28227 and ISL28227SEH are
immune to output phase reversal, even when the input voltage is
1V beyond the supplies.
Unused Channels
The user must configure unused channels to prevent them from
oscillating. The unused channel(s) oscillates if the input and
output pins are floating. This results in higher than expected
supply currents and possible noise injection into the other
channel(s) being used. The proper way to prevent this oscillation
is to short the output to the inverting input and ground the
positive input, as shown in Figure 40.
-
• The amplifier input is supplied from a low impedance source.
• The input voltage rate-of-rise (dV/dt) exceeds the maximum
slew rate of the amplifier (±3.6V/µs).
If the output lags far enough behind the input, the anti-parallel
input diodes can conduct. For example, if an input pulse ramps
from 0V to +10V in 1µs, then the output of the amplifier will reach
only +3.6V (slew rate = 3.6V/µs) while the input is at 10V, The
input differential voltage of 6.4V will force input ESD diodes to
conduct, dumping the input current directly into the output stage
and the load. The resulting current flow can cause permanent
damage to the ESD diodes. The ESD diodes are rated to 20mA and
in the previous example, setting RIN to 1k resistor (see Figure 38)
would limit the current to < 6.4mA and provide additional
protection up to ±20V at the input.
+
FIGURE 40. PREVENTING OSCILLATIONS IN UNUSED CHANNELS
Power Dissipation
It is possible to exceed the +150°C maximum junction
temperatures under certain load and power supply conditions. It
is therefore important to calculate the maximum junction
temperature (TJMAX) for all applications to determine if power
supply voltages, load conditions, or package type need to be
modified to remain in the safe operating area. These parameters
are related using Equation 1:
T JMAX = T MAX +  JA xPD MAXTOTAL
(EQ. 1)
In applications where one or both amplifier input terminals are at
risk of exposure to high voltage, current limiting resistors may be
Submit Document Feedback
19
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Where:
LICENSE STATEMENT
• PDMAXTOTAL is the sum of the maximum power dissipation of
each amplifier in the package (PDMAX)
The information in this SPICE model is protected under the
United States copyright laws. Intersil Corporation hereby grants
users of this macro-model hereto referred to as “Licensee”, a
nonexclusive, nontransferable license to use this model as long
as the Licensee abides by the terms of this agreement. Before
using this macro-model, the Licensee should read this license. If
the Licensee does not accept these terms, permission to use the
model is not granted.
• PDMAX for each amplifier can be calculated using Equation 2:
V OUTMAX
PD MAX = V S  I qMAX +  V S - V OUTMAX   ---------------------------R
L
(EQ. 2)
Where:
• TMAX = Maximum ambient temperature
• JA = Thermal resistance of the package
• PDMAX = Maximum power dissipation of 1 amplifier
• VS = Total supply voltage
• IqMAX = Maximum quiescent supply current of 1 amplifier
• VOUTMAX = Maximum output voltage swing of the application
• RL = Load resistance
ISL28127, ISL28227 SPICE Model
Figure 41 shows the SPICE model schematic and Figure 42 shows
the net list for the ISL28127, ISL28227 SPICE model. The model is
a simplified version of the actual device and simulates important
AC and DC parameters. AC parameters incorporated into the
model are: 1/f and flatband noise, slew rate, CMRR, gain and
phase. The DC parameters are VOS, IOS, total supply current and
output voltage swing. The model does not model input bias
current. The model uses typical parameters given in the “Electrical
Specifications” Table beginning on page 6. The AVOL is adjusted for
128dB with the dominant pole at 5Hz. The CMRR is set higher
than the “Electrical Specifications” table beginning on page 6 to
better match design simulations (150dB, f = 50Hz). The input
stage models the actual device to present an accurate AC
representation. The model is configured for +25°C ambient
temperature. The Spice model for the ISL28227SEH can be
found here “ISL70227SEH SPICE MODEL”.
The Licensee may not sell, loan, rent, or license the
macro-model, in whole, in part, or in modified form, to anyone
outside the Licensee’s company. The Licensee may modify the
macro-model to suit his/her specific applications and the
Licensee may make copies of this macro-model for use within
their company only.
This macro-model is provided “AS IS, WHERE IS AND WITH NO
WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED,
INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.”
In no event will Intersil be liable for special, collateral, incidental, or
consequential damages in connection with or arising out of the use
of this macro-model. Intersil reserves the right to make changes to
the product and the macro-model without prior notice.
Figures 43 through 58 show the characterization vs simulation
results for the noise voltage, closed loop gain vs frequency,
closed loop gain vs Rf/Rg, closed loop gain vs RL, closed loop
gain vs CL, large signal 10V step response, open loop gain phase
and simulated CMRR vs frequency.
Submit Document Feedback
20
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
.
V++
V++
R3
R4
4.45k
4.45k
CASCODE
4
5
Q4
-
+
0.1V
SUPERB
DX
8
7
MIRROR
VCM
-
+
5E11
+
-
En
+ VOS
-
In+
VIN+
Vmid
-
9
IEE
200E-6
R2
Vc
+
+
-
Q3
1E-9
377.4
C5
2.5pF
EOS
1
IOS
R17
25
D1
5E11
C6
2pF
5
3
R1
24
DN
2
4
6
Q1 Q2
V5
D12
CASCODE
Q5
C4
2.5pF SUPERB
VIN-
VIN-
IEE1
96E-6
10E-6
V-VCM
Voltage Noise
Input Stage
V++
V++
4
10
+
-
5
G3
13
+
R5
1
-
D4
DX
+
V3
- 1.86V
11
G5
R7
572.9E6
Vg
+
V2
1.86V
+
-
12
14
D3
DX
+
V--
R8
G4
1ST Gain Stage
-
Vc
572.9E6
V4
1.86V
R10
1
C3
55.55pF
3.18E-3
R11
1
Vg
R12
1
G6
18
-
+
VCM
R6
1
G2
17
-
Vmid
Vc
Vmid
+
R9
1
C2
55.55pF
L1
VCM
D5
DX
L2
+
D2
DX
+
V1
- 1.86V
G1
3.18E-3
V--
2nd Gain Stage
Mid Supply Ref
Common-Mode Gain Stage
V++
D8
DX
+
-
-
E2
Vg
D6
DX
23
20
V5
+
1.12V
V-
V6
21
+
DX
-
D7
1.12V
G8
-
E3
+
V-
V--
D10
DY
+
+
-
G9
D11
DY
VOUT
VOUT
R16
90
-
+
R15
90
-
22
ISY
2.2mA
G7
+
+
D9
DX
-
V+
+
V+
G10
Output Stage
Supply Isolation Stage
FIGURE 41. SPICE SCHEMATIC
Submit Document Feedback
21
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
* source ISL28127_SPICEmodel
* Revision C, August 8th 2009 LaFontaine
* Model for Noise, supply currents, 150dB f=50Hz
CMRR, *128dB f=5Hz AOL
*Copyright 2009 by Intersil Corporation
*Refer to data sheet “LICENSE STATEMENT” Use of
*this model indicates your acceptance with the
*terms and provisions in the License Statement.
* Connections: +input
*
|
-input
*
|
|
+Vsupply
*
|
|
|
-Vsupply
*
|
|
|
|
output
*
|
|
|
|
|
.subckt ISL28127subckt Vin+ Vin-V+ V- VOUT
* source ISL28127_SPICEMODEL_0_0
*
*Voltage Noise
E_En
IN+ VIN+ 25 0 1
R_R17
25 0 377.4 TC=0,0
D_D12
24 25 DN
V_V7
24 0 0.1
*
*Input Stage
I_IOS
IN+ VIN- DC 1e-9
C_C6
IN+ VIN- 2E-12
R_R1
VCM VIN- 5e11 TC=0,0
R_R2
IN+ VCM 5e11 TC=0,0
Q_Q1
2 VIN- 1 SuperB
Q_Q2
3 8 1 SuperB
Q_Q3
V-- 1 7 Mirror
Q_Q4
4 6 2 Cascode
Q_Q5
5 6 3 Cascode
R_R3
4 V++ 4.45e3 TC=0,0
R_R4
5 V++ 4.45e3 TC=0,0
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
D_D1
6 7 DX
I_IEE
1 V-- DC 200e-6
I_IEE1
V++ 6 DC 96e-6
V_VOS
9 IN+ 10e-6
E_EOS
8 9 VC VMID 1
*
*1st Gain Stage
G_G1
V++ 11 4 5 0.0487707
G_G2
V-- 11 4 5 0.0487707
R_R5
11 V++ 1 TC=0,0
R_R6
V-- 11 1 TC=0,0
D_D2
10 V++ DX
D_D3
V-- 12 DX
V_V1
10 11 1.86
V_V2
11 12 1.86
*
*2nd Gain Stage
G_G3
V++ VG 11 VMID 4.60767E-3
G_G4
V-- VG 11 VMID 4.60767E-3
R_R7
VG V++ 572.958E6 TC=0,0
R_R8
V-- VG 572.958E6 TC=0,0
C_C2
VG V++ 55.55e-12 TC=0,0
C_C3
V-- VG 55.55e-12 TC=0,0
D_D4
13 V++ DX
D_D5
V-- 14 DX
V_V3
13 VG 1.86
V_V4
VG 14 1.86
*
*Mid supply Ref
R_R9
VMID V++ 1 TC=0,0
R_R10
V-- VMID 1 TC=0,0
I_ISY
V+ V- DC 2.2E-3
E_E2
V++ 0 V+ 0 1
E_E3
V-- 0 V- 0 1
*
*Common Mode Gain Stage with Zero
G_G5
V++ VC VCM VMID 31.6228e-9
G_G6
V-- VC VCM VMID 31.6228e-9
R_R11
VC 17 1 TC=0,0
R_R12
18 VC 1 TC=0,0
L_L1
17 V++ 3.183e-3
L_L2
18 V-- 3.183e-3
*
*Output Stage with Correction Current Sources
G_G7
VOUT V++ V++ VG 1.11e-2
G_G8
V-- VOUT VG V-- 1.11e-2
G_G9
22 V-- VOUT VG 1.11e-2
G_G10
23 V-- VG VOUT 1.11e-2
D_D6
VG 20 DX
D_D7
21 VG DX
D_D8
V++ 22 DX
D_D9
V++ 23 DX
D_D10
V-- 22 DY
D_D11
V-- 23 DY
V_V5
20 VOUT 1.12
V_V6
VOUT 21 1.12
R_R15
VOUT V++ 9E1 TC=0,0
R_R16
V-- VOUT 9E1 TC=0,0
*
.model SuperB npn
+ is=184E-15 bf=30e3 va=15 ik=70E-3 rb=50
+ re=0.065 rc=35 cje=1.5E-12 cjc=2E-12
+ kf=0 af=0
.model Cascode npn
+ is=502E-18 bf=150 va=300 ik=17E-3 rb=140
+ re=0.011 rc=900 cje=0.2E-12 cjc=0.16E-12f
+ kf=0 af=0
.model Mirror pnp
+ is=4E-15 bf=150 va=50 ik=138E-3 rb=185
+ re=0.101 rc=180 cje=1.34E-12 cjc=0.44E-12
+ kf=0 af=0
.model DN D(KF=6.69e-9 AF=1)
.MODEL DX D(IS=1E-12 Rs=0.1)
.MODEL DY D(IS=1E-15 BV=50 Rs=1)
.ends ISL28127subckt
FIGURE 42. SPICE NET LIST
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22
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Characterization vs Simulation Results
100
INPUT NOISE VOLTAGE (nV/Hz)
INPUT NOISE VOLTAGE (nV/Hz)
100
VS = ±19V
AV = 1
10
1
0.1
1
10
100
1k
10k
10
V(INOISE)
1
0.1
100k
1
10
70
Rg = 100, Rf = 100k
20
Rg = 10k, Rf = 100k
10
Rg = OPEN, Rf = 0
1k
15
10k
100k
1M
FREQUENCY (Hz)
10M
13
30
20
11
9
Rf = Rg = 1k
7
5
10k
Rf = Rg = 100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 47. CHARACTERIZED CLOSED LOOP GAIN vs Rf/Rg
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AV = 10
Rg = 10k, Rf = 100k
23
AV = 1
Rg = OPEN, Rf = 0
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 46. SIMULATED CLOSED LOOP GAIN vs FREQUENCY
15
Rf = Rg = 10k
3 VS = ±15V
RL = 10k
1
CL = 3.5pF
-1 A = +2
V
-3 VOUT = 100mVP-P
Rg = 100, Rf = 100k
Rg = 1k, Rf = 100k
-10
100
100M
Rf = Rg = 100k
1k
40
0
FIGURE 45. CHARACTERIZED CLOSED LOOP GAIN vs FREQUENCY
NORMALIZED GAIN (dB)
100k
AV = 100
10
AV = 1
-10
100
-5
GAIN (dB)
VS = ±15V
CL = 3.5pF
RL = INF
VOUT = 100mVP-P
AV = 10
AV = 1000
50
NORMALIZED GAIN (dB)
GAIN (dB)
60
Rg = 1k, Rf = 100k
AV = 100
30
0
10k
70
AV = 1000
50
40
1k
FIGURE 44. SIMULATED INPUT NOISE VOLTAGE
FIGURE 43. CHARACTERIZED INPUT NOISE VOLTAGE
60
100
FREQUENCY (Hz)
FREQUENCY (Hz)
Rf = Rg = 100k
13
11
Rf = Rg = 10k
9
7
Rf = Rg = 1k
5
3 VS = ±15V
RL = 10k
1
CL = 3.5pF
-1 A = +2
V
-3 VOUT = 100mVP-P
-5
1k
10k
Rf = Rg = 100
100k
1M
10M
100M
FREQUENCY (Hz)
FIGURE 48. SIMULATED CLOSED LOOP GAIN vs Rf/Rg
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Characterization vs Simulation Results (Continued)
2
2
1
RL = 1k
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
RL = 10k
0
-1
RL = 499
-2
RL = 100
VS = ±15V
-3
RL = 49.9
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
-4
-5
1k
10k
100k
1M
FREQUENCY (Hz)
10M
1
4
3
-4
CL = 1000pF
CL = 220pF
0
-1
CL = 3.5pF
-2
-3
1k
10k
100k
1M
FREQUENCY (Hz)
5
4
10M
100M
CL = 1000pF
CL = 220pF
2
CL = 100pF
1
0
CL = 25.5pF
-1
-2
10M
-3
100M
CL = 3.5pF
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
FIGURE 52. SIMULATED CLOSED LOOP GAIN vs CL
6
6
5
5
4
4
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0, Rg = INF
3
2
1
0
LARGE SIGNAL (V)
LARGE SIGNAL (V)
100k
1M
FREQUENCY (Hz)
3
FIGURE 51. CHARACTERIZED CLOSED LOOP GAIN vs CL
VOUT = 10VP-P
1
-2
-3
RL = 2k
RL = 10k
-4
VS = ±15V
CL = 3.5pF
AV = 1
Rf = 0, Rg = INF
VOUT = 10VP-P
3
2
1
0
1
RL = 10k
-2
-3
-4
-5
-5
-6
10k
RL = 49.9
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
6
CL = 25.5pF
1
CL = 3.5pF
AV = +1
VOUT = 100mVP-P
7
CL = 100pF
2
RL = 100
VS = ±15V
-3
FIGURE 50. SIMULATED CLOSED LOOP GAIN vs RL
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
5
RL = 499
-2
-5
1k
100M
7
VS = ±15V
RL = 10k
AV = +1
VOUT = 100mVP-P
RL = 1k
-1
FIGURE 49. CHARACTERIZED CLOSED LOOP GAIN vs RL
6
RL = 10k
0
-6
0
5
10
15
TIME (µs)
20
25
FIGURE 53. CHARACTERIZED LARGE SIGNAL 10V STEP
RESPONSE
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24
30
0
5
10
15
TIME (µs)
20
25
30
FIGURE 54. SIMULATED LARGE SIGNAL 10V STEP RESPONSE
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
200
180
160
140
120
100
80
60
40
20
0
-20 R = 10k
L
-40
CL = 10pF
-60
SIMULATION
-80
-100
0.1m 1m 10m100m 1
200
OPEN LOOP GAIN (dB)/PHASE (°)
OPEN LOOP GAIN (dB)/PHASE (°)
Characterization vs Simulation Results (Continued)
PHASE
GAIN
10 100 1k 10k 100k 1M 10M100M
FREQUENCY (Hz)
130
120
110
100
90
80
70
60
50
40
30
20
10
0
-10
10
PHASE
100
50
GAIN
0
RL = 10k
-50 CL = 10pF
MODEL VOS SET TO ZERO
FOR THIS TEST
-100
0.1Hz
10Hz
1.0k
100k
10M
FREQUENCY (Hz)
FIGURE 56. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
150
VS = ±5V
VS = ±2.25V
100
CMRR (dB)
CMRR (dB)
FIGURE 55. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY
150
VS = ±15V
RL = INF
CL = 5.25pF
AV = +1
VCM = 1VP-P
100
50
0
1k
10k
100k
1M
FREQUENCY (Hz)
FIGURE 57. CHARACTERIZED CMRR vs FREQUENCY
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25
10M
GENERATED USING FULL
MODEL. CMRR DELTA INPUT
BASE VOLTAGE/VCM
INPUT VOLTAGE
-50
10m
1.0Hz
100Hz 10k
1.0M
100M
10G 1.0T
FREQUENCY (Hz)
FIGURE 58. SIMULATED CMRR vs FREQUENCY
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev.
REVISION
DATE
CHANGE
April 1, 2016
FN6633.8
-Added the ISL28227SEH throughout the datasheet.
-Updated ordering information on page 3 by changing in Pkg Dwg. # column L8.3x3A to L8.3x3K and M8.118 to
M8.118B.
-Updated Tjc Note 10 by removing words "the exposed metal pad on" from the sentence to cover both TDFN and
Flatpack packages.
-Added ISL70227HMEVAL1Z to ordering information table on page 3 and added hermetic package note.
- Absolute Maximum Ratings table on page 6 as follow:
Updated HBM for ISL28127 from 4.0kV to 4.5kV.
Added ESD Tolerance for ISL28227SEH.
-Updated Electrical Spec Table page 10: ISL28227SEH (±15V) for IOS and IB as follows:
Added ±25 Post Rad
Added ±25 Post Rad
Added TA = -55°C, +125°C
Added the rad level is implied by the tighter BOLD Temp Spec.
-Added ISL28227SEH values.
-Updated POD from: L8.3x3A to: L8.3x3k.
-Updated POD from: M8.118 to: M8.118B.
September 10, 2015
FN6633.7
-Updated About Intersil Verbiage.
-Updated POD L8.3X3A to most current version change is as follows:
From: Tiebar shown (if present) is a non-functional feature.
To: Tiebar shown (if present) is a non-functional feature and may be located on any of the 4 sides (or ends).
-Updated POD M8.118 to most current version change is as follows:
Corrected lead width dimension in side view 1 from "0.25 - 0.036" to "0.25 - 0.36"
December 13, 2010
FN6633.6
Page 3: The ISL28227 8 LD TDFN Pin configuration: Vout_A and Vout_B labels on pins 1 and 7 changed to VoutA
and VoutB
Figure 8: labeled red curve Vs = ±5V and blue curve Vs = ±15V.
-Converted to New Intersil Template
-Added AN1509 in Related Literature on page 1
-Removed Titles from Graphics on page 1 and replaced with Figure names
-Changed copyright to legal's suggested verbiage on page 1
-Updated Ordering Information table on page 2. Removed Coming Soon for ISL28127FRTBZ and ISL28127FUBZ
parts. Added in the Vos (MAX) numbers in those rows (75 and 70 respectively).
-Changed Tape and Reel Note in ordering information to "Add T*…" to include all Tape and Reel additions
-Updated Electrical Spec Table page 5 and page 6 for Vos and TCVos
oAdded data row for Offset Voltage; MSOP Grade B Package; ISL28127
oAdded data row for Offset Voltage; TDFN Grade B Package; ISL28127
oAdded data row for Offset Voltage Drift; MSOP Grade B Package; ISL28127
oAdded data row for Offset Voltage Drift; TDFN Grade B Package; ISL28127
oRemoved - Temperature data established by characterization from conditions (New standard note covers this
verbiage)
oChanged Note: "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified.
Temperature limits established by characterization and are not production tested". TO: Compliance to datasheet
limits is assured by one or more methods: production test, characterization and/or design.
-Updated Typical Performance Curves
oUpdated typical plot of Vos vs Temp for Figure 8.
oAdded: IB+ vs Temp vs Vsupply plot; IB- vs Temp vs Vsupply plot; Ios vs Temp vs Vsupply plot; Figures 9, 10, 11
Added: Vos distribution Vs=15V plot; Vos distribution Vs=5V plot; TCVos distribution Vs=15V plot; TCVos distribution
Vs=5V plot; TCIB+ distribution Vs=15V plot; TCIB+ distribution Vs=5V plot; TCIB- distribution Vs=15V plot; TCIBdistribution Vs=5V plot; TCIos distribution Vs=15V plot; TCIos distribution Vs=5V plot (Figures 13 thru 22)
September 10, 2010
FN6633.5
Submit Document Feedback
26
- Updated ordering information by removing Note 2, which referenced “-T13” tape and reel option and revised Note
1 to include ”-T7A” tape and reel option. Removed Note reference next to part numbers and placed under part
number in table head indicating that it references all parts. Change shows that all parts now have -T7, -T7A and T13 tape and reel options.
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev. (Continued)
REVISION
DATE
CHANGE
July 2, 2010
FN6633.4
In “Ordering Information” on page 2:
Removed “Coming Soon” from ISL28127FRTZ, ISL28227FRTBZ, ISL28227FRTZ, ISL28227FUBZ & ISL28227FUZ.
Updated the part marking for ISL28127FRTBZ from “127Z” to “8127”
Updated the part marking for ISL28127FRTZ from “-C 127Z” to “-C 8127”
Updated the part marking for ISL28227FRTBZ from “227Z” to “8227”
Updated the part marking for ISL28227FRTZ from “-C 227Z” to “-C 8227”
Added VOS of 75µV for ISL28227FRTBZ
Added VOS of 75µV for ISL28227FUBZ
Added Evaluation Boards ISL28127MSOPEVAL1Z and ISL28227SOICEVAL2Z
In Thermal Information table on page 5, for 8 Ld TDFN, corrected Theta JA note from Note 8 to Note 7.
In VS ±15V “Electrical Specifications” table on page 5, added VOS specs for ISL28227 MSOP, TDFN Grade B
Packages. Added TCVOS specs for ISL28227 MSOP, TDFN Grade B Packages
Changed TYP for “Offset Voltage; MSOP, TDFN Grade C Package” from 10µV to -10µV
In VS ±5V “Electrical Specifications” table on page 7 added VOS specs for SOIC ISL28227. Added VOS specs for
MSOP, TDFN Grade B and C Packages. Added TCVOS specs for SOIC ISL28227. Added TCVOS specs for MSOP, TDFN
Grade B and C Packages
March 11, 2010
FN6633.3
PODs M8.118 and L8.3x3A - Updated to new intersil format by adding land pattern and moving dimensions from
table onto drawing.
On page 2:
Under "Ordering Information”
ISL28227FBZ: Changed Vos max from 80µV to 75µV
On page 5:
Changed:
1. ISL28227 SOIC Room Temp limit for Vos from 80µV (MAX) and -80µV (MIN) to 75µV (MAX) and -75µV (MIN).
2. ISL28227 SOIC Full Temp limit for Vos from 160µV (MAX) and -160µV (MIN) to 150µV (MAX) and -150µV (MIN)
3. ISL28227 SOIC limit for TCVos from 0.8µV (MAX) and -0.8µV (MIN) to 0.75µV (MAX) and -0.75µV (MIN)
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27
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev. (Continued)
REVISION
March 11, 2010
(Continued)
DATE
CHANGE
FN6633.3 In “Absolute Maximum Ratings” on page 6, HBM for ISL28227 changed from “4kV” to “6kV”
(Continued) In “Thermal Information” on page 6, Tjc values for ISL28227 changed:
For MSOP from “50” to “45”
For SOIC from “60” to “55”
In the “Ordering Information” (page 2):
Part Number
Part Marking
ISL28127FRTBZ
ISL28127FRTZ
-C 127Z instead of 127Z C
ISL28127FUBZ
ISL28127FUZ
8127Z -C instead of 8127Z
Removed “Coming Soon) for ISL28127FUZ package
ISL28227FBZ
Removed “Coming Soon) for ISL28227FBZ package
ISL28227FRTBZ
ISL28227FRTZ
-C 227Z instead of 227Z C
ISL28227FUZ
8227Z -C instead of 8227Z
Added the following row of data
ISL28227FUBZ
8227Z
Vos (Max) (uV)
TBD instead of 70
TBD instead of 70
150 instead of 70
80 instead of 70
TBD instead of 70
150 instead of 70
TBD
In the “Electrical specifications” on page 6 and page 8 the following changes were made. The change applies to
the same spec found on page 4 and page 6.
VOS Offset Voltage; SOIC Package, ISL28127: Added -70 to MIN across room temp and -120 MIN across full temp
VOS Offset Voltage; SOIC Package, ISL28227: Added -80 to MIN across room temp and -160 MIN across full temp
VOS Offset Voltage; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -150 to MIN across room temp
and -250 MIN across full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28127: Added -0.5 to MIN across full temp
TCVOS Offset Voltage Drift; SOIC Package, ISL28227: Added -0.8 to MIN across full temp
TCVOS Offset Voltage Drift; MSOP and TDFN Package Grade C, ISL28127/ISL28227: Added -1 to MIN across full
temp
IOS Input Offset Current: Added -10 to MIN across room temp and -12 to MIN across full temp
IB Input Bias Current:Added -10 to MIN across room temp and -12 to MIN across full temp
In the “Ordering Information” (page 3), added differentiated part numbers for B-grade and C-grade for TDFN and
MSOP.
In “Absolute Maximum Ratings” on page 6, added ESD and latch-up information.
In “Thermal Information” on page 6, broke out Theta JA to list the single and dual and added Theta JC.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
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28
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you
have the latest Rev. (Continued)
REVISION
DATE
CHANGE
January 29, 2010
FN6633.2
Added license statement for P-Spice Model.
Updated Spice Schematic by adding capacitors
C4, C5 and C6
Updated Spice Net List as follows:
From:
Revision B, July 23 2009
To:
Revision C, August 8th 2009 LaFontaine
From:
source ISL28127_SPICEMODEL_7_9
To:
source ISL28127_SPICEMODEL_0_0
Added after I_IOS:
C_C6
IN+ VIN- 2E-12
Added after R_R4:
C_C4 VIN- 0 2.5e-12
C_C5 8 0 2.5e-12
From:
.ends ISL28127
To:
.ends ISL28127subckt
Replaced POD MDP0027 with M8.15E to match ASYD in Intrepid (no dimension changes; the PODs are the same.
The change was to update to the Intersil format, moving dimensions from table onto drawing and adding land
pattern)
September 14, 2009
FN6633.1
Functional Description on page 17. Corrected low 1/f noise corner frequency from 3Hz to 5Hz to match Figure 2
on page 1. Corrected high open loop gain from 1400V/mV to 1500V/mV to match “Open-Loop Gain on page 6
spec table.
Operating Voltage Range on page 17. Removed following 2 sentences since there are no graphs illustrating
common mode voltage sensitivity vs temperature or VOS as a function of supply voltage and temperature:
“The input common mode voltage sensitivity to temperature is shown in Figure 3 (±15V). Figure 20 shows VOS as
a function of supply voltage and temperature with the common mode voltage at 0V for split supply operation.”
Added Theta JC in Thermal Information on page 5 for TDFN package.
Updated Features to show only key features and updated applications section. Added Typical Application Circuit
and performance graph, Updated Ordering Information to match Intrepid and added POD's L8.3x3A and M8.118,
also added MSL level as part of new format. Added TDFN pinouts, updated pin descriptions to include TDFN
pinouts, Added Theta Ja in Thermal information for TDFN and MSOP packages. Added Revision History and
Products Text with device info links. Added SPICE Model with referencing text and Net List.
May 28, 2009
FN6633.0
Techdocs Issued File Number FN6633. Initial release of Datasheet with file number FN6633 making this a Rev 0.
About Intersil
Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products
address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets.
For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
information page found at www.intersil.com.
You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask.
Reliability reports are also available from our website at www.intersil.com/support.
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29
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Package Outline Drawing
M8.15E
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 0, 08/09
4
4.90 ± 0.10
A
DETAIL "A"
0.22 ± 0.03
B
6.0 ± 0.20
3.90 ± 0.10
4
PIN NO.1
ID MARK
5
(0.35) x 45°
4° ± 4°
0.43 ± 0.076
1.27
0.25 M C A B
SIDE VIEW “B”
TOP VIEW
1.75 MAX
1.45 ± 0.1
0.25
GAUGE PLANE
C
SEATING PLANE
0.10 C
0.175 ± 0.075
SIDE VIEW “A
0.63 ±0.23
DETAIL "A"
(0.60)
(1.27)
NOTES:
(1.50)
(5.40)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension does not include interlead flash or protrusions.
Interlead flash or protrusions shall not exceed 0.25mm per side.
5.
The pin #1 identifier may be either a mold or mark feature.
6.
Reference to JEDEC MS-012.
TYPICAL RECOMMENDED LAND PATTERN
Submit Document Feedback
30
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Package Outline Drawing
L8.3x3K
8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
Rev 2, 5/15
2X 1.95
3.00
6X 0.65
A
B
1
PIN #1
INDEX AREA
3.00
6
6
PIN 1
INDEX AREA
(4X)
1.50 ±0.10
0.15
8
TOP VIEW
8X 0.25 ±0.05
0.40 ± 0.05
4
0.10 M C A B
2.30 ±0.10
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
0.75 ±0.05
0 . 203 REF
5
C
0 . 02 NOM.
0 . 05 MAX.
0.08 C
SIDE VIEW
DETAIL "X"
( 2.30)
( 1.95)
NOTES:
( 8X 0.50)
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2.
Dimensioning and tolerancing conform to ASME Y14.5m-1994.
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
(1.50)
( 2.90 )
between 0.15mm and 0.20mm from the terminal tip.
PIN 1
5.
Tiebar shown (if present) is a non-functional feature and may be
located on any of the 4 sides (or ends).
6.
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
(6x 0.65)
( 8 X 0.25)
either a mold or mark feature.
TYPICAL RECOMMENDED LAND PATTERN
7.
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31
Compliant to JEDEC MO-229 WEEC-2 except for the foot length.
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Package Outline Drawing
M8.118B
8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE
Rev 1, 3/12
3.0±0.10mm
5
A
D
8
4.9±0.20mm
DETAIL "X"
3.0±0.10mm
5
1.10 MAX
0.15±0.05mm
PIN# 1 ID
SIDE VIEW 2
1
2
B
0.65mm BSC
TOP VIEW
0.95 REF
0.86±0.05mm
H
GAUGE
PLANE
C
0.25
SEATING PLANE
0.23 - 0.36mm
0.08 M C A-B D
0.10 ± 0.05mm
3°±3°
0.10 C
0.53 ± 0.10mm
SIDE VIEW 1
DETAIL "X"
(5.80)
NOTES:
(4.40)
(3.00)
1. Dimensions are in millimeters.
(0.65)
(0.40)
(1.40)
TYPICAL RECOMMENDED LAND PATTERN
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32
2. Dimensioning and tolerancing conform to JEDEC MO-187-AA
and AMSEY14.5m-1994.
3. Plastic or metal protrusions of 0.15mm max per side are not
included.
4. Plastic interlead protrusions of 0.15mm max per side are not
included.
5. Dimensions are measured at Datum Plane "H".
6. Dimensions in ( ) are for reference only.
FN6633.8
April 1, 2016
ISL28127, ISL28227, ISL28227SEH
Ceramic Metal Seal Flatpack Packages (Flatpack)
K10.A
e
MIL-STD-1835 CDFP3-F10 (F-4A, CONFIGURATION B)
10 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
A
A
-APIN NO. 1
ID AREA
b
E1
0.004 M
H A-B S
Q
D S
S1
0.036 M
H A-B S
D S
C
E
-D-
A
-C-
-HL
E2
E3
SEATING AND
BASE PLANE
c1
L
E3
LEAD FINISH
BASE
METAL
INCHES
D
-B-
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.045
0.115
1.14
2.92
-
b
0.015
0.022
0.38
0.56
-
b1
0.015
0.019
0.38
0.48
-
c
0.004
0.009
0.10
0.23
-
c1
0.004
0.006
0.10
0.15
-
D
-
0.290
-
7.37
3
E
0.240
0.260
6.10
6.60
-
E1
-
0.280
-
7.11
3
E2
0.125
-
3.18
-
-
E3
0.030
-
0.76
-
7
e
(c)
MILLIMETERS
0.050 BSC
1.27 BSC
-
k
0.008
0.015
0.20
0.38
2
L
0.250
0.370
6.35
9.40
-
Q
0.026
0.045
0.66
1.14
8
S1
0.005
-
0.13
-
6
(b)
M
-
0.0015
-
SECTION A-A
N
b1
M
M
NOTES:
10
0.04
10
Rev. 0 3/07
1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded
area shown. The manufacturer’s identification shall not be used
as a pin one identification mark. Alternately, a tab (dimension k)
may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply.
3. This dimension allows for off-center lid, meniscus, and glass
overrun.
4. Dimensions b1 and c1 apply to lead base metal only. Dimension
M applies to lead plating and finish thickness. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate
lead finish is applied.
5. N is the maximum number of terminal positions.
6. Measure dimension S1 at all four corners.
7. For bottom-brazed lead packages, no organic or polymeric materials shall be molded to the bottom of the package to cover the
leads.
8. Dimension Q shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension Q minimum
shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied.
9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
10. Controlling dimension: INCH.
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33
FN6633.8
April 1, 2016