HI-7153 S IG N DES W NE r at FO R D ente c E C D 0 t 1 N ME e HI58 uppor .com/ts C OM Se nicl S tersil E R h T e c w w w .in NOT r ou r t o c S IL ont a or c 8-INTER 1-88 ® December 1997 8-Channel, 10-Bit High Speed Sampling A/D Converter Features Description • 5µs Conversion Time The HI-7153 is an 8 channel high speed 10 bit A/D converter which uses a Two Step Flash algorithm to achieve through-put rates of 200kHz. The converter features an 8 channel CMOS analog multiplexer with random channel addressing. A unique switched capacitor technique allows a new input voltage to be sampled while a conversion is taking place. • 8 Channel Input Multiplexer • 200,000 Channels/Second Throughput Rate • Over 9 Effective Bits at 20kHz • No Offset or Gain Adjustments Necessary • Analog and Reference Inputs Fully Buffered Internal high speed CMOS buffers at both the analog and reference inputs simplifies interface requirements. • On-Chip Track and Hold Amplifier • µP Compatible Interface A Track and Hold amplifier is included on the chip, consisting of two high speed amplifiers and an internal hold capacitor, reducing external circuitry. • 2’s Complement Data Output • 150mW Power Consumption • Only a Single 2.5V Reference Required for a ±2.5V Input Range • Out-of-Range Flag • /883 Version Available Microprocessor bus interfacing is simplified by the use of standard Chip Select, Read, and Write control signals. The digital three-state outputs are byte organized for bus interface to 8 or 16 bit systems. An Out-of-Range pin, together with the MSB bit, can be used to indicate an under or over-range condition. The HI-7153 operates with ±5V supplies. Only a single +2.5V reference is required to provide a bipolar input range from -2.5V to +2.5V. Applications • µP Controlled Data Acquisition Systems • DSP - Avionics - Sonar Ordering Information • Process Control - Automotive Transducer Sensing - Industrial • Robotics • Digital Communications VREF (ANALOG GND) AIN0 AIN1 REF AMP REF INVERT AG INPUT BUFFER AMP AIN2 AIN3 + - LINEARITY (MAX ILE) TEMPERATURE RANGE HI3-7153J-5 ±1.0 LSB 0oC to +70oC 40 Lead Plastic DIP HI3-7153A-9 ±1.0 LSB -40oC to +85oC 40 Lead Plastic DIP HI1-7153S-2 ±1.0 LSB -55oC to +125oC 40 Lead Ceramic DIP PACKAGE DO 33 RESISTOR LADDER Functional Diagram PART NUMBER TWO STEP FLASH LATCHES AND OUTPUT BUFFERS 1 BUS CTRL DATA OUTPUTS D9 OVR BUS HBE AIN4 AIN5 AIN6 HOLD MUX AIN7 TRACK HOLD AMP RD CONTROL LOGIC A0 A1 A2 ALE TEST V+ VGND (DIGITAL GND) POWER SUPPLY DISTRIBUTION DG CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 WR CS SMODE CLK EOC File Number 2787.4 HI-7153 Pinouts HI-7153 (CDIP, PDIP) TOP VIEW VREF 1 40 V- AG 2 39 GND AIN0 3 38 V+ AIN1 4 37 OVR AIN2 5 36 D9 (MSB) AIN3 6 35 D8 AIN4 7 34 D7 AIN5 8 33 D6 AIN6 9 32 D5 AIN7 10 31 D4 NC 11 30 D3 TEST 12 29 D2 A0 13 28 D1 A1 14 27 D0 (LSB) A2 15 26 HOLD 25 EOC ALE 16 WR 17 24 DG CS 18 23 CLK RD 19 22 HBE SMODE 20 21 BUS 2 HI-7153 Absolute Maximum Ratings Thermal Information Supply Voltage V+ to GND (DG/AG/GND) . . . . . . . . . . . . . . . -0.3V < V+ < +5.7V V- to GND (DG/AG/GND) . . . . . . . . . . . . . . . . .-5.7V < V- < +0.3V Analog InputPins (Note 1) (A IN0 - AIN7, VREF) . . . . . . . . . . . . . . . V- -0.3V < VINA < V+ +0.3V Digital I/O Pins (Note 1) . . . . . . . . . . . . . DG -0.3V <VI/O < V+ +0.3V (D0 - D9, OVR, CLK, CS, RD, WR, ALE, SMODE, HOLD, EOC, HBE, BUS, A0 - A2, TEST) Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC Thermal Resistance θJA Plastic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50oC/W Operating Temperature Range HI3-7153X-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC HI3-7153X-9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC HI1-7153X-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC Power Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . 500mW Derate above +70oC at 10mW/oC NOTES: 1. Input voltages may exceed the supply voltage, on input or channel at a time, provided the input current is limited to ±10mA 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = t F ≤ 25ns, 50% Duty Cycle. All Typical Values have been Characterized but are Not Tested. (NOTE 4) PARAMETER (NOTE 3) J, A, S GRADE SYMBOL TEMPERATURE MIN TYP MAX UNITS TA = +25oC 10 - - Bits TMIN ≤ TA ≤ TMAX 10 - - Bits +25oC - ±0.5 ±1.0 LSB TMIN ≤ TA ≤ TMAX - ±0.75 ±1.0 LSB +25oC - ±0.5 ±1.0 LSB TMIN ≤ TA ≤ TMAX - ±0.75 ±1.0 LSB TA = +25 C - ±1.0 ±2.5 LSB TMIN ≤ TA ≤ TMAX - ±1.5 ±3.0 LSB +25oC - ±1.0 ±2.5 LSB TMIN ≤ TA ≤ TMAX - ±1.5 ±3.0 LSB +25oC - ±0.002 - LSB TMIN ≤ TA ≤ TMAX - ±0.002 - LSB ACCURACY Resolution (Note 5) Integral Linearity Error Differential Linearity Error Bipolar Offset Error Unadjusted Gain Error Channel to Channel Mismatch RES ILE DLE VOS FSE TA = TA = o TA = TA = NOTES: 1. Input voltages may exceed the supply voltage, one input or channel at a time, provided the input current is limited to 10mA. 2. Dissipation rating assumes device is mounted with all leads soldered to printed circuit board. 3. See Ordering Information Table. 4. FSR (Full Scale Range) = 2 x VREF (5.00V at VREF = 2.50V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.50V). 5. Parameter Not tested. Parameter guaranteed by design, simulation, or characterization. 6. TMIN and TMAX limits guaranteed by +25oC test. 3 HI-7153 Electrical Specifications o TA = +25 C, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, tR = tF ≤ 25ns, 50% Duty Cycle. All Typical Values have been Characterized but are Not Tested. +25oC (NOTE 1) PARAMETER TYP UNITS fIN = 4.932kHz, ±2.5V 59 dB fIN = 14.697kHz, ±2.5V 59 dB fIN = 24.462kHz, ±2.5V 58 dB fIN = 43.994kHz, ±2.5V 56 dB fIN = 4.932kHz, ±2.5V 59 dB fIN = 14.697kHz, ±2.5V 58 dB fIN = 24.462kHz, ±2.5V 55 dB fIN = 43.994kHz, ±2.5V 48 dB fIN = 4.932kHz, ±2.5V -66 dBc fIN = 14.697kHz, ±2.5V -61 dBc fIN = 24.462kHz, ±2.5V -56 dBc fIN = 43.994kHz, ±2.5V -48 dBc fIN = 4.932kHz, ±2.5V -76 dB fIN = 14.697kHz, ±2.5V -77 dB fIN = 24.462kHz, ±2.5V -77 dB fIN = 43.994kHz, ±2.5V -74 dB SYMBOL CONDITIONS DYNAMIC CHARACTERISTICS Signal to Noise Ratio SNR Signal to Noise + Distortion SINAD Total Harmonic Distortion THD Spurious-Free Dynamic Range SFDR NOTE: 1. FSR (Full Scale Range) = 2 x VREF (5.00V at VREF = 2.50V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.50V) DC Electrical Specifications TA = +25oC, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = tF ≤ 25ns, 50% Duty Cycle, Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. (NOTE 1) PARAMETER +25oC SYMBOL CONDITIONS 0oC to +75oC -40oC to +85oC -55oC to +125o C MIN TYP MAX MIN MAX MIN MAX MIN MAX UNIT ANALOG MULTIPLEXER INPUT Input Range VIR -VREF - +VREF -VREF +VREF -VREF +VREF -VREF +VREF V Input Resistance RIN - 10 - - - - - - - MΩ Input Leakage Current IBI AIN = 0V - 0.01 100 - 100 - 100 - 100 nA On Channel Input Capacitance CA IN(ON) AIN = 0V, Note 2 - 10 30 - 30 - 30 - 30 pF Off Channel Input Capacitance CAIN(OFF) AIN = 0V, Note 2 - 8 20 - 20 - 20 - 20 pF RDS(ON) AIN = ±2.5V, IIN =100µA - 1.1 2.5 - 2.5 - 2.5 - 2.5 KΩ ∆RDS(ON) -2.5V ≤ AIN ≤ +2.5V - 2.5 - - - - - - - % MUX On-Resistance Greatest Change in RDS(ON) Between Any Two Channels 4 HI-7153 DC Electrical Specifications TA = +25oC, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = tF ≤ 25ns, 50% Duty Cycle, Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. (NOTE 1) PARAMETER +25oC SYMBOL CONDITIONS 0oC to +75oC -40oC to +85oC (Con- -55oC to +125o C MIN TYP MAX MIN MAX MIN MAX MIN MAX UNIT Off-Channel Isolation OIRR FIN =100kHz, Note 4 - -96 - - - - - - - dB Channel to Channel Isolation CCRR FIN =100kHz, Note 4 - -83 - - - - - - - dB 2.2 - 2.6 2.2 2.6 2.2 2.6 2.2 2.6 V REFERENCE INPUT Reference Input Range VRR Note 3 Reference Input Bias Current IBR VREF = +2.50V - 0.01 100 - 100 - 100 - 100 nA Reference Input Capacitance CVR Note 2 - 8 20 - - - - - - pF LOGIC INPUTS Input High Voltage V IH 2.4 - - 2.4 - 2.4 - 2.4 - V Input Low Voltage VIL - - 0.8 - 0.8 - 0.8 - 0.8 V Logic Input Current IIL VIN = 0V, +5V - 0.05 1 - 1 - 1 - 1 µA Input Capacitance CIN Note 2 - 7 17 - - - - - - pF Output High Voltage VOH IOH = -200µA 2.4 - - 2.4 - 2.4 - 2.4 - V Output Low Voltage VOL IOL = 1.6mA - - 0.4 - 0.4 - 0.4 - 0.4 V Output Leakage Current IOL RD = +5V, VOUT = +5V - 0.04 1 - 10 - 10 - 10 µA RD = +5V, VOUT = 0V -1 -0.01 - -10 - -10 - -10 - µA High-Z State, Note 2 - 7 15 - - - - - - pF 4.5 5.0 5.5 4.5 5.5 4.5 5.5 4.5 5.5 V -4.5 -5.0 -5.5 -4.5 -5.5 -4.5 -5.5 -4.5 -5.5 V V+ = 5V, V- = -4.75V, -5.25V - 0.1 0.5 - 0.6 - 0.6 - 0.8 LSB V- = -5V, V+ = 4.75V, 5.25V - 0.1 0.5 - 0.6 - 0.6 - 0.8 LSB V+ = 5V, V- = -4.75V, -5.25V - 0.15 0.5 - 0.6 - 0.6 - 0.8 LSB V- = -5V, V+ = 4.75V, 5.25V - 0.15 0.5 - 0.6 - 0.6 - 0.8 LSB LOGIC OUTPUTS Output Capacitance COUT POWER SUPPLY VOLTAGE RANGE V+ V- Functional Operation Only, Note 3 POWER SUPPLY REJECTION V+, V- Gain Error V+, V- Offset Error ∆FSE ∆VOS 5 HI-7153 DC Electrical Specifications TA = +25oC, V+ = +5V, V- = -5V, VREF = +2.50V, fCLK = 600kHz, t R = tF ≤ 25ns, 50% Duty Cycle, Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. (NOTE 1) PARAMETER +25oC SYMBOL 0oC to +75oC -40oC to +85oC (Con- -55oC to +125o C CONDITIONS MIN TYP MAX MIN MAX MIN MAX MIN MAX UNIT V+ = 5V, V- = -5V, VIN = 0V, Digital Outputs Are Unloaded - 20 30 - 30 - 30 - 30 mA - -10 -15 - -15 - -15 - -15 mA - -8 - - - - - - - mA - -2 - - - - - - - mA - 0.02 - - - - - - - µA SUPPLY CURRENTS V+ Supply Current I+ V- Supply Current I- GND Current IGND DG Current IDG AG Current IAG NOTES: 1. FSR (Full Scale Range) = 2 x VREF (5.00V at VREF = 2.50V). LSB (Least Significant Bit) = FSR/1024 (4.88mV at VREF = 2.50V) 2. Parameter Not tested. Parameter guaranteed by design, simulation, or characterization 3. Functionality is guaranteed by negative GAIN ERROR test. 4. Channel Isolation is tested with an input signal of ±2.5Vp-p, 100kHz and the measured pin is loaded with 100Ω to GND DC Electrical Specifications TA = +25oC, V+ = 5V ±10%, V- = -5V, VREF = 2.50V, fCLK = 600kHz, tR = t F ≤ 25ns, 50% Duty Cycle, CL = 100pF (Including Stray for D0-D9, OVR, HOLD), Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. (NOTE 4) PARAMETER +25oC SYMBOL CONDITIONS 0oC to +75oC -40o C to +85oC -55oC to +125oC MIN TYP MAX MIN MAX MIN MAX MIN MAX UNIT Note 2 - - 5 - 5 - 5 - 5 µs Note 9 60 - - 60 - 60 - 60 - µs Notes 2, 8 - - 3tCLK - 3tCLK - 3tCLK - 3tCLK µs Notes 1, 9 - - 4tCLK + 0.63 - 4tCLK + 0.75 - 4tCLK + 0.75 - 4tCLK + 0.8 µs Note 2 - - tCLK/3 - tCLK/3 - tCLK/3 - tCLK/3 CPS - 1/fCLK - - - - - - - - TIMING CHARACTERISTICS Continuous Conversion Time Conversion Time, First Conversion tSPS tCONV Continuous Throughput tCYC Clock Period tCLK Clock Input Duty Cycle D Note 9 45 50 55 45 55 45 55 45 55 % ALE Pulse Width tALEW Note 9 30 15 - 40 - 40 - 50 - ns Address Setup Time tAS Note 9 40 15 - 80 - 80 - 80 - ns Address Hold Time tAH 0 -16 - 0 - 0 - 0 - ns 100 20 tCLK/2 100 tCLK/2 100 tCLK/2 100 tCLK/2 ns WR Pulse Width tWRL WR to EOC Low tWREOC Notes 1, 9 - 80 130 - 160 - 160 - 160 ns WR to HOLD Delay tHOLD Notes 1, 9 - 80 150 - 170 - 170 - 170 ns Clock to HOLD Rise Delay tCKHR Note 9 150 265 450 140 500 120 500 120 500 ns Clock to HOLD Fall Delay tCKHF Notes 2, 9 50 95 200 40 225 40 225 40 225 ns Notes 1, 3, 9 6 HI-7153 DC Electrical Specifications TA = +25oC, V+ = 5V ±10%, V- = -5V, VREF = 2.50V, fCLK = 600kHz, tR = t F ≤ 25ns, 50% Duty Cycle, CL = 100pF (Including Stray for D0-D9, OVR, HOLD), Unless Otherwise Specified. All Typical Values have been Characterized but are Not Tested. (NOTE 4) PARAMETER Clock to EOC High HOLD to DATA Change +25oC SYMBOL CONDITIONS 0oC to +75oC (Continued) -40o C to +85oC -55oC to +125oC MIN TYP MAX MIN MAX MIN MAX MIN MAX UNIT tCKEOC Notes 1, 9 - 460 630 - 750 - 750 - 800 ns tDATA Notes 2, 9 100 200 350 90 400 90 400 90 400 ns CS to DATA tCD Note 9 - 40 70 - 85 - 85 - 85 ns HBE to DATA tAD Note 9 - 30 50 - 70 - 70 - 70 ns RD LOW to Active tRD Notes 6, 9 - 70 100 - 125 - 125 - 125 ns RD HIGH to Inactive tRX Notes 7, 9 - 30 60 - 70 - 70 - 70 ns Output Rise Time tR Notes 5, 9 - 20 40 - 60 - 60 - 60 ns Output Fall Time tF Notes 5, 9 - 15 30 - 50 - 50 - 50 ns NOTES: 1. Slow memory mode timing 2. Fast memory or DMA mode of operation, except the first conversion which is equal to tCONV 3. Maximum specification to prevent multiple triggering with WR 4. All input drive signals are specified with tR = tF ≤ 10ns and shall swing from 0.4V to 2.4V for all timing specifications. A signal is considered to change state as it crosses a 1.4V threshold (except tRD and tRX) 5. tR and tF load is CL = 100pF (including stray capacitance) to DG and is measured from the 10% - 90% point 6. tRD is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. High-Z to VOH is measured with R L = 2.5KΩ and CL = 100pF (including stray) to DG. High-Z to VOL is measured with R L = 2.5KΩ to V+ and CL = 100pF (including stray) to DG 7. tRX is the time required for the data output level to change by 10% in response to RD crossing a voltage level of 1.4V. VOH to High-Z is measured with RL = 2.5KΩ and CL = 10pF (including stray) to DG. VOL to High-Z is measured with RL = 2.5KΩ to V+ and CL = 10pF (including stray) to DG 8. For clock frequencies other than 600kHz 9. Parameter Not Tested. Parameter guaranteed by design, simulation, or characterization 7 HI-7153 Timing Diagrams FAST MEMORY MODE (8 BIT DATA BUS) 0 1 2 3 CLOCK tCD CS HOLD tSPS (WR MAY BE WIRED LOW) WR TRACK N tHOLD HOLD N tCKHF tCKHR HOLD N+1 TRACK N+1 TRACK N+2 HOLD N+2 TRACK N+3 tALEW ALE tAH tAS A0 - A2 N+3 ADDRESS tDATA INTERNAL DATA N-1 DATA N DATA N+1 DATA RD tRD HBE tAD tRX D0 - D9, OVR DATA HIGH BYTE N DATA LOW BYTE HIGH BYTE N+1 DATA LOW BYTE CONDITIONS: SMODE = DG. Bus = DG NOTE: With SMODE = DG, the internal logic diables the output latches from being updated during a read. The EOC output is LOW continuously. DMA MODE (16 BIT DATA BUS) CLOCK ALE A0 - A2 HOLD N+1 ADDRESS TRACK N HOLD N N+2 ADDRESS HOLD N+1 TRACK N+1 N+3 ADDRESS TRACK N+2 HOLD N+2 INTERNAL DATA N-1 DATA N DATA N+1 DATA D0 - D9, OVR DATA N-1 DATA N DATA N+1 DATA CONDITIONS: SMODE = V+, CS = WR = RD = DG, Bus = V+, HBE = DG or V+ NOTE: EOC output is low continuously 8 HI-7153 Timing Diagrams (Continued) SLOW MEMORY MODE (16 BIT DATA BUS) 0 1 2 tCK 3 CLOCK CS tWR WR tSLEW ALE tAS tAH AO - A2 N ADDRESS tHOLD HOLD TRACK N INTERNAL DATA N-1 DATA RD tCKHR HOLD N TRACK N+1 N DATA tWREOC tCKEOC EOC tRD D0 - D9, OVR DATA tRX N DATA tCONV CONDITIONS: SMODE = V+, Bus = V+, HBE = DG or V+ 9 HI-7153 Typical Dynamic Performance Characteristics EFFECTIVE NUMBER OF BITS SIGNAL-TO-NOISE RATIO 10 65 60 8 SNR (dB) EFFECTIVE BITS 9 7 50 6 5 55 0 10 20 30 40 50 60 45 70 0 10 20 FREQUENCY (kHz) TOTAL HARMONIC DISTORTION 40 50 60 70 50 60 70 PEAK NOISE -70 -80 -65 -75 -70 NOISE (dB) -60 -55 -50 -65 -60 -55 -50 -45 -40 -45 0 10 20 30 40 50 60 -40 70 0 10 20 FREQUENCY (kHz) 30 70 65 60 55 50 45 40 0 40 FREQUENCY (kHz) SPURIOUS-FREE DYNAMIC RANGE SFDR (dB) THD (dBc) 30 FREQUENCY (kHz) 10 20 30 40 FREQUENCY (kHz) 10 50 60 70 HI-7153 Typical Dynamic Performance Characteristics (Continued) FFT SPECTRUMS 0 -10 -20 -40 AMPLITUDE (dB) AMPLITUDE (dB) -30 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10 20 30 40 50 60 70 80 90 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 100 0 10 20 30 FREQUENCY (kHz) NOTES: 50 60 70 80 90 100 80 90 100 NOTES: INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 4931Hz 200kHz 59.40dB -67.26dB -75.98dB -68.36dB -77.19dB INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 0 0 -10 -10 -20 -20 -30 -30 -40 -40 AMPLITUDE (dB) AMPLITUDE (dB) 40 FREQUENCY (kHz) -50 -60 -70 -80 -90 -50 -60 -70 -80 -90 -100 -100 -110 -110 -120 -120 -130 14697Hz 200kHz 58.98dB -61.44dB -77.29dB -63.42dB -72.44dB -130 0 10 20 30 40 50 60 70 80 90 100 0 FREQUENCY (kHz) 20 30 40 50 60 70 FREQUENCY (kHz) NOTES: INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 10 NOTES: 24462Hz 200kHz 58.36dB -55.59dB -76.65dB -57.72dB -64.53dB INPUT FREQUENCY: SAMPLING RATE: SNR: THD: PEAK NOISE: SPURIOUS FREE DYNAMIC RANGE: 3RD HARMONIC: 11 4399Hz 200kHz 56.26dB -48.19dB -74.34dB -48.66dB -62.87dB HI-7153 Pin Description DIP PIN SYMBOL 1 VREF 2 AG Analog ground reference (0V) 3 AIN0 Analog input channel 0 4 AIN1 Analog input channel 1 5 AIN2 Analog input channel 2 6 AIN3 Analog input channel 3 7 AIN4 Analog input channel 4 8 AIN5 Analog input channel 5 9 AIN6 Analog input channel 6 10 AIN7 Analog input channel 7 11 NC No connect or tie to V+ only 12 TEST 13 A0 Mux address input. (LSB) Active high. 14 A1 Mux address input. (LSB) Active high. 15 A2 Mux address input. (MSB) Active high. 16 ALE DESCRIPTION Reference voltage input (+2.50V) Test pin. Connect to DG for normal operation Mux address enable. When high, the latch is transparent. Address data is latched on the falling edge. DIP PIN SYMBOL DESCRIPTION 21 BUS Bus select input. High = all outputs enabled together D0-D9, OVR Low = Outputs enabled by HBE 22 HBE Byte select (HBE/LBE) input for 8 bit bus. High = High byte select, D8 - D9, OVR Low = Low byte select, D0 - D7 23 CLK Clock input. TTL compatible. 24 DG Digital ground (0V) 25 EOC End-of-conversion status. Pulses high at the end-of-conversion. 26 HOLD Start of conversion status. Pulses low at the start-of-conversion. 27 D0 Bit 0 (LSB) 28 D1 Bit 1 29 D2 Bit 2 Output 30 D3 Bit 3 Data 31 D4 Bit 4 Bits 32 D5 Bit 5 33 D6 Bit 6 34 D7 Bit 7 35 D8 Bit 8 Bit 9 (MSB) 17 WR Write input. With CS low, starts conversion when pulsed low; continuous conversions when kept low. 36 D9 18 CS Chip select input. Active low. 37 OVR 19 RD Read input. With CS low, enables output buffers when pulsed low; outputs updated at the end of conversion. 38 V+ Positive supply voltage input (+5.0V) 39 GND Ground return for comparators (0V) 40 V- 20 SMODE Slow memory mode input. Active high. Out of Range flag. Valid at end of conversion when output exceeds full scale. Negative supply voltage input (-5.0V) Detailed Description Analog to Digital The HI-7153 is an 8 channel high speed 10 bit A/D converter which achieves throughput rates of 200kHz by use of a Two Step Flash algorithm. A pipelined operation has been achieved through the use of switched capacitor techniques which allows the device to sample a new input voltage while a conversion is taking place. The 8 channel multiplexer can be randomly addressed. The HI-7153 requires a single reference input of +2.5V, which is internally inverted to 2.5V, thereby allowing an input range of -2.5V to +2.5V. The ten bits are two’s complement coded. The analog and reference inputs are internally buffered by high speed CMOS buffers, which greatly simplifies the external analog drive requirements for the device. Section The HI-7153 uses a conversion technique which is generally called a ‘‘Two Step Flash’’ algorithm. This algorithm enables very fast conversion rates without the penalty of high power dissipation or high cost. A detailed functional diagram is presented in Figure 1. The reference input to the HI-7153 is buffered by a high speed CMOS amplifier which is used to drive one end of the resistor string. Another high speed amplifier configured in the inverting unity gain mode inverts the reference voltage with respect to analog ground and forces it onto the other end of the resistor string. Both reference amplifiers are offset trimmed during manufacturing in order to increase the accuracy of the HI-7153 and to simplify its usage. 12 HI-7153 The conversion takes place in three clock cycles and is illustrated in Figure 2. When the conversion begins, the track and hold goes into its hold mode for 1 clock cycle. During the first half clock cycle the comparator array is in its auto-zero mode and it samples the input voltage. During the second half clock cycle, the comparators make a comparison between the input voltage and the ladder voltages. At the beginning of the third half clock cycle, the first most significant 5 bit result becomes available. During the first clock cycle, the SCA was sampling the input voltage. After the first flash result becomes available and a ladder tap voltage has been selected the SCA amplifies the residue between the input and ladder tap voltages. During the next three half clock cycles, while the SCA output is settling to its required accuracy, the comparators go into their auto-zero mode and sample this voltage. During the sixth half clock cycle, the comparators perform another comparison whose 5 bit result becomes available on the next clock edge. The input voltage is first converted into a 5 bit result (plus Out of Range information) by the flash converter. This flash converter consists of an array of 33 auto-zeroed comparators which perform a comparison between the input voltage and subdivisions of the reference voltage. These subdivisions of the reference voltage are formed by forcing the reference voltage and its negative on the two ends of a string of 32 resistors. The 5 bit result of the first flash conversion is latched into the upper five bits of double buffered latches. It is also converted back into an analog signal by choosing the ladder voltage which is closest to but less than the input voltage. The selected voltage (VTAP) is then subtracted from the input voltage. The residual is then amplified by a factor of 32 and referenced to the negative reference voltage (VSCA = 32(VIN - VTAP) + VREF-). This subtraction and amplification operation is performed by a Switched Capacitor amplifier (SCA). The output of the SCA amplifier is between the positive and negative reference voltages and can therefore be digitized by the original 5 bit flash converter (second flash conversion). Reference Input The reference input to the HI-7153 is buffered by a high speed CMOS amplifier. The reference input range is 2.2V to 2.6V. The reference input voltage should be applied following the application of V+ and V- supplies. The 5 bit result of the second flash conversion is latched into the lower five bits of double buffered latches. At the end of a conversion, 10 bits of data plus an Out of Range bit are latched into the second level of latches and can then be put on the digital output pins. 5 TO 32 DECODER AZ + 33 REF (+) AMP AG AZ AZ R 32 LATCH AZ AIN0 AZ AIN1 AIN2 AIN4 2 AIN6 AZ 1 (-VREF ) LATCH SCAZ SCAZ BUS CTRL + TEST MUX DECODER ALE LATCHES A0 A1 A2 TRACK BUFFER AMP CH (AG) HOLD AMP BUS HBE SCAZ SCAZ + DATA OUTPUTS D0 HOLD C HOLD D9 AZ (AG) AIN7 LATCH AZ REF (-) AMP AIN5 AZ R + AIN3 OVR LATCH AZ 32 TO 5 ENCODER AND OVR LOGIC VREF AZ LATCHES AND OUTPUT BUFFER (+VREF) RD 32C + SCAZ (-VREF ) WR SWITCHED CAP. AMP POWER SUPPLY DISTRIBUTION CONTROL LOGIC CS SMODE CLK EOC V+ V- GND DG FIGURE 1. DETAILED BLOCK DIAGRAM 13 HI-7153 The timing signals for the Track and Hold amplifier are generated internally, and are also provided externally (HOLD) for synchronization purposes. Analog Multiplexer The multiplexer channel assignments are shown in Table 1 and can be randomly addressed. Address inputs A0 - A2 are binary coded and are TTL/CMOS compatible. During power up the circuit is initialized and multiplexer channel AIN0 is selected. The multiplexer address is transparent when ALE is high and CS is low. The address data is latched on the falling edge of the ALE signal. The multiplexer channel acquisition timing (Timing Diagrams, Slow Memory Mode) occurs approximately 500ns after the rising edge of HOLD. The multiplexer features a typical break-before-make switch action of 44ns. All of the internal amplifiers are offset trimmed during manufacturing to give improved accuracy and to minimize the number of external components. If necessary, offset error can be adjusted by using digital post correction. TABLE 1. MULTIPLEXER CHANNEL SELECTION ADDRESS AND CONTROL INPUTS Track And Hold A Track and Hold amplifier has been fully integrated on the front end of the A/D converter. Because of the sampling nature of this A/D converter, the input is required to stay constant only during the first clock cycle. Therefore, the Track and Hold (T/H) amplifier ‘‘holds’’ the input voltage only during the first clock cycle and it acquires the input voltage for the next conversion during the remaining two clock cycles. The high input impedance of the T/H input amplifier simplifies analog interfacing. Input signals up to ±VREF can be directly connected to the A/D without buffering. The T/H amplifier typically settles to within 1/4 LSB in 1.5µs. The A/D output code table is presented in Table 2. A2 A1 A0 CS ALE ANALOG CHANNEL SELECTED 0 0 0 0 1 AIN0 0 0 1 0 1 AIN1 0 1 0 0 1 AIN2 0 1 1 0 1 AIN3 1 0 0 0 1 AIN4 1 0 1 0 1 AIN5 1 1 0 0 1 AIN6 1 1 1 0 1 AIN7 N CONVERSION CLOCK 1 TRACK AND HOLD COMPARATOR AUTO-ZERO (AZ) SCA AUTO-ZERO (SCAZ) N+1 CONVERSION 2 3 4 6 TRACK VIN (N+1) HOLD VIN (N) CONVERT UPPER 5 BITS SAMPLE VIN (N) 5 HOLD VIN (N+1) CONVERT LOWER 5 BITS SAMPLE RESIDUAL SAMPLE VIN (N) AMPLIFY RESIDUAL SAMPLE VIN (N+1) SAMPLE VIN (N+1) INTERNAL DATA 10 BITS + OVR VIN (N) DATA FIGURE 2. INTERNAL ADC TIMING DIAGRAM TABLE 2. A/D OUTPUT CODE TABLE ANALOG INPUT* OUTPUT DATA (2’S COMPLEMENT) VREF = 2.500V OVR MSB 9 8 7 6 5 4 3 2 1 LSB 0 ≥ +VREF 2.500 to V+ (+OVR) 1 0 0 0 0 0 0 0 0 0 0 +VREF - 1LSB 2.49512 (+Full Scale) 0 0 1 1 1 1 1 1 1 1 1 +1LSB 0.00488 0 0 0 0 0 0 0 0 0 0 1 LSB = 2(VREF)/1024 0 0.000 0 0 0 0 0 0 0 0 0 0 0 -1LSB -0.00488 0 1 1 1 1 1 1 1 1 1 1 -VREF -2.500 (-Full Scale) 0 1 0 0 0 0 0 0 0 0 0 ≤ -VREF - 1LSB 2.50488 to V- (-OVR) 1 1 0 0 0 0 0 0 0 0 0 * The voltages listed above are the ideal centers of each output code shown as a function of its associated reference voltage. 14 HI-7153 Dynamic Performance Microprocessor Interface Fast Fourier Transform (FFT) techniques are used to evaluate the dynamic performance for one channel of the A/D system. A low distortion sine wave is applied to the input of the A/D converter. The input is sampled by the A/D and its output stored in RAM. The data is then transformed into the frequency domain with a 4096 point FFT and analyzed to evaluate the converters dynamic performance such as SNR and THD. See typical performance characteristics. The HI-7153 can be interfaced to microprocessors through the use of standard Write, Read, Chip Select, and HBE control pins. The digital outputs are two’s complement coded, three-state gated, and byte organized for bus interface with 8 and 16 bit systems. The digital outputs (D0 - D9, OVR) may be accessed under control of BUS, byte enable input HBE, chip select, and read inputs for a simple parallel bus interface. The microprocessor can read the current data in the output latches in typically 60ns/byte (tRD). An over-range pin (OVR) together with the MSB (D9) pin set to either a logic 0 or 1 will indicate a positive or negative over-range condition respectively. All digital output buffers are capable of driving one TTL load. The multiplexer can be interfaced to either multiplexed or separate address and data bus systems. Signal-To-Noise Ratio The signal to noise ratio (SNR) is the measured rms signal to rms sum of noise at a specified input and sampling frequency. The noise is the rms sum of all except the fundamental and the first five harmonic signals. The SNR is dependent on the number of quantization levels used in the converter. The theoretical SNR for an N-bit converter with no differential or integral linearity error is: SNR = (6.02N + 1.76)dB. For an ideal 10 bit converter the SNR is 62dB. Differential and integral linearity errors will degrade SNR. The HI-7153 can be interfaced to a microprocessor using one of three modes: slow memory, fast memory, or DMA mode. Slow Memory Mode Sinewave Signal Power SNR = 10 log ------------------------------------------------------Total Noise Power In slow memory mode, the conversion will be initiated by the microprocessor by selecting the chip (CS) and pulsing WR low. This mode is selected by hardwiring the SMODE pin to V+. Note that the converter will change to the DMA interface mode if the WR to RD active timing is less than 100ns. The end-of-conversion (EOC) output signals an interrupt for the microprocessor to jump to a read subroutine at the end of conversion. When the 8 bit bus operation is selected, high and low byte data may be accessed in either order. An I/O truth table is presented in Table 3 for the slow memory mode of operation. Signal-To-Noise + Distortion Ratio SINAD is the measured rms signal to rms sum of noise plus harmonic power and is expressed by the following. Sinewave Signal Power SINAD = 10 log -------------------------------------------------------------------------------------------------------Noise + Harmonic Power (2nd thru 6th) Effective Number of Bits The effective number of bits (ENOB) is derived from the SINAD data; Fast Memory Mode SINAD – 1.76 ENOB = -----------------------------------6.02 The fast memory mode of operation is selected by tying the SMODE and WR pins to DG. In this mode, the chip performs continuous conversions and only CS and RD are required to read the data. Whenever the SMODE pin is low, WR is independent of CS in starting a conversion cycle. During the first conversion cycle, HOLD follows WR going low. HOLD will be one clock period wide for subsequent conversion cycles. Total Harmonic Distortion The total harmonic distortion (THD) is the ratio of the RMS sum of the second through sixth harmonic components to the fundamental RMS signal for a specified input and sampling frequency. Data can be read a byte at a time or all 11 bits at once. When the 8 bit bus operation is selected, high and low byte data may be accessed in either order. EOC is continuously low in this mode of operation. The conversion data can be read after HOLD has gone low. An I/O truth table is presented in Table 4 for the fast memory mode of operation. Harmonic Power (2nd - 6th harmonics) THD = 10 log Total -----------------------------------------------------------------------------------------------------------------Sinewave Signal Power Spurious-Free Dynamic Range The spurious-free dynamic range (SFDR) is the ratio of the fundamental RMS amplitude to the RMS amplitude of the next largest spur or spectral component. It is usually determined by the largest harmonic. However, if the harmonics are buried in the noise floor it is the largest peak. DMA Mode This is a hardwired mode where the HI-7153 continuously converts. The user implements hardware to store the results in memory, bypassing the microprocessor. This mode is recognized by the chip when SMODE is connected to V+ and CS, RD, WR are connected to DG. When 8 bit bus operation is selected, high and low byte data may be accessed in either order. EOC is continuously low in this mode. The conversion data can be read approximately 300ns after HOLD has gone low. An I/O truth table is Sinewave Signal Power SFDR = 10 log ---------------------------------------------------------------------------------Highest Spurious Signal Power Clock The clock input is TTL compatible. The converter will function with clock inputs between 10kHz and 800kHz. 15 HI-7153 TABLE 3. SLOW MEMORY MODE I/O TRUTH TABLE (SMODE = V+) CS WR RD BUS HBE ALE 0 0 X X X X Initiates a conversion. 0 X X X X 1 Selects mux channel. Address data is latched on falling edge of ALE. Latch is transparent when ALE is high. 1 X X X X X Disables all chip commands. 0 X 0 1 X X Enables D0 - D9 and OVR. 0 X 0 0 0 X Low byte enable: D0 - D7 0 X 0 0 1 X High byte enable: D8 - D9, OVR X X 1 X X X Disables all outputs (high impedance). FUNCTION X = Don’t Care TABLE 4. FAST MEMORY MODE I/O TRUTH TABLE (SMODE = DG) CS WR RD BUS HBE ALE 0 0 X X X X Continuous conversion, WR may be tied to DG. 0 X X X X 1 Selects mux channel. Address data is latched on falling edge of ALE. Latch is transparent when ALE is high. 1 X X X X X Disables all chip commands. 0 X 0 1 X X Enables D0 - D9 and OVR. 0 X 0 0 0 X Low byte enable: D0 - D7 0 X 0 0 1 X High byte enable: D8 - D9, OVR X X 1 X X X Disables all outputs (high impedance). FUNCTION X = Don’t Care TABLE 5. DMA MODE I/O TRUTH TABLE (SMODE = V+, CS = WR = RD = DG) BUS HBE ALE FUNCTION X X 1 Selects mux channel. Address data is latched on falling edge of ALE. Latch is transparent when ALE is high. 1 X X Enables D0 - D9 and OVR. 0 0 X Low byte enable: D0 - D7 0 1 X High byte enable: D8 - D9, OVR X = Don’t Care presented in Table 5 for the DMA mode of operation. fore, the system ground star connection should be located as close to this pin as possible. Optimizing System Performance As in any analog system, good supply bypassing is necessary in order to achieve optimum system performance. The power supplies should be bypassed with at least a 20µF tantalum and a 0.1µF ceramic capacitor to GND. The reference input should be bypassed with a 0.1µF ceramic capacitor to AG. The capacitor leads should be as short as possible. The HI-7153 has three ground pins (AG, DG, GND) for improved system accuracy. Proper grounding and bypassing is illustrated in Figure 3. The AG pin is a ground pin and is used internally as a reference ground. The reference input and analog input should be referenced to the analog ground (AG) pin. The digital inputs and outputs should be referenced to the digital ground (DG) pin. The GND pin is a return point for the supply current of the comparator array. The comparator array is designed such that this current is approximately constant at all times and does not vary with input voltage. By virtue of the switched capacitor nature of the comparators, it is necessary to hold GND firmly at zero volts at all times. There- The pins on the HI-7153 are arranged such that the analog pins are well isolated from the digital pins. In spite of this arrangement, there is always some pin-to-pin coupling. Therefore the analog inputs to the device should not be driven from very high output impedance sources. PC board layout should screen the analog and reference inputs with guard rings on both sides of the PC board, connected to AG. 16 HI-7153 Applications mum throughput. The output data is configured for 16 bit bus operation in these applications. By tying BUS to DG and connecting the HBE input to the system address decoder, the output data can be configured for 8 bit bus systems. Figure 4 illustrates an application where the HI-7153 is used to form a multi-channel data acquisition system. Either slow memory or fast memory modes of operation can be selected. Fast memory mode should be selected for maxi- - +2.5 REF 0.1µF ANALOG INPUT 1 VREF V- 40 2 AG GND 39 3 AIN0 V+ 38 4 AIN1 OVR 37 5 AIN2 D9 36 6 AIN3 D8 35 7 AIN4 D7 34 8 AIN5 D6 33 9 AIN6 D5 32 10 AIN7 D4 31 11 NC D3 30 12 TEST D2 29 13 A0 D1 28 14 A1 D0 27 15 A2 HOLD 26 16 ALE -5V P.S. 0.1µF 20µF 0.1µF 20µF + -5V P.S. + EOC 25 17 WR DG 24 18 CS CLK 23 19 RD HBE 22 20 SMODE BUS 21 FIGURE 3. GROUND AND POWER SUPPLY DECOUPLING ADDRESS BUS ADDRESS DECODER A0 - A2 CS VREF MICROPROCESSOR WR SIGNAL GND +5V V+ -5V VDG HI-7153 AG RD ALE EOC GND TEST 600kHz CLK D0 - D9, OVR 8 BIT DATA BUS FIGURE 4. MULTI-CHANNEL DATA ACQUISITION SYSTEM 17