74LV132-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 11 November 2013 Product data sheet 1. General description The 74LV132-Q100 is a low-voltage Si-gate CMOS device that is pin and function compatible with 74HC132-Q100 and 74HCT132-Q100. The 74LV132-Q100 contains four 2-input NAND gates which accept standard input signals. These gates are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. The gate switches at different points for positive and negative-going signals. The difference between the positive voltage VT+ and the negative voltage VT is defined as the input hysteresis voltage VH. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Wide operating voltage: 1.0 V to 5.5 V Optimized for low voltage applications: 1.0 V to 3.6 V Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and Tamb = 25 C ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 3. Applications Wave and pulse shapers for highly noisy environments Astable multivibrators Monostable multivibrators 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 4. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 74LV132PW-Q100 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 74LV132BQ-Q100 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 74LV132D-Q100 5. Functional diagram 1 1A 1Y 2 4 2A 2Y 5 3 1B 6 2B 1 4 9 3A 3 & 6 & 8 5 3Y 10 & 2 8 3B 9 10 12 4A 4Y 13 12 11 4B 74LV132_Q100 Product data sheet 11 Y 13 B mna407 Fig 1. Logic symbol A & mna408 Fig 2. IEC logic symbol All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 mna409 Fig 3. Logic diagram (one gate) © NXP B.V. 2013. All rights reserved. 2 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 6. Pinning information 6.1 Pinning % < $ $ < % % < $ *1' < < $ $ < % < 9&& % % % 9&& < % *1' /94 $ $ WHUPLQDO LQGH[DUHD 9&& /94 $ DDD 7UDQVSDUHQWWRSYLHZ (1) The die substrate is attached to the exposed die pad using conductive die attach material. It cannot be used as a supply pin or input. DDD Fig 4. Pin configuration SO14 and TSSOP14 Fig 5. Pin configuration DHVQFN14 6.2 Pin description Table 2. Pin description Symbol Pin Description 1A 1 data input 1B 2 data input 1Y 3 data output 2A 4 data input 2B 5 data input 2Y 6 data output GND 7 ground (0 V) 3Y 8 data output 3A 9 data input 3B 10 data input 4Y 11 data output 4A 12 data input 4B 13 data input VCC 14 supply voltage 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 3 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 7. Functional description Table 3. Function table H = HIGH voltage level; L = LOW voltage level. Input Output nA nB nY L L H L H H H L H H H L 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current VO = 0.5 V to (VCC + 0.5 V) ICC IIK Min Max Unit 0.5 +7.0 V - 20 mA - 50 mA - 25 mA supply current - 50 mA IGND ground current 50 - mA Tstg storage temperature 65 +150 C Ptot total power dissipation Tamb = 40 C to +125 C SO14 package [2] - 500 mW TSSOP14 package [3] - 500 mW DHVQFN14 package [4] - 500 mW [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Ptot derates linearly with 8 mW/K above 70 C. [3] Ptot derates linearly with 5.5 mW/K above 60 C. [4] Ptot derates linearly with 4.5 mW/K above 60 C. 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 4 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min [1] Typ Max Unit VCC supply voltage 1.0 3.3 5.5 V VI input voltage 0 - VCC V VO output voltage 0 - VCC V Tamb ambient temperature 40 +25 +125 C [1] The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V. LV devices are guaranteed to function down to VCC = 1.0 V (with input levels GND or VCC). 10. Static characteristics Table 6. Static characteristics Voltages are referenced to GND (ground = 0 V). Symbol Parameter VOH HIGH-level output voltage LOW-level output voltage VOL Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ[1] Max Min Max lO = 100 A; VCC = 1.2 V - 1.2 - - - V lO = 100 A; VCC = 2.0 V 1.8 2.0 - 1.8 - V lO = 100 A; VCC = 2.7 V 2.5 2.7 - 2.5 - V lO = 100 A; VCC = 3.0 V 2.8 3.0 - 2.8 - V lO = 100 A; VCC = 4.5 V 4.3 4.5 - 4.3 - V lO = 6 mA; VCC = 3.0 V 2.4 2.82 - 2.2 - V lO = 12 mA; VCC = 4.5 V 3.6 4.2 - 3.5 - V IO = 100 A; VCC = 1.2 V - 0 - - - V IO = 100 A; VCC = 2.0 V - 0 0.2 - 0.2 V IO = 100 A; VCC = 2.7 V - 0 0.2 - 0.2 V IO = 100 A; VCC = 3.0 V - 0 0.2 - 0.2 V IO = 100 A; VCC = 4.5 V - 0 0.2 - 0.2 V IO = 6 mA; VCC = 3.0 V - 0.25 0.40 - 0.50 V IO = 12 mA; VCC = 4.5 V - 0.35 0.55 - 0.65 V VI = VT+ or VT VI = VT+ or VT II input leakage current VI = VCC or GND; VCC = 5.5 V - - 1.0 - 1.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 20.0 - 40 A ICC additional supply current per input; VI = VCC 0.6 V; VCC = 2.7 V to 3.6 V - - 500 - 850 A CI input capacitance - 3.5 - - - pF [1] Typical values are measured at Tamb = 25 C. 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 5 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; for test circuit, see Figure 7. Symbol Parameter propagation delay tpd 40 C to +85 C Conditions power dissipation capacitance Unit Min Max Min Max VCC = 1.2 V - 65 - - - ns VCC = 2.0 V - 18 34 - 43 ns [2] nA, nB to nY; see Figure 6 VCC = 2.7 V CPD 40 C to +125 C Typ[1] - 15 24 - 30 ns VCC = 3.0 V to 3.6 V; CL = 15 pF [3] - 10 - - - ns VCC = 3.0 V to 3.6 V [3] - 12 20 - 25 ns VCC = 4.5 V to 5.5 V [3] - 9.0 14 - 17 ns CL = 50 pF; fi = 1 MHz; VI = GND to VCC [4] - 24 - - - pF [1] All typical values are measured at Tamb = 25 C. [2] tpd is the same as tPLH and tPHL. [3] Typical values are measured at nominal supply voltage (VCC = 3.3 V and VCC = 5.0 V). [4] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz, fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in V N = number of inputs switching (CL VCC2 fo) = sum of the outputs. 12. Waveforms VI VM nA, nB input GND t PHL t PLH VOH VM nY output VOL 001aaa662 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. The input (nA, nB) to output (nY) propagation delays 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 6 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 8. Measurement points Supply voltage Input Output VCC VM VM < 2.7 V 0.5VCC 0.5VCC 2.7 V to 3.6 V 1.5 V 1.5 V 4.5 V 0.5VCC 0.5VCC VCC PULSE GENERATOR VI VO DUT CL 50 pF RT RL 1 kΩ 001aaa663 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. RL = Load resistance. CL = Load capacitance including jig and probe capacitance. Fig 7. Load circuit for switching times Table 9. Test data Supply voltage Input VCC VI tr, tf < 2.7 V VCC 2.5 ns 2.7 V to 3.6 V 2.7 V 2.5 ns 4.5 V VCC 2.5 ns 13. Transfer characteristics Table 10. Transfer characteristics GND = 0 V; for test circuit, see Figure 7. Symbol Parameter VT+ positive-going threshold voltage 74LV132_Q100 Product data sheet 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 0.70 - - - V see Figure 6 VCC = 2.0 V 0.8 1.10 1.4 0.8 1.4 V VCC = 2.7 V 1.0 1.45 2.0 1.0 2.0 V VCC = 3.0 V 1.2 1.60 2.2 1.2 2.2 V VCC = 3.6 V 1.5 1.95 2.4 1.5 2.4 V VCC = 4.5 V 1.7 2.50 3.2 1.7 3.2 V VCC = 5.5 V 2.1 3.00 3.9 2.1 3.9 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 7 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger Table 10. Transfer characteristics …continued GND = 0 V; for test circuit, see Figure 7. Symbol Parameter VT negative-going threshold voltage hysteresis voltage VH [1] 40 C to +85 C Conditions 40 C to +125 C Unit Min Typ[1] Max Min Max VCC = 1.2 V - 0.34 - - - V VCC = 2.0 V 0.3 0.65 0.9 0.3 0.9 V VCC = 2.7 V 0.4 0.90 1.4 0.4 1.4 V VCC = 3.0 V 0.6 1.05 1.5 0.6 1.5 V VCC = 3.6 V 0.8 1.30 1.8 0.8 1.8 V VCC = 4.5 V 0.9 1.60 2.0 0.9 2.0 V VCC = 5.5 V 1.2 2.00 2.6 1.2 2.6 V VCC = 1.2 V - 0.3 - - - V VCC = 2.0 V 0.2 0.55 0.8 0.2 0.8 V VCC = 2.7 V 0.3 0.60 1.1 0.3 1.1 V VCC = 3.0 V 0.4 0.65 1.2 0.4 1.2 V VCC = 3.6 V 0.4 0.70 1.2 0.4 1.2 V VCC = 4.5 V 0.4 0.80 1.4 0.4 1.4 V VCC = 5.5 V 0.6 1.00 1.5 0.6 1.5 V see Figure 6 (VT+ VT); see Figure 6 All typical values are measured at Tamb = 25 C. 14. Waveforms transfer characteristics VT+ VO VI VH VT− VO VI VH VT− VT+ Fig 8. Transfer characteristic 74LV132_Q100 Product data sheet mna208 mna207 VT+ and VT limits at 70 % and 20 %. Fig 9. Definition of VT+, VT and VH All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 8 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 001aaa659 12 001aaa660 100 ICC (μA) ICC (μA) 80 8 60 40 4 20 0 0 0 0.3 0.6 0.9 1.2 0 0.4 VI (V) 0.8 1.2 1.6 2 VI (V) VCC = 1.2 V. VCC = 2.0 V. Fig 10. Typical 74LV132-Q100 transfer characteristics Fig 11. Typical 74LV132-Q100 transfer characteristics 001aaa661 300 ICC (μA) 200 100 0 0 0.6 1.2 1.8 2.4 3 VI (V) VCC = 3.0 V. Fig 12. Typical 74LV132-Q100 transfer characteristics 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 9 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 15. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT108-1 (SO14) 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 10 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA MO-153 EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 Fig 14. Package outline SOT402-1 (TSSOP14) 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 11 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 15. Package outline SOT762-1 (DHVQFN14) 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 12 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 16. Abbreviations Table 11. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 17. Revision history Table 12. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LV132_Q100 v.1 20131111 Product data sheet - - 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 13 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. Definition [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74LV132_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 14 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74LV132_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 11 November 2013 © NXP B.V. 2013. All rights reserved. 15 of 16 74LV132-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transfer characteristics . . . . . . . . . . . . . . . . . . 7 Waveforms transfer characteristics. . . . . . . . . 8 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 13 Legal information. . . . . . . . . . . . . . . . . . . . . . . 14 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Contact information. . . . . . . . . . . . . . . . . . . . . 15 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 11 November 2013 Document identifier: 74LV132_Q100