HEF4093B-Q100 Quad 2-input NAND Schmitt trigger Rev. 1 — 12 July 2012 Product data sheet 1. General description The HEF4093B-Q100 is a quad two-input NAND gate. Each input has a Schmitt trigger circuit. The gate switches at different points for positive-going and negative-going signals. The difference between the positive voltage (VT+) and the negative voltage (VT) is defined as hysteresis voltage (VH). It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS (usually ground). Unused inputs must be connected to VDD, VSS, or another input. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Schmitt trigger input discrimination Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics ESD protection: MIL-STD-833, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pf, R = 0 ) Complies with JEDEC standard JESD 13-B 3. Applications Wave and pulse shapers Astable multivibrators Monostable multivibrators 4. Ordering information Table 1. Ordering information All types operate from 40 C to +125 C Type number HEF4093BT-Q100 Package Name Description Version SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 5. Functional diagram 1A 1 3 1B 2A 2 5 4 2B 3A 4A nA nY 8 nB 3Y 001aag105 9 12 11 4B 2Y 6 10 3B 1Y 4Y 13 001aag104 Fig 1. Functional diagram Fig 2. Logic diagram (one gate) 6. Pinning information 6.1 Pinning HEF4093B-Q100 1A 1 14 VDD 1B 2 13 4B 1Y 3 12 4A 2Y 4 11 4Y 2A 5 10 3Y 2B 6 9 3B VSS 7 8 3A aaa-003547 Fig 3. Pin configuration HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 2 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 6.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 5, 8, 12 input 1B to 4B 2, 6, 9, 13 input 1Y to 4Y 3, 4, 10, 11 output VDD 14 supply voltage VSS 7 ground (0 V) 7. Functional description Table 3. Function table[1] Input Output nA nB L L H L H H H L H H H L [1] nY H = HIGH voltage level; L = LOW voltage level. 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground). Symbol Parameter VDD supply voltage Conditions IIK input clamping current VI input voltage IOK output clamping current - 10 mA II/O input/output current - 10 mA IDD supply current - 50 mA Tstg storage temperature 65 +150 C Tamb ambient temperature 40 +125 C Ptot total power dissipation VI < 0.5 V or VI > VDD + 0.5 V VO < 0.5 V or VO > VDD + 0.5 V [1] power dissipation Max Unit 0.5 +18 V - 10 mA 0.5 VDD + 0.5 V Tamb = 40 C to +125 C SO14 P Min per output [1] - 500 mW - 100 mW For SO14 package: above Tamb = 70 C, Ptot derates linearly with 8 mW/K. HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 3 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 9. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter VDD Conditions Min Max Unit supply voltage 3 15 V VI input voltage 0 VDD V Tamb ambient temperature 40 +125 C in free air 10. Static characteristics Table 6. Static characteristics VSS = 0 V; VI = VSS or VDD; unless otherwise specified. Symbol Parameter VOH VOL IOH IOL HIGH-level output voltage IO < 1 A VDD Tamb = 40 C Tamb = +25 C Tamb = +85 C Tamb = +125 C Unit Min Max Min Max Min Max Min Max 4.95 - 4.95 - 4.95 - 4.95 - V 10 V 9.95 - 9.95 - 9.95 - 9.95 - V 15 V 14.95 - 14.95 - 14.95 - 14.95 - V 5V - 0.05 - 0.05 - 0.05 - 0.05 V 10 V - 0.05 - 0.05 - 0.05 - 0.05 V V 5V LOW-level output voltage IO < 1 A 15 V - 0.05 - 0.05 - 0.05 - 0.05 HIGH-level output current VO = 2.5 V 5V 1.7 - 1.4 - 1.1 - 1.1 - mA VO = 4.6 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 9.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA LOW-level output current II input leakage current IDD supply current CI Conditions input capacitance HEF4093B_Q100 Product data sheet VO = 13.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA VO = 0.4 V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA VO = 0.5 V 10 V 1.6 - 1.3 - 0.9 - 0.9 - mA VO = 1.5 V 15 V 4.2 - 3.4 - 2.4 - 2.4 - mA 15 V - 0.1 - 0.1 - 1.0 - 1.0 A 5V all valid input combinations; 10 V IO = 0 A 15 V - 0.25 - 0.25 - 7.5 - 7.5 A - 0.5 - 0.5 - 15.0 - 15.0 A - 1.0 - 1.0 - 30.0 - 30.0 A - - - 7.5 - - - - pF All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 4 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 11. Dynamic characteristics Table 7. Dynamic characteristics Tamb = 25 C; CL = 50 pF; tr = tf 20 ns; wave forms see Figure 4; test circuit see Figure 5; unless otherwise specified. Symbol Parameter HIGH to LOW propagation delay tPHL tPLH tTHL [1] nA or nB to nY LOW to HIGH propagation delay nA or nB to nY HIGH to LOW output transition time nY to LOW LOW to HIGH output transition time tTLH Conditions nA or nB to HIGH Extrapolation formula[1] Min Typ Max Unit 5V 63 ns + (0.55 ns/pF)CL - 90 185 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 58 ns + (0.55 ns/pF)CL - 85 170 ns 10 V 29 ns + (0.23 ns/pF)CL - 40 80 ns 15 V 22 ns + (0.16 ns/pF)CL - 30 60 ns 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns VDD 5V 10 ns + (1.00 ns/pF)CL - 60 120 ns 10 V 9 ns + (0.42 ns/pF)CL - 30 60 ns 15 V 6 ns + (0.28 ns/pF)CL - 20 40 ns Typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (CL in pF). Table 8. Dynamic power dissipation VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. Symbol Parameter PD dynamic power dissipation VDD Typical formula where: 5V PD = 1300 fi + (fo CL) VDD (W) fi = input frequency in MHz; 10 V PD = 6400 fi + (fo CL) VDD2 (W) fo = output frequency in MHz; 15 V PD = 18700 fi + (fo CL) VDD2 (W) 2 CL = output load capacitance in pF; (fo CL) = sum of the outputs; VDD = supply voltage in V. HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 5 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 12. Waveforms tr VI tf 90 % input VM 10 % 0V tPHL VOH tPLH 90 % output VM 10 % VOL tTHL tTLH 001aag197 Measurement points are given in Table 9. Logic levels: VOL and VOH are typical output voltage levels that occur with the output load. tr, tf = input rise and fall times. Fig 4. Propagation delay and output transition time Table 9. Measurement points Supply voltage Input Output VDD VM VM 5 V to 15 V 0.5VDD 0.5VDD VDD VI VO G DUT CL RT 001aag182 Test data given in Table 10. Definitions for test circuit: DUT = Device Under Test. CL = load capacitance including jig and probe capacitance. RT = termination resistance should be equal to the output impedance Zo of the pulse generator. Fig 5. Test circuit Table 10. Test data Supply voltage Input VDD VI tr, tf CL 5 V to 15 V VSS or VDD 20 ns 50 pF HEF4093B_Q100 Product data sheet Load All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 6 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 13. Transfer characteristics Table 11. Transfer characteristics VSS = 0 V; Tamb = 25 C; see Figure 6 and Figure 7. Symbol Parameter VT+ VT VH Conditions positive-going threshold voltage negative-going threshold voltage hysteresis voltage VDD Min Typ Max Unit 5V 1.9 2.9 3.5 10 V 3.6 5.2 7 V 15 V 4.7 7.3 11 V 5V 1.5 2.2 3.1 V 10 V 3 4.2 6.4 V 15 V 4 6.0 10.3 V 5V 0.4 0.7 - V 10 V 0.6 1.0 - V 15 V 0.7 1.3 - V V VO VI VT+ VT− VI VH VT− Fig 6. VT+ Transfer characteristic HEF4093B_Q100 Product data sheet VH VO 001aag107 001aag108 Fig 7. Waveforms showing definition of VT+ and VT (between limits at 30 % and 70 %) and VH All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 7 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 001aag109 200 001aag110 1000 IDD (μA) IDD (μA) 100 500 0 0 0 2.5 5 0 5 VI (V) 10 VI (V) a. VDD = 5 V; Tamb = 25 C b. VDD = 10 V; Tamb = 25 C 001aag111 2000 IDD (μA) 1000 0 0 10 20 VI (V) c. Fig 8. VDD = 15 V; Tamb = 25 C Typical drain current as a function of input HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 8 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 001aag112 10 VI (V) VT+ VT− 5 0 2.5 5 7.5 10 12.5 15 17.5 VDD (V) Tamb = 25 C. Fig 9. Typical switching levels as a function of supply voltage 14. Application information Some examples of applications for the HEF4093B-Q100 are: • Wave and pulse shapers • Astable multivibrators • Monostable multivibrators Cp VDD 14 VDD 14 R 1 1 3 3 VDD 2 VDD 2 C 7 7 001aag113 001aag114 Fig 10. Astable multivibrator Fig 11. Schmitt trigger driven via a high-impedance input If a Schmitt trigger is driven via a high-impedance (R > 1 k), then it is necessary to V DD – V SS C > ------------------------ ; otherwise oscillation can occur incorporate a capacitor C with a value of -----CP VH on the edges of a pulse. Cp is the external parasitic capacitance between inputs and output; the value depends on the circuit board layout. Remark: The two inputs may be connected together, but this will result in a larger through-current at the moment of switching. HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 9 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 15. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 12. Package outline SOT108-1 (SO14) HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 10 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 16. Abbreviations Table 12. Abbreviations Acronym Description HBM Human Body Model ESD ElectroStatic Discharge MM Machine Model MIL Military 17. Revision history Table 13. Revision history Document ID Release date Data sheet status Change notice Supersedes HEF4093B_Q100 v.1 20120712 Product specification - - HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 11 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 18. Legal information 18.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 18.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 18.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. 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This document supersedes and replaces all information supplied prior to the publication hereof. HEF4093B_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 12 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 18.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] HEF4093B_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 12 July 2012 © NXP B.V. 2012. All rights reserved. 13 of 14 HEF4093B-Q100 NXP Semiconductors Quad 2-input NAND Schmitt trigger 20. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 17 18 18.1 18.2 18.3 18.4 19 20 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Transfer characteristics . . . . . . . . . . . . . . . . . . 7 Application information. . . . . . . . . . . . . . . . . . . 9 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 11 Legal information. . . . . . . . . . . . . . . . . . . . . . . 12 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 12 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Contact information. . . . . . . . . . . . . . . . . . . . . 13 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2012. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 12 July 2012 Document identifier: HEF4093B_Q100