Using Spansion Flash Devices with TI Sitara™ – AM3517 based Version 1.0 September 2010 Spansion LLC Using Spansion Flash with TI Sitara TM - AM3517 based Intentionally Blank ii Using Spansion Flash with TI Sitara TM - AM3517 based Table of Contents 1 Introduction .........................................................................................................................................................1 1.1 Reference ..........................................................................................................................................................1 1.2 Abbreviations ....................................................................................................................................................1 1.3 Revision History ................................................................................................................................................1 2 Sitara™ Processors ...............................................................................................................................................2 2.1 3 Memory Subsystem in Sitara™ .........................................................................................................................4 General –Purpose Memory Controller (GPMC) ...................................................................................................6 3.1 Understanding of GPMC ...................................................................................................................................6 3.2 Spansion Devices and Read Setting Parameters .............................................................................................10 3.3 GPMC Interface to 16-bit, ADP, Asynchronous NOR Flash .............................................................................14 3.4 GPMC Interface to 16-bit, ADM, Synchronous NOR Flash ..............................................................................21 3.5 GPMC Interface to 16-bit, ADP, Synchronous NOR Flash ...............................................................................25 Table of Figures Figure 1. AM35x Block Diagram and Memory Block .....................................................................................................3 Figure 2. AM18x Block Diagram and Memory Block .....................................................................................................3 TM Figure 3. Memory Subsystem in Sitara .......................................................................................................................4 Figure 4. On-chip Memory Subsystem ..........................................................................................................................4 Figure 6. GPMC ..............................................................................................................................................................5 Figure 5. SDRC.................................................................................................................................................................. Figure 7. Synchronous Mode Timing Conditions for NOR Flash Device ........................................................................6 Figure 8. Recommended Power Suppliers .....................................................................................................................8 Figure 9. Example of Level Shifters for multi-level signals application ..........................................................................8 Figure 10. sys_boot pin[4:0] configuration for NOR boot .............................................................................................9 Figure 11. Spansion Device Families ............................................................................................................................10 Figure 12. Synchronous READ Timing Parameters ......................................................................................................11 Figure 13. Asynchronous Single READ Timing Parameters ..........................................................................................12 Figure 14, Asynchronous Page READ Timing Parameters ............................................................................................13 Figure 15. GPMC Interface to Spansion ADP Asynchronous Devices ..........................................................................14 Figure 16. GL-P AC Characteristics for Asynchronous Page Read ................................................................................15 Figure 17. GL-P Asynchronous Read Waveform ..........................................................................................................15 iii Using Spansion Flash with TI Sitara TM - AM3517 based Figure 18. GL-P Asynchronous Page Read Waveform Generation ..............................................................................17 Figure 19. AL-J AC Characteristics for Asynchronous Single Read ...............................................................................18 Figure 20. AL-J Asynchronous Read Waveform ...........................................................................................................18 Figure 21. AL-J Asynchronous Single Read Waveform Generation .............................................................................20 Figure 22. GPMC Interface to Spansion ADM Synchronous Devices ...........................................................................21 Figure 23. VS-R AC Characteristics for Synchronous Burst Read .................................................................................22 Figure 24. VS-R Synchronous Read Waveform ............................................................................................................22 Figure 25. Wait State and Frequency for VS-R ............................................................................................................23 Figure 26. VS-R Synchronous Read Waveform Generation .........................................................................................24 Figure 27. GPMC Interface to Spansion ADP Synchronous Devices ............................................................................25 Figure 28. WS-P AC Characteristics for Synchronous Burst Read ................................................................................26 Figure 29. WS-P Synchronous Read Waveform ...........................................................................................................26 Figure 30. Wait State and Frequency for WS-P ...........................................................................................................27 Figure 31. WS-P Synchronous Read Waveform Generation ........................................................................................28 iv Using Spansion Flash with TI Sitara TM - AM3517 based 1 Introduction TI Sitara™ Processors are designed with ARM architecture solutions from ARM9™ to ARM® Cortex™-A8. It supports NAND, NOR, pSRAM, and DDR to run application. Code shadowing into DDR RAM is commonly used for fast code execution. General memory combinations are as below. NAND / DDR NOR / DDR NOR / NAND / DDR This Application Note explains Memory Controllers in TI Sitara™ Processors, memory interface to Spansion NOR devices, and register setting parameters for timing interface. All of register setting parameters explained here in chapter 3 are only for reference. 1.1 Reference R1) AM35x ARM Microprocessor Technical Reference Manual Version B (Rev. B) Chapter 2 : Memory Mapping Chapter 9 : Memory Subsystem Chapter 24 : Applications Processor Initialization R2) AM3517/05 ARM Microprocessor (Rev. B) Chapter 6 : Timing requirements and switching characteristics R3) Spansion S29GL-P NOR Device R4) Spansion S29AL-J NOR Device R5) Spansion S29VS-R NOR Device R6) Spansion S29WS-P NOR Device 1.2 Abbreviations ADP Address Data Parallel known as Demux Interface ADM Address Data Multiplex known as Mux Interface 1.3 Revision History 1 Revision Date Comments v1.0.0 06/Oct/2010 Initial Draft Using Spansion Flash with TI Sitara 2 TM - AM3517 based Sitara™ Processors The Sitara TM microprocessor family features are shown as below. ARM® Cortex™-A8 and ARM9™-based solutions with performance ranging from 375 MHz to 1 GHz Highly reusable software code bases that allow designers to easily scale within the product family by utilizing ARM processors and common peripheral sets Multiple operating frequencies, 3-D graphics acceleration, multiple packaging options and temperature operating points to further provide optimal flexibility to fit most application requirements. Low-cost development tools and free Linux and Windows® Embedded CE software baseports to accelerate both software and hardware development It is suitable for a wide variety of applications such as portable data terminals, portable medical equipment, home and building automation, navigation systems, smart displays and human machine interaction (HMI) industrial interfaces and other applications which require high-performance, low-power processing capabilities. AM37x: Cortex-A8 processors 800 MHz and 1 GHz processors delivering up to 2000 Dhrystone MIPS – AM3703 and AM3715 Memory : SDRAM – LPDDR1, Flash – NOR/NAND/OneNAND AM35x: Coretex-A8 Processors 600 MHz ARM Cortex-A8 core providing 1200 Dhrystone MIPS – AM3503 and AM3517 Memory : SDRAM – DDR2/LPDDR1, Flash – NOR/NAND/OneNAND AM17x and AM18x processors 375 MHz and 450 MHz ARM9 processors – AM1705 and AM1808 Memory : SDRAM – DDR/DDR2/mDDR, Flash – NOR/NAND 2 Using Spansion Flash with TI Sitara TM - AM3517 based Figure 1. AM35x Block Diagram and Memory Block Figure 2. AM18x Block Diagram and Memory Block 3 Using Spansion Flash with TI Sitara TM - AM3517 based 2.1 Memory Subsystem in Sitara™ Memory system consists of On-chip memory (OCM) and two dedicated memory controllers – GPMC and SDRC. Figure 3. Memory Subsystem in Sitara TM On-chip memory (OCM) Subsystem The On-chip memory subsystem consists of two separate on-chip memory controllers connected to on-chip ROM and on-chip RAM. These allow transactions between the system initiators and the multiple memories on booting time. Boot code and stack are placed here to run on booting sequence. Figure 4. On-chip Memory Subsystem 4 Using Spansion Flash with TI Sitara TM - AM3517 based SDRC – SDRAM Controller Subsystem The SDRC subsystem provides connectivity between the processor and external discrete DDR SDRAM and highperformance interface to a variety of fast memory devices. It supports DDR2 and LPDDR1 device. Sitara™ Processor SDRC Interface AM37x LPDDR 1.8V, 16 or 32-bit, 1GB address AM35x DDR2, LPDDR1 1.8V, 16 or 32-bit, 1GB address In AM17x and AM18x architecture, there is DDR2/mDDR controller instead of SDRC. Also SDRAM can be connected through EMIFA which is originally dedicated to NAND and NOR Flash. Sitara™ Processor DDR controller / EMIF Interface AM17x, AM18x DDR2, mDDR 1.8V, 16-bit, 512MB(DDR2), 256MB(mDDR) SDRAM 3V, 16-bit Figure 5. SDRC GPMC – General Purpose Memory Controller The general-purpose memory controller (GPMC) is dedicated for interfacing external memory devices like SRAMlike memories, ASIC, NAND and NOR Flash and PSRAM. Figure 6. GPMC 5 Using Spansion Flash with TI Sitara TM - AM3517 based 3 General –Purpose Memory Controller (GPMC) 3.1 Understanding of GPMC Memory Access Type The GPMC is a 16-bit external memory controller. It provides a flexible programming model for communication with all standard memories and supports various accesses: Access Type Features Asynchronous Read / Write Page Read access with 4, 8, 16 Word Synchronous Read / Write access with and without Wrap Capability (4, 8, 16 Word) Address Data Access Address/Data Multiplexed Access Endian Little- and Big-endian 1.8V and 3V device can be applied by connecting supply voltage to GPMC IO voltage plane. It supports up to 100MHz for Synchronous access. There is load capacitance limit. To reach maximum frequency, do not connect many devices on GPMC. Figure 7. Synchronous Mode Timing Conditions for NOR Flash Device Chip Selects and Memory Mapping Address The system has two level memory mapping – Level 1 and Level 2. Level 1: 4 quarters labeled Q0, Q1, Q2, and Q3 and each quarter has 1GB address space. Level 2 : each quarter is divided into 8 blocks of 128MB 6 Using Spansion Flash with TI Sitara TM - AM3517 based Quarter Device Name Start Address (HEX) End Address (HEX) Q0 (1GB) Boot and GPMC 0x0000 0000 0x3FFF FFFF Q1 (1GB) On-Chip memory, L3, L4, SGX, IPSS 0x4000 0000 0x7FFF FFFF Q2 (1GB) EMIF4/SMS (SDRAM) 0x8000 0000 0xBFFF FFFF Q3 (1GB) RSVD 0xC000 0000 0xFFFF FFFF GPMC is located in Q0 with 1GB access size. It has 8 independent GPMC chip selects (gpmc_ncs0 - 7) for NOR / NAND Flash and PSRAM memories. The chip-selects have a programmable start address and programmable size (16MB, 32MB, 64MB, or 128MB) in a total memory space of 1GB. In power up sequence, CS0 is only available to use. Spansion devices are connected to CS0-7 on 1GB size Q0. External Device Example External Devices to communicate are as below. List of devices 8 bit Asynchronous / Synchronous devices 16 bit Asynchronous / Synchronous devices 16-bit Asynchronous / synchronous devices with ADP interface – 2KB limited address range 16-bit Asynchronous / synchronous devices with ADP interface adding latch circuit to cover max address 16-bit NOR device with ADM Interface 8-bit and 16-bit NAND Flash device 16-bit pseudo SRAM (pSRAM) devices Summary of GPMC Features and Settings 7 Items Descriptions Device Type Up to eight NOR or NAND protocol external memories or devices Operating Voltage 1.8V preferred and 3V possible Max Op. Frequency Up to 100MHz (single device) with an L3-clock of 100MHz. Up to 83MHz (L3clock divided by two) with an L3-clock of 166MHz Addressing Capability 1GB divided into eight chip-selects Max Memory Size 128MB Min Memory Size 16MB. Aliasing occurs when addressing smaller memories Data width 8-bit and 16-bit wide Burst and Page Access Burst of 4-8-16 Word Others Bus keeping and bus turn around Using Spansion Flash with TI Sitara TM - AM3517 based Power Domains There are many power domains to apply. VDDSHV is power supply to Memory and Peripherals. It supports both 1.8V and 3.3V. Figure 8. Recommended Power Suppliers Level shifters are used for signal conversion if multi-level signals need to be applied in system as below. Figure 9. Example of Level Shifters for multi-level signals application 8 Using Spansion Flash with TI Sitara TM - AM3517 based Memory Booting Configuration for NOR devices Figure 10. sys_boot pin[4:0] configuration for NOR boot In this memory booting configuration, XIP is used for NOR Flash memory booting. 9 Using Spansion Flash with TI Sitara TM - AM3517 based 3.2 Spansion Devices and Read Setting Parameters Spansion Device Families are shown as below. Figure 11. Spansion Device Families Spansion Target devices for TI Sitara TM processors are as below. GL / PL can be used for asynchronous page read / asynchronous single write AL / JL can be used for asynchronous single read / asynchronous single write WS/NS/VS can be used for synchronous burst read / asynchronous single write 10 Device Group Density (bit) Data Interface Bank Voltage S29GL-P 32Mb – 2Gb 16-bit, ADP, Asynch Page 1 3V S29AL-J/D 4Mb – 256Mb 8/16-bit, ADP, Asynch 1 3V S29PL-N 128Mb 16-bit, ADP, Asynch Page 4 3V S29JL-J/H 32Mb – 512Mb 8/16-bit, ADP, Asynch 4 3V S29WS-P 128Mb – 512Mb 16-bit, ADP, Synch Burst 16 1.8V S29VS-R 64Mb – 256Mb 16-bit, ADM, Synch Burst 4, 8 1.8V S92NS-R 512Mb 16-bit, ADM, Synch Burst 8 1.8V Using Spansion Flash with TI Sitara TM - AM3517 based Synchronous Multiple Read Timing Setup Parameters in TI SitaraTM Processors Signal Parameter Description CLK GPMCFCLKDIVIDER GPMC_CLK divider ratio 0 = 1:1, 1 = 1:2, 2 = 1:4 CLKACTIVATIONTIME GPMC_CLK output delay count RDCYCLETIME Read Op. Cycle Count : RDCYCLETIME0 + RDCYCLETIME1 RDACCESSTIME Initial Access Time to 1 Data Out CSONTIME nCS Active Count CSRDOFFTIME nCS De-active Count ADVONTIME nADV Asserted Count ADVOFFTIME nADV De-asserted Count OEONTIME nOE Asserted Count OEOFFTIME nOE De-asserted Count : OEOFFTIME0 + OEOFFTIME1 Read Op nCS nADV nOE PageBurstAccess PAGEBURSTACCESSTIME WAIT Monitor WAITMONITORINGTIME st Delay between successive data reads in burst operation WAIT pin de-asserted time with valid data 0 : same cycle as valid data / 1 : one cycle before valid data WAIT Polarity WAITxPINPOLARITY Indicate valid data is not ready on bus 0/1 : Active Low/ High Wrap Burst WRAPBURST Synchronous wrapping feature 0/1 : Disable/Enable Page Length ATTACHEDDEVICEPAGELENGTH Page (burst) Size 0/1/2 : 4/8/16 words Figure 12. Synchronous READ Timing Parameters 11 Using Spansion Flash with TI Sitara TM - AM3517 based Asynchronous Single/Page Read Timing Setup Parameters in TI SitaraTM Processors Signal Parameter CLK GPMCFCLKDIVIDER Description CLKACTIVATIONTIME Read Op RDCYCLETIME Read Op. Cycle Count RDACCESSTIME Initial Access Time to Data Out CSONTIME nCS Active Count CSRDOFFTIME nCS De-active Count ADVONTIME nADV Asserted Count ADVOFFTIME nADV De-asserted Count OEONTIME nOE Asserted Count OEOFFTIME nOE De-asserted Count : OEOFFTIME0 + OEOFFTIME1 PageBurstAccess PAGEBURSTACCESSTIME Delay between successive data reads in burst operation WAIT Monitor WAITMONITORINGTIME WAIT Polarity WAITxPINPOLARITY Wrap Burst WRAPBURST Page Length ATTACHEDDEVICEPAGELENGTH nCS nADV nOE Page (burst) Size 0/1/2 : 4/8/16 words Figure 13. Asynchronous Single READ Timing Parameters 12 Using Spansion Flash with TI Sitara TM - AM3517 based Figure 14, Asynchronous Page READ Timing Parameters All of register setting parameters explained here after are only for reference and need to test on target board. 13 Using Spansion Flash with TI Sitara TM - AM3517 based 3.3 GPMC Interface to 16-bit, ADP, Asynchronous NOR Flash Below shows interface between GPMC and Spansion ADP Asynchronous NOR devices S29GL-N/P : 32Mbit, 64Mbit, 128Mbit, 256Mbit, 512Mbit, 1Gbit, 2Gbit S29AL-J/D : 8Mbit, 16Mbit, 32Mbit S29PL-N : 128Mbit S29JL-J : 32Mbit, 64Mbit Features S29GL-N/P S29AL-J/D Voltage S29PL-N S29JL-J 3V Initial Access Time 90ns 55ns 65ns 55ns Page Access Time 25ns N/A 25ns N/A 1 1 4 4 Uniform : GL-N/P Top and Bottom Dual Boot Top and Bottom 64KB : Main 64KB : Main 256KB : Main 64KB : Main 8KB : Boot (GL-P) 8/16/32KB : Boot 64KB : Boot 8KB : Boot Burst Length 8 words Single 8 words Single Write Protection Pin (WP#) Available Available Available Available Bank # Boot Mode Top/Bottom : GL-N Erase Block Size Figure 15. GPMC Interface to Spansion ADP Asynchronous Devices 14 Using Spansion Flash with TI Sitara TM - AM3517 based Asynchronous Page Read Device Timing Configuration based on GL-P Figure 16. GL-P AC Characteristics for Asynchronous Page Read Figure 17. GL-P Asynchronous Read Waveform 15 Using Spansion Flash with TI Sitara TM - AM3517 based We can find below register settings to run, given 104MHz GPMC_FCLK (9.615ns clock duration). Signal Parameter CLK GPMCFCLKDIVIDER Value and Description CLKACTIVATIONTIME Read Op nCS nADV nOE RDCYCLETIME 0x0F : ReadAccessTime + DataHolding(1Clk) + tDF(2Clk) = 15 clocks RDACCESSTIME CSONTIME 0x0B : AddressLatch (2Clk) + InitialAccessTime(90ns) >> 12 clocks to make 115.4ns 0x2 : Assert after address latch CSRDOFFTIME 0x0C : ReadAccessTimg + DataHolding(1CLK) ADVONTIME 0x0 : Immediate Assert with Read Cycle ADVOFFTIME 0x01 : Provide AVD assertion duration with 1 cycle OEONTIME 0x2 : Assert after address latch OEOFFTIME 0x0C : ReadAccessTimg + DataHolding(1CLK) PageBurstAccess PAGEBURSTACCESSTIME WAIT Monitor WAITMONITORINGTIME WAIT Polarity WAITxPINPOLARITY Wrap Burst WRAPBURST Page Length ATTACHEDDEVICEPAGELENGTH 16 0x03 : tPACC = 25ns >> 3 Clk access time 1 : 8 words burst size Using Spansion Flash with TI Sitara TM - AM3517 based Address Latch Figure 18. GL-P Asynchronous Page Read Waveform Generation 17 Using Spansion Flash with TI Sitara TM - AM3517 based Asynchronous Single Read Device Timing Configuration based on AL-J Figure 19. AL-J AC Characteristics for Asynchronous Single Read Figure 20. AL-J Asynchronous Read Waveform 18 Using Spansion Flash with TI Sitara TM - AM3517 based We can find below register settings to run, given 104MHz GPMC_FCLK (9.615ns clock duration). Signal Parameter CLK GPMCFCLKDIVIDER Value and Description CLKACTIVATIONTIME Read Op nCS nADV nOE RDCYCLETIME 0x0C : ReadAccessTime + DataHolding(1Clk) + tDF(2Clk) = 13 clocks RDACCESSTIME CSONTIME 0x0A : AddressLatch (2Clk) + InitialAccessTime(70ns) >> 10 clocks to make 96.2ns 0x2 : Assert after address latch CSRDOFFTIME 0x0B : ReadAccessTimg + DataHolding(1CLK) ADVONTIME 0x0 : Immediate Assert with Read Cycle ADVOFFTIME 0x01 : Provide AVD assertion duration with 1 cycle OEONTIME 0x2 : Assert after address latch OEOFFTIME 0x0B : ReadAccessTimg + DataHolding(1CLK) PageBurstAccess PAGEBURSTACCESSTIME WAIT Monitor WAITMONITORINGTIME WAIT Polarity WAITxPINPOLARITY Wrap Burst WRAPBURST Page Length ATTACHEDDEVICEPAGELENGTH 19 3 : Single Word Using Spansion Flash with TI Sitara TM - AM3517 based Address Latch Figure 21. AL-J Asynchronous Single Read Waveform Generation 20 Using Spansion Flash with TI Sitara TM - AM3517 based 3.4 GPMC Interface to 16-bit, ADM, Synchronous NOR Flash Below shows interface between GPMC and Spansion ADM Synchronous NOR Flash devices S29VS-R (256Mbit, 128Mbit, 64Mbit) S29NS-R (512Mbit) devices. Figure 22. GPMC Interface to Spansion ADM Synchronous Devices Spansion ADM NOR Flash Device features are as below. Features S29VS064R Voltage 104MHz Initial Access Time 80ns Boot Mode Erase Block Size Burst Length Write Protection Pin (WP#) 21 S29NS512R 1.8V Max Synch. Speed Bank # S29VS128R / S29VS256R 108MHz 104MHz 75ns 4 8 16 Top Top or Bottom Uniform 64KB : Main 128KB : Main 128KB 16KB : Boot 32KB : Boot 8-, 16-Word Linear Burst with Wrap and Continuous Not Available Using Spansion Flash with TI Sitara TM - AM3517 based Figure 23. VS-R AC Characteristics for Synchronous Burst Read Figure 24. VS-R Synchronous Read Waveform 22 Using Spansion Flash with TI Sitara TM - AM3517 based Figure 25. Wait State and Frequency for VS-R We can find below register settings to run, given 104MHz GPMC_FCLK (9.615ns clock duration). Signal Parameter Value and Description CLK GPMCFCLKDIVIDER 0x00 : Clock divider radio 1:1 GPMC_CLK = GPMC_FCLK CLKACTIVATIONTIME 0x01 (1 clock delay ) : GPMC_CLK output delay count RDCYCLETIME 0x0B : ReadAccessTime + 1clock = 11 clocks to generate 105.76ns RDACCESSTIME CSONTIME 0x0A : 92.215ns = ClkActiavationTime + tIACC + DataSetuptTime (9.615ns + 75ns + 7.6ns) >> 10 clocks to make 96.12ns 0x0 : Immediate Assert with Read Cycle CSRDOFFTIME 0x0B : Same with RDCYCLETIME ADVONTIME 0x0 : Immediate Assert with Read Cycle ADVEXTRADELAY 0x1 : nADV half clock delay of GPMC_FCLK ADVOFFTIME OEONTIME nADV De-asserted Count : Provide AVD assertion duration with 1 cycle 0x04 : Assert after 3 clocks OEOFFTIME 0x0B : Same with CSRDOFFTIME PageBurstAccess PAGEBURSTACCESSTIME 0x01 : tBACC = 7.6ns >> 1 clock access time WAIT Monitor WAITMONITORINGTIME 0x1 : one cycle before valid data WAIT Polarity WAITxPINPOLARITY 0x0 : Active Low Wrap Burst WRAPBURST 1 : Wrap Burst Enable Page Length ATTACHEDDEVICEPAGELENGTH Read Op nCS nADV nOE 23 2 : 16 words burst size Using Spansion Flash with TI Sitara TM - AM3517 based Figure 26. VS-R Synchronous Read Waveform Generation 24 Using Spansion Flash with TI Sitara TM - AM3517 based 3.5 GPMC Interface to 16-bit, ADP, Synchronous NOR Flash Below shows interface between GPMC and Spansion ADP Synchronous NOR Flash devices S29WS-R (64Mbit) S29WS-P (128Mbit, 256Mbit, 512Mbit) Figure 27. GPMC Interface to Spansion ADP Synchronous Devices Spansion S29WS-P and S29WS-R ADP NOR Flash Device features are shown as below. Features S29WS064R Voltage S29WS128P / 29WS256P / S29WS512P 1.8V Max Synch. Speed 108MHz 104MHz Initial Access Time 80ns Depending on burst speed 4 16 Top or Bottom Top and Bottom 64KB : Main 128KB : Main 16KB : Boot 32KB : Boot Bank # Boot Mode Erase Block Size Burst Length Write Protection Pin (WP#) 25 8-, 16-Word Linear Burst with Wrap and Continuous Not Available Available Using Spansion Flash with TI Sitara TM - AM3517 based Figure 28. WS-P AC Characteristics for Synchronous Burst Read Figure 29. WS-P Synchronous Read Waveform 26 Using Spansion Flash with TI Sitara TM - AM3517 based Figure 30. Wait State and Frequency for WS-P We can find below register settings to run, given 104MHz GPMC_FCLK (9.615ns clock duration). Signal Parameter Value and Description CLK GPMCFCLKDIVIDER 0x00 : Clock divider radio 1:1 GPMC_CLK = GPMC_FCLK CLKACTIVATIONTIME 0x02 (2 clock delay) : GPMC_CLK output delay count RDCYCLETIME 0x0C : ReadAccessTime + 1clock = 12 clocks to generate 115ns RDACCESSTIME CSONTIME 0x0C : 122.98ns = Addr Latch + ClkActiavationTime + tIACC(11CLK and tBACC) = 9.615ns + 9.615ns + ((11-1)x9.615ns + 7.6ns) >> 12 clocks to make 122.98ns 0x0 : Immediate Assert with Read Cycle CSRDOFFTIME 0x0D : Same with RDCYCLETIME ADVONTIME 0x0 : Immediate Assert with Read Cycle ADVEXTRADELAY 0x1 : nADV half clock delay of GPMC_FCLK ADVOFFTIME OEONTIME 0x02 : nADV De-asserted Count with 2 cycles st nd (1 : Address Latch, 2 : Address Capture on Processor) 0x04 : Assert after 4 clocks OEOFFTIME 0x0D : Same with CSRDOFFTIME PAGEBURSTACCESSTI ME WAITMONITORINGTI ME WAITxPINPOLARITY 0x01 : tBACC = 7.6ns >> 1 clock access time WRAPBURST 1 : Wrap Burst Enable ATTACHEDDEVICEPA GELENGTH 2 : 16 words burst size Read Op nCS nADV nOE PageBurst Access WAIT Monitor WAIT Polarity Wrap Burst Page Length 27 0x1 : one cycle before valid data 0x0 : Active Low Using Spansion Flash with TI Sitara TM - AM3517 based Address Latch Figure 31. WS-P Synchronous Read Waveform Generation 28 Using Spansion Flash with TI Sitara TM - AM3517 based Intentionally Blank 29 Using Spansion Flash with TI Sitara TM - AM3517 based Using Spansion Flash with TI SitaraTM – AM3517 based 30