AN99207
Understanding AC Characteristics
Author: Russell Hanabusa
AN99207 provides a basic explanation of AC characteristics and clarifies some frequently misunderstood ones tOE, tACC, tCE,
tPACC, tIACC, tBACC, and tRDYS.
1
Introduction
Obtaining the maximum performance from Flash devices requires a clear understanding of their AC
characteristics. AC characteristics define the bus cycle timing of the Flash. This application note provides a basic
explanation of AC characteristics and clarifies some frequently misunderstood ones tOE, tACC, tCE, tPACC, tIACC,
tBACC, and tRDYS.
2
The System and the Flash
Figure 1 shows a simplified block diagram of a Flash connected to the ‘System’. The ‘System’ block represents all
the non-Flash parts of the circuit. This includes the microprocessor, power supply, printed circuit board, and other
components.
Figure 1. System and Flash Block Diagram
CLK
ADDR
The System
CE#
FLASH
RDY
DATA
Flash data sheets are written from the point-of-view of the Flash and define two things:
1.
What the Flash will provide to the System.
2.
What the Flash requires of the System.
Figure 1 shows examples of the three types of Flash signals: Input (CLK), Output (RDY), and Bi-directional
(DATA).
Input — The CLK, ADDR, and CE# are input signals to the Flash. For an input signal, the data sheet defines what
the Flash requires of the System.
Output — The RDY signal is an output from the Flash. For an output signal, the data sheet defines what the Flash
will provide to the System.
Bi-directional — The DATA signals are bi-directional. At times they are inputs to the Flash and at other times
they are outputs. For bi-directional signals, the data sheet defines what the Flash requires and provides in each of
these modes respectively.
In the following sub-sections some simple examples of the AC characteristics for the CLK and RDY signals are
discussed.
www.cypress.com
Document No. 001-99207 Rev. *A
1
Understanding AC Characteristics
2.1
CLK – tCLK
CLK is an input to Burst mode Flash devices. The t CLK AC timing characteristic defines the time period
requirements that the System must satisfy. For example, a 108 MHz S29WS256P has a minimum clock period
tCLK of 9.26 [ns]. See Figure 2. CLK has additional requirements such as the minimum high and low times and
slew rate.
Figure 2. Minimum CLK Period
For a 108 MHz Flash the minimum period is 9.26 [ns]
tCLK
CLK
2.2
RDY – tRDY
RDY is a Flash output. See Figure 3. For the S29WS-P family tRDY defines the maximum delay in from the fall of
CE# until the Flash has activated its RDY output. When the RDY output is activated the Flash is ready to drive it.
This does not mean that the RDY output is driven high, or low, or Hi-Z. It only means that at this time the Flash can
drive it. The System designer must wait until the RDY signal is activated before he can assume the Flash has
control over it. Note that the tRDY characteristic applies in both asynchronous and synchronous mode.
Figure 3. Asynchronous Mode tRDY
CE#
RDY
Hi-Z
tRDY
For the S 29WS256P t RDY defined the maximum time
delay after CE # goes low unit the Flash RDY signal is
activated (ready to be driven ).
3
Asynchronous Read – AC Characteristic
The following sub-sections discuss some asynchronous mode AC characteristics. Asynchronous mode does not
use the CLK signal in defining bus cycle timing.
3.1
tACC, tOE, and tCE
The AC characteristics tACC, tOE, and tCE are used in asynchronous reads. The time when valid read data can first
be expected is determined by the satisfaction of all of the AC characteristics involved in an asynchronous read
bus cycle.
The following defines tACC, tOE, and tCE.
tACC — The memory access time from stable address to data output valid provided that all other relevant AC
timing characteristics are satisfied.
tOE —The data buffer output delay from OE# low to data output valid provided that all other relevant AC timing
characteristics are satisfied.
tCE — The memory access time from CE# low to data output valid provided that all other relevant AC timing
characteristics are satisfied.
It is a common misunderstanding that output read data should be valid after the tOE time period without satisfying
the other AC characteristic like tACC and tCE.
www.cypress.com
Document No. 001-99207 Rev. *A
2
Understanding AC Characteristics
Figure 4 shows a simplified S29WS128J asynchronous read bus cycle. Only tACC, tOE, and tCE are considered. In
this example all three of the following things happen at the same time:
Address becomes stable.
CE# goes low.
OE# goes low.
Figure 4. S29WS128J Asynchronous Read Timing
t ACC = 55[ns]
ADDR
Address Stable
t CE = 55[ns]
CE#
OE#
tOE =
11.2[ns]
33.2[ns]
Output Valid
DATA
t ACC, t OE, and tCE
During an asynchronous read valid output data can not be expected until the AC
characteristics t ACC, t OE, and tCE are all satisfied. This is shown by the vertical bar
(within the oval) that joins the satisfaction of all three of these AC characteristics
together with the beginning of ‘Output Valid’.
In Figure 4 valid read data can not be expected by 11.2 [ns] after OE# goes low. The output data will not be
assured valid until 55 [ns] after CE# and OE# both go low. This is because tACC and tCE must also be satisfied.
The blue oval around the vertical bar emphasizes that all three AC characteristics must be satisfied before valid
read data can be expected. Even if OE# went low as much as 43.8 [ns] after CE# went low it still would not make
the read data become valid any earlier.
To measurement tOE both tACC and tCE should both be satisfied before OE# is brought low as shown in Figure 5.
Note that Figure 5 does not mean that it will always take 66.2 [ns] (55+11.2) to access memory. Only if the ADDR,
CE#, and OE# signals are changed as show in Figure 5 will this be so. As shown in Figure 4, reads can be faster.
Figure 5. True Measurement of tOE
t ACC = 55[ns]
ADDR
CE#
Address Stable
t CE = 55[ns]
t OE
OE#
DATA
Output Valid
True measurement of t OE.
www.cypress.com
Document No. 001-99207 Rev. *A
3
Understanding AC Characteristics
3.2
Page Mode Initial Read Access Time – tACC
Page mode devices have the main memory divided into pages. This allows for faster data read because all of the
addresses of a given page can be read in the same bus cycle just by changing the address bits as shown in
Figure 6.
However, the first read of data (DATA 1) from a given page is slower when compared to the following ones (DATA
5, and DATA 2). This is because the first read must allow for the initial read access time, tACC, which takes longer
than the same page read access time, tPACC. Note that page mode bus cycles must still allow for all the other AC
timing characteristics too. Burst mode devices use tACC when they are in asynchronous mode.
Figure 6. Page Mode Asynchronous Read Bus Cycle – tACC and tPACC
CE#
ADDR
Stable page address
Different address same page
DATA
DATA 1
t ACC
Different address same page
DATA 5
tPACC
DATA 2
t PACC
OE#
t PACC is the maximum time delay after a change in address to valid
read data provided that the page address remains the same .
3.3
Same Page Read – tPACC
The tPACC characteristic is provided by Page mode devices like the S29GL128. For a Same Page Read, tPACC
defines the time from stable ADDR until valid data output. In Figure 6, three different memory addresses of the
same page are read in random order. The first data DATA_1 is assured valid by the longer initial access time tACC
while DATA_5 and DATA_2 will be valid by the shorter Page access time tPACC.
So long as the read bus cycle is not terminated, other addresses in the memory page can be read randomly.
Reading addresses from a different page will terminate the current page read bus cycle and tACC is required to
read data.
For an address to remain on the same page only the lowest few address bits are allowed to change. The identity
of these changeable address bits depends on the device page size and its mode (word or byte). For example, if
the page size is 16 bytes and the device is in byte mode then the page address bits are A2, A1, A0, and A-1.
For more information on Page mode refer to the Cypress® Application Note, “Understanding Page mode Flash
Memory Devices”.
3.4
Burst Mode Initial Read Access Time – tIACC
Figure 7 shows a block diagram for a Synchronous Flash and the System. In synchronous bus cycles CLK is used
to define bus timing.
Figure 7. Synchronous Block Diagram
CE#
CLK
ADDR
System
AVD#
Synchronous
Flash
DATA
OE#
RDY
The Circuit
www.cypress.com
Document No. 001-99207 Rev. *A
4
Understanding AC Characteristics
3.5
tIACC
The tIACC (not equal tACC) characteristic defines the time delay between the first active (rising) clock edge when
CE# and AVD# are both low until the first data of a burst read, D0, is valid. A burst read bus cycle for an 80 MHz
S29WS064J is shown in Figure 8.
Figure 8. S29WS064J Synchronous Burst Read Bus Cycle - tIACC
For the S29WS 064J tBACC is the delay from the
active clock edge to data valid for data beats
following D0 provided that RDY remains high.
Six Wait States are used.
CE#
CLK
AVD#
ADDR
12 .5ns
80 MHz
ADDR Valid
WS 1
WS2
WS3
WS4
WS5
WS6
tBDH = 2.0 [ns]
tIACC = 71 [ns]
t BACC = 9.1 [ns]
D0
DATA
D1
D2
D3
D4
OE #
t RACC = 9.1 [ns]
RDY
For the S29WS064 J the 1 st
data beat (D0) of the burst
read is valid after tIACC .
RDY has been configured to assert on the rising CLK edge as soon as output
data becomes valid. RDY is a totem pole output in synchronous mode.
Burst Read performance is increased by minimizing the number of wait states needed for the first read of data,
D0. Every active clock edge from AVD# low until D0 is valid is another wait state. In Figure 8 the number of
needed wait states is 6. D0 becomes valid during WS6.
Shown below is an equation for calculating the minimum number of wait states. The number of wait states is equal
to the initial access time, tIACC, divided by the clock period, tCLK, and the result rounded up to the next whole
number.
wait states = rounded up ( tIACC / tCLK )
Using tIACC equals 71 [ns] and tCLK equals 12.5[ns]:
wait states = rounded up ( 71 / 12.5 )
wait states = rounded up ( 5.68 )
wait states = 6
The System can have other time factors that could increase the number of wait states. For example, data setup
time, propagation delays, and clock skew will add other time factors to the wait state calculation. In most cases
their effect is to add to the delay when DO is valid at the System processor. For such factors their delays are
grouped together under the label ‘other_time_factors’. The above equation is modified as follows:
wait states = rounded up { ( tIACC + other_time_factors ) / tCLK }
3.6
Burst Access Time – tBACC
As shown in Figure 8 above, tBACC defines the maximum time delay between the active clock edge and the next
data beat provided that the Flash continues to assert RDY. The Flash uses the CLK signal to increment an internal
address counter. In Figure 8 the Flash outputs the next sequential data beats D1, D2, and D3 after tBACC time
from the active edge of the CLK. The tBDH characteristic is the minimum data hold time.
Note that the S29WS128J will pulse the RDY signal low and insert wait states when needed to handle the initial
access delay and the crossing of internal memory boundaries. The System used the RDY signal to wait until the
next burst data is valid.
www.cypress.com
Document No. 001-99207 Rev. *A
5
Understanding AC Characteristics
3.7
tRDYS
As shown in Figure 9, tRDYS is the minimum amount of time the Flash will assert RDY before the next active clock
edge. Figure 9 shows a waveform of with tRDYS for a S29WS256 66 Mhz device with a clock of 66 MHz.
Figure 9. Synchronous Burst Read Bus Cycle - tRDYS
CE#
CLK
tCLK
DATA
DATA 1
DATA 0
DATA 2
DATA 3
tBDH = 2.0 [ns]
OE#
tRACC
RDY
tRDYS = 4 [ns]
This minimum time for tRDYS is defined by taking the minimum allowed clock period, tCLK, and subtracting the
maximum data RDY assertion time, tRACC.
tCLK - tRACC = tRDYS
or
tRDYS = tCLK - tRACC
tRDYS = 15.2 [ns] - 11.2 [ns] = 4 [ns]
For more information on Synchronous mode refer to the Cypress Application Note, “Understanding Burst mode
NOR Flash Devices”.
4
Additional Delays
The System contains sources of delay other than just the active devices like trace delays, and load capacitance,
and more. The effects of these sources must be accounted for in bus cycle timing.
5
Things to Remember
All of the involved AC timing characteristics must be satisfied.
All sources of delay must be considered in bus cycle timing.
The System must be able to handle a transition of a Flash signal at anytime within the signal's minimum and
maximum transition times.
www.cypress.com
Document No. 001-99207 Rev. *A
6
Understanding AC Characteristics
Document History Page
Document Title: AN99207 - Understanding AC Characteristics
Document Number: 001-99207
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
–
–
12/12/2007
Initial version
*A
4958611
MSWI
10/12/2015
Updated in Cypress template
www.cypress.com
Document No. 001-99207 Rev. *A
7
Understanding AC Characteristics
Worldwide Sales and Design Support
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturers’ representatives, and distributors. To find the
office closest to you, visit us at Cypress Locations.
#
999
Products
PSoC® Solutions
Automotive..................................cypress.com/go/automotive
psoc.cypress.com/solutions
Clocks & Buffers ................................ cypress.com/go/clocks
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Interface......................................... cypress.com/go/interface
Cypress Developer Community
Lighting & Power Control ............cypress.com/go/powerpsoc
Memory........................................... cypress.com/go/memory
PSoC ....................................................cypress.com/go/psoc
Touch Sensing .................................... cypress.com/go/touch
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
USB Controllers ....................................cypress.com/go/USB
Wireless/RF .................................... cypress.com/go/wireless
MirrorBit®, MirrorBit® Eclipse™, ORNAND™, EcoRAM™ and combinations thereof, are trademarks and registered trademarks of Cypress Semiconductor Corp. All
other trademarks or registered trademarks referenced herein are the property of their respective owners.
Cypress Semiconductor
198 Champion Court
San Jose, CA 95134-1709
Phone:
Fax:
Website:
408-943-2600
408-943-4730
www.cypress.com
© Cypress Semiconductor Corporation, 2007-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation
assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or
other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant
to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a
malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application
implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
This Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive,
non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating
custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without
further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein.
Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in
significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in
doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
www.cypress.com
Document No. 001-99207 Rev. *A
8