Data Sheet

74LV164-Q100
8-bit serial-in/parallel-out shift register
Rev. 2 — 18 September 2014
Product data sheet
1. General description
The 74LV164-Q100 is a low-voltage, Si-gate CMOS device and is pin and function
compatible with the 74HC164-Q100 and 74HCT164-Q100.
The 74LV164-Q100 is an 8-bit edge-triggered shift register with serial data entry and an
output from each of the eight stages. Data is entered serially through one of two inputs
(DSA or DSB). Either input can be used as an active HIGH enable for data entry through
the other input. Both inputs must be connected together or an unused input must be tied
HIGH.
Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP).
It enters Q0, which is the logical AND-function of the two data inputs (DSA and DSB).
Data inputs DSA and DSB, existed one set-up time prior to the rising clock edge.
A LOW on the master reset input (MR) overrides all other inputs and clears the register
asynchronously, forcing all outputs LOW.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +85 C and from 40 C to +125 C
 Wide operating voltage: 1.0 V to 5.5 V
 Optimized for low-voltage applications: 1.0 V to 3.6 V
 Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V
 Typical output ground bounce < 0.8 V at VCC = 3.3 V and Tamb = 25 C
 Typical HIGH-level output voltage (VOH) undershoot: > 2 V at VCC = 3.3 V and
Tamb = 25 C
 Gated serial data inputs
 Asynchronous master reset
 ESD protection:
 MIL-STD-883, method 3015 exceeds 2000 V
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads;
body width 3.9 mm
SOT108-1
74LV164PW-Q100 40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74LV164BQ-Q100 40 C to +125 C
DHVQFN14
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 14 terminals;
body 2.5  3  0.85 mm
SOT762-1
74LV164D-Q100
4. Functional diagram
65*
&
5
'
'6$
'6%
&3
05
4
4
4
4
4
4
4
4
DDF
DDF
Fig 1.
Logic symbol
Fig 2.
'6$
'6%
&3
05
IEC logic symbol
%,76(5,$/ ,13$5$//(/ 287
6+,)75(*,67(5
4 4 4 4 4 4 4 4
DDF
Fig 3.
Functional diagram
74LV164_Q100
Product data sheet
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Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
2 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
5. Pinning information
5.1 Pinning
/94
'6$
WHUPLQDO
LQGH[DUHD
9&&
/94
9&&
'6%
4
'6%
4
4
4
4
4
4
4
4
4
4
9&&
4
4
05
4
*1'
&3
&3
4
*1'
4
'6$
05
DDD
7UDQVSDUHQWWRSYLHZ
DDD
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to VCC.
Fig 4.
Pin configuration SO14 and TSSOP14
Fig 5.
Pin configuration DHVQFN14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
DSA
1
data input SA
DSB
2
data input SB
Q0
3
output 0
Q1
4
output 1
Q2
5
output 2
Q3
6
output 3
GND
7
ground (0 V)
CP
8
clock input (edge triggered LOW-to-HIGH)
MR
9
master reset input (active LOW)
Q4
10
output 4
Q5
11
output 5
Q6
12
output 6
Q7
13
output 7
VCC
14
supply voltage
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
3 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
6. Functional description
Table 3.
Function table[1]
Operating mode
Input
Output
MR
CP
DSA
DSB
Q0
Q1 to Q7
Reset (clear)
L
X
X
X
L
L to L
Shift
H

l
l
L
q0 to q6
H

l
h
L
q0 to q6
H

h
l
L
q0 to q6
H

h
h
H
q0 to q6
[1]
H = HIGH voltage level;
L = LOW voltage level;
 = LOW-to-HIGH clock transition;
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition;
l = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition;
q = lower case letter indicates the state of referenced input one set-up time prior to the LOW-to-HIGH CP transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
Max
Unit
0.5
+7.0
V
-
20
mA
-
50
mA
-
25
mA
IO
output current
ICC
supply current
-
50
mA
IGND
ground current
-
50
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
-
500
mW
[1]
[2]
output source or sink current,
VO = 0.5 V to (VCC + 0.5 V)
[1]
Min
Tamb = 40 C to +125 C
[2]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
TSSOP14 package: Ptot derates linearly with 5.5 mW/K above 60 C.
DHVQFN14 package: Ptot derates linearly with 4.5 mW/K above 60 C.
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
4 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
8. Recommended operating conditions
Table 5.
Symbol
Recommended operating conditions
Parameter
Conditions
[1]
VCC
supply voltage
VI
input voltage
VO
output voltage
Tamb
ambient temperature
in free air
tr
rise time
input
fall time
tf
[1]
Min
Typ
Max
Unit
1.0
3.3
5.5
V
0
-
VCC
V
0
-
VCC
V
40
-
+125
C
VCC = 1.0 V to 2.0 V
-
-
500
ns/V
VCC = 2.0 V to 2.7 V
-
-
200
ns/V
VCC = 2.7 V to 3.6 V
-
-
100
ns/V
VCC = 3.6 V to 5.5 V
-
-
50
ns/V
input
VCC = 1.0 V to 2.0 V
-
-
500
ns/V
VCC = 2.0 V to 2.7 V
-
-
200
ns/V
VCC = 2.7 V to 3.6 V
-
-
100
ns/V
VCC = 3.6 V to 5.5 V
-
-
50
ns/V
The static characteristics are guaranteed from VCC = 1.2 V to VCC = 5.5 V. LV devices are guaranteed to function down to VCC = 1.0 V
(with input levels GND or VCC).
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Tamb = 40 C to +85
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
74LV164_Q100
Product data sheet
Conditions
Min
Typ
Max
Unit
C[1]
VCC = 1.2 V
0.9
-
-
V
VCC = 2.0 V
1.4
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
VCC = 4.5 V to 5.5 V
0.7  VCC -
-
V
VCC = 1.2 V
-
-
0.3
V
VCC = 2.0 V
-
-
0.6
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3  VCC V
lO = 100 A; VCC = 1.2 V
-
1.2
-
V
lO = 100 A; VCC = 2.0 V
1.8
2.0
-
V
lO = 100 A; VCC = 2.7 V
2.5
2.7
-
V
VI = VIH or VIL
lO = 100 A; VCC = 3.0 V
2.8
3.0
-
V
lO = 6 mA; VCC = 3.0 V
2.4
2.82
-
V
lO = 100 A; VCC = 4.5 V
4.3
4.5
-
V
lO = 12 mA; VCC = 4.5 V
3.6
4.2
-
V
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Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
5 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
VOL
VI = VIH or VIL
LOW-level output voltage
Min
Typ
Max
Unit
IO = 100 A; VCC = 1.2 V
-
0
-
V
IO = 100 A; VCC = 2.0 V
-
0
0.2
V
IO = 100 A; VCC = 2.7 V
-
0
0.2
V
IO = 100 A; VCC = 3.0 V
-
0
0.2
V
IO = 6 mA; VCC = 3.0 V
-
0.25
0.40
V
IO = 100 A; VCC = 4.5 V
-
0
0.2
V
IO = 12 mA; VCC = 4.5 V
-
0.35
0.55
V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
A
ICC
supply current
quiescent: VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
20.0
A
ICC
additional supply current
quiescent, per input: VI = VCC  0.6 V;
VCC = 2.7 V to 3.6 V
-
-
500
A
CI
input capacitance
-
3.5
-
pF
VCC = 1.2 V
0.9
-
-
V
VCC = 2.0 V
1.4
-
-
V
VCC = 2.7 V to 3.6 V
2.0
-
-
V
Tamb = 40 C to +125 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
74LV164_Q100
Product data sheet
VCC = 4.5 V to 5.5 V
0.7  VCC -
-
V
VCC = 1.2 V
-
-
0.3
V
VCC = 2.0 V
-
-
0.6
V
VCC = 2.7 V to 3.6 V
-
-
0.8
V
VCC = 4.5 V to 5.5 V
-
-
0.3  VCC V
lO = 100 A; VCC = 1.2 V
-
-
-
V
lO = 100 A; VCC = 2.0 V
1.8
-
-
V
lO = 100 A; VCC = 2.7 V
2.5
-
-
V
lO = 100 A; VCC = 3.0 V
2.8
-
-
V
lO = 6 mA; VCC = 3.0 V
2.2
-
-
V
lO = 100 A; VCC = 4.5 V
4.3
-
-
V
lO = 12 mA; VCC = 4.5 V
3.5
-
-
V
IO = 100 A; VCC = 1.2 V
-
-
-
V
IO = 100 A; VCC = 2.0 V
-
-
0.2
V
IO = 100 A; VCC = 2.7 V
-
-
0.2
V
IO = 100 A; VCC = 3.0 V
-
-
0.2
V
IO = 6 mA; VCC = 3.0 V
-
-
0.5
V
IO = 100 A; VCC = 4.5 V
-
-
0.2
V
IO = 12 mA; VCC = 4.5 V
-
-
0.65
V
VI = VIH or VIL
VI = VIH or VIL
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
6 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min
Typ
Max
Unit
ILI
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
A
ICC
supply current
quiescent: VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
160
A
ICC
additional supply current
quiescent, per input: VI = VCC  0.6 V;
VCC = 2.7 V to 3.6 V
-
-
850
A
[1]
All typical values are measured at Tamb = 25 C.
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; RL = 1 k; for test circuit, see Figure 9.
Symbol Parameter
Tamb = 40 C to +85
tpd
Conditions
Min
Typ
Max
Unit
VCC = 1.2 V
-
75
-
ns
VCC = 2.0 V
-
26
39
ns
VCC = 2.7 V
-
19
29
ns
VCC = 3.0 V to 3.6 V
-
14
23
ns
-
12
19
ns
-
12
-
ns
VCC = 2.0 V
34
9
-
ns
VCC = 2.7 V
25
6
-
ns
VCC = 3.0 V to 3.6 V
20
5
-
ns
VCC = 4.5 V to 5.5 V
13
4
-
ns
VCC = 2.0 V
34
10
-
ns
VCC = 2.7 V
25
8
-
ns
VCC = 3.0 V to 3.6 V
20
6
-
ns
VCC = 4.5 V to 5.5 V
13
5
-
ns
VCC = 1.2 V
-
30
-
ns
VCC = 2.0 V
19
10
-
ns
VCC = 2.7 V
14
8
-
ns
VCC = 3.0 V to 3.6 V
11
6
-
ns
VCC = 4.5 V to 5.5 V
8
5
-
ns
C[1]
propagation delay
CP - see Figure 6: MR - see Figure 7
[2]
VCC = 4.5 V to 5.5 V
VCC = 3.0 V to 3.6 V; CL = 15 pF
tW
pulse width
[3]
CP - see Figure 6
MR - see Figure 7
trem
removal time
74LV164_Q100
Product data sheet
MR to CP - see Figure 7
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Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; RL = 1 k; for test circuit, see Figure 9.
Symbol Parameter
Conditions
tsu
Dn to CP - see Figure 8
th
fmax
set-up time
hold time
maximum frequency
Min
Typ
Max
Unit
VCC = 1.2 V
-
15
-
ns
VCC = 2.0 V
22
5
-
ns
VCC = 2.7 V
16
4
-
ns
VCC = 3.0 V to 3.6 V
13
3
-
ns
VCC = 4.5 V to 5.5 V
9
2
-
ns
VCC = 1.2 V
-
10
-
ns
VCC = 2.0 V
5
3
-
ns
VCC = 2.7 V
5
2
-
ns
VCC = 3.0 V to 3.6 V
5
2
-
ns
VCC = 4.5 V to 5.5 V
5
1
-
ns
14
40
-
MHz
Dn to CP - see Figure 8
see Figure 6
VCC = 2.0 V
VCC = 2.7 V
19
58
-
MHz
VCC = 3.0 V to 3.6 V
24
70
-
MHz
VCC = 4.5 V to 5.5 V
36
100
-
MHz
-
78
-
MHz
-
40
-
pF
VCC = 1.2 V
-
-
-
ns
VCC = 2.0 V
-
-
49
ns
VCC = 2.7 V
-
-
36
ns
VCC = 3.0 V to 3.6 V
-
-
29
ns
VCC = 4.5 V to 5.5 V
-
-
24
ns
VCC = 2.0 V
41
-
-
ns
VCC = 2.7 V
30
-
-
ns
VCC = 3.0 V to 3.6 V
24
-
-
ns
VCC = 4.5 V to 5.5 V
16
-
-
ns
VCC = 1.2 V
-
-
-
ns
VCC = 2.0 V
24
-
-
ns
VCC = 2.7 V
18
-
-
ns
VCC = 3.0 V to 3.6 V
14
-
-
ns
VCC = 4.5 V to 5.5 V
10
-
-
ns
VCC = 3.3 V; CL = 15 pF
CPD
power dissipation capacitance
per gate: VCC = 3.3 V
[4][5]
Tamb = 40 C to +125 C
tpd
tW
trem
propagation delay
pulse width
removal time
74LV164_Q100
Product data sheet
CP - see Figure 6: MR - see Figure 7
[2]
CP - see Figure 6: MR - see Figure 7
MR to CP - see Figure 7
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Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
8 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
Table 7.
Dynamic characteristics …continued
GND = 0 V; tr = tf  2.5 ns; CL = 50 pF; RL = 1 k; for test circuit, see Figure 9.
Symbol Parameter
Conditions
tsu
Dn to CP - see Figure 8
set-up time
hold time
th
maximum frequency
fmax
[1]
Min
Typ
Max
Unit
VCC = 1.2 V
-
-
-
ns
VCC = 2.0 V
26
-
-
ns
VCC = 2.7 V
19
-
-
ns
VCC = 3.0 V to 3.6 V
15
-
-
ns
VCC = 4.5 V to 5.5 V
10
-
-
ns
VCC = 1.2 V
-
-
-
ns
VCC = 2.0 V
5
-
-
ns
VCC = 2.7 V
5
-
-
ns
VCC = 3.0 V to 3.6 V
5
-
-
ns
VCC = 4.5 V to 5.5 V
5
-
-
ns
VCC = 2.0 V
12
-
-
MHz
VCC = 2.7 V
16
-
-
MHz
VCC = 3.0 V to 3.6 V
20
-
-
MHz
VCC = 4.5 V to 5.5 V
30
-
-
MHz
Dn to CP - see Figure 8
see Figure 6
Typical values are measured at nominal VCC and Tamb = 25 C.
[2]
tpd is the same as tPLH and tPHL.
[3]
Typical values are measured at nominal supply voltage (VCC = 3.3 V).
[4]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of the outputs.
[5]
The condition is VI = GND to VCC.
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
9 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
11. Waveforms
IPD[
9,
&3LQSXW
90
*1'
W:
W 3+/
W 3/+
92+
90
4QRXWSXW
DDF
92/
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 6.
Propagation delay clock (CP) to output (Qn), clock pulse width and maximum clock frequency
9,
90
05LQSXW
*1'
W:
IUHF
9,
&3LQSXW
90
*1'
W3+/
92+
90
4QRXWSXW
92/
DDF
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
Fig 7.
Pulse width master reset (MR), propagation delay master reset (MR) to output (Qn) and removal time
master reset (MR) to clock (CP)
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
10 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
9,
90
&3LQSXW
*1'
W VX
W VX
WK
WK
9,
90
'QLQSXW
*1'
92+
90
4QRXWSXW
92/
DDF
Measurement points are given in Table 8.
VOL and VOH are typical output voltage levels that occur with the output load.
The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 8.
Table 8.
Data set-up and hold times inputs (Dn) to clock (CP)
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
1.2 V
0.5  VCC
0.5  VCC
2.0 V
0.5  VCC
0.5  VCC
2.7 V
1.5 V
1.5 V
3.0 V to 3.6 V
1.5 V
1.5 V
4.5 V to 5.5 V
0.5  VCC
0.5  VCC
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
11 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
9&&
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Test data is given in Table 9.
Definitions for test circuit:
RL = Load resistor.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
Fig 9.
Table 9.
Test circuit for measuring switching times
Test data
Supply voltage
Input
VCC
VI
tr, tf
CL
RL
1.2 V
VCC
 2.5 ns
50 pF
1 k
tPHL, tPLH
2.0 V
VCC
 2.5 ns
50 pF
1 k
tPHL, tPLH
2.7 V
2.7 V
 2.5 ns
50 pF
1 k
tPHL, tPLH
3.0 V to 3.6 V
2.7 V
 2.5 ns
50 pF, 15 pF
1 k
tPHL, tPLH
4.5 V to 5.5 V
VCC
 2.5 ns
50 pF
1 k
tPHL, tPLH
74LV164_Q100
Product data sheet
Load
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
Test
© NXP Semiconductors N.V. 2014. All rights reserved.
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NXP Semiconductors
8-bit serial-in/parallel-out shift register
12. Package outline
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74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
13 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
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74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
14 of 19
74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
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74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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74LV164-Q100
NXP Semiconductors
8-bit serial-in/parallel-out shift register
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL
Military
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74LV164_Q100 v.2
20140918
Product data sheet
-
74LV164_Q100 v.1
Modifications:
74LV164_Q100 v.1
74LV164_Q100
Product data sheet
•
Section 2: ESD protection: MIL-STD-833 changed to MIL-STD883
20130626
Product data sheet
-
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
-
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8-bit serial-in/parallel-out shift register
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74LV164_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
17 of 19
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NXP Semiconductors
8-bit serial-in/parallel-out shift register
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74LV164_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 18 September 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
18 of 19
NXP Semiconductors
74LV164-Q100
8-bit serial-in/parallel-out shift register
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 13
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 16
Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Contact information. . . . . . . . . . . . . . . . . . . . . 18
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2014.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 18 September 2014
Document identifier: 74LV164_Q100