74HC597; 74HCT597
8-bit shift register with input flip-flops
Rev. 4 — 25 February 2016
Product data sheet
1. General description
The 74HC597; 74HCT597 is an 8-bit shift register with input flip-flops. It consists of an
8-bit storage register feeding a parallel-in, serial-out 8-bit shift register. Both the storage
register and the shift register have positive edge-triggered clocks. The shift register also
has direct load (from storage) and clear inputs. Inputs include clamp diodes that enable
the use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Input levels:
For 74HC597: CMOS level
For 74HCT597: TTL level
8-bit parallel storage register inputs
Shift register has direct overriding load and clear
ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
Specified from 40 C to +85 C and from 40 C to +125 C
Multiple package options
3. Ordering information
Table 1.
Ordering information
Type number
74HC597D
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads; body width
3.9 mm
SOT109-1
40 C to +125 C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT597D
74HC597DB
74HCT597DB
74HC597PW
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
4. Functional diagram
67&3
'
'
'
'
'
'
'
'
05
'6
67&3
05
'6
'
'
'
'
'
'
'
'
,1387
)/,3)/236
%,7
6+,)7
5(*,67(5
3/
4
,1387
)/,3
)/236
6+&3
DDD
Fig 1.
3/
6+&3
4
DDD
Functional diagram
Fig 2.
5
Logic symbol
65*
&
&
%,7
6+,)7
5(*,67(5
&
'
'
'
'
'
DDD
Fig 3.
IEC Logic symbol
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
05
6+&3
3/
67&3
'6
'
&
6
'
'
&
'
5
& 6
6
5
'
&
'
5
& 6
6
5
'
&
'
5
& 6
6
5
'
&
'
5
& 6
6
5
'
&
'
5
& 6
6
5
'
&
'
5
& 6
6
5
'
&
'
5
& 6
5
6
'
4
&
5
DDD
Fig 4.
Logic diagram
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
3 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
5. Pinning information
5.1 Pinning
+&
+&7
'
'
9&&
'
'
'6
'
3/
'
67&3
'
6+&3
'
05
*1'
4
DDD
Fig 5.
Pin configuration SO16, SSOP16 and TSSOP16
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
GND
8
ground (0 V)
Q
9
serial data output
MR
10
asynchronous master reset input (active LOW)
SHCP
11
shift register clock input (LOW-to-HIGH, edge-triggered)
STCP
12
storage register clock input (LOW-to-HIGH, edge-triggered)
PL
13
parallel load input (active LOW)
DS
14
serial data input
D0, D1, D2, D3, D4, D5, D6, D7
15, 1, 2, 3, 4, 5, 6, 7
parallel data inputs
VCC
16
supply voltage
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
6. Functional description
Function table[1]
Table 3.
Inputs
Function
STCP
SHCP
PL
MR
X
X
X
data loaded to input latches
X
L
H
data loaded from inputs to shift register
no clock edge
X
L
H
data transferred from input flip-flops to shift register
X
X
L
L
invalid logic, state of shift register is indeterminate
when signals removed
X
X
H
L
shift register cleared
X
H
H
shift register clocked Qn = Qn1, Q0 = DS
[1]
H = HIGH voltage level.
L = LOW voltage level.
X = don’t care.
= positive-going transition.
6+&3
'6
05
3/
67&3
'
+
/
/
'
/
/
/
'
+
/
/
'
/
/
/
'
+
/
+
'
+
/
+
'
/
/
/
'
+
+
/
/
4
UHVHW
VKLIW
UHJLVWHU
+
/
+
+
/
+
/
+
/ +
VHULDOVKLIW
/
/
VHULDOVKLIW
/
/
/
+
+
VHULDOVKLIW
VHULDOVKLIW
ORDGLQSXW
UHJLVWHU
Fig 6.
/
SDUDOOHOORDG
VKLIWUHJLVWHU
ORDGLQSXW
UHJLVWHU
SDUDOOHOORDG
VKLIWUHJLVWHU
SDUDOOHOORDGERWK
LQSXWDQGVKLIWUHJLVWHUV
DDD
Timing diagram
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
IIK
input clamping current
IOK
output clamping current
IO
output current
ICC
Min
Max
0.5
+7
V
VI < 0.5 V or VI > VCC + 0.5 V
-
20
mA
VO < 0.5 V or VO > VCC + 0.5 V
-
20
mA
VO = 0.5 V to (VCC + 0.5 V)
-
25
mA
supply current
-
+50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
-
500
mW
total power dissipation
Ptot
[1]
Conditions
SO16, SSOP16 and TSSOP16 packages
[1]
Unit
For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC597
74HCT597
Unit
Min
Typ
Max
Min
Typ
Max
2.0
5.0
6.0
4.5
5.0
5.5
V
input voltage
0
-
VCC
0
-
VCC
V
output voltage
0
-
VCC
0
-
VCC
V
VCC
supply voltage
VI
VO
Tamb
ambient temperature
t/V
input transition rise and fall rate
74HC_HCT597
Product data sheet
40
+25
+125
40
+25
+125
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
C
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
Typ
VCC = 2.0 V
1.5
VCC = 4.5 V
VCC = 6.0 V
40 C to +85 C 40 C to +125 C Unit
Max
Min
Max
Min
Max
1.2
-
1.5
-
1.5
-
V
3.15
2.4
-
3.15
-
3.15
-
V
4.2
3.2
-
4.2
-
4.2
-
V
74HC597
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
-
80.0
-
160.0
A
CI
input
capacitance
-
3.5
-
-
-
-
-
pF
74HCT597
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4.0 mA
3.98
4.32
-
3.84
-
3.7
-
V
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA
-
0.15
0.26
-
0.33
-
0.4
V
VI = VCC or GND;
VCC = 5.5 V
-
-
0.1
-
1.0
-
1.0
A
VOL
II
input leakage
current
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
7 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
Min
Typ
Max
Min
Max
Min
Max
-
-
8.0
-
80.0
-
160.0
A
per input pin; DS input
-
25
90
-
112.5
-
122.5
A
per input pin; Dn inputs
-
30
108
-
135
-
147
A
per input pin; PL, MR
inputs
-
150
540
-
675
-
735
A
per input pin; STCP,
SHCP inputs
-
150
540
-
675
-
735
A
-
3.5
-
-
-
-
-
pF
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
ICC
additional
supply current
VI = VCC 2.1 V;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V;
IO = 0 A
CI
40 C to +85 C 40 C to +125 C Unit
input
capacitance
10. Dynamic characteristics
Table 7.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
-
55
175
-
220
-
265
ns
VCC = 4.5 V
-
20
35
-
44
-
53
ns
VCC = 5.0 V; CL = 15 pF
-
17
-
-
-
-
-
ns
-
16
30
-
37
-
45
ns
VCC = 2.0 V
-
58
175
-
220
-
265
ns
VCC = 4.5 V
-
21
35
-
44
-
53
ns
-
17
30
-
37
-
45
ns
VCC = 2.0 V
-
80
250
-
315
-
375
ns
VCC = 4.5 V
-
29
50
-
63
-
75
ns
74HC597
tpd
propagation
delay
[1]
SHCP to Q; see Figure 7
VCC = 6.0 V
[1]
MR to Q; see Figure 8
VCC = 6.0 V
[1]
STCP to Q; see Figure 7
VCC = 5.0 V; CL = 15 pF
-
25
-
-
-
-
-
ns
VCC = 6.0 V
-
23
43
-
54
-
64
ns
VCC = 2.0 V
-
69
215
-
270
-
325
ns
[1]
PL to Q; see Figure 9
74HC_HCT597
Product data sheet
VCC = 4.5 V
-
25
43
-
54
-
65
ns
VCC = 5.0 V; CL = 15 pF
-
21
-
-
-
-
-
ns
VCC = 6.0 V
-
20
37
-
46
-
55
ns
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter
tt
tW
transition
time
pulse width
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
[2]
see Figure 9
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC = 4.5 V
-
7
15
-
19
-
22
ns
VCC = 6.0 V
-
6
13
-
16
-
19
ns
VCC = 2.0 V
80
11
-
100
-
120
-
ns
VCC = 4.5 V
16
4
-
20
-
24
-
ns
VCC = 6.0 V
14
3
-
17
-
20
-
ns
VCC = 2.0 V
80
14
-
100
-
120
-
ns
VCC = 4.5 V
16
5
-
20
-
24
-
ns
VCC = 6.0 V
14
4
-
17
-
20
-
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
VCC = 2.0 V
60
3
-
75
-
90
-
ns
VCC = 4.5 V
12
1
-
15
-
18
-
ns
VCC = 6.0 V
10
1
-
13
-
15
-
ns
STCP HIGH or LOW;
see Figure 7
SHCP HIGH or LOW;
see Figure 7
MR LOW; see Figure 8
PL LOW; see Figure 9
trec
recovery
time
74HC_HCT597
Product data sheet
MR to SHCP; see
Figure 10
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter
tsu
set-up time
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
60
8
-
75
-
90
-
ns
VCC = 4.5 V
12
3
-
15
-
18
-
ns
VCC = 6.0 V
10
2
-
13
-
15
-
ns
VCC = 2.0 V
60
11
-
75
-
90
-
ns
VCC = 4.5 V
12
4
-
15
-
18
-
ns
VCC = 6.0 V
10
3
-
13
-
15
-
ns
VCC = 2.0 V
60
11
-
75
-
90
-
ns
VCC = 4.5 V
12
4
-
15
-
18
-
ns
VCC = 6.0 V
10
3
-
13
-
15
-
ns
Dn to STCP; see
Figure 11
DS to SHCP; see
Figure 11
PL to SHCP; see
Figure 12
th
hold time
Dn to STCP; see
Figure 11
VCC = 2.0 V
5
3
-
5
-
5
-
ns
VCC = 4.5 V
5
1
-
5
-
5
-
ns
VCC = 6.0 V
5
1
-
5
-
5
-
ns
VCC = 2.0 V
5
6
-
5
-
5
-
ns
VCC = 4.5 V
5
2
-
5
-
5
-
ns
VCC = 6.0 V
5
2
-
5
-
5
-
ns
VCC = 2.0 V
6.0
29
-
4.8
-
4.0
-
MHz
VCC = 4.5 V
30
87
-
24
-
20
-
MHz
-
96
-
-
-
-
-
MHz
35
104
-
28
-
24
-
MHz
-
29
-
-
-
-
-
pF
PL, DS to SHCP; see
Figure 11
fmax
maximum
frequency
SHCP; see Figure 7
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V
CPD
power
CL = 50 pF; f = 1 MHz;
dissipation
VI = GND to VCC
capacitance
74HC_HCT597
Product data sheet
[3]
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
23
40
-
50
-
60
ns
-
20
-
-
-
-
-
ns
-
28
49
-
61
-
74
ns
-
33
57
-
71
-
86
ns
-
29
-
-
-
-
-
ns
-
30
52
-
65
-
78
ns
-
26
-
-
-
-
-
ns
-
7
15
-
19
-
22
ns
16
6
-
20
-
24
-
ns
16
7
-
20
-
24
-
ns
25
14
-
31
-
38
-
ns
20
10
-
25
-
30
-
ns
12
2
-
15
-
18
-
ns
12
5
-
15
-
18
-
ns
12
2
-
15
-
18
-
ns
12
4
-
15
-
18
-
ns
74HCT597
tpd
propagation
delay
[1]
SHCP to Q; see Figure 7
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
[1]
MR to Q; see Figure 8
VCC = 4.5 V
[1]
STCP to Q; see Figure 7
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
[1]
PL to Q; see Figure 9
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
[2]
tt
transition
time
see Figure 7
tW
pulse width
STCP HIGH or LOW;
see Figure 7
VCC = 4.5 V
VCC = 4.5 V
SHCP HIGH or LOW;
see Figure 7
VCC = 4.5 V
MR LOW; see Figure 8
VCC = 4.5 V
PL LOW; see Figure 9
VCC = 4.5 V
trec
recovery
time
MR to SHCP; see
Figure 10
VCC = 4.5 V
tsu
set-up time
Dn to STCP; see
Figure 11
VCC = 4.5 V
DS to SHCP; see
Figure 11
VCC = 4.5 V
PL to SHCP; see
Figure 12
VCC = 4.5 V
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Product data sheet
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8-bit shift register with input flip-flops
Table 7.
Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 13.
Symbol Parameter
th
hold time
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
5
1
-
5
-
5
-
ns
5
2
-
5
-
5
-
ns
30
75
-
24
-
20
-
MHz
-
83
-
-
-
-
-
MHz
-
32
-
-
-
-
-
pF
Dn to STCP; see
Figure 11
VCC = 4.5 V
PL, DS to SHCP; see
Figure 11
VCC = 4.5 V
maximum
frequency
fmax
SHCP; see Figure 7
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
[3]
power
CL = 50 pF; f = 1 MHz;
dissipation
VI = GND to VCC 1.5 V
capacitance
CPD
[1]
tpd is the same as tPLH and tPHL.
[2]
tt is the same as tTHL and tTLH.
[3]
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
IPD[
9,
67&36+&3
LQSXW
90
*1'
W:
W3+/
W3/+
92+
4RXWSXW
90
92/
DDD
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7.
Shift clock and storage clock inputs to output, propagation delays, pulse widths and maximum clock
frequency
74HC_HCT597
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74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
9,
90
05LQSXW
*1'
W:
W3+/
92+
4RXWSXW
90
92/
DDD
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8.
input (MR) to (Q), output propagation delays and (MR) pulse width
IPD[
9,
90
3/LQSXW
*1'
W:
W3/+
W3+/
92+
4RXWSXW
90
92/
W7+/
W7/+
DDD
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9.
Input (PL) to (Q), output propagation delays, PL pulse width and output transition times
9,
90
05LQSXW
*1'
WUHF
9,
6+&3LQSXW
90
*1'
DDD
Measurement points are given in Table 8.
Fig 10. Input (MR) to shift clock (SHCP) and storage clock (STCP) recovery times
74HC_HCT597
Product data sheet
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74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
9,
SRVLWLYH
'6'QLQSXW
90
*1'
9,
QHJDWLYH
'6'QLQSXW
90
*1'
WVX
WK
9,
90
6+&3LQSXW
*1'
9,
90
67&3LQSXW
*1'
WVX
WK
DDD
Measurement points are given in Table 8.
Fig 11. Hold and set-up times for (DS), (Dn) inputs to (SHCP), (STCP) inputs
9,
3/LQSXW
90
*1'
9,
90
6+&3LQSXW
*1'
WVX
WK
DDD
Measurement points are given in Table 8.
Fig 12. Set-up times for (PL) input to (SHCP) input
Table 8.
Measurement points
Type
Input
VM
Output
VI
VM
74HC597
0.5 VCC
GND to VCC
0.5 VCC
74HCT597
1.3 V
GND to 3 V
1.3 V
74HC_HCT597
Product data sheet
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Rev. 4 — 25 February 2016
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74HC597; 74HCT597
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8-bit shift register with input flip-flops
9,
W:
QHJDWLYH
SXOVH
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
9
90
90
90
W:
9&&
9&&
*
9,
92
5/
6
RSHQ
'87
&/
57
DDG
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 13. Test circuit for measuring switching times
Table 9.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC597
VCC
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HCT597
3V
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HC_HCT597
Product data sheet
Load
S1 position
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8-bit shift register with input flip-flops
12. Package outline
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74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
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74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
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74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
17 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
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Fig 16. Package outline SOT403-1 (TSSOP16)
74HC_HCT597
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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8-bit shift register with input flip-flops
13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT597 v.4
20160225
Product data sheet
-
74HC_HCT597 v.3
Modifications:
74HC_HCT597 v.3
Modifications:
74HC_HCT597_CNV v.2
74HC_HCT597
Product data sheet
•
Type numbers 74HC597N and 74HCT597N (SOT38-4) removed.
20140415
Product data sheet
-
74HC_HCT597_CNV v.2
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
19901201
Product specification
-
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
-
© NXP Semiconductors N.V. 2016. All rights reserved.
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8-bit shift register with input flip-flops
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT597
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 25 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
20 of 22
74HC597; 74HCT597
NXP Semiconductors
8-bit shift register with input flip-flops
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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Product data sheet
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Rev. 4 — 25 February 2016
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74HC597; 74HCT597
8-bit shift register with input flip-flops
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Recommended operating conditions. . . . . . . . 6
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 16
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 19
Legal information. . . . . . . . . . . . . . . . . . . . . . . 20
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 20
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Contact information. . . . . . . . . . . . . . . . . . . . . 21
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 25 February 2016
Document identifier: 74HC_HCT597