74HC164-Q100; 74HCT164-Q100 8-bit serial-in, parallel-out shift register Rev. 1 — 16 August 2013 Product data sheet 1. General description The 74HC164-Q100; 74HCT164-Q100 is an 8-bit serial-in/parallel-out shift register. The device features two serial data inputs (DSA and DSB), eight parallel data outputs (Q0 to Q7). Data is entered serially through DSA or DSB and either input can be used as an active HIGH enable for data entry through the other input. Data is shifted on the LOW-to-HIGH transitions of the clock (CP) input. A LOW on the master reset input (MR) clears the register and forces all outputs LOW, independently of other inputs. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Input levels: For 74HC164-Q100: CMOS level For 74HCT164-Q100: TTL level Gated serial data inputs Asynchronous master reset Complies with JEDEC standard no. 7A ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) Multiple package options 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register 3. Ordering information Table 1. Ordering information Type number Package 74HC164D-Q100 Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced SOT762-1 very thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 74HCT164D-Q100 74HC164PW-Q100 74HCT164PW-Q100 74HC164BQ-Q100 74HCT164BQ-Q100 4. Functional diagram SRG8 8 9 1 2 C1/ R & 1D 3 4 DSA DSB 1 2 CP MR 8 9 5 3 Q0 4 Q1 6 5 Q2 10 6 Q3 10 Q4 11 11 Q5 12 12 Q6 13 Q7 13 001aac423 Fig 1. 001aac424 Logic symbol Fig 2. DSA DSB CP MR IEC logic symbol 1 2 8 8-BIT SERIAL−IN/PARALLEL−OUT SHIFT REGISTER 9 3 4 5 6 10 11 12 13 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac425 Fig 3. Logic diagram 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 2 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register DSA D Q D CP FF1 RD DSB Q D CP FF2 RD Q D CP FF3 RD Q D CP FF4 RD Q D CP FF5 RD Q D CP FF6 RD Q D CP FF7 RD Q CP FF8 RD CP MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 001aac616 Fig 4. Functional diagram 5. Pinning information 5.1 Pinning '6$ WHUPLQDO LQGH[DUHD +&4 +&74 9&& +&4 +&74 '6% 4 '6$ 9&& 4 4 '6% 4 4 4 4 4 4 4 4 4 4 4 4 05 *1' &3 *1' 4 *1' &3 05 DDD 7UDQVSDUHQWWRSYLHZ DDD (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 5. Pin configuration SO14 and TSSOP14 74HC_HCT164_Q100 Product data sheet Fig 6. Pin configuration DHVQFN14 All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 3 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register 5.2 Pin description Table 2. Pin description Symbol Pin Description DSA 1 data input DSB 2 data input Q0 to Q7 3, 4, 5, 6, 10, 11, 12, 13 output GND 7 ground (0 V) CP 8 clock input (LOW-to-HIGH, edge-triggered) MR 9 master reset input (active LOW) VCC 14 positive supply voltage 6. Functional description Table 3. Function table[1] Operating modes Input MR CP DSA DSB Q0 Q1 to Q7 Reset (clear) L X X X L L to L Shift H l l L q0 to q6 H l h L q0 to q6 H h l L q0 to q6 H h h H q0 to q6 [1] Output H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced input one set-up time prior to the LOW-to-HIGH clock transition = LOW-to-HIGH clock transition 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 4 of 18 NXP Semiconductors 74HC164-Q100; 74HCT164-Q100 8-bit serial-in, parallel-out shift register 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA 50 mA IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC supply current - IGND ground current 50 - mA Tstg storage temperature 65 +150 C - 500 mW [2] total power dissipation Ptot [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For TSSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC164-Q100 74HCT164-Q100 Unit Min Typ Max Min Typ Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate - - 625 - - - ns/V 74HC_HCT164_Q100 Product data sheet VCC = 2.0 V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 5 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V 74HC164-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V VI = VIH or VIL IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V VI = VIH or VIL IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - - - - - pF 74HCT164-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V - 0.15 0.26 - 0.33 - 0.4 V - - 0.1 - 1 - 1 A VOL II input leakage current 74HC_HCT164_Q100 Product data sheet VI = VCC or GND; VCC = 6.0 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 6 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8 - 80 - 160 A ICC additional supply current per input pin; VI = VCC 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 100 360 - 450 - 490 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit, see Figure 10; unless otherwise specified Symbol Parameter 25 C Conditions Min 40 C to +85 C Typ Max 40 C to +125 C Unit Min Max Min Max 74HC164-Q100 tpd tPHL propagation delay HIGH to LOW propagation delay [1] CP to Qn; see Figure 7 VCC = 2.0 V - 41 170 - 215 - 255 ns VCC = 4.5 V - 15 34 - 43 - 51 ns VCC = 5.0 V; CL = 15 pF - 12 - - - - - ns VCC = 6.0 V - 12 29 - 37 - 43 ns VCC = 2.0 V - 39 140 - 175 - 210 ns VCC = 4.5 V - 14 28 - 35 - 42 ns VCC = 5.0 V; CL = 15 pF - 11 - - - - - ns - 11 24 - 30 - 36 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 60 17 - 75 - 90 - ns VCC = 4.5 V 12 6 - 15 - 18 - ns VCC = 6.0 V 10 5 - 13 - 15 - ns MR to Qn; see Figure 8 VCC = 6.0 V tt tW transition time pulse width [2] see Figure 7 CP HIGH or LOW; see Figure 7 MR LOW; see Figure 8 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 7 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit, see Figure 10; unless otherwise specified Symbol Parameter 25 C Conditions Min trec tsu th fmax recovery time set-up time hold time maximum frequency Min Max Min Max VCC = 2.0 V 60 17 - 75 - 90 - ns VCC = 4.5 V 12 6 - 15 - 18 - ns VCC = 6.0 V 10 5 - 13 - 15 - ns VCC = 2.0 V 60 8 - 75 - 90 - ns VCC = 4.5 V 12 3 - 15 - 18 - ns VCC = 6.0 V 10 2 - 13 - 15 - ns VCC = 2.0 V +4 6 - 4 - 4 - ns VCC = 4.5 V +4 2 - 4 - 4 - ns VCC = 6.0 V +4 2 - 4 - 4 - ns VCC = 2.0 V 6 23 - 5 - 4 - MHz VCC = 4.5 V 30 71 - 24 - 20 - MHz DSA, and DSB to CP; see Figure 9 DSA, and DSB to CP; see Figure 9 for Cp, see Figure 7 VCC = 5.0 V; CL = 15 pF - 78 - - - - - MHz 35 85 - 28 - 24 - MHz - 40 - - - - - pF VCC = 4.5 V - 17 36 - 45 - 54 ns VCC = 5.0 V; CL = 15 pF - 14 - - - - - ns - 19 38 - 48 - 57 ns - 16 - - - - - ns - 7 15 - 19 - 22 ns 18 7 - 23 - 27 - ns 18 10 - 23 - 27 - ns 16 7 - 20 - 24 - ns 12 6 - 15 - 18 - ns per package; VI = GND to VCC [3] propagation delay CP to Qn; see Figure 7 [1] HIGH to LOW propagation delay MR to Qn; see Figure 8 power dissipation capacitance Typ Max 40 C to +125 C Unit MR to CP; see Figure 8 VCC = 6.0 V CPD 40 C to +85 C 74HCT164-Q100 tpd tPHL tt transition time VCC = 4.5 V VCC = 5.0 V; CL = 15 pF [2] see Figure 7 VCC = 4.5 V tW pulse width CP HIGH or LOW; see Figure 7 VCC = 4.5 V MR LOW; see Figure 8 VCC = 4.5 V trec recovery time MR to CP; see Figure 8 tsu set-up time DSA, and DSB to CP; see Figure 9 VCC = 4.5 V VCC = 4.5 V 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 8 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register Table 7. Dynamic characteristics …continued GND = 0 V; tr = tf = 6 ns; CL = 50 pF; test circuit, see Figure 10; unless otherwise specified Symbol Parameter 25 C Conditions Min th hold time maximum frequency for Cp, see Figure 7 power dissipation capacitance per package; VI = GND to VCC 1.5 V VCC = 4.5 V VCC = 5.0 V; CL = 15 pF CPD Typ Max 40 C to +125 C Unit Min Max Min Max DSA, and DSB to CP; see Figure 9 VCC = 4.5 V fmax 40 C to +85 C [3] +4 2 - 4 - 4 - ns 27 55 - 22 - 18 - MHz - 61 - - - - - MHz - 40 - - - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 1/fmax VI CP input VM GND tW tPHL VOH tPLH VY VM VX Qn output VOL tTHL tTLH 001aal392 (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 7. Table 8. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output transition times and the maximum clock frequency Measurement points Type Input Output VM VM VX VY 74HC164-Q100 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT164-Q100 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 9 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register VI VM MR input GND tW frec VI CP input VM GND tPHL VOH VM Qn output VOL 001aac427 (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Waveforms showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time VI VM CP input GND t su t su th th VI VM Dn input GND VOH VM Qn output VOL 001aac428 (1) Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig 9. Waveforms showing the data set-up and hold times for Dn inputs 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 10 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register VI negative pulse tW 90 % VM VM 10 % GND tr tf tr tf VI 90 % positive pulse GND VM VM 10 % tW VCC G VI VO DUT RT CL 001aah768 Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 10. Test circuit for measuring switching times Table 9. Test data Type Input Load Test VI tr, tf CL 74HC164-Q100 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT164-Q100 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 11 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register 11. Package outline SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 D E A X c y HE v M A Z 8 14 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.35 0.014 0.0075 0.34 0.16 0.15 0.010 0.057 inches 0.069 0.004 0.049 0.05 0.244 0.039 0.041 0.228 0.016 0.028 0.024 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT108-1 076E06 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 11. Package outline SOT108-1 (SO14) 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 12 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 E D A X c y HE v M A Z 8 14 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 7 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.72 0.38 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT402-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 12. Package outline SOT402-1 (TSSOP14) 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 13 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT762-1 14 terminals; body 2.5 x 3 x 0.85 mm A B D A A1 E c detail X terminal 1 index area terminal 1 index area C e1 e 2 6 y y1 C v M C A B w M C b L 1 7 Eh e 14 8 13 9 Dh X 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A(1) max. A1 b c D (1) Dh E (1) Eh e e1 L v w y y1 mm 1 0.05 0.00 0.30 0.18 0.2 3.1 2.9 1.65 1.35 2.6 2.4 1.15 0.85 0.5 2 0.5 0.3 0.1 0.05 0.05 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC JEITA SOT762-1 --- MO-241 --- EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27 Fig 13. Package outline SOT762-1 (DHVQFN14) 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 14 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register 12. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MIL Military MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT164_Q100 v.1 20130816 Product data sheet - - 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 15 of 18 74HC164-Q100; 74HCT164-Q100 NXP Semiconductors 8-bit serial-in, parallel-out shift register 14. Legal information 14.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 14.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. 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This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT164_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 16 of 18 NXP Semiconductors 74HC164-Q100; 74HCT164-Q100 8-bit serial-in, parallel-out shift register No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 14.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 15. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT164_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 16 August 2013 © NXP B.V. 2013. All rights reserved. 17 of 18 NXP Semiconductors 74HC164-Q100; 74HCT164-Q100 8-bit serial-in, parallel-out shift register 16. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 14.1 14.2 14.3 14.4 15 16 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 16 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Contact information. . . . . . . . . . . . . . . . . . . . . 17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 16 August 2013 Document identifier: 74HC_HCT164_Q100