Supertex inc. MD1213DB1 MD1213 + TC6320 Demoboard High Speed ±100V 2A Pulser General Description Demoboard Features The MD1213DB1 can drive a transducer as a single channel transmitter for ultrasound and other applications. The demoboard consists of one MD1213 in a 12-Lead 4x4x0.9mm QFN (K6) package, combined with Supertex’s TC6320, an IC containing high voltage P- and N- channel FETs in a 8Lead SOIC package. Logic control inputs INA, INB and OE of the MD1213 are controlled via the six-pin head connector on the board. Due to the fast signal rise and fall time requirement, every ground wire of the ribbon cable must be used to connect from the logic signal source. When OE is enabled, it should recieve the same voltage as the logic source circuit’s power supply. The MD1213DB1 output waveforms can be displayed directly using an oscilloscope by connecting the scope probe to the test point TP10-1 and TP10-2 (GND). The J5 jumper can select whether or not to connect the on-board equivalentload, a 220pF 200V capacitor paralleled with a 1.0kΩ, 1W resistor. Also, a coaxial cable can be used to easily connect to the user’s transducer. ► Demonstrates one channel ultrasound transmitter ► MD1213 driving a TC6320 power MOSFET ► ±2.0 A source and sink current capability ► Logic control signal input connector ► SMA connectors for cable to a transducer ► 1.8 to 3.3V CMOS logic interface Designing a Pulser with the MD1213 Low input capacitance and fast switching speed are the important features of the MD1213’s input stage. Its logic inputs have an input impedance of about 20kΩ in parallel with 5pF, and an internal speed of around 100MHz. The output enable pin, OE, determines the threshold voltage for the input-channel level translators. The input stage logic is fully compatible with 1.8V, 2.0V, 2.5V, 3.3V, or 5.0V CMOS logic. The level translators are also compatible with these logic voltage levels, up to the MOSFET’s gate-driver voltage level, which is typically 5.0 to 12V. When OE is low, the chip disables its’ outputs, setting OUTA high and OUTB low. This condition helps to properly precharge the AC coupling capacitors that the user can optionally add in series with the gate-driver circuit of the external P/Nchannel FET pair. Block Diagram VCC VDD VDD1 VDD2 VH VH OE VCC 0 to 100V OUTA INA 1.0µF OE Level Shifter INA VSS2 VDD2 INB HVOUT VL XDCF VH 0 to 100V OUTB INB TC6320 CL RL 1.0µF MD1213 GND VSS1 VSS2 VSS Doc.# DSDB-MD1213DB1 B032114 VL VL Supertex inc. www.supertex.com MD1213DB1 The MD1213’s output stage has separate power pins that enable users to select the output signal’s high and low levels independently from the supply voltages used by the main the circuit. For example, the input logic levels could be 0V and 3.3V, and the output levels may lie anywhere in the range of ±5.0V. voltage, 2.0A peak current output capabilities, and low input capacitance (110pF maximum). The TC6320 integrates the gate-source resistors and Zener diodes that a high voltage pulse-driver requires. The high output current capability of the TC6320 MOSFET speeds output waveform rise and fall time, while their low input capacitance minimizes propagation delays. During power up/down conditions, the high voltage supplies VPP and VNN can inject transient voltages greater than 20V via the output transistor’s parasitic gate-to-source capacitances. The maximum permissible gate-to-source voltage (VGS) is ±20V. The TC6320’s integral 15 - 18V Zener diodes across its’ gate and source terminals protect against such transient voltages. But even if it is possible to slowly ramp the high voltage supplies, these Zener diodes are still crucial, as they also serve as the DC voltage restoration stage for the gates. Typically, the MD1213’s output has rise and fall times of about 6.0ns when driving a 1000pF load. The output stage is capable of peak currents of up to ±2.0A, depending on the system’s supply voltages and load capacitance. Such high currents are necessary to drive the input capacitances of the output MOSFETs for fast switching speeds. The bottom of the MD1213 12-Lead QFN package has a thermal pad for power dissipation enhancement. It must externally connect to the VSS pin on the PCB. This pad is connected internally to the substrate of the IC circuit. It must have the lowest potential voltage of the circuit at all times, including during the power up or down periods, or it could cause circuit latch-up or damage. Note that it is possible to vary the VPP and VNN voltages without making significant changes to the circuit configuration. For example, VNN can be 0V and VPP +200V for positive unipolar pulses. Or VNN can be -200V and VPP 0V for a negative unipolar pulser. If the user plans to operate the demoboard above 100V, he must adjust the bypass capacitors (C8 or C16) to a voltage rating of 200V. Due to the BV limitation of the TC6320, the differential voltage (VPP-VNN) must not be greater then 200V. The Supertex TC6320 is comprised of an N- and P-channel MOSFET pair with low threshold voltages (2.0V maximum). This 8-Lead SO packaged device features 200V breakdown Operating Supply Voltages Symbol VSS VL VDD VH Parameter Negative drive supply Positive drive supply Min Typ Max -5.5 0 0 VSS - VDD -2.0 4.5 10 12 VSS +2.0 10 VDD 1.8 3.3 Units Conditions V (VDD - VSS) ≤ 13 V (VDD - VSS) ≤ 13 5.5 V --- VCC Logic supply VPP TC6320 HV positive supply 0 - 100 V --- VNN TC6320 HV negative supply -100 - 0 V --- Board Layout Doc.# DSDB-MD1213DB1 B032114 2 Supertex inc. www.supertex.com MD1213DB1 Current Consumption Symbol Typ Units Conditions IDD 0.7 mA VDD = 12V IH 0.7 mA VH = 12V ICC 58 mA VCC = 3.3V IPP 2.4 mA VPP = 100V INN 2.5 mA VNN = -100V Waveform C, 20MHz, 8 cycles, VSS = VL = 0 Load: 220pF//1.0k Voltage Supply Power-Up Sequence 1 VCC Logic voltage supply, and all OE = INA = INB = Low 2 VDD Positive drive voltage for VDD1,2 3 VSS 0 or -5.0V negative bias voltage for VSS1,2 and IC substrate voltage 4 VL 0 to -5.0V or VSS negative driver voltage for VL 5 VH 0 to +10 or VDD positive driver voltage for VH 6 VPP/VNN +/-HV supply, slew rate not exceed 2.0V/ms Note: The power-down sequence should be the reverse of the power-up sequence above Board Connector and Test Pin Description Logic Control Signal Input Connector Pin Name Description J3-1 VCC J3-2 OE J3-3 GND J3-4 INA J3-5 GND Logic ground J3-6 INB --- Logic voltage supply for VCC MD1213 OE signal for pulser output enable, when OE=0, TC6320 P and N MOSFET both off. Logic ground --- Power Supply Connector Pin Name J1-1 VCC +3.3 logic voltage supply for VCC J1-2 VSS 0 or -5.0V negative bias supply for VSS1, VSS2 and SUB J1-3 VL J1-4 GND Power supply ground J1-5 VDD +10V positive driver voltage supply for VDD1 and VDD2 J1-6 VH +10 or +5.0V positive voltage supply for driver output stage J2-1 VPP 0 to +100V positive high voltage supply with current limiting maximum to 2.0A J2-2 GND High voltage power supply return, 0V J2-3 VNN 0 to -100V Negative high voltage supply with current limiting maximum to -2.0A Doc.# DSDB-MD1213DB1 B032114 Description 0 or -5.0V negative voltage supply for driver output stage 3 Supertex inc. www.supertex.com D1B C22 0.1 4 TP1 4 3 C1 10 16V J3 1 2 TP6 VCC VSS 1 3 5 + Doc.# DSDB-MD1213DB1 B032114 4 J1 VL 3 2 4 6 5 6 TP2 C2 10 16V TP7 3 C24 1.0 6 C27 0.1 VSS2 TP4 + C4 10 16V TP3 VH + C3 10 16V VDD C28 0.1 VSS 13 5 VSS1 SUB VDD2 VDD1 4 10 11 C20 0.1 2 VDD GND INB INA TP11 1 TP12 OE 12 TP13 U2 MD1213 + VCC C21 0.1 1 FB1 8 VL VDD VCC 1 6 7 9 D1A D2A 6 2 C25 1.0 VL OUTB OUTA VH VH 1 VSS R14 200Ω 1 R9 200Ω D2B 2 VH C10 10n 200V C9 10n 200V VL 6 D3A 1 3 3 2 D3B TP5 4 4 1 TP9 2 4 P D4 B1100-13 N TC6320 U3 2 1 2 1 VNN VPP 1 8 7 5 6 3 VPP 3 1 C5 1.0µ 100V 1 J2 2 3 3 1 J5 TP8 R10 200Ω TP10 2 C12 C8 220 1.0µ 100V D11 BAV99 C11 1.0µ 100V 4 2 1 C6 1.0µ 100V 2 VNN R15 1.0kΩ 1.0W R11 200Ω D5 B1100-13 J6 XDCR MD1213DB1 Schematic Diagram Supertex inc. www.supertex.com MD1213DB1 Waveforms Fig 1: INA, INB, OUTA, OUTB and HVOUT with 220pF//1K Load, VDD= VH=+12V, VSS= VL= 0V, VPP/VNN= +/-100V, 10MHz Fig 2: INA, INB, OUTA, OUTB and HVOUT with 220pF//1K Load, VDD= VH= +12V, VSS= VL= 0V, VPP/VNN= +/-100V, 20MHz Fig 3 :INA, INB, OUTA, OUTB and HVOUT with 220pF//1K Load, VDD= VH=+12V, VSS= VL= 0V, VPP/VNN= +/-100V, 312.5kHz Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2014 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSDB-MD1213DB1 B032114 5 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com