Supertex inc. MD1820 High Speed, Four Channel MOSFET Driver with Non-Inverting Outputs Features ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► ►► Non-inverting, four channel MOSFET driver 6.0ns rise and fall time 2.0A peak output source/sink current 1.8 to 5.0V input CMOS compatible 5.0 to 10V total supply voltage Smart logic threshold Low jitter design Four matched channels Drives two P- and two N-channel MOSFETs Outputs can swing below ground Low inductance quad flat no-lead package High performance, thermally-enhanced package Applications ►► ►► ►► ►► ►► ►► Medical ultrasound imaging Piezoelectric transducer drivers Non-Destructive Testing (NDT) PIN diode driver CCD Clock driver/buffer High speed level translator General Description The Supertex MD1820 is a high speed, four channel MOSFET driver designed to drive high voltage P- and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1820 can operate from a 1.8 to 5.0V logic interface with an optimum operating input signal range of 1.8 to 3.3V. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground-referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1820 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8V, the control logic may be powered by +5.0 and -5.0V, and the output L and H levels may be varied anywhere over the range of -5.0 to +5.0V. The output stage is capable of peak currents of up to ±2.0A, depending on the supply voltages used and load capacitance present. The PE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Second, when PE is low, the outputs are HiZ. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair. Typical Application Circuit 1.0µF 0.47µF 0.47µF VDD VH 10nF PE OUTA INA 3.3V CMOS Logic Inputs +100V +10V +10V 10nF -100V OUTB INB Supertex TC6320 OUTC INC GND VSS Supertex MD1820 VL HVOUT +10V 1.0µF OUTD IND 10nF 10nF -10V Supertex TC6320 Supertex inc. 1.0µF 1.0µF ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com MD1820 Ordering Information 16-Lead QFN Device 3.00x3.00mm body 1.00mm height (max) 0.50mm pitch MD1820 MD1820K6-G -G indicates package is RoHS compliant (‘Green’) Absolute Maximum Ratings Parameter Value VDD -VSS, Logic supply voltage Pin Configuration 16 -0.5V to +12.5V VH, Output high supply voltage VL - 0.5V to VDD +0.5V VL, Output low supply voltage VSS - 0.5V to VH+0.5V VSS, Low side supply voltage 1 -6.0V to +0.5V Logic input levels VSS - 0.5V to GND +5.5V Maximum junction temperature +125°C Storage temperature -65°C to 150°C Operating temperature -20°C to +85°C Package power dissipation 2.2W Thermal resistance (θJA)* 16-Lead QFN (K6) (top view) Product Marking 55°C/W 1820 YWLL Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Package may or may not include the following marks: Si or * 1.0oz 4-layer 3x4” PCB 16-Lead QFN (K6) DC Electrical Characteristics (V H Sym Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = “Green” Packaging = VDD = 10V, VL = VSS = GND = 0V, VPE = 3.3V, TA = 25°C) Parameter Min Typ Max Units Logic supply voltage 4.75 - 11.5 V 4.0V ≤ VDD ≤11.5V VSS Low side supply voltage -5.5 - 0 V --- VH Output high supply voltage VSS +2.0 - VDD V --- VL Output low supply voltage VSS - VDD -4.0 V --- VDD - VSS IDDQ VDD quiescent current - 60 - µA IHQ VH quiescent current - 2.0 - µA IDDQ VDD quiescent current - 0.8 - mA IHQ VH quiescent current - 2.0 - µA IDD VDD average current - 3.5 - mA IH VH average current - 10 - mA VIH Input logic voltage high VPE -0.3 - VPE V VIL Input logic voltage low 0 - 0.3 V IIH Input logic current high - 1.0 µA IIL Input logic current low - - 1.0 µA VIH PE input logic voltage high 1.70 3.30 5.25 V VIL PE input logic voltage low 0 - 0.3 V 100 - - KΩ RIN_PE PE input impedance to GND Supertex inc. Conditions No input transitions, PE = 0 No input transitions, PE = 1 One channel on at 5.0Mhz, No load For logic inputs INA, INB, INC, and IND For logic input PE ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 2 MD1820 DC Electrical Characteristics (cont.) (V H Sym Parameter = VDD = 10V, VL = VSS = GND = 0V, VPE = 3.3V, TA = 25°C) Min Typ Max Units Conditions CIN Logic input capacitance - 5.0 10 pF --- RSINK Output sink resistance - 1.5 - Ω ISINK = 50mA RSOURCE Output source resistance - 2.0 - Ω ISOURCE = 50mA ISINK Peak output sink current - 2.0 - A --- Peak output source current - 2.0 - A --- ISOURCE AC Electrical Characteristics (V H Sym tirf tPLH tPHL Parameter Input or PE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low = VDD = 10V, VL = VSS = GND = 0V, VPE = 3.3V, TA = 25°C) Min Typ Max Units Conditions - - 10 ns - 6.5 - ns - 6.5 - ns CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2.0ns Logic input edge speed requirement tr Output rise time - 7.0 - ns tf Output fall time - 7.0 - ns l tr - tf l Rise and fall time matching - 1.0 - ns l tPLH-tPHL l Propagation low to high and high to low matching - 1.0 - ns ∆tdm Propagation delay matching - ±2.0 - ns Device to device delay match tPE-ON PE on-time - - 5.0 µs tPE-OFF PE off-time - - 4.0 µs VPE = 1.7 ~ 5.25V VDD = 7.5 ~ 11.5V -20 ~ 85OC For each channel Logic Truth Table Logic Inputs Output PE IN H L VL H H VH L X High Z Supertex inc. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 3 MD1820 Simplified Block Diagram MD1820 VDD VH PE INA OUTA INB OUTB INC OUTC IND OUTD GND Detailed Block Diagram PE VSS VL MD1820 VDD VH Level Shifter VSS VDD INA Level Shifter VSS VDD OUTA VL VH VSS VDD INB VSS Level Shifter VDD OUTB VL VH VSS VDD INC VSS Level Shifter VDD OUTC VL VH VSS VDD IND Level Shifter SUB GND Supertex inc. OUTD VSS VL ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 4 MD1820 Typical Applications 2-Channel +100V to -100V Pulser +100V +10V +10V 0.1µF 0.47μF 0.47μF VDD 10nF VH To Piezoelectric Transducer PE OUTA INA 10nF OUTB INB 3.3V CMOS Logic Inputs -100V Supertex TC6320 +100V OUTC INC 0.1µF OUTD IND 0.1µF 10nF To Piezoelectric Transducer GND VSS VL 10nF Supertex MD1820 -100V 0.1µF Supertex TC6320 Single Channel ±100V to 0V Pulser +5.0V +100V +5.0V 0.1µF 0.47μF 0.47μF VDD 10nF VH To Piezoelectric Transducer PE OUTA INA 10nF -100V OUTB INB 0.1µF Supertex TC6320 3.3V CMOS Logic Inputs OUTC INC OUTD IND GND VSS VL -5.0V -5.0V 0.47μF Supertex MD1820 Supertex inc. 0.47μF Supertex TC2320 ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 5 MD1820 Timing Diagram VTH / VPE Curve VTH vs VPE 3.3V IN 50% 50% 0V tPLH OUT 0V 1.5 tPHL 10V 90% VTH 1.0 90% 10% 10% tr tf 0.5 0 Application Information For proper operation of the MD1820, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB, INC, IND, and PE pins should be connected to a logic source with a swing of GND to PE, where PE is 1.8 to 5.0V. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1820 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the powerleads. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2.0A, so they should be provided with an appropriate bypass Supertex inc. VPE/2 2.0 0 1.0 2.0 VPE 3.0 4.0 5.0 capacitor located next to the chip pins. A ceramic capacitor of up to 1.0µF may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.8V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 6 MD1820 MD1820 tr & tf vs Temperature MD1820 Delay vs Temperature 9 8 8 7 7 Time (ns) Delay Time (ns) 9 tPHL 6 5 tPLH 4 3 tr tf 6 5 4 -50 0 50 3 125 Temperature ( C) -50 0 O MD1820 Delay vs VDD MD1820 tr & tf vs VDD 14 125 14 12 12 tPHL 10 8 Time (ns) Delay Time (ns) 50 Temperature (OC) tPLH 6 4 10 tf 8 tr 6 4 2 5 8 10 12 2 5 VDD Voltage (V) 8 10 12 VDD Voltage (V) Pin Description Pin # Function Description 1 INB Logic input. 2 VDD High side supply voltage. 3 VSS Low side supply voltage. VSS is also connected to the IC substrate. It is required to connect to the most negative potential of voltage supplies. 4 INC 5 IND 6 GND 7 VL 8 OUTC 9 OUTD 10, 11 VH 12 OUTA 13 OUTB 14 VL Supply voltage for N-channel output stage. 15 PE Power enable logic input. When PE is high, sets the input logic threshold. When PE is low, all outputs are at default state (see truth table) and IC in standby mode. 16 INA Logic input. Substrate Supertex inc. Logic input. Logic input ground reference. Supply voltage for N-channel output stage. Output drivers Supply voltage for P-channel output stage. Output drivers The IC substrate is internally connected to the thermal pad. Thermal pad and VSS must be connected externally. ● 1235 Bordeaux Drive, Sunnyvale, CA 94089 ● Tel: 408-222-8888 ● www.supertex.com 7 MD1820 16-Lead QFN Package Outline (K6) 3.00x3.00mm body, 1.00mm height (max), 0.50mm pitch D 16 D2 Note 1 (Index Area D/2 x E/2) 16 1 1 e Note 1 (Index Area D/2 x E/2) E E2 b Top View Bottom View View B Note 3 θ L A A3 A1 Seating Plane L1 Note 2 Side View View B Notes: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol Dimension (mm) A A1 MIN 0.80 0.00 NOM 0.90 0.02 MAX 1.00 0.05 A3 0.20 REF b D D2 E E2 e 0.18 2.85* 1.50 2.85* 1.50 0.25 3.00 1.65 3.00 1.65 0.30 3.15* 1.80 3.15* 1.80 0.50 BSC L L1 θ 0.20† 0.00 0O 0.30† - - 0.45 0.15 14O JEDEC Registration MO-220, Variation VEED-4, Issue K, June 2006. * This dimension is not specified in the JEDEC drawing. † This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-16QFNK63X3P050, Version A092909. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.) Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http//www.supertex.com) Supertex inc. ©2012 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-MD1820 C011612 8 1235 Bordeaux Drive, Sunnyvale, CA 94089 Tel: 408-222-8888 www.supertex.com