Data Sheet

NPIC6C596-Q100
Power logic 8-bit shift register; open-drain outputs
Rev. 2 — 4 July 2013
Product data sheet
1. General description
The NPIC6C596-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage
register and open-drain outputs. Both the shift and storage register have separate clocks.
The device features a serial input (DS) and a serial output (Q7S) to enable cascading and
an asynchronous reset MR input. A LOW on MR resets both the shift register and storage
register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in
the shift register is transferred to the storage register on a LOW-to-HIGH transition of the
STCP input. If both clocks are connected together, the shift register is always one clock
pulse ahead of the storage register. To provide additional hold time in cascaded
applications, the serial output QS7 is clocked out on the falling edge of SHCP. Data in the
storage register drives the gate of the output extended-drain NMOS (EDNMOS) transistor
whenever the output enable input (OE) is LOW. A HIGH on OE causes the outputs to
assume a high-impedance OFF-state. Operation of the OE input does not affect the state
of the registers.
The open-drain outputs are 33 V/100 mA continuous current extended-drain NMOS
transistors designed for use in systems that require moderate load power such as LEDs.
Integrated voltage clamps in the outputs provide protection against inductive transients
making the device suitable for power driver applications such as relays, solenoids and
other low-current or medium-voltage loads.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
 Automotive product qualification in accordance with AEC-Q100 (Grade 1)
 Specified from 40 C to +125 C
 Low RDSon
 Eight Power EDNMOS transistor outputs of 100 mA continuous current
 250 mA current limit capability
 Output clamping voltage 33 V
 30 mJ avalanche energy capability
 Enhanced cascading for multiple stages
 All registers cleared with single input
 Low power consumption
 ESD protection:
 HBM AEC-Q100-002 revision D exceeds 2500 V
 CDM AEC-Q100-011 revision B exceeds 1000 V
NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
3. Applications
 LED sign
 Graphic status panel
 Fault status indicator
4. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
NPIC6C596PW-Q100 40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
NPIC6C596BQ-Q100 40 C to +125 C
DHVQFN16 plastic dual in-line compatible thermal enhanced
SOT763-1
very thin quad flat package; no leads; 16 terminals;
body 2.5  3.5  0.85 mm
NPIC6C596D-Q100
5. Functional diagram
15
SHCP
10
STCP
Q0
Q1
Q2
2
Q3
DS
Q4
Q5
Q6
Q7
Q7S
MR
OE
7
8
3
4
2
DS
15
SHCP
7
MR
10
STCP
8
OE
Logic symbol
NPIC6C596_Q100
Product data sheet
9
5
6
11
8-BIT STORAGE REGISTER
12
13
14
OPEN-DRAIN OUTPUTS
9
Q0 Q1 Q2
Q3 Q4 Q5 Q6 Q7
3
6
4
5
11
12
13
14
aaa-002548
aaa-002547
Fig 1.
Q7S
8-STAGE SHIFT REGISTER
Fig 2.
Functional diagram
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NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
VCC
Qn
33 V
GND
GND
aaa-002551
aaa-002550
Fig 3.
Schematic of all inputs
Fig 4.
STAGE 0
DS
D
Schematic of open-drain outputs (Qn)
STAGE 1 TO 6
Q
D
STAGE 7
Q
D
FF0
Q
STAGE 7S
CP
Q7S
FF7
CP
R
Q
D
FF7
CP
R
R
SHCP
MR
R
D
Q
R
D
FF
Q
FF
CP
CP
STCP
OE
GND
GND
aaa-002552
Q0
Fig 5.
Q1 Q2 Q3 Q4 Q5 Q6
Q7
Logic diagram
NPIC6C596_Q100
Product data sheet
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NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
7
6
5
4
3
2
1
0
SHCP
5V
GND
5V
OE
GND
5V
DS
GND
5V
STCP
GND
5V
MR
GND
Q1
VOH
VOL
aaa-002553
Fig 6.
Timing diagram
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
6. Pinning information
6.1 Pinning
VCC
1
terminal 1
index area
NPIC6C596-Q100
16 GND
NPIC6C596-Q100
DS
2
15 SHCP
VCC
1
16 GND
Q0
3
14 Q7
DS
2
15 SHCP
Q1
4
13 Q6
Q0
3
14 Q7
Q2
5
Q1
4
13 Q6
Q3
6
Q2
5
12 Q5
MR
7
Q3
6
11 Q4
MR
7
10 STCP
OE
8
11 Q4
8
9
OE
10 STCP
Q7S
9
12 Q5
GND(1)
Q7S
aaa-002555
Transparent top view
aaa-002554
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 7.
Pin configuration SO16 and TSSOP16
Fig 8.
Pin configuration DHVQFN16
6.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
VCC
1
supply voltage
DS
2
serial data input
Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7
3, 4, 5, 6, 11, 12, 13, 14
parallel data output (open-drain)
MR
7
master reset (active LOW)
OE
8
output enable input (active LOW)
Q7S
9
serial data output
STCP
10
storage register clock input
SHCP
15
shift register clock input
GND
16
ground (0 V)
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
7. Limiting values
Table 3.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Max
Unit
VCC
supply voltage
0.5
+7.0
V
VI
input voltage
VDS
drain-source voltage
power EDNMOS drain-source
voltage
0.3
+7.0
V
-
+33
V
Id(SD)
source-drain diode current
continuous
-
250
mA
-
500
mA
-
100
mA
[2]
-
250
mA
[2]
-
250
mA
non-repetitive avalanche energy single pulse; see Figure 9
[3]
-
30
mJ
IAL
avalanche current
[3]
Tstg
storage temperature
pulsed
[2]
Tamb = 25 C
drain current
ID
[1]
continuous; each output;
all outputs on
pulsed; each output;
all outputs on
single output; Tamb = 25 C
peak drain current
IDM
EAS
see Figure 9
Tamb = 25 C
total power dissipation
Ptot
-
200
mA
65
+150
C
-
800
mW
[4]
SO16
TSSOP16
-
725
mW
DHVQFN16
-
1825
mW
-
160
mW
Tamb = 125 C
SO16
[4]
TSSOP16
-
145
mW
DHVQFN16
-
365
mW
[1]
Each power EDNMOS source is internally connected to GND.
[2]
Pulse duration  100 s and duty cycle  2 %.
[3]
VDS = 15 V; starting junction temperature (Tj) = 25 C; L = 1.5 H; avalanche current (IAL) = 200 mA.
[4]
For SO16 packages: above 25 C the value of Ptot derates linearly with 6.4 mW/C.
For TSSOP16 packages: above 25 C the value of Ptot derates linearly with 5.8 mW/C.
For DHVQFN16 packages: above 25 C the value of Ptot derates linearly with 14.6 mW/C.
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
7.1 Test circuit and waveform
5V
15 V
VCC
7
15
WORD
GENERATOR(1)
2
10
8
lD
1
MR
SHCP
DUT
DS
Qn
3-6,
11-14
tAL
tw(2)
30 Ω
5V
1.5 mH
0V
lAL = 200 mA
ID
VDS
STCP
OE
V(BR)DSS = 33 V
VDS
GND
min
16
aaa-002556
(1) The word generator has the following characteristics: tr, tf  10 ns; ZO = 50 .
(2) The input pulse duration (tW) is increased until peak current IAL = 200 mA. Energy test level is defined as:
EAS = IAL  V(BR)DSS  tAL/2 = 30 mJ.
Fig 9.
Test circuit and waveform for measuring single-pulse avalanche energy
8. Recommended operating conditions
Table 4.
Recommended operating conditions
Symbol
Parameter
VCC
supply voltage
VI
input voltage
Conditions
ID
drain current
Tamb
ambient temperature
pulsed drain output current;
VCC = 5 V; Tamb = 25 C;
all outputs on
[1]
Pulse duration  100 s and duty cycle  2 %.
[2]
Technique should limit Tj  Tamb to 10 C maximum.
[1][2]
Min
Typ
Max
Unit
4.5
-
5.5
V
0
-
5.5
V
-
-
250
mA
40
-
+125
C
9. Static characteristics
Table 5.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VCC = 5.0 V; Tamb = 25 C
Conditions
Min
Typ
Max
Unit
VIH
HIGH-level input
voltage
VCC = 4.5 V to 5.5 V
0.85VCC
-
-
V
VIL
LOW-level input
voltage
VCC = 4.5 V to 5.5 V
-
-
0.15VCC
V
VOH
HIGH-level
output voltage
serial data output Q7S; VI = VIH or VIL
IO = 20 A; VCC = 4.5 V
4.4
4.49
-
V
IO = 4 mA; VCC = 4.5 V
4.0
4.2
-
V
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
Table 5.
Static characteristics …continued
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
VOL
VCC = 5.0 V; Tamb = 25 C
Conditions
LOW-level output serial data output Q7S; VI = VIH or VIL
voltage
IO = 20 A; VCC = 4.5 V
IO = 4 mA; VCC = 4.5 V
Min
Typ
Unit
Max
-
0.005
0.1
V
-
0.3
0.5
V
IIH
HIGH-level input
current
VCC = 5.5 V; VI = VCC
-
-
1
A
IIL
LOW-level input
current
VCC = 5.5 V; VI = 0 V
1
-
-
A
V(BR)DSS drain-source
breakdown
voltage
ID = 1 mA
33
37
-
V
VSD
source-drain
voltage
diode forward voltage; IF = 100 mA
-
0.85
1.2
V
ICC
supply current
logic supply current; VCC = 5.5 V;
VI = VCC or GND
-
0.004
200
A
-
0.006
500
A
-
0.75
5
mA
-
140
-
mA
-
0.002
0.2
A
-
0.15
0.3
A
-
3.0
9

5.4
12

3.1
10

all outputs off
[1]
all outputs on
all outputs off; SHCP = 5 MHz;CL = 30 pF;
see Figure 14 and Figure 16
IO(nom)
nominal output
current
VDS = 0.5 V; Tamb = 85 C; Iout = ID
IDSX
drain cut-off
current
VCC = 5.5 V; VDS = 30 V
RDSon
drain-source
on-state
resistance
[2][3][4]
VCC = 5.5 V; VDS = 30 V; Tamb = 125 C
see Figure 17 and Figure 18
[2][3]
VCC = 4.5 V; ID = 50 mA
VCC = 4.5 V; ID = 50 mA; Tamb = 125 C
VCC = 4.5 V; ID = 100 mA
-
[1]
Output currents below 250 mA current limit.
[2]
Technique should limit Tj  Tamb to 10 C maximum.
[3]
These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
[4]
Nominal output current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at Tamb = 85 C.
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
10. Dynamic characteristics
Table 6.
Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 14.
Symbol Parameter
VCC = 5.0 V; Tamb = 25 C
Conditions
Min
Typ
Max
Unit
tPLH
LOW to HIGH
propagation delay
OE to Qn; ID = 75 mA; see Figure 10 and
Figure 19
-
97
-
ns
tPHL
HIGH to LOW
propagation delay
OE to Qn; ID = 75 mA; see Figure 10 and
Figure 19
-
9
-
ns
tr
rise time
OE to Qn; ID = 75 mA; see Figure 10 and
Figure 19
-
60
-
ns
tf
fall time
OE to Qn; ID = 75 mA; see Figure 10 and
Figure 19
-
18
-
ns
tpd
propagation delay
SHCP to Q7S; ID = 75 mA; see Figure 11
[1]
-
5
-
fmax
maximum frequency
SHCP; ID = 75 mA; see Figure 11
[2]
-
-
10
trr
reverse recovery time
IF = 100 mA; dI/dt = 10 A/s;
see Figure 13
[3][4]
-
120
-
ns
ta
reverse recovery
current rise time
IF = 100 mA; dI/dt = 10 A/s;
see Figure 13
[3][4]
-
100
-
ns
tsu
set-up time
DS to SHCP; see Figure 12
15
-
-
ns
th
hold time
DS to SHCP; see Figure 12
15
-
-
ns
tW
pulse width
40
-
-
ns
[1]
[2]
ns
MHz
tpd is the same as tPLH and tPHL.
This is the maximum serial clock frequency assuming cascaded operation where serial data is passed from one stage to a second
stage. The clock period allows for SHCP → Q7S propagation delay and setup time plus some timing margin.
[3]
Technique should limit Tj  Tamb to 10 C maximum.
[4]
These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
10.1 Test circuits and waveforms
VI
OE input
VM
GND
tPLH
24 V
Qn output
LOW-to-OFF
OFF-to-LOW
VOL
tPHL
VY
VY
VX
VX
tr
tf
aaa-002557
Measurement points are given in Table 7.
VOL is the typical output voltage level that occurs with the output load.
Fig 10. The output enable (OE) input to data output (Qn) propagation delays and (Qn) output rise and fall times
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
1/fmax
VI
SHCP input
VM
GND
tW
tPLH
tPHL
VOH
VM
Q7S output
VOL
aaa-002558
Measurement points are given in Table 7.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 11. The shift clock (SHCP) to serial data output (Q7S) propagation delays with the minimum shift clock pulse
width and maximum shift clock frequency
Table 7.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
VX
VY
5V
0.5VCC
0.5VDS
0.1VDS
0.9VDS
VI
SHCP input
VM
GND
tsu
tsu
th
th
VI
DS input
VM
GND
VOH
VM
Q7S output
VOL
aaa-002559
Measurement points are given in Table 8.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VOL and VOH are the typical output voltage levels that occur with the output load.
Fig 12. The data set-up and hold times for the serial data input (DS)
Table 8.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
5V
0.5VCC
0.5VCC
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
K(1)
Qn
DUT
0.85 mH
2500 μF
250 V
0.1 A
15 V
di/dt = 10 A/μs
IF
IF
A(1)
0
t2
t1
25 % of lRM
t3
driver
RG
VI(2)
G
IRM
ta
50 Ω
trr
aaa-002560
(1) The open-drain Qn terminal under test is connected to test point K. All other terminals are connected together and connected to
test point A.
(2) The VI amplitude and RG are adjusted for dI/dt = 10 A/s. A VI double-pulse train is used to set IF = 0.1 A, where t1 = 10 s, t2 =
7 s and t3 = 3 s.
Fig 13. Test circuit and waveform for measuring reverse recovery current
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
VI
tW
90 %
negative
pulse
VM
VM
10 %
0V
tf
tr
tr
tf
VI
90 %
VM
positive
pulse
VM
10 %
0V
tW
5V
VDS = 15 V
1
7
15
WORD
GENERATOR (1)
2
10
8
VCC
MR
RL
SHCP
Qn
DS
3, 4, 5, 6
11, 12,13, 14
CL (2)
STCP
OE
GND
16
aaa-002561
(1) The word generator has the following characteristics: tr, tf  10 ns; tW = 300 ns; pulsed repetition rate (PRR) = 5 kHz; ZO = 50 .
(2) CL includes probe and jig capacitance.
Test data is given in Table 9. Definitions for test circuit:
VDS = External voltage for Power EDNMOS drain-source voltage.
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
Fig 14. Test circuit for measuring switching times
Table 9.
Test data
Supply voltage
5V
NPIC6C596_Q100
Product data sheet
Input
Load
VI
tr, tf
VM
CL
RL
5V
 10 ns
50 %
30 pF
200 
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Power logic 8-bit shift register; open-drain outputs
aaa-002562
1
aaa-002563
6
lCC
(mA)
IAL
(A)
4
10-1
2
10-2
10-1
1
0
10-1
10
1
fi (MHz)
Tamb = 25 C.
Tamb = 40 C to 125 C; VCC = 5 V.
Fig 15. Avalanche current (peak) versus time duration
of avalanche
aaa-002564
5
4
Fig 16. Supply current versus frequency
aaa-002565
5
(1)
RDSon
(Ω)
102
10
tAL (ms)
RDSon
(Ω)
4
(2)
(1)
(2)
(3)
3
3
(3)
(4)
2
2
1
(4)
1
0
0
50
100
150
200
250
300
lD (mA)
4
5
8
VI = VCC or GND and VO = open circuit.
VI = VCC or GND and VO = GND or VCC.
(1) Tamb = 125 C
(2) Tamb = 85 C
(2) Tamb = 85 C
(3) Tamb = 25 C
(3) Tamb = 25 C
(4) Tamb = 40 C
(4) Tamb = 40 C
Fig 17. Drain-source on-state resistance versus drain
current
Product data sheet
7
VCC (V)
(1) Tamb = 125 C
NPIC6C596_Q100
6
Fig 18. Static drain-source on-state resistance versus
supply voltage
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Power logic 8-bit shift register; open-drain outputs
aaa-002546
140
switching time
(ns)
120
(1)
(2)
100
(3)
80
60
(4)
40
20
0
-50
-25
0
25
50
75
100
125
Tamb (°C)
Technique should limit TJ  TC to 10 C maximum.
(1) tPLH.
(2) tr.
(3) tf.
(4) tPHL.
Fig 19. Switching time versus case temperature
NPIC6C596_Q100
Product data sheet
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Power logic 8-bit shift register; open-drain outputs
11. Package outline
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
D
E
A
X
c
y
HE
v M A
Z
16
9
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
1
L
8
e
0
detail X
w M
bp
2.5
5 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
Z (1)
mm
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
1.05
1.0
0.4
0.7
0.6
0.25
0.25
0.1
0.7
0.3
0.01
0.019 0.0100 0.39
0.014 0.0075 0.38
0.039
0.016
0.028
0.020
inches
0.010 0.057
0.069
0.004 0.049
0.16
0.15
0.05
0.244
0.041
0.228
0.01
0.01
0.028
0.004
0.012
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT109-1
076E07
MS-012
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 20. Package outline SOT109-1 (SO16)
NPIC6C596_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
15 of 21
NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
E
D
A
X
c
y
HE
v M A
Z
9
16
Q
(A 3)
A2
A
A1
pin 1 index
θ
Lp
L
1
8
e
detail X
w M
bp
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z (1)
θ
mm
1.1
0.15
0.05
0.95
0.80
0.25
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
1
0.75
0.50
0.4
0.3
0.2
0.13
0.1
0.40
0.06
8o
o
0
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT403-1
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-18
MO-153
Fig 21. Package outline SOT403-1 (TSSOP16)
NPIC6C596_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
16 of 21
NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
DHVQFN16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;
SOT763-1
16 terminals; body 2.5 x 3.5 x 0.85 mm
A
B
D
A
A1
E
c
detail X
terminal 1
index area
terminal 1
index area
C
e1
e
2
7
y
y1 C
v M C A B
w M C
b
L
1
8
Eh
e
16
9
15
10
Dh
X
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
mm
A(1)
max.
A1
b
1
0.05
0.00
0.30
0.18
c
D (1)
Dh
E (1)
Eh
0.2
3.6
3.4
2.15
1.85
2.6
2.4
1.15
0.85
e
0.5
e1
L
v
w
y
y1
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT763-1
---
MO-241
---
EUROPEAN
PROJECTION
ISSUE DATE
02-10-17
03-01-27
Fig 22. Package outline SOT763-1 (DHVQFN16)
NPIC6C596_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
17 of 21
NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
12. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CDM
Charged Device Model
CMOS
Complementary Metal Oxide Semiconductor
DUT
Device Under Test
EDNMOS
Extended Drain Negative Metal Oxide Semiconductor
ESD
ElectroStatic Discharge
HBM
Human Body Model
TTL
Transistor-Transistor Logic
13. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
NPIC6C596_Q100 v.2
20130704
Product data sheet
-
NPIC6C596_Q100 v.1
-
-
Modifications:
NPIC6C596_Q100 v.1
NPIC6C596_Q100
Product data sheet
•
Figure 5 corrected (errata).
20120712
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
18 of 21
NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
14. Legal information
14.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
14.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
14.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
NPIC6C596_Q100
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
19 of 21
NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
14.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
15. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
NPIC6C596_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 4 July 2013
© NXP B.V. 2013. All rights reserved.
20 of 21
NPIC6C596-Q100
NXP Semiconductors
Power logic 8-bit shift register; open-drain outputs
16. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
8
9
10
10.1
11
12
13
14
14.1
14.2
14.3
14.4
15
16
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 5
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
Test circuit and waveform . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
Dynamic characteristics . . . . . . . . . . . . . . . . . . 9
Test circuits and waveforms . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18
Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Contact information. . . . . . . . . . . . . . . . . . . . . 20
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 4 July 2013
Document identifier: NPIC6C596_Q100