74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register Rev. 1 — 30 January 2013 Product data sheet 1. General description The 74HC4094-Q100; 74HCT4094-Q100 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (D) and two serial outputs (QS1 and QS2) to enable cascading. Data is shifted on the LOW-to-HIGH transitions of the CP input. Data is available at QS1 on the LOW-to-HIGH transitions of the CP input to allow cascading when clock edges are fast. The same data is available at QS2 on the next HIGH-to-LOW transition of the CP input to allow cascading when clock edges are slow. The data in the shift register is transferred to the storage register when the STR input is HIGH. Data in the storage register appears at the outputs whenever the output enable input (OE) is HIGH. A LOW on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the registers. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in excess of VCC. This product has been qualified to the Automotive Electronics Council (AEC) standard Q100 (Grade 1) and is suitable for use in automotive applications. 2. Features and benefits Automotive product qualification in accordance with AEC-Q100 (Grade 1) Specified from 40 C to +85 C and from 40 C to +125 C Complies with JEDEC standard JESD7A Input levels: For 74HC4094-Q100: CMOS level For 74HCT4094-Q100: TTL level Low-power dissipation ESD protection: MIL-STD-883, method 3015 exceeds 2000 V HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 ) 3. Applications Serial-to-parallel data conversion Remote control holding register 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register 4. Ordering information Table 1. Ordering information Type number Package 74HC4094D-Q100 Temperature range Name Description Version 40 C to +125 C SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 40 C to +125 C TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm 74HCT4094D-Q100 74HC4094DB-Q100 74HCT4094DB-Q100 74HC4094PW-Q100 SOT403-1 5. Functional diagram 3 1 CP 2 1 C2 15 STR QS1 9 QS2 10 QP0 4 QP1 5 QP2 6 QP3 7 EN3 SRG8 3 C1/ 2 2D 1D 4 5 6 D 7 QP4 14 QP5 13 QP6 12 QP7 11 14 13 12 11 9 OE 10 15 Fig 1. 3 001aaf111 001aaf112 Functional diagram Fig 2. 2 3 Logic symbol D 8-STAGE SHIFT REGISTER CP QS2 QS1 1 15 STR 10 9 8-BIT STORAGE REGISTER OE 3-STATE OUTPUTS QP0 QP1 QP2 QP3 QP4 QP5 QP6 QP7 4 Fig 3. 5 6 7 14 13 12 11 001aaf119 Logic diagram 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 2 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register STAGE 0 D STAGES 1 TO 6 Q D D STAGE 7 Q D CP QS1 Q CP FF 0 D FF 7 CP CP Q QS2 LE LATCH D Q D Q LE LE LATCH 0 LATCH 7 STR OE QP2 QP0 QP1 Fig 4. QP4 QP3 001aag799 QP6 QP5 QP7 Logic diagram 6. Pinning information 6.1 Pinning +&4 +&74 675 9&& ' 2( &3 43 +&4 +&74 675 9&& ' 2( &3 43 43 43 43 43 43 43 43 43 43 46 43 43 43 46 *1' 43 43 *1' 46 DDD Fig 5. Pin configuration SO16 74HC_HCT4094_Q100 Product data sheet 46 DDD Fig 6. Pin configuration SSOP16 and TSSOP16 All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 3 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register 6.2 Pin description Table 2. Pin description Symbol Pin Description STR 1 strobe input D 2 data input CP 3 clock input QP0 to QP7 4, 5, 6, 7, 14, 13, 12, 11 parallel output VSS 8 ground supply voltage QS1, QS2 9, 10 serial output OE 15 output enable input VDD 16 supply voltage 7. Functional description Table 3. Function table[1] Inputs Parallel outputs Serial outputs CP OE STR D QP0 QPn QS1 QS2 L X X Z Z Q6S NC L X X Z Z NC Q7S H L X NC NC Q6S NC H H L L QPn 1 Q6S NC H H H H QPn 1 Q6S NC H H H NC NC NC Q7S [1] At the positive clock edge, the information in the 7th register stage is transferred to the 8th register stage and the QSn outputs. H = HIGH voltage level; L = LOW voltage level; X = don’t care; = positive-going transition; = negative-going transition; Z = HIGH-impedance OFF-state; NC = no change; Q6S = the data in register stage 6 before the LOW to HIGH clock transition; Q7S = the data in register stage 7 before the HIGH to LOW clock transition. CLOCK INPUT DATA INPUT STROBE INPUT OUTPUT ENABLE INPUT INTERNAL Q0S (FF 0) Z-state OUTPUT QP0 INTERNAL Q6S (FF 6) Z-state OUTPUT QP6 SERIAL OUTPUT QS1 SERIAL OUTPUT QS2 001aaf117 Fig 7. Timing diagram 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 4 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register 8. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter VCC supply voltage Conditions Min Max Unit 0.5 +7 V IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V - 20 mA IO output current VO = 0.5 V to (VCC + 0.5 V) - 25 mA ICC supply current - +50 mA IGND ground current - 50 mA Tstg storage temperature 65 +150 C Ptot total power dissipation - 500 mW [1] [1] For SO16: Ptot derates linearly with 8 mW/K above 70 C. For SSOP16 and TSSOP16 packages: Ptot derates linearly with 5.5 mW/K above 60 C. 9. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC4094-Q100 74HCT4094-Q100 Unit Min Typ Max Min Typ Max 2.0 5.0 6.0 4.5 5.0 5.5 V input voltage 0 - VCC 0 - VCC V output voltage 0 - VCC 0 - VCC V VCC supply voltage VI VO Tamb ambient temperature t/V input transition rise and fall rate 74HC_HCT4094_Q100 Product data sheet 40 +25 +125 40 +25 +125 VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 C © NXP B.V. 2013. All rights reserved. 5 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register 10. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V 74HC4094-Q100 VIH VIL VOH VOL HIGH-level input voltage LOW-level input voltage HIGH-level output voltage LOW-level output voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VO = VCC or GND; VCC = 6.0 V - - 0.5 - 5.0 - 10.0 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - 8.0 - 80 - 160 A CI input capacitance - 3.5 - pF 74HCT4094-Q100 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V 2.0 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 0.8 - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A 4.4 4.5 - 4.4 - 4.4 - V IO = 4.0 mA 3.98 4.32 - 3.84 - 3.7 - V IO = 20 A - 0 0.1 - 0.1 - 0.1 V IO = 4.0 mA - 0.15 0.26 - 0.33 - 0.4 V VOL LOW-level output voltage 74HC_HCT4094_Q100 Product data sheet VI = VIH or VIL; VCC = 4.5 V All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 6 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register Table 6. Static characteristics …continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max II input leakage current VI = VCC or GND; VCC = 5.5 V - - 0.1 - 1.0 - 1.0 A IOZ OFF-state output current VI = VIH or VIL; VCC = 5.5 V; VO = VCC or GND per input pin; other inputs at VCC or GND; IO = 0 A - - 0.5 - 5.0 - 10 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 5.5 V - - 8.0 - 80 - 160 A ICC additional supply current VI = VCC 2.1 V; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V; IO = 0 A per input pin; STR input - 100 360 - 450 - 490 A per input pin; OE input - 150 540 - 675 - 735 A per input pin; CP input - 150 540 - 675 - 735 A per input pin; D input - 40 144 - 180 - 196 A - 3.5 - CI input capacitance 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 pF © NXP B.V. 2013. All rights reserved. 7 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register 11. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V - 50 150 - 190 - 225 ns VCC = 4.5 V - 18 30 - 38 - 45 ns 74HC4094-Q100 tpd propagation delay [1] CP to QS1; see Figure 8 VCC = 5 V; CL = 15 pF - 15 - - - - - ns VCC = 6.0 V - 14 26 - 33 - 38 ns VCC = 2.0 V - 44 135 - 170 - 205 ns VCC = 4.5 V - 16 27 - 34 - 41 ns VCC = 5 V; CL = 15 pF - 13 - - - - - ns - 13 23 - 29 - 35 ns VCC = 2.0 V - 63 195 - 245 - 295 ns VCC = 4.5 V - 23 39 - 49 - 59 ns VCC = 5 V; CL = 15 pF - 20 - - - - - ns - 18 33 - 42 - 50 ns VCC = 2.0 V - 58 180 - 225 - 270 ns VCC = 4.5 V - 21 36 - 45 - 54 ns VCC = 5 V; CL = 15 pF - 18 - - - - - ns - 17 31 - 38 - 46 ns VCC = 2.0 V - 55 175 - 220 - 265 ns VCC = 4.5 V - 20 35 - 44 - 53 ns - 16 30 - 37 - 45 ns VCC = 2.0 V - 41 125 - 155 - 190 ns VCC = 4.5 V - 15 25 - 31 - 38 ns - 12 21 - 26 - 32 ns VCC = 2.0 V - 19 75 - 95 - 110 ns VCC = 4.5 V - 7 15 - 19 - 22 ns VCC = 6.0 V - 6 13 - 16 - 19 ns [1] CP to QS2; see Figure 8 VCC = 6.0 V [1] CP to QPn; see Figure 8 VCC = 6.0 V STR to QPn; see Figure 9 [1] VCC = 6.0 V ten enable time OE to QPn; see Figure 11 [2] VCC = 6.0 V tdis disable time OE to QPn; see Figure 11 [3] VCC = 6.0 V tt transition time 74HC_HCT4094_Q100 Product data sheet QPn and QSn; see Figure 8 [4] All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 8 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter tW pulse width 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 80 14 - 100 - 120 - ns VCC = 4.5 V 16 5 - 20 - 24 - ns VCC = 6.0 V 14 4 - 17 - 20 - ns VCC = 2.0 V 50 14 - 65 - 75 - ns VCC = 4.5 V 10 5 - 13 - 15 - ns VCC = 6.0 V 9 4 - 11 - 13 - ns VCC = 2.0 V 100 28 - 125 - 150 - ns VCC = 4.5 V 20 10 - 25 - 30 - ns VCC = 6.0 V 17 8 - 21 - 26 - ns VCC = 2.0 V 3 -6 - 3 - 3 - ns VCC = 4.5 V 3 -2 - 3 - 3 - ns VCC = 6.0 V 3 -2 - 3 - 3 - ns VCC = 2.0 V 0 -14 - 0 - 0 - ns VCC = 4.5 V 0 -5 - 0 - 0 - ns VCC = 6.0 V 0 -4 - 0 - 0 - ns VCC = 2.0 V 6.0 28 - 4.8 - 4.0 - MHz VCC = 4.5 V 30 87 - 24 - 20 - MHz - 95 - - - - - MHz 35 103 - 28 - 24 - MHz - 83 - - - - - pF CP HIGH or LOW; see Figure 8 STR HIGH; see Figure 9 tsu set-up time D to CP; see Figure 10 CP to STR; see Figure 9 th hold time D to CP; see Figure 10 CP to STR; see Figure 9 fmax maximum frequency CP; see Figure 8 VCC = 5 V; CL = 15 pF VCC = 6.0 V CPD power CL = 50 pF; f = 1 MHz; dissipation VI = GND to VCC capacitance 74HC_HCT4094_Q100 Product data sheet [5] All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 9 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register Table 7. Dynamic characteristics …continued Voltages are referenced to GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit see Figure 12. Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 23 39 - 49 - 59 ns - 19 - - - - - ns VCC = 4.5 V - 21 36 - 45 - 54 ns VCC = 5 V; CL = 15 pF - 18 - - - - - ns - 25 43 - 54 - 65 ns - 21 - - - - - ns - 22 39 - 49 - 59 ns - 19 - - - - - ns - 20 35 - 44 - 53 ns - 21 35 - 44 - 53 ns - 7 15 - 19 - 22 ns 16 7 - 20 - 24 - ns 16 5 - 20 - 24 - ns 10 4 - 13 - 15 - ns 20 9 - 25 - 30 - ns 4 0 - 4 - 4 - ns 0 4 - 0 - 0 - ns 30 80 - 24 - 20 - MHz - 86 - - - - - MHz - 92 - - - - - pF 74HCT4094-Q100 tpd propagation delay [1] CP to QS1; see Figure 8 VCC = 4.5 V VCC = 5 V; CL = 15 pF [1] CP to QS2; see Figure 8 [1] CP to QPn; see Figure 8 VCC = 4.5 V VCC = 5 V; CL = 15 pF STR to QPn; see Figure 9 [1] VCC = 4.5 V VCC = 5 V; CL = 15 pF ten enable time OE to QPn; see Figure 11 [2] VCC = 4.5 V tdis disable time OE to QPn; see Figure 11 [3] VCC = 4.5 V tt transition time QPn and QSn; see Figure 8 [4] VCC = 4.5 V tW pulse width CP HIGH or LOW; see Figure 8 VCC = 4.5 V STR HIGH; see Figure 9 VCC = 4.5 V tsu set-up time Dn to CP; see Figure 10 VCC = 4.5 V CP to STR; see Figure 9 VCC = 4.5 V th hold time Dn to CP; see Figure 10 VCC = 4.5 V CP to STR; see Figure 9 VCC = 4.5 V fmax maximum frequency CP; see Figure 8 VCC = 4.5 V VCC = 5 V; CL = 15 pF CPD [1] power CL = 50 pF; f = 1 MHz; dissipation VI = GND to VCC capacitance [5] tpd is the same as tPLH and tPHL. 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 10 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register [2] ten is the same as tPZH and tPZL. [3] tdis is the same as tPLZ and tPHZ. [4] tt is the same as tTHL and tTLH. [5] CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 12. Waveforms IPD[ 9, &3LQSXW 90 *1' W: 92+ 43Q46RXWSXW W3+/ W3/+ 90 92/ W7/+ W7+/ W3+/ W3/+ 92+ 46RXWSXW 90 92/ DDD Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 8. Propagation delay input (CP) to output (QPn, QS1, QS2), output transition time, clock input (CP) pulse width and the maximum frequency (CP) 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 11 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register VI CP input VM GND tsu th VI STR input VM GND tW tPHL tPLH VOH QPn output VM VOL 001aaf114 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 9. Propagation delay strobe input (STR) to output (QPn), strobe input (STR) pulse width and the clock set-up and hold times for strobe input VI VM CP input GND t su t su th th VI VM D input GND VOH VM QPn, QS1, QS2 output VOL 001aaf115 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 10. The data input (D) to clock input (CP) set-up times and clock input (CP) to data input (D) hold times 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 12 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register VI VM OE input GND tPZL tPLZ VCC output LOW-to-OFF OFF-to-LOW VOL VM VX tPHZ VOH output HIGH-to-OFF OFF-to-HIGH GND tPZH VY VM outputs enabled outputs disabled outputs enabled 001aaf116 Measurement points are given in Table 8. VOL and VOH are typical voltage output levels that occur with the output load. Fig 11. Enable and disable times Table 8. Measurement points Type Input Output VM VM VX VY 74HC4094-Q100 0.5VCC 0.5VCC 0.1VOH 0.9VOH 74HCT4094-Q100 1.3 V 1.3 V 0.1VOH 0.9VOH 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 13 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register VI tW 90 % negative pulse VM 0V tf tr tr tf VI 90 % positive pulse 0V VM 10 % VM VM 10 % tW VCC VCC G VI VO RL S1 open DUT CL RT 001aad983 Test data is given in Table 9. Definitions test circuit: RT = Termination resistance should be equal to output impedance Zo of the pulse generator. CL = Load capacitance including jig and probe capacitance. RL = Load resistance. S1 = Test selection switch. Fig 12. Test circuit for measuring switching times Table 9. Test data Type Input VI tr, tf CL RL tPHL, tPLH tPZH, tPHZ tPZL, tPLZ 74HC4094-Q100 VCC 6 ns 15 pF, 50 pF 1 k open GND VCC 74HCT4094-Q100 3 V 6 ns 15 pF, 50 pF 1 k open GND VCC 74HC_HCT4094_Q100 Product data sheet Load S1 position All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 14 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register 13. Package outline SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 D E A X c y HE v M A Z 16 9 Q A2 A (A 3) A1 pin 1 index θ Lp 1 L 8 e 0 detail X w M bp 2.5 5 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) mm 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 1.05 1.0 0.4 0.7 0.6 0.25 0.25 0.1 0.7 0.3 0.01 0.019 0.0100 0.39 0.014 0.0075 0.38 0.039 0.016 0.028 0.020 inches 0.010 0.057 0.069 0.004 0.049 0.16 0.15 0.05 0.244 0.041 0.228 0.01 0.01 0.028 0.004 0.012 θ 8o o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT109-1 076E07 MS-012 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig 13. Package outline SOT109-1 (SO16) 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 15 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm D SOT338-1 E A X c y HE v M A Z 9 16 Q A2 A (A 3) A1 pin 1 index θ Lp L 8 1 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y Z (1) θ mm 2 0.21 0.05 1.80 1.65 0.25 0.38 0.25 0.20 0.09 6.4 6.0 5.4 5.2 0.65 7.9 7.6 1.25 1.03 0.63 0.9 0.7 0.2 0.13 0.1 1.00 0.55 8o o 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT338-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-150 Fig 14. Package outline SOT338-1 (SSOP16) 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 16 of 21 74HC4094-Q100; 74HCT4094-Q100 NXP Semiconductors 8-stage shift-and-store bus register TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1 E D A X c y HE v M A Z 9 16 Q (A 3) A2 A A1 pin 1 index θ Lp L 1 8 e detail X w M bp 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.40 0.06 8o o 0 Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT403-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-18 MO-153 Fig 15. Package outline SOT403-1 (TSSOP16) 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 17 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register 14. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal Oxide Semiconductor ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model MIL Military 15. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT4094_Q100 v.1 20130130 Product data sheet - - 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 18 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register 16. Legal information 16.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 16.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 16.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 74HC_HCT4094_Q100 Product data sheet Suitability for use in automotive applications — This NXP Semiconductors product has been qualified for use in automotive applications. Unless otherwise agreed in writing, the product is not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 19 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. 16.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] 74HC_HCT4094_Q100 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 — 30 January 2013 © NXP B.V. 2013. All rights reserved. 20 of 21 NXP Semiconductors 74HC4094-Q100; 74HCT4094-Q100 8-stage shift-and-store bus register 18. Contents 1 2 3 4 5 6 6.1 6.2 7 8 9 10 11 12 13 14 15 16 16.1 16.2 16.3 16.4 17 18 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . 4 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 Recommended operating conditions. . . . . . . . 5 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Contact information. . . . . . . . . . . . . . . . . . . . . 20 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 30 January 2013 Document identifier: 74HC_HCT4094_Q100