74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
Rev. 5 — 30 November 2015
Product data sheet
1. General description
The 74HC107; 74HCT107 is a dual negative edge triggered JK flip-flop featuring
individual J and K inputs, clock (CP) and reset (R) inputs and complementary Q and Q
outputs. The reset is an asynchronous active LOW input and operates independently of
the clock input. The J and K inputs control the state changes of the flip-flops as described
in the mode select function table. The J and K inputs must be stable one set-up time prior
to the HIGH-to-LOW clock transition for predictable operation. Inputs include clamp
diodes that enable the use of current limiting resistors to interface inputs to voltages in
excess of VCC.
2. Features and benefits
Complies with JEDEC standard no. 7A
Input levels:
The 74HC107: CMOS levels
The 74HCT107: TTL levels
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1.
Ordering information
Type number
Package
Temperature range
Name
Description
Version
40 C to +125 C
SO14
plastic small outline package; 14 leads; body width
3.9 mm
SOT108-1
74HC107DB
40 C to +125 C
SSOP14
plastic shrink small outline package; 14 leads; body
width 5.3 mm
SOT337-1
74HC107PW
40 C to +125 C
TSSOP14
plastic thin shrink small outline package; 14 leads; body SOT402-1
width 4.4 mm
74HC107D
74HCT107D
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
4. Functional diagram
-
-
4
))
&3
&3
&3
.
.
.
4
4
4
4 4 5
5 5
-
.
5
-
&
.
5
DDD
DDD
Fig 1.
&
Logic symbol
Fig 2.
&
&
IEC logic symbol
&
&
.
4
&
&
&
&
4
5
&3
&
&
Fig 3.
DDE
Logic diagram (one flip-flop)
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
2 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
5. Pinning information
5.1 Pinning
+&
+&7
- 9&&
4 5
4 &3
. .
4 5
4 &3
*1' DDD
Fig 4.
Pin configuration SO14 and (T)SSOP14
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
1J, 2J
1, 8
synchronous J input
1Q, 2Q
2, 6
complement output
1Q, 2Q
3, 5
true output
1K, 2K
4, 11
synchronous K input
1CP, 2CP
12, 9
clock input (HIGH-to-LOW edge-triggered)
1R, 2R
13, 10
asynchronous reset input (active LOW)
GND
7
ground (0 V)
VCC
14
supply voltage
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
3 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
6. Functional description
Table 3.
Function table[1]
Input
Output
Operating mode
R
CP
J
K
Q
Q
L
X
X
X
L
H
H
h
h
q
q
toggle
H
l
h
L
H
load 0 (reset)
H
h
l
H
L
load 1 (set)
H
l
l
q
q
hold (no change)
[1]
asynchronous reset
H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
q = state of referenced output one set-up time prior to the HIGH-to-LOW clock transition;
X = don’t care;
= HIGH-to-LOW clock transition.
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
VCC
supply voltage
Conditions
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
VO = 0.5 V to VCC + 0.5 V
Min
Max
Unit
0.5
+7.0
V
[1]
-
20
mA
[1]
-
20
mA
IO
output current
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
50
-
mA
Tstg
storage temperature
65
+150
C
Ptot
total power dissipation
Tamb = 40 C to +125 C
SO14 package
[2]
-
500
mW
(T)SSOP14 package
[3]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
Ptot derates linearly with 8 mW/K above 70 C.
[3]
Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
4 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter
Conditions
74HC107
Min
Typ
74HCT107
Max
Min
Typ
Unit
Max
VCC
supply voltage
2.0
5.0
6.0
4.5
5.0
5.5
V
VI
input voltage
0
-
VCC
0
-
VCC
V
VO
output voltage
0
-
VCC
0
-
VCC
V
Tamb
ambient temperature
40
+25
+125
40
+25
+125
C
t/V
input transition rise and fall rate
VCC = 2.0 V
-
-
625
-
-
-
ns/V
VCC = 4.5 V
-
1.67
139
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
-
-
-
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
1.5
1.2
-
1.5
-
1.5
-
V
VCC = 4.5 V
3.15
2.4
-
3.15
-
3.15
-
V
VCC = 6.0 V
4.2
3.2
-
4.2
-
4.2
-
V
VCC = 2.0 V
-
0.8
0.5
-
0.5
-
0.5
V
VCC = 4.5 V
-
2.1
1.35
-
1.35
-
1.35
V
VCC = 6.0 V
-
2.8
1.8
-
1.8
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
1.9
-
1.9
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
4.4
-
4.4
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
5.9
-
5.9
-
V
IO = 4.0 mA; VCC = 4.5 V
3.98
4.32
-
3.84
-
3.7
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
5.34
-
5.2
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
-
0.1
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
-
0.33
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
-
0.33
-
0.4
V
74HC107
VIH
VIL
VOH
VOL
HIGH-level
input voltage
LOW-level
input voltage
HIGH-level
output voltage
LOW-level
output voltage
VI = VIH or VIL
VI = VIH or VIL
II
input leakage
current
VI = VCC or GND;
VCC = 6.0 V
-
-
0.1
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
4.0
-
40
-
80
A
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
5 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 6.
Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
CI
25 C
Conditions
input
capacitance
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
-
3.5
-
Min
Max
Min
Max
pF
74HCT107
VIH
HIGH-level
input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
2.0
-
2.0
-
V
VIL
LOW-level
input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
-
0.8
-
0.8
V
VOH
HIGH-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
4.4
-
4.4
-
V
IO = 4 mA
3.98
4.32
-
3.84
-
3.7
-
V
LOW-level
output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
-
0
0.1
-
0.1
-
0.1
V
IO = 4.0 mA
-
0.16
0.26
-
0.33
-
0.4
V
VOL
II
input leakage
current
VI = VCC or GND;
VCC = 5.5 V
-
-
0.1
-
1.0
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
4.0
-
40
-
80
A
ICC
additional
supply current
per input pin;
VI = VCC 2.1 V; IO = 0 A;
other inputs at VCC or GND;
VCC = 4.5 V to 5.5 V
CI
input
capacitance
74HC_HCT107
Product data sheet
pin nCP, nJ
-
100
360
-
450
-
490
A
pin nR
-
65
234
-
293
-
319
A
pin nK
-
60
216
-
270
-
294
A
-
3.5
-
-
-
-
-
pF
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
6 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
Min
Max
Min
Max
74HC107
tpd
propagation
delay
nCP to nQ; see Figure 5
[1]
VCC = 2.0 V
-
52
160
-
200
-
240
ns
VCC = 4.5 V
-
19
32
-
40
-
48
ns
VCC = 5.0 V; CL = 15 pF
-
16
-
-
-
-
-
ns
VCC = 6.0 V
-
15
27
-
34
-
41
ns
VCC = 2.0 V
-
52
160
-
200
-
240
ns
nCP to nQ; see Figure 5
VCC = 4.5 V
-
19
32
-
40
-
48
ns
VCC = 5.0 V; CL = 15 pF
-
16
-
-
-
-
-
ns
VCC = 6.0 V
-
15
27
-
34
-
41
ns
VCC = 2.0 V
-
52
155
-
195
-
235
ns
VCC = 4.5 V
-
19
31
-
39
-
47
ns
VCC = 5.0 V; CL = 15 pF
-
16
-
-
-
-
-
ns
-
15
26
-
33
-
40
ns
VCC = 2.0 V
-
19
75
-
95
-
110
ns
VCC = 4.5 V
-
7
15
-
19
-
22
ns
VCC = 6.0 V
-
6
13
-
16
-
19
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
VCC = 2.0 V
60
19
-
75
-
90
-
ns
VCC = 4.5 V
12
7
-
15
-
18
-
ns
VCC = 6.0 V
20
6
-
13
-
15
-
ns
VCC = 2.0 V
100
22
-
125
-
150
-
ns
VCC = 4.5 V
20
8
-
25
-
30
-
ns
VCC = 6.0 V
17
6
-
21
-
26
-
ns
nR to nQ, nQ; see Figure 6
VCC = 6.0 V
tt
tW
[2]
transition time nQ, nQ; see Figure 5
pulse width
nCP input, HIGH or LOW;
see Figure 5
nR input, HIGH or LOW;
see Figure 6
trec
tsu
recovery time
set-up time
74HC_HCT107
Product data sheet
nR to nCP; see Figure 6
nJ, nK to nCP; see Figure 5
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
7 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter
th
fmax
hold time
maximum
frequency
25 C
Conditions
Min
Max
Min
Max
VCC = 2.0 V
3
6
-
3
-
3
-
ns
VCC = 4.5 V
3
2
-
3
-
3
-
ns
VCC = 6.0 V
3
2
-
3
-
3
-
ns
nCP input; see Figure 5
VCC = 2.0 V
6
23
-
4.8
-
4.0
-
MHz
VCC = 4.5 V
30
70
-
24
-
20
-
MHz
-
78
-
-
-
-
-
MHz
35
85
-
28
-
24
-
MHz
-
30
-
-
-
-
-
pF
VCC = 4.5 V
-
19
36
-
45
-
54
ns
VCC = 5.0 V; CL = 15 pF
-
16
-
-
-
-
-
ns
VCC = 4.5 V
-
21
36
-
45
-
54
ns
VCC = 5.0 V; CL = 15 pF
-
18
-
-
-
-
-
ns
-
20
38
-
48
-
57
ns
-
17
-
-
-
-
-
ns
-
7
15
-
19
-
22
ns
16
9
-
20
-
24
-
ns
20
11
-
25
-
30
-
ns
14
8
-
18
-
21
-
ns
20
7
-
25
-
30
-
ns
5
2
-
5
-
5
-
ns
VCC = 6.0 V
power
dissipation
capacitance
Min Typ Max
nJ, nK to nCP; see Figure 5
VCC = 5.0 V; CL = 15 pF
CPD
40 C to +85 C 40 C to +125 C Unit
per flip-flop;
VI = GND to VCC
[3]
nCP to nQ; see Figure 5
[1]
74HCT107
tpd
propagation
delay
nCP to nQ; see Figure 5
nR to nQ, nQ; see Figure 6
VCC = 4.5 V
VCC = 5.0 V; CL = 15 pF
tt
[2]
transition time nQ, nQ; see Figure 5
VCC = 4.5 V
tW
pulse width
nCP input, HIGH or LOW;
see Figure 5
VCC = 4.5 V
nR input, HIGH or LOW;
see Figure 6
VCC = 4.5 V
trec
recovery time
nR to nCP; see Figure 6
VCC = 4.5 V
tsu
set-up time
nJ, nK to nCP; see Figure 5
th
hold time
nJ, nK to nCP; see Figure 5
VCC = 4.5 V
VCC = 4.5 V
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
8 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
Table 7.
Dynamic characteristics …continued
GND (ground = 0 V); CL = 50 pF unless otherwise specified; for test circuit, see Figure 7
Symbol Parameter
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min Typ Max
fmax
maximum
frequency
power
dissipation
capacitance
VCC = 4.5 V
[3]
per flip-flop;
VI = GND to VCC 1.5 V
[1]
tpd is the same as tPHL, tPLH.
[2]
tt is the same as tTHL, tTLH.
[3]
Max
Min
Max
nCP input; see Figure 5
VCC = 5.0 V; CL = 15 pF
CPD
Min
30
66
-
24
-
20
-
MHz
-
73
-
-
-
-
-
MHz
-
30
-
-
-
-
-
pF
CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
11. Waveforms
9,
Q-Q.
LQSXW
*1'
90
WK
WVX
IPD[
9,
WVX
WK
90
Q&3LQSXW
*1'
W:
W3/+
W3+/
92+
Q4RXWSXW
90
92/
W7+/
92+
W7/+
Q4RXWSXW
90
92/
W7/+
W3/+
W7+/
W3+/
DDE
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 5.
Clock propagation delays, pulse width, set-up and hold times, output transition times and the maximum
frequency
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
9,
90
Q&3LQSXW
*1'
WUHF
W:
9,
90
Q5LQSXW
*1'
W3+/
92+
Q4RXWSXW
92/
92+
W3/+
Q4RXWSXW
DDE
92/
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6.
Reset propagation delays, pulse width and recovery time
Table 8.
Measurement points
Type
Input
VI
VM
VM
74HC107
VCC
0.5VCC
0.5VCC
74HCT107
3V
1.3 V
1.3 V
74HC_HCT107
Product data sheet
Output
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
10 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
9,
W:
QHJDWLYH
SXOVH
90
9
WI
WU
WU
WI
9,
SRVLWLYH
SXOVH
9
90
90
90
W:
9&&
9&&
*
9,
92
5/
6
RSHQ
'87
&/
57
DDG
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 7.
Test circuit for measuring switching times
Table 9.
Test data
Type
Input
VI
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
74HC107
VCC
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HCT107
3V
6 ns
15 pF, 50 pF
1 k
open
GND
VCC
74HC_HCT107
Product data sheet
Load
S1 position
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 18
74HC107; 74HCT107
NXP Semiconductors
Dual JK flip-flop with reset; negative-edge trigger
12. Package outline
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74HC_HCT107
Product data sheet
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Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 18
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Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 18
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74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 18
74HC107; 74HCT107
NXP Semiconductors
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13. Abbreviations
Table 10.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
14. Revision history
Table 11.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT107 v.5
20151130
Product data sheet
-
74HC_HCT107 v.4
Modifications:
74HC_HCT107 v.4
Modifications:
74HC_HCT107 v.3
Modifications:
74HC_HCT107_CNV v.2
74HC_HCT107
Product data sheet
•
Type numbers 74HC107N and 74HCT107N (SOT27-1) removed.
20150126
•
Product data sheet
-
74HC_HCT107 v.3
Table 7: Power dissipation capacitance condition for 74HCT107 is corrected.
20131118
Product data sheet
-
74HC_HCT107_CNV v.2
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
Legal texts have been adapted to the new company name where appropriate.
19901201
Product specification
-
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
-
© NXP Semiconductors N.V. 2015. All rights reserved.
15 of 18
74HC107; 74HCT107
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15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT107
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
16 of 18
74HC107; 74HCT107
NXP Semiconductors
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74HC_HCT107
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 30 November 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
17 of 18
NXP Semiconductors
74HC107; 74HCT107
Dual JK flip-flop with reset; negative-edge trigger
17. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
15.1
15.2
15.3
15.4
16
17
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 1
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 16
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 16
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Contact information. . . . . . . . . . . . . . . . . . . . . 17
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 30 November 2015
Document identifier: 74HC_HCT107