Presettable synchronous 4-bit binary up/down counter

74HC193; 74HCT193
Presettable synchronous 4-bit binary up/down counter
Rev. 5 — 29 January 2016
Product data sheet
1. General description
The 74HC193; 74HCT193 is a 4-bit synchronous binary up/down counter. Separate
up/down clocks, CPU and CPD respectively, simplify operation. The outputs change state
synchronously with the LOW-to-HIGH transition of either clock input. If the CPU clock is
pulsed while CPD is held HIGH, the device will count up. If the CPD clock is pulsed while
CPU is held HIGH, the device will count down. Only one clock input can be held HIGH at
any time to guarantee predictable behavior. The device can be cleared at any time by the
asynchronous master reset input (MR); it may also be loaded in parallel by activating the
asynchronous parallel load input (PL). The terminal count up (TCU) and terminal count
down (TCD) outputs are normally HIGH. When the circuit has reached the maximum
count state of 15, the next HIGH-to-LOW transition of CPU will cause TCU to go LOW.
TCU will stay LOW until CPU goes HIGH again, duplicating the count up clock. Likewise,
the TCD output will go LOW when the circuit is in the zero state and the CPD goes LOW.
The terminal count outputs can be used as the clock input signals to the next higher order
circuit in a multistage counter, since they duplicate the clock waveforms. Multistage
counters will not be fully synchronous, since there is a slight delay time difference added
for each stage that is added. The counter may be preset by the asynchronous parallel
load capability of the circuit. Information present on the parallel data inputs (D0 to D3) is
loaded into the counter and appears on the outputs (Q0 to Q3) regardless of the
conditions of the clock inputs when the parallel load (PL) input is LOW. A HIGH level on
the master reset (MR) input will disable the parallel load gates, override both clock inputs
and set all outputs (Q0 to Q3) LOW. If one of the clock inputs is LOW during and after a
reset or load operation, the next LOW-to-HIGH transition of that clock will be interpreted
as a legitimate signal and will be counted. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
 Input levels:
 For 74HC193: CMOS level
 For 74HCT193: TTL level
 Synchronous reversible 4-bit binary counting
 Asynchronous parallel load
 Asynchronous reset
 Expandable without external logic
 Complies with JEDEC standard no. 7A
 ESD protection:
 HBM JESD22-A114F exceeds 2000 V
 MM JESD22-A115-A exceeds 200 V.
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
 Multiple package options
 Specified from 40 C to +85 C and 40 C to +125 C.
3. Ordering information
Table 1.
Ordering information
Type number
Package
74HC193D
Temperature
range
Name
Description
Version
40 C to +125 C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
SOT109-1
40 C to +125 C
SSOP16
plastic shrink small outline package; 16 leads;
body width 5.3 mm
SOT338-1
40 C to +125 C
TSSOP16
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
SOT403-1
74HCT193D
74HC193DB
74HCT193DB
74HC193PW
74HCT193PW
4. Functional diagram
'
3/
'
'
'
7&8
&38
&2817(5
7&'
&3'
05
)/,3)/236
4
Fig 1.
4
4
&38
&3'
DDJ
Functional diagram
Fig 2.
&
*
*
5
'
'
'
'
05
4
4
4
4
4
3/
7&8
7&'
DDJ
Logic symbol
&75
'
&7 &7 DDJ
Fig 3.
IEC logic symbol
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
2 of 28
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'
'
NXP Semiconductors
74HC_HCT193
Product data sheet
'
'
3/
&38
7&8
6'
))
7
6'
4
))
4
7
))
4
5'
6'
4
7
4
5'
4
))
4
5'
5'
7&'
&3'
05
Fig 4.
Logic diagram
4
4
4
DDJ
3 of 28
© NXP Semiconductors N.V. 2016. All rights reserved.
74HC193; 74HCT193
4
Presettable synchronous 4-bit binary up/down counter
Rev. 5 — 29 January 2016
All information provided in this document is subject to legal disclaimers.
7
6'
4
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
5. Pinning information
5.1 Pinning
+&
+&7
'
9&&
4
'
4
05
&3'
7&'
&38
7&8
4
3/
4
*1'
+&
+&7
'
'
'
4
9&&
'
4
05
&3'
7&'
&38
7&8
4
3/
4
'
*1'
DDJ
DDJ
Fig 5.
'
Pin configuration SO16
Fig 6.
Pin configuration TSSOP16 and SSOP16
5.2 Pin description
Table 2.
Pin description
Symbol
Pin
Description
D0
15
data input 0
D1
1
data input 1
D2
10
data input 2
D3
9
data input 3
Q0
3
flip-flop output 0
Q1
2
flip-flop output 1
Q2
6
flip-flop output 2
Q3
7
flip-flop output 3
CPD
4
count down clock input[1]
CPU
5
count up clock input[1]
GND
8
ground (0 V)
PL
11
asynchronous parallel load input (active LOW)
TCU
12
terminal count up (carry) output (active LOW)
TCD
13
terminal count down (borrow) output (active LOW)
MR
14
asynchronous master reset input (active HIGH)
VCC
16
supply voltage
[1]
LOW-to-HIGH, edge triggered.
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
4 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
6. Functional description
Table 3.
Function table[1]
Operating mode
Inputs
Outputs
MR
PL
CPU CPD D0
D1
D2
D3
Q0
Q1
Q2
Q3
TCU TCD
H
X
X
L
X
X
X
X
L
L
L
L
H
L
H
X
X
H
X
X
X
X
L
L
L
L
H
H
L
L
X
L
L
L
L
L
L
L
L
L
H
L
L
L
X
H
L
L
L
L
L
L
L
L
H
H
L
L
L
X
H
H
H
H
H
H
H
H
L
H
L
L
H
X
H
H
H
H
H
H
H
H
H
H
Count up
L
H

H
X
X
X
X
count up
H[2]
H
Count down
L
H
H

X
X
X
X
count down
H
H[3]
Reset (clear)
Parallel load
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
 = LOW-to-HIGH clock transition.
[2]
TCU = CPU at terminal count up (HHHH)
[3]
TCD = CPD at terminal count down (LLLL).
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
05
3/
'
'
'
'
&38
&3'
4
4
4
4
7&8
7&'
&/($5
35(6(7
&281783
&2817'2:1
DDJ
(1) Clear overrides load, data and count inputs.
(2) When counting up, the count down clock input (CPD) must be HIGH, when counting down the count up clock input (CPU) must
be HIGH.
Sequence
Clear (reset outputs to zero);
load (preset) to binary thirteen;
count up to fourteen, fifteen, terminal count up, zero, one and two;
count down to one, zero, terminal count down, fifteen, fourteen and thirteen.
Fig 7.
Typical clear, load and count sequence
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
6 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VCC
supply voltage
IIK
input clamping current
VI < 0.5 V or VI > VCC + 0.5 V
[1]
IOK
output clamping current
VO < 0.5 V or VO > VCC + 0.5 V
[1]
IO
output current
VO = 0.5 V to VCC + 0.5 V
Min
Max
Unit
0.5
+7.0
V
-
20
mA
-
20
mA
-
25
mA
ICC
supply current
-
50
mA
IGND
ground current
-
50
mA
Tstg
storage temperature
total power dissipation
Ptot
65
+150
C
SO16 package
[2]
-
500
mW
SSOP16 package
[2]
-
500
mW
TSSOP16 package
[2]
-
500
mW
[1]
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2]
For SO16 packages: above 70 C the value of Ptot derates linearly at 8 mW/K.
For SSOP16 and TSSOP16 packages: above 60 C the value of Ptot derates linearly at 5.5 mW/K.
8. Recommended operating conditions
Table 5.
Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
2.0
5.0
6.0
V
74HC193
VCC
supply voltage
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
Tamb
ambient temperature
t/V
input transition rise and fall rate
40
+25
+125
C
VCC = 2.0 V
-
-
625
ns/V
VCC = 4.5 V
-
1.67
139
ns/V
VCC = 6.0 V
-
-
83
ns/V
4.5
5.0
5.5
V
74HCT193
VCC
supply voltage
VI
input voltage
0
-
VCC
V
VO
output voltage
0
-
VCC
V
40
+25
+125
C
-
1.67
139
ns/V
Tamb
ambient temperature
t/V
input transition rise and fall rate
74HC_HCT193
Product data sheet
VCC = 4.5 V
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
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74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
9. Static characteristics
Table 6.
Static characteristics type 74HC193
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC = 2.0 V
1.5
1.2
-
V
VCC = 4.5 V
3.15
2.4
-
V
VCC = 6.0 V
4.2
3.2
-
V
Tamb = 25 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
VCC = 2.0 V
-
0.8
0.5
V
VCC = 4.5 V
-
2.1
1.35
V
VCC = 6.0 V
-
2.8
1.8
V
VI = VIH or VIL
-
-
-
IO = 20 A; VCC = 2.0 V
1.9
2.0
-
V
IO = 20 A; VCC = 4.5 V
4.4
4.5
-
V
IO = 20 A; VCC = 6.0 V
5.9
6.0
-
V
IO = 4.0 mA; VCC = 4.5 V
3.98
4.32
-
V
IO = 5.2 mA; VCC = 6.0 V
5.48
5.81
-
V
IO = 20 A; VCC = 2.0 V
-
0
0.1
V
IO = 20 A; VCC = 4.5 V
-
0
0.1
V
VI = VIH or VIL
IO = 20 A; VCC = 6.0 V
-
0
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
0.15
0.26
V
IO = 5.2 mA; VCC = 6.0 V
-
0.16
0.26
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
0.1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
8.0
A
Ci
input capacitance
-
3.5
-
pF
Tamb = 40 C to +85 C
VIH
VIL
VOH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
74HC_HCT193
Product data sheet
VCC = 2.0 V
1.5
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 4.0 mA; VCC = 4.5 V
3.84
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.34
-
-
V
VI = VIH or VIL
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
8 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 6.
Static characteristics type 74HC193 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VOL
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
-
0.33
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.33
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
80
A
VCC = 2.0 V
1.5
-
-
V
VCC = 4.5 V
3.15
-
-
V
VCC = 6.0 V
4.2
-
-
V
VCC = 2.0 V
-
-
0.5
V
VCC = 4.5 V
-
-
1.35
V
VCC = 6.0 V
-
-
1.8
V
Tamb = 40 C to +125 C
VIH
VIL
VOH
VOL
HIGH-level input voltage
LOW-level input voltage
HIGH-level output voltage
LOW-level output voltage
VI = VIH or VIL
IO = 20 A; VCC = 2.0 V
1.9
-
-
V
IO = 20 A; VCC = 4.5 V
4.4
-
-
V
IO = 20 A; VCC = 6.0 V
5.9
-
-
V
IO = 4.0 mA; VCC = 4.5 V
3.7
-
-
V
IO = 5.2 mA; VCC = 6.0 V
5.2
-
-
V
IO = 20 A; VCC = 2.0 V
-
-
0.1
V
IO = 20 A; VCC = 4.5 V
-
-
0.1
V
VI = VIH or VIL
IO = 20 A; VCC = 6.0 V
-
-
0.1
V
IO = 4.0 mA; VCC = 4.5 V
-
-
0.4
V
IO = 5.2 mA; VCC = 6.0 V
-
-
0.4
V
II
input leakage current
VI = VCC or GND; VCC = 6.0 V
-
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 6.0 V
-
-
160
A
Conditions
Min
Typ
Max
Unit
Table 7.
Static characteristics type 74HCT193
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Tamb = 25 C
VIH
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
1.6
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
1.2
0.8
V
VOH
HIGH-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
4.5
-
V
IO = 4.0 mA
3.98
4.32
-
V
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
9 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 7.
Static characteristics type 74HCT193 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
VOL
LOW-level output voltage
VI = VIH or VIL; VCC = 4.5 V
Min
Typ
Max
Unit
IO = 20 A
-
0
0.1
V
IO = 4.0 mA
-
0.15
0.26
V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
0.1
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
8.0
A
ICC
additional supply current
per input pin; VI = VCC  2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
Ci
pin Dn
-
35
126
A
pins CPU, CPD
-
140
504
A
pin PL
-
65
234
A
pin MR
-
105
378
A
-
3.5
-
pF
input capacitance
Tamb = 40 C to +85 C
VIH
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
V
VOH
HIGH-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
-
-
V
IO = 4.0 mA
3.84
-
-
V
IO = 20 A
-
-
0.1
V
IO = 4.0 mA
-
-
0.33
V
VOL
LOW-level output voltage
VI = VIH or VIL; VCC = 4.5 V
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
80
A
ICC
additional supply current
per input pin; VI = VCC  2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
157.5
A
pins CPU, CPD
-
-
630
A
pin PL
-
-
292.5
A
pin MR
-
-
472.5
A
Tamb = 40 C to +125 C
VIH
HIGH-level input voltage
VCC = 4.5 V to 5.5 V
2.0
-
-
V
VIL
LOW-level input voltage
VCC = 4.5 V to 5.5 V
-
-
0.8
V
VOH
HIGH-level output voltage
VI = VIH or VIL; VCC = 4.5 V
IO = 20 A
4.4
-
-
V
IO = 4.0 mA
3.7
-
-
V
IO = 20 A
-
-
0.1
V
IO = 4.0 mA
-
-
0.4
V
VOL
LOW-level output voltage
74HC_HCT193
Product data sheet
VI = VIH or VIL; VCC = 4.5 V
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
10 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 7.
Static characteristics type 74HCT193 …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
II
input leakage current
VI = VCC or GND; VCC = 5.5 V
-
-
1.0
A
ICC
supply current
VI = VCC or GND; IO = 0 A;
VCC = 5.5 V
-
-
160
A
ICC
additional supply current
per input pin; VI = VCC  2.1 V and
other inputs at VCC or GND;
IO = 0 A; VCC = 4.5 V to 5.5 V
pin Dn
-
-
171.5
A
pins CPU, CPD
-
-
686
A
pin PL
-
-
318.5
A
pin MR
-
-
514.5
A
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
10. Dynamic characteristics
Table 8.
Dynamic characteristics type 74HC193
Symbol Parameter
25 C
Conditions
Min
tpd
propagation
delay
[1]
CPU, CPD to Qn;
see Figure 8
40 C to +85 C 40 C to +125 C Unit
Typ
Max
Min
Max
Min
Max
-
VCC = 2.0 V
-
63
215
-
270
-
325
ns
VCC = 4.5 V
-
23
43
-
54
-
65
ns
VCC = 6.0 V
-
18
37
-
46
-
55
ns
VCC = 2.0 V
-
39
125
-
155
-
190
ns
VCC = 4.5 V
-
14
25
-
31
-
38
ns
VCC = 6.0 V
-
11
21
-
26
-
32
ns
VCC = 2.0 V
-
39
125
-
155
-
190
ns
VCC = 4.5 V
-
14
25
-
31
-
38
ns
VCC = 6.0 V
-
11
21
-
26
-
32
ns
VCC = 2.0 V
-
69
220
-
275
-
330
ns
VCC = 4.5 V
-
25
44
-
55
-
66
ns
VCC = 6.0 V
-
20
37
-
47
-
56
ns
VCC = 2.0 V
-
58
200
-
250
-
300
ns
VCC = 4.5 V
-
21
40
-
50
-
60
ns
VCC = 6.0 V
-
17
34
43
-
51
ns
VCC = 2.0 V
-
69
210
-
265
-
315
ns
VCC = 4.5 V
-
25
42
-
53
-
63
ns
VCC = 6.0 V
-
20
36
-
45
-
54
ns
VCC = 2.0 V
-
80
290
-
365
-
435
ns
VCC = 4.5 V
-
29
58
-
73
-
87
ns
VCC = 6.0 V
-
23
49
-
62
-
74
ns
VCC = 2.0 V
-
74
285
-
355
-
430
ns
VCC = 4.5 V
-
27
57
-
71
-
86
ns
VCC = 6.0 V
-
22
48
-
60
-
73
ns
CPU to TCU; see Figure 9
CPD to TCD; see Figure 9
PL to Qn; see Figure 10
MR to Qn; see Figure 11
Dn to Qn; see Figure 10
PL to TCU, PL to TCD;
see Figure 13
MR to TCU, MR to TCD;
see Figure 13
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
12 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 8.
Dynamic characteristics type 74HC193 …continued
Symbol Parameter
tpd
tTHL
tTLH
tW
propagation
delay
25 C
Conditions
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
-
80
290
-
365
-
435
ns
VCC = 4.5 V
-
29
58
-
73
-
87
ns
VCC = 6.0 V
-
23
49
-
62
-
74
ns
-
19
75
-
95
-
110
ns
-
7
15
-
19
-
22
ns
-
6
13
-
16
-
19
ns
-
19
75
-
95
-
110
ns
-
7
15
-
19
-
22
ns
-
6
13
-
16
-
19
ns
VCC = 2.0 V
100
22
-
125
-
150
-
ns
VCC = 4.5 V
20
8
-
25
-
30
-
ns
VCC = 6.0 V
17
6
-
21
-
26
-
ns
VCC = 2.0 V
100
25
-
125
-
150
-
ns
VCC = 4.5 V
20
9
-
25
-
30
-
ns
VCC = 6.0 V
17
7
-
21
-
26
-
ns
VCC = 2.0 V
100
19
-
125
-
150
-
ns
VCC = 4.5 V
20
7
-
25
-
30
-
ns
VCC = 6.0 V
17
6
-
21
-
26
-
ns
VCC = 2.0 V
50
8
-
65
-
75
-
ns
VCC = 4.5 V
10
3
-
13
-
15
-
ns
VCC = 6.0 V
9
2
-
11
-
13
-
ns
VCC = 2.0 V
50
0
-
65
-
75
-
ns
VCC = 4.5 V
10
0
-
13
-
15
-
ns
VCC = 6.0 V
9
0
-
11
-
13
-
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
14
6
-
17
-
20
-
ns
Dn to TCU, Dn to TCD;
see Figure 13
HIGH to LOW see Figure 11
output
VCC = 2.0 V
transition
VCC = 4.5 V
time
VCC = 6.0 V
LOW to HIGH see Figure 11
output
VCC = 2.0 V
transition
VCC = 4.5 V
time
VCC = 6.0 V
pulse width
40 C to +85 C 40 C to +125 C Unit
CPU, CPD (HIGH or LOW);
see Figure 8
MR (HIGH); see Figure 11
PL (LOW); see Figure 10
trec
recovery time PL to CPU, CPD;
see Figure 10
MR to CPU, CPD;
see Figure 11
tsu
set-up time
74HC_HCT193
Product data sheet
Dn to PL; see Figure 12;
note: CPU = CPD = HIGH
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74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 8.
Dynamic characteristics type 74HC193 …continued
Symbol Parameter
th
hold time
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
VCC = 2.0 V
0
14
-
0
-
0
-
ns
VCC = 4.5 V
0
5
-
0
-
0
-
ns
VCC = 6.0 V
0
4
-
0
0
-
ns
VCC = 2.0 V
80
22
-
100
-
120
-
ns
VCC = 4.5 V
16
8
-
20
-
24
-
ns
VCC = 6.0 V
8
6
-
17
-
20
-
ns
VCC = 2.0 V
4.0
13.5
-
3.2
-
2.6
-
MHz
VCC = 4.5 V
20
41
-
16
-
13
-
MHz
24
49
-
19
-
15
-
MHz
-
24
-
-
-
-
-
pF
Dn to PL; see Figure 12
CPU to CPD, CPD to CPU;
see Figure 14
maximum
frequency
fmax
CPU, CPD; see Figure 8
VCC = 6.0 V
power
dissipation
capacitance
CPD
[1]
[2]
[2]
VI = GND to VCC;
VCC = 5 V; fi = 1 MHz
tpd is the same as tPHL and tPLH.
CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
14 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 9.
Dynamic characteristics type 74HCT193
Symbol Parameter
tpd
25 C
Conditions
40 C to +85 C 40 C to +125 C Unit
Min
Typ
Max
Min
Max
Min
Max
-
23
43
-
54
-
65
ns
-
15
27
-
34
-
41
ns
-
15
27
-
34
-
41
ns
-
26
46
-
58
-
69
ns
-
22
40
-
50
-
60
ns
-
27
46
-
58
-
69
ns
-
31
55
-
69
-
83
ns
-
29
55
-
69
-
83
ns
VCC = 4.5 V
-
32
58
-
73
-
87
ns
HIGH to LOW
see Figure 11
output transition
VCC = 4.5 V
time
-
7
15
-
19
-
22
ns
LOW to HIGH
see Figure 11
output transition
VCC = 4.5 V
time
-
7
15
-
19
-
22
ns
25
11
-
31
-
38
-
ns
20
7
-
25
-
30
-
ns
20
8
-
25
-
30
-
ns
10
2
-
13
-
15
-
ns
10
0
-
13
-
15
-
ns
propagation
delay
[1]
CPU, CPD to Qn;
see Figure 8
VCC = 4.5 V
CPU to TCU; see Figure 9
VCC = 4.5 V
CPD to TCD; see Figure 9
VCC = 4.5 V
PL to Qn; see Figure 10
VCC = 4.5 V
MR to Qn; see Figure 11
VCC = 4.5 V
Dn to Qn; see Figure 10
VCC = 4.5 V
PL to TCU, PL to TCD;
see Figure 13
VCC = 4.5 V
MR to TCU, MR to TCD;
see Figure 13
VCC = 4.5 V
Dn to TCU, Dn to TCD;
see Figure 13
tTHL
tTLH
tW
pulse width
CPU, CPD (HIGH or
LOW); see Figure 8
VCC = 4.5 V
MR (HIGH); see Figure 11
VCC = 4.5 V
PL (LOW); see Figure 10
VCC = 4.5 V
trec
recovery time
PL to CPU, CPD;
see Figure 10
VCC = 4.5 V
MR to CPU, CPD;
see Figure 11
VCC = 4.5 V
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
15 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
Table 9.
Dynamic characteristics type 74HCT193 …continued
Symbol Parameter
tsu
set-up time
25 C
Conditions
hold time
Min
Typ
Max
Min
Max
Min
Max
16
8
-
20
-
24
-
ns
0
6
-
0
-
0
-
ns
16
7
-
20
-
24
-
ns
Dn to PL; see Figure 12;
note: CPU = CPD = HIGH
VCC = 4.5 V
th
40 C to +85 C 40 C to +125 C Unit
Dn to PL; see Figure 12
VCC = 4.5 V
CPU to CPD, CPD to
CPU; see Figure 14
VCC = 4.5 V
fmax
maximum
frequency
CPU, CPD; see Figure 8
CPD
power
dissipation
capacitance
VI = GND to VCC  1.5 V;
VCC = 5 V; fi = 1 MHz
VCC = 4.5 V
[2]
20
43
-
16
-
13
-
MHz
-
26
-
-
-
-
-
pF
[1]
tpd is the same as tPHL and tPLH.
[2]
CPD is used to determine the dynamic power dissipation (PD in W):
PD = CPD  VCC2  fi  N + (CL  VCC2  fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL  VCC2  fo) = sum of outputs.
11. Waveforms
IPD[
9,
&38&3'
LQSXW
*1'
90
W:
W 3+/
W 3/+
92+
90
4QRXWSXW
DDJ
92/
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 8.
The clock (CPU, CPD) to output (Qn) propagation delays, the clock pulse width, and the maximum clock
pulse frequency
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
16 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
9,
&38&3'
LQSXW
*1'
90
W3+/
W3/+
92+
7&87&'
RXWSXW
92/
90
DDJ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 9.
The clock (CPU, CPD) to terminal count output (TCU, TCD) propagation delays
9,
'QLQSXW
*1'
90
9,
3/LQSXW
*1'
9,
&38&3'
LQSXW
*1'
90
W UHF
W:
90
W 3/+
W 3+/
92+
4QRXWSXW
92/
90
DDJ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 10. The parallel load input (PL) and data (Dn) to Qn output propagation delays and PL removal time to clock
input (CPU, CPD)
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
17 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
9,
05LQSXW
*1'
90
W:
W UHF
9,
&38&3'
LQSXW
*1'
90
W 3+/
92+
90
4QRXWSXW
92/
W 7+/
W 7/+
DDJ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 11. The master reset input (MR) pulse width, MR to Qn propagation delays, MR to CPU, CPD removal time
and output transition times
9,
90
'QLQSXW
*1'
WVX
WVX
WK
WK
9,
3/LQSXW
*1'
90
92+
4QRXWSXW
92/
DDJ
The shaded areas indicate when the input is permitted to change for predictable output performance.
Measurement points are given in Table 10.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 12. The data input (Dn) to parallel load input (PL) set-up and hold times
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
18 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
9,
3/05'Q
LQSXW
90
*1'
W3/+
W3+/
92+
7&87&'
RXWSXW
92/
90
DDJ
Measurement points are given in Table 10.
tPLH and tPHL are the same as tpd.
Logic levels VOL and VOH are typical output voltage levels that occur with the output load.
Fig 13. The data input (Dn), parallel load input (PL) and the master reset input (MR) to the terminal count outputs
(TCU, TCD) propagation delays
9,
&38RU&3'
LQSXW
*1'
90
WK
9,
&3'RU&38
LQSXW
90
*1'
DDJ
Measurement points are given in Table 10.
Fig 14. The CPU to CPD or CPD to CPU hold times
Table 10.
Measurement points
Type
Input
Output
VM
VI
VM
74HC193
0.5  VCC
GND to VCC
0.5  VCC
74HCT193
1.3 V
GND to 3 V
1.3 V
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
19 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
9,
W:
QHJDWLYH
SXOVH
90
9
9,
WI
WU
WU
WI
SRVLWLYH
SXOVH
9
90
90
90
W:
9&&
9&&
*
9,
92
5/
6
RSHQ
'87
&/
57
DDG
Test data is given in Table 11.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator
CL = Load capacitance including jig and probe capacitance
RL = Load resistor
S1 = Test selection switch
Fig 15. Test circuit for measuring switching times
Table 11.
Test data
Type
Input
Load
S1 position
VI
tr, tf
CL
RL
tPHL, tPLH
74HC193
VCC
6 ns
15 pF, 50 pF
1 k
open
74HCT193
3V
6 ns
15 pF, 50 pF
1 k
open
74HC_HCT193
Product data sheet
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Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
20 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
12. Application information
GDWDLQSXW
' ' ' '
' ' ' '
XSFORFN
&38
7&8
&38
7&8
GRZQFORFN
&3'
,& 7&'
&3'
,& 7&'
3/
05
3/
4 4 4 4
FDUU\
ERUURZ
05
4 4 4 4
DV\QFKURQRXV
SDUDOOHOORDG
UHVHW
GDWDRXWSXW
DDJ
Fig 16. Application for cascaded up/down counter with parallel load
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
21 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
13. Package outline
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74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
22 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
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Fig 18. Package outline SOT338-1 (SSOP16)
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
23 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP
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Fig 19. Package outline SOT403-1 (TSSOP16)
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
24 of 28
74HC193; 74HCT193
NXP Semiconductors
Presettable synchronous 4-bit binary up/down counter
14. Abbreviations
Table 12.
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MM
Machine Model
TTL
Transistor-Transistor Logic
15. Revision history
Table 13.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
74HC_HCT193 v.5
20160129
Product data sheet
-
74HC_HCT193 v.4
Modifications:
74HC_HCT193 v.4
Modifications:
74HC_HCT193 v.3
Modifications:
74HC_HCT193_CNV v.2
74HC_HCT193
Product data sheet
•
Type numbers 74HC193N and 74HCT193N (SOT38-4) removed.
20130624
•
Product data sheet
-
74HC_HCT193 v.3
-
74HC_HCT193_CNV v.2
General description updated.
20070523
Product data sheet
•
The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
•
•
Legal texts have been adapted to the new company name where appropriate.
Family specification included
19970828
Product specification
-
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
-
© NXP Semiconductors N.V. 2016. All rights reserved.
25 of 28
74HC193; 74HCT193
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16. Legal information
16.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
74HC_HCT193
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
26 of 28
74HC193; 74HCT193
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Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
74HC_HCT193
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 29 January 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
27 of 28
74HC193; 74HCT193
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18. Contents
1
2
3
4
5
5.1
5.2
6
7
8
9
10
11
12
13
14
15
16
16.1
16.2
16.3
16.4
17
18
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
Functional description . . . . . . . . . . . . . . . . . . . 5
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 7
Recommended operating conditions. . . . . . . . 7
Static characteristics. . . . . . . . . . . . . . . . . . . . . 8
Dynamic characteristics . . . . . . . . . . . . . . . . . 12
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information. . . . . . . . . . . . . . . . . . 21
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 25
Legal information. . . . . . . . . . . . . . . . . . . . . . . 26
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 26
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Contact information. . . . . . . . . . . . . . . . . . . . . 27
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2016.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 29 January 2016
Document identifier: 74HC_HCT193