ISL8013 ® Data Sheet December 27, 2007 3A Low Quiescent Current 1MHz High Efficiency Synchronous Buck Regulator The ISL8013 is a high efficiency, monolithic, synchronous step-down DC/DC converter that can deliver up to 3A continuous output current from a 2.7V to 5.5V input supply. It uses a current control architecture to deliver very low duty cycle operation at high frequency with fast transient response and excellent loop stability. The ISL8013 integrates a pair of low ON-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 400mV dropout voltage at 3A output current. High 1MHz pulse-width modulation (PWM) switching frequency allows the use of small external components and SYNC input enables multiple ICs to synchronize out of phase to reduce ripple and eliminate beat frequencies. The ISL8013 can be configured for discontinuous or forced continuous operation at light load. Forced continuous operation reduces noise and RF interference while discontinuous mode provides high efficiency by reducing switching losses at light loads. Fault protection is provided by internal hiccup mode current limiting during short circuit and overcurrent conditions, an output over voltage comparator and over-temperature monitor circuit. A power good output voltage monitor indicates when the output is in regulation. The ISL8013 is offered in a space saving 4x4 QFN lead free package with exposed pad lead frames for low thermal resistance. The ISL8013 includes a pair of low ON-resistance P-Channel and N-Channel internal MOSFETs to maximize efficiency and minimize external component count. The 100% duty-cycle operation allows less than 300mV dropout voltage at 3A. The ISL8013 offers a 1ms Power Good (PG) timer at power-up. When shutdown, ISL8013 discharges the output capacitor. Other features include internal soft-start, internal compensation, overcurrent protection, and thermal shutdown. FN6309.1 Features • High Efficiency Synchronous Buck Regulator with up to 97% Efficiency • Power-Good (PG) Output with a 1ms Delay • 2.7V to 5.5V Supply Voltage • 3% Output Accuracy Over-Temperature/Load/Line • 3A Output Current • Start-up with Pre-Biased Output • Internal Soft-Start - 1ms • Soft-Stop Output Discharge During Disabled • 35µA Quiescent Supply Current in PFM Mode • Selectable Forced PWM Mode and PFM Mode • External Synchronization up to 4MHz • Less than 1µA Logic Controlled Shutdown Current • 100% Maximum Duty Cycle • Internal Current Mode Compensation • Peak Current Limiting and Hiccup Mode Short Circuit Protection • Over-Temperature Protection • Small 16 Ld 4mmx4mm QFN • Pb-Free (RoHS Compliant) Applications • DC/DC POL Modules • µC/µP, FPGA and DSP Power • Plug-in DC/DC Modules for Routers and Switchers • Portable Instruments • Test and Measurement Systems • Li-ion Battery Powered Devices • Small Form Factor (SFP) Modules • Bar Code Readers The ISL8013 is offered in a 4mmx4mm 16 Ld QFN package with 1mm maximum height. The complete converter occupies less than 0.4in2 area. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL8013 Pinout Ordering Information *Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. LX -40 to +85 16 Ld 4x4 QFN L16.4x4 LX PKG. DWG. # LX 16 15 14 13 VIN 1 12 PGND VIN 2 11 PGND VDD 3 10 SGND SYNCH 4 9 6 7 SGND 8 VFB 5 PG ISL8013IRZ* 8013IRZ PACKAGE (Pb-Free) NC PART MARKING ISL8013 (16 LD QFN) TOP VIEW NC TEMP. RANGE (°C) EN PART NUMBER (Note) Typical Application INPUT 2.7V TO 5.5V OUTPUT 1.8V L 1.5µH VIN LX C2 2 x 22µF VDD C1 2 x 22µF PGND R2 124k C3 47pF ISL8013 EN R1 100k VFB R3 100k PG SYNCH SGND FIGURE 1. TYPICAL APPLICATION DIAGRAM 2 FN6309.1 December 27, 2007 ISL8013 Block Diagram SYNCH SHUTDOWN SOFT Soft START SHUTDOWN 27pF 390k - BANDGAP 0.8V + EN + COMP - EAMP - VIN OSCILLATOR PWM/PFM LOGIC CONTROLLER PROTECTION DRIVER 3pF + LX PGND VFB SLOPE Slope COMP 6k + - CSA - 0.864V + + 0.736V PG + OCP - 1.4V + SKIP - 0.5V - 1ms DELAY SGND ZERO-CROSS SENSING 0.2V SCP + FIGURE 2. FUNCTIONAL BLOCK DIAGRAM 3 FN6309.1 December 27, 2007 ISL8013 Absolute Maximum Ratings (Reference to GND) Thermal Information VIN, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V EN, SYNCH, PG . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN+0.3V LX. . . . . . . . . . . . . . . . . . . . . . . . . .-1.5V (100ns)/-0.3V (DC) to 6.5V VFB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 2.7V Thermal Resistance (Typical, Notes 1, 2) θJA (°C/W) θJC (°C/W) 16 Ld 4x4 QFN Package . . . . . . . . . 37 6 Junction Temperature Range. . . . . . . . . . . . . . . . . .-55°C to +125°C Storage Temperature Range . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions VIN Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Load Current Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0A to 3A Ambient Temperature Range . . . . . . . . . . . . . . . . . . .-40°C to +85°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 2. θJC, “case temperature” location is at the center of the exposed metal pad on the package underside. See Tech Brief TB379. Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD, unless otherwise noted. Typical values are at TA = +25°C. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Rising, no load - 2.5 2.7 V Falling, no load 2.2 2.4 - V SYNCH = GND, no load at the output - 35 - µA SYNCH = GND, no load at the output and no switches switching - 30 45 µA SYNCH = VDD, FS = 1MHz, no load at the output - 6.5 10 mA VIN = 5.5V, EN = low - 0.1 2 µA 0.790 0.8 0.810 V VFB = 0.75V - 0.1 - µA VIN = VO + 0.5V to 5.5V (minimal 2.7V) - 0.2 - %/V - 1 - ms INPUT SUPPLY VIN Undervoltage Lockout Threshold Quiescent Supply Current VUVLO IVIN Shut Down Supply Current ISD OUTPUT REGULATION Reference Voltage VREF VFB Bias Current IVFB Line Regulation Soft-Start Ramp Time Cycle OVERCURRENT PROTECTION Current Limit Blanking Time tOCON - 17 - Clock pulses Overcurrent and Auto Restart Period tOCOFF - 4 - SS cycle Switch Current Limit ILIMIT (Note 3) 4.0 4.8 5.9 A Peak Skip Limit ISKIP (Note 3) - 1.2 - A - 20 - µA/V 0.213 0.25 0.287 Ω VIN = 5V, IO = 200mA - 50 75 mΩ VIN = 2.7V, IO = 200mA - 70 100 mΩ COMPENSATION Error Amplifier Trans-Conductance Trans-Resistance RT LX P-Channel MOSFET ON-Resistance 4 FN6309.1 December 27, 2007 ISL8013 Electrical Specifications Unless otherwise noted, all parameter limits are established over the recommended operating conditions and the typical specification are measured at the following conditions: TA = -40°C to +85°C, VIN = 3.6V, EN = VDD, unless otherwise noted. Typical values are at TA = +25°C. (Continued) PARAMETER SYMBOL N-Channel MOSFET ON-Resistance TEST CONDITIONS MIN TYP MAX UNITS VIN = 5V, IO = 200mA - 50 75 mΩ VIN = 2.7V, IO = 200mA - 70 100 mΩ - 100 - % 0.80 1.00 1.20 MHz SYNCH = High - - 140 ns Sinking 1mA - - 0.3 V 0.65 1 1.35 ms - 0.01 0.1 µA LX Maximum Duty Cycle PWM Switching Frequency fS LX Minimum On-Time PG Output Low Voltage Delay Time (Rising Edge) PG Pin Leakage Current PG = VIN = 3.6V PGOOD Rising Threshold Percentage of regulation voltage 89 92 95 % PGOOD Falling Threshold Percentage of regulation voltage 85 88 91.5 % - 15 - µs Logic Input Low - - 0.4 V Logic Input High 1.4 - - V - 0.1 1 μA - 0.1 1 μA Thermal Shutdown - 140 - °C Thermal Shutdown Hysteresis - 25 - °C PGOOD Delay Time (Falling Edge) EN, SYNCH Synch Logic Input Leakage Current ISYNCH Enable Logic Input Leakage Current IEN Pulled up to 5.5V NOTE: 3. Limits established by characterization and are not production tested. 5 FN6309.1 December 27, 2007 ISL8013 Pin Descriptions LX VIN Switching node connection. Connect to one terminal of the inductor. Input supply voltage. Connect a 10µF ceramic capacitor to power ground. PGND Power ground. VDD Input supply voltage for the analog circuitry. Connect to VIN pin. SGND EN VFB Regulator enable pin. Enable the output when driven to high. Shut down the chip and discharge output capacitor when driven to low. Do not leave this pin floating. Buck regulator output feedback. Connect to the output through a resistor divider for adjustable output voltage. For 0.8V output voltage, connect this pin to the output. PG NC 1ms timer output. At power-up or EN HI, this output is a 1ms delayed Power-Good signal for the output voltage. No connect. SYNCH The exposed pad must be connected to the SGND pin for proper electrical performance. Place as much vias as possible under the pad connecting to SGND plane for optimal thermal performance. Mode Selection pin. Connect to logic high or input voltage VDD for PWM mode. Connect to logic low or ground for PFM mode. Connect to an external function generator for synchronization with the negative edge trigger. Do not leave this pin floating. 6 Signal ground. Exposed Pad FN6309.1 December 27, 2007 ISL8013 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). 100 100 90 2.5VOUT-PWM 80 EFFICIENCY (%) EFFICIENCY (%) 90 1.8VOUT-PWM 1.5VOUT-PWM 1.2VOUT-PWM 70 60 2.5VOUT-PFM 80 1.8VOUT-PFM 1.5VOUT-PFM 1.2VOUT-PFM 70 60 50 50 40 0.0 0.5 1.0 1.5 2.0 2.5 40 0.0 3.0 0.1 0.2 0.3 OUTPUT LOAD (A) 100 90 90 70 EFFICIENCY (%) EFFICIENCY (%) 100 2.5VOUT-PWM 1.8VOUT-PWM 1.5VOUT-PWM 1.2VOUT-PWM 3.3VOUT-PWM 60 2.5VOUT-PFM 1.8VOUT-PFM 70 0.5 1.0 1.5 2.0 2.5 40 0.0 3.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 OUTPUT LOAD (A) FIGURE 6. EFFICIENCY vs LOAD (1MHz 5VIN PFM) 2.00 125 1.75 POWER DISSIPATION (mW) POWER DISSIPATION (W) 1.2VOUT-PFM 1.5VOUT-PFM 50 FIGURE 5. EFFICIENCY vs LOAD (1MHz 5VIN PWM) 1.50 1.25 1.00 5VIN-PFM 0.75 3.3VIN-PWM 3.3VIN-PFM 5VIN-PWM 0.25 0.00 0.0 1.0 3.3VOUT-PFM 60 OUTPUT LOAD (A) 0.50 0.9 80 50 40 0.0 0.8 FIGURE 4. EFFICIENCY vs LOAD (1MHz 3.3 VIN PFM) FIGURE 3. EFFICIENCY vs LOAD (1MHz 3.3 VIN PWM) 80 0.4 0.5 0.6 0.7 OUTPUT LOAD (A) 0.5 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) FIGURE 7. POWER DISSIPATION vs LOAD (1MHz, VOUT = 1.8V) 7 100 75 50 25 0 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 5.5 FIGURE 8. POWER DISSIPATION WITH NO LOAD vs VIN (PWM VOUT = 1.8V) FN6309.1 December 27, 2007 ISL8013 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Continued) 1.24 1.23 0.20 OUTPUT VOLTAGE (V) POWER DISSIPATION (mW) 0.25 0.15 0.10 0.05 1.22 3.3VIN-PFM 1.21 1.20 1.19 1.18 5VIN-PWM 3.3VIN-PWM 5VIN-PFM 1.17 0 2.0 2.5 3.0 3.5 4.0 VIN (V) 4.5 5.0 1.16 0.0 5.5 2.5 3.0 1.82 3.3VIN-PFM 3.3VIN-PFM OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 2.0 1.83 1.53 1.52 1.51 5VIN-PWM 1.50 3.3VIN-PWM 5VIN-PFM 1.49 1.48 1.81 1.80 1.79 5VIN-PWM 1.78 1.77 3.3VIN-PWM 5VIN-PFM 1.76 1.47 0.0 0.5 1.0 1.5 2.0 2.5 1.75 0.0 3.0 0.5 OUTPUT LOAD (A) 1.0 1.5 2.0 2.5 3.0 OUTPUT LOAD (A) FIGURE 11. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.5V) FIGURE 12. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.8V) 2.52 3.36 3.35 4.5VIN-PWM 3.3VIN-PFM 3.3VIN-PWM 2.50 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.5 FIGURE 10. VOUT REGULATION vs LOAD (1MHz, VOUT = 1.2V) 1.55 2.51 1.0 OUTPUT LOAD (A) FIGURE 9. POWER DISSIPATION WITH NO LOAD vs VIN (PFM VOUT = 1.8V) 1.54 0.5 2.49 2.48 2.47 5VIN-PWM 2.46 2.45 2.44 0.0 5VIN-PFM 0.5 5VIN-PWM 3.34 3.33 3.32 3.31 3.30 5VIN-PFM 4.5VIN-PFM 3.29 1.0 1.5 2.0 OUTPUT LOAD (A) 2.5 3.0 FIGURE 13. VOUT REGULATION vs LOAD (1MHz, VOUT = 2.5V) 8 3.28 0.0 0.5 1.0 1.5 2.0 OUTPUT LOAD (A) 2.5 3.0 FIGURE 14. VOUT REGULATION vs LOAD (1MHz, VOUT = 3.3V) FN6309.1 December 27, 2007 ISL8013 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Continued) 1.830 1.830 1.820 0A LOAD PWM 3A LOAD PWM 1.810 1.800 1.790 1.780 1.770 3A LOAD 1.810 0A LOAD 1.800 1.790 1.780 1.770 1.760 1.760 1.750 2.0 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) 1.820 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1.750 2.0 2.5 3.0 FIGURE 15. OUTPUT VOLTAGE REGULATION vs VIN (PWM VOUT = 1.8 ) 3.5 4.0 4.5 5.0 5.5 INPUT VOLTAGE (V) INPUT VOLTAGE (V) FIGURE 16. OUTPUT VOLTAGE REGULATION vs VIN (PFM VOUT = 1.8V) LX 2V/DIV LX 2V/DIV VOUT RIPPLE 20mV/DIV VOUT RIPPLE 20mV/DIV IL 0.5A/DIV IL 0.5A/DIV FIGURE 17. STEADY STATE OPERATION AT NO LOAD (PWM) FIGURE 18. STEADY STATE OPERATION AT NO LOAD (PFM) LX 2V/DIV LX 2V/DIV IL 1A/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV VOUT RIPPLE 20mV/DIV FIGURE 19. STEADY STATE OPERATION WITH FULL LOAD 9 FIGURE 20. MODE TRANSITION CCM TO DCM FN6309.1 December 27, 2007 ISL8013 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Continued) LX 2V/DIV VOUT RIPPLE 50mV/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV IL 1A/DIV FIGURE 21. MODE TRANSITION DCM TO CCM LX 2V/DIV FIGURE 22. LOAD TRANSIENT (PWM) EN 5V/DIV VOUT 0.5V/DIV VOUT RIPPLE 50mV/DIV IL 1A/DIV IL 1A/DIV FIGURE 23. LOAD TRANSIENT (PFM) PG 5V/DIV FIGURE 24. SOFT-START WITH NO LOAD (PWM) EN 5V/DIV EN 5V/DIV VOUT 0.5V/DIV VOUT 0.5V/DIV IL 5A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV FIGURE 25. SOFT-START AT NO LOAD (PFM) 10 FIGURE 26. SOFT-START WITH PRE-BIASED 1V FN6309.1 December 27, 2007 ISL8013 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Continued) EN 5V/DIV EN 5V/DIV VOUT 0.5V/DIV VOUT 0.5V/DIV IL 1A/DIV IL 1A/DIV PG 5V/DIV PG 5V/DIV FIGURE 27. SOFT-START AT FULL LOAD FIGURE 28. SOFT-DISCHARGE SHUTDOWN LX 2V/DIV LX 2V/DIV SYNCH 2V/DIV IL 1A/DIV SYNCH 2V/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV FIGURE 29. STEADY STATE OPERATION AT NO LOAD WITH FREQUENCY = 2MHz VOUT RIPPLE 20mV/DIV FIGURE 30. STEADY STATE OPERATION AT FULL LOAD WITH FREQUENCY = 2MHz LX 2V/DIV LX 2V/DIV IL 1A/DIV SYNCH 2V/DIV VOUT RIPPLE 20mV/DIV SYNCH 2V/DIV VOUT RIPPLE 20mV/DIV IL 1A/DIV FIGURE 31. STEADY STATE OPERATION AT NO LOAD WITH FREQUENCY = 4MHz 11 FIGURE 32. STEADY STATE OPERATION AT FULL LOAD (PWM) WITH FREQUENCY = 4MHz FN6309.1 December 27, 2007 ISL8013 Typical Operating Performance (Unless otherwise noted, operating conditions are: TA = +25°C, VVIN = 2.5V to 5.5V, EN = VIN, SYNCH = 0V, L = 1.5µH, C1 = 2x22µF, C2 = 2x22µF, IOUT = 0A to 3A). (Continued) LX 2V/DIV PHASE 2V/DIV VOUT 1V/DIV VOUT 0.5V/DIV IL 2A/DIV IL 2A/DIV PG 5V/DIV PG 5V/DIV FIGURE 34. OUTPUT SHORT CIRCUIT RECOVERY FIGURE 33. OUTPUT SHORT CIRCUIT 5.000 OUTPUT CURRENT (A) 4.875 4.750 OCP_3.3VIN 4.625 4.500 4.375 OCP_5VIN 4.250 4.125 4.000 -50 -25 0 25 50 75 100 TEMPERATURE (°C) FIGURE 35. OUTPUT CURRENT LIMIT vs TEMPERATURE Theory of Operation The ISL8013 is a step-down switching regulator optimized for battery-powered handheld applications. The regulator operates at 1MHz fixed switching frequency under heavy load conditions to allow smaller external inductors and capacitors to be used for minimal printed-circuit board (PCB) area. At light load, the regulator reduces the switching frequency, unless forced to the fixed frequency, to minimize the switching loss and to maximize the battery life. The quiescent current when the output is not loaded is typically only 35µA. The supply current is typically only 0.1µA when the regulator is shut down. PWM Control Scheme Pulling the SYNCH pin HI (>2.5V) forces the converter into PWM mode, regardless of output current. The ISL8013 employs the current-mode pulse-width modulation (PWM) control scheme for fast transient response and pulse-by-pulse current limiting. Figure 2 shows the block diagram. The current loop consists of the oscillator, the PWM comparator, current sensing circuit and the slope compensation for the current loop stability. The gain for the current sensing circuit is typically 12 250mV/A. The control reference for the current loops comes from the error amplifier's (EAMP) output. The PWM operation is initialized by the clock from the oscillator. The P-Channel MOSFET is turned on at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current amplifier CSA and the slope compensation (237mV/µs) reaches the control reference of the current loop, the PWM comparator COMP sends a signal to the PWM logic to turn off the P-MOSFET and turn on the N-Channel MOSFET. The N-MOSFET stays on until the end of the PWM cycle. Figure 36 shows the typical operating waveforms during the PWM operation. The dotted lines illustrate the sum of the slope compensation ramp and the current-sense amplifier’s CSA output. The output voltage is regulated by controlling the VEAMP voltage to the current loop. The bandgap circuit outputs a 0.8V reference voltage to the voltage loop. The feedback signal comes from the VFB pin. The soft-start block only affects the operation during the start-up and will be discussed separately. The error amplifier is a transconductance amplifier that converts the voltage error FN6309.1 December 27, 2007 ISL8013 signal to a current output. The voltage loop is internally compensated with the 27pF and 390kΩ RC network. The maximum EAMP voltage output is precisely clamped to 1.6V. The regulator resumes normal PWM mode operation when the output voltage drops 1.5% below the nominal voltage. Synchronization Control The frequency of operation can be synchronized up to 4MHz by an external signal applied to the SYNCH pin. The falling edge on the SYNCH triggers the rising edge of the LX pulse. Make sure that the minimum on time of the LX node is greater than 140ns. VEAMP VCSA DUTY CYCLE Overcurrent Protection IL VOUT FIGURE 36. PWM OPERATION WAVEFORMS SKIP Mode Pulling the SYNCH pin LO (<0.4V) forces the converter into PFM mode. The ISL8013 enters a pulse-skipping mode at light load to minimize the switching loss by reducing the switching frequency. Figure 37 illustrates the skip-mode operation. A zero-cross sensing circuit shown in Figure 2 monitors the N-MOSFET current for zero crossing. When 8 consecutive cycles of the inductor current crossing zero are detected, the regulator enters the skip mode. During the eight detecting cycles, the current in the inductor is allowed to become negative. The counter is reset to zero when the current in any cycle does not cross zero. Once the skip mode is entered, the pulse modulation starts being controlled by the SKIP comparator shown in Figure 2. Each pulse cycle is still synchronized by the PWM clock. The P-MOSFET is turned on at the clock's rising edge and turned off when the output is higher than 1.5% of the nominal regulation or when its current reaches the peak Skip current limit value. Then the inductor current is discharging to zero Ampere and stays at zero. The internal clock is disabled.The output voltage reduces gradually due to the load current discharging the output capacitor. When the output voltage drops to the nominal voltage, the P-MOSFET will be turned on again at the rising edge of the internal clock as it repeats the previous operations. The overcurrent protection is realized by monitoring the CSA output with the OCP comparator, as shown in Figure 2. The current sensing circuit has a gain of 250mV/A, from the P-MOSFET current to the CSA output. When the CSA output reaches 1.4V, which is equivalent to 4.8A for the switch current, the OCP comparator is tripped to turn off the P-MOSFET immediately. The overcurrent function protects the switching converter from a shorted output by monitoring the current flowing through the upper MOSFET. Upon detection of overcurrent condition, the upper MOSFET will be immediately turned off and will not be turned on again until the next switching cycle. Upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1. If, on the subsequent cycle, another overcurrent condition is detected, the OC fault counter will be incremented. If there are 17 sequential OC fault detections, the regulator will be shut down under an overcurrent fault condition. An overcurrent fault condition will result in the regulator attempting to restart in a hiccup mode within the delay of four soft-start periods. At the end of the fourth soft-start wait period, the fault counters are reset and soft-start is attempted again. If the overcurrent condition goes away during the delay of four soft-start periods, the output will resume back into regulation point after hiccup mode expires. Short-Circuit Protection The short-circuit protection SCP comparator monitors the VFB pin voltage for output short-circuit protection. When the VFB is lower than 0.2V, the SCP comparator forces the PWM oscillator frequency to drop to 1/3 of the normal operation value. This comparator is effective during start-up or an output short-circuit event. CLOCK 8 CYCLES IL CURRENT LIMIT LOAD CURRENT 0 NOMINAL +1.5% VOUT NOMINAL FIGURE 37. SKIP MODE OPERATION WAVEFORMS 13 FN6309.1 December 27, 2007 ISL8013 PG Thermal Shut-Down During power-up, the open-drain power good output holds low for about 1ms after VOUT reaches the regulation voltage. The PG output also serves as a 1ms delayed the Power Good signal when the pull-up resistor R1 is installed. The ISL8013 has built-in thermal protection. When the internal temperature reaches +140°C, the regulator is completely shut down. As the temperature drops to +115°C, the ISL8013 resumes operation by stepping through the soft-start. UVLO Applications Information When the input voltage is below the undervoltage lock-out (UVLO) threshold, the regulator is disabled. Output Inductor and Capacitor Selection Soft Start-Up The soft-start-up reduces the inrush current during the startup. The soft-start block outputs a ramp reference to the input of the error amplifier. This voltage ramp limits the inductor current as well as the output voltage speed so that the output voltage rises in a controlled fashion. When VFB is less than 0.2V at the beginning of the soft-start, the switching frequency is reduced to 1/3 of the nominal value so that the output can start up smoothly at light load condition. During soft-start, the IC operates in the SKIP mode to support pre-biased output condition. Enable The enable (EN) input allows the user to control the turning on or off the regulator for purposes such as power-up sequencing. When the regulator is enabled, there is typically a 600µs delay for waking up the bandgap reference and then the soft-start-up begins. Discharge Mode (Soft-Stop) When a transition to shutdown mode occurs or the VIN UVLO is set, the outputs discharge to GND through an internal 100Ω switch. Power MOSFETs To consider steady state and transient operations, ISL8013 typically uses a 1.5µH output inductor. The higher or lower inductor value can be used to optimize the total converter system performance. For example, for higher output voltage 3.3V application, in order to decrease the inductor current ripple and output voltage ripple, the output inductor value can be increased. It is recommended to set the ripple inductor current approximately 30% of the maximum output current for optimized performance. The inductor ripple current can be expressed as shown in Equation 1: VO ⎞ ⎛ V O • ⎜ 1 – ---------⎟ V ⎝ IN⎠ ΔI = --------------------------------------L • fS (EQ. 1) The inductor’s saturation current rating needs to be at least larger than the peak current. The ISL8013 protects the typical peak current 4.8A. The saturation current needs be over 5.5A for maximum output current application. ISL8013 uses internal compensation network and the output capacitor value is dependent on the output voltage. The ceramic capacitor is recommended to be X5R or X7R. The recommended X5R or X7R minimum output capacitor values are shown in Table 1. TABLE 1. OUTPUT CAPACITOR VALUE vs VOUT The power MOSFETs are optimized for best efficiency. The ON-resistance for the P-MOSFET is typically 50mΩ and the ON-resistance for the N-MOSFET is typically 50mΩ. 100% Duty Cycle The ISL8013 features 100% duty cycle operation to maximize the battery life. When the battery voltage drops to a level that the ISL8013 can no longer maintain the regulation at the output, the regulator completely turns on the P-MOSFET. The maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the ON-resistance of the P-MOSFET. 14 VOUT COUT L 0.8V 2 x 22µF 1.0µH~2.2µH 1.2V 2 x 22µF 1.0µH~2.2µH 1.5V 2 x 22µF 1.5µH~3.3µH 1.8V 2 x 22µF 1.5µH~3.3µH 2.5V 2 x 22µF 1.5µH~3.3µH 3.3V 2 x 22µF 2.2µH~4.7µH 3.6V 2 x 22µF 2.2µH~4.7µH In Table 1, the minimum output capacitor value is given for the different output voltage to make sure that the whole converter system is stable. FN6309.1 December 27, 2007 ISL8013 Output Voltage Selection The output voltage of the regulator can be programmed via an external resistor divider that is used to scale the output voltage relative to the internal reference voltage and feed it back to the inverting input of the error amplifier. Refer to Figure 1. The output voltage programming resistor, R3, will depend on the value chosen for the feedback resistor and the desired output voltage of the regulator. The value for the feedback resistor is typically between 10kΩ and 100kΩ, as shown in Equation 2. R 2 × 0.8V R 3 = ---------------------------------V OUT – 0.8V (EQ. 2) If the output voltage desired is 0.8V, then R3 is left unpopulated and R2 is shorted. There is a leakage current from VIN to LX. It is recommended to preload the output with 10µA minimum. For better performance, add 47pF in parallel with R2 (100kΩ). Input Capacitor Selection The main functions for the input capacitor are to provide decoupling of the parasitic inductance and to provide filtering function to prevent the switching current flowing back to the battery rail. Two 22µF X5R or X7R ceramic capacitors are a good starting point for the input capacitor selection. 15 FN6309.1 December 27, 2007 ISL8013 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP) L16.4x4 16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220-VGGC ISSUE C) MILLIMETERS SYMBOL MIN NOMINAL MAX NOTES A 0.80 0.90 1.00 - A1 - - 0.05 - A2 - - 1.00 A3 b 0.23 D 0.28 9 0.35 5, 8 4.00 BSC D1 D2 9 0.20 REF - 3.75 BSC 1.95 2.10 9 2.25 7, 8 E 4.00 BSC - E1 3.75 BSC 9 E2 1.95 e 2.10 2.25 7, 8 0.65 BSC - k 0.25 - - - L 0.50 0.60 0.75 8 L1 - - 0.15 10 N 16 2 Nd 4 3 Ne 4 3 P - - 0.60 9 θ - - 12 9 Rev. 5 5/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & θ are present when Anvil singulation method is used and not present for saw singulation. 10. Depending on the method of lead termination at the edge of the package, a maximum 0.15mm pull back (L1) maybe present. L minus L1 to be equal to or greater than 0.3mm. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 16 FN6309.1 December 27, 2007