SiI9589 Port Processor Data Sheet SiI-DS-1097-D March 2016 SiI9589 Port Processor Data Sheet Contents 1. General Description ......................................................................................................................................................5 1.1. Features...............................................................................................................................................................5 1.2. HDMI Inputs and Output .....................................................................................................................................5 1.3. Performance Improvement Features ..................................................................................................................5 1.4. Control Capability ................................................................................................................................................5 1.5. Packaging.............................................................................................................................................................5 2. Functional Description ..................................................................................................................................................7 2.1. Always-on Section ...............................................................................................................................................7 2.1.1. Serial Ports Block.............................................................................................................................................8 2.1.2. Static RAM Block .............................................................................................................................................8 2.1.3. NVRAM Block ..................................................................................................................................................8 2.1.4. HDCP Register Block ........................................................................................................................................8 2.1.5. OTP ROM Block ...............................................................................................................................................8 2.1.6. Booting Sequencer ..........................................................................................................................................9 2.1.7. Configuration, Status, and Interrupt Control Registers Blocks .......................................................................9 2.1.8. MHL Control Block ..........................................................................................................................................9 2.2. Power-down Section ...........................................................................................................................................9 2.2.1. TMDS Receiver Blocks .....................................................................................................................................9 2.2.2. 5:1 Input Multiplexer Blocks ...........................................................................................................................9 2.2.3. MHL Demultiplexer Blocks ..............................................................................................................................9 2.2.4. 2:1 HDMI/MHL Multiplexer Blocks .................................................................................................................9 2.2.5. Packet Analyzer Blocks ....................................................................................................................................9 2.2.6. HDCP Authentication Block .............................................................................................................................9 2.2.7. MP and RP HDMI Receive Data Path and HDCP Unmask Blocks ....................................................................9 2.2.8. Repeater SHA Block ......................................................................................................................................10 2.2.9. AV Mute Block...............................................................................................................................................10 2.2.10. TMDS Transmitter Block ...........................................................................................................................10 2.3. ARC Block...........................................................................................................................................................10 3. Electrical Specifications ..............................................................................................................................................11 3.1. Absolute Maximum Conditions .........................................................................................................................11 3.2. Normal Operating Conditions ...........................................................................................................................12 3.3. DC Specifications ...............................................................................................................................................13 3.4. AC Specifications ...............................................................................................................................................15 3.5. Miscellaneous Timing ........................................................................................................................................16 3.6. Reset Timing ......................................................................................................................................................16 4. Pin Diagram and Pin Descriptions ...............................................................................................................................17 4.1. Pin Diagram .......................................................................................................................................................17 4.2. Pin Descriptions .................................................................................................................................................18 4.2.1. HDMI and MHL Receiver Port Pins ................................................................................................................18 4.2.2. Audio Pins .....................................................................................................................................................19 4.2.3. HDMI Transmitter Port Pins ..........................................................................................................................19 4.2.4. System Switching Pins ...................................................................................................................................19 4.2.5. Control Pins ...................................................................................................................................................20 4.2.6. Configuration Pins .........................................................................................................................................20 4.2.7. Power and Ground Pins ................................................................................................................................21 4.2.8. Reserved Pins ................................................................................................................................................21 5. Feature Information....................................................................................................................................................22 5.1. Standby and HDMI Port Power Supplies ...........................................................................................................22 5.2. Hardware Reset .................................................................................................................................................23 5.3. Built-in Pattern Generator.................................................................................................................................24 5.4. 3D Video Formats ..............................................................................................................................................25 5.5. 3D Markers and VS Insertion .............................................................................................................................25 © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 2 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 5.6. Input Video Resolution Detection and InfoFrame Extraction ........................................................................... 26 5.7. Repeater Support .............................................................................................................................................. 26 5.8. Audio Return Channel ....................................................................................................................................... 27 5.9. EDID Memory .................................................................................................................................................... 28 2 5.10. Local I C Port ..................................................................................................................................................... 29 6. Design Recommendations .......................................................................................................................................... 30 6.1. Audio Return Channel Design ........................................................................................................................... 30 6.2. MHL Power and Cable Detect Design ............................................................................................................... 31 6.3. Power Supply Decoupling ................................................................................................................................. 31 6.4. Power Supply Sequencing ................................................................................................................................. 32 7. Package Information ................................................................................................................................................... 33 7.1. ePad Requirements ........................................................................................................................................... 33 7.2. Package Dimensions .......................................................................................................................................... 34 7.3. Marking Specification ........................................................................................................................................ 35 7.4. Ordering Information ........................................................................................................................................ 35 References .......................................................................................................................................................................... 36 Standards Documents..................................................................................................................................................... 36 Standards Groups ........................................................................................................................................................... 36 Lattice Semiconductor Documents ................................................................................................................................. 36 Technical Support ........................................................................................................................................................... 36 Revision History .................................................................................................................................................................. 37 © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 3 SiI9589 Port Processor Data Sheet Figures Figure 1.1. Port Processor Application..................................................................................................................................6 Figure 2.1. Functional Block Diagram ...................................................................................................................................7 2 Figure 2.2. I C Control Mode Configuration .........................................................................................................................8 Figure 3.1. Test Point VDDTP for VDD33 Noise Tolerance Specification ............................................................................12 Figure 3.2. RESET# Minimum Timing ..................................................................................................................................16 Figure 4.1. Pin Diagram (Top View) ....................................................................................................................................17 Figure 5.1. Standby Power Supply Diagram ........................................................................................................................23 Figure 5.2. External Reset Circuit ........................................................................................................................................24 Figure 5.3. VS Insertion in Active Space ..............................................................................................................................26 Figure 5.4. 3D Markers on CTL0/1 Signals ..........................................................................................................................26 Figure 5.5. Audio Return Channel Example Application .....................................................................................................27 Figure 5.6. EDID Block Diagram ..........................................................................................................................................28 Figure 6.1. Connection of ARC to HDMI Port ......................................................................................................................30 Figure 6.2. Connection of MHL Power and Cable Detect ...................................................................................................31 Figure 6.3. Decoupling and Bypass Schematic ....................................................................................................................31 Figure 6.4. Decoupling and Bypass Capacitor Placement ...................................................................................................32 Figure 7.1. Package Diagram ...............................................................................................................................................34 Figure 7.2. Marking Diagram ..............................................................................................................................................35 Tables Table 3.1. Absolute Maximum Conditions ..........................................................................................................................11 Table 3.2. Normal Operating Conditions ............................................................................................................................12 Table 3.3. Digital I/O Specifications ....................................................................................................................................13 Table 3.4. Power Requirements..........................................................................................................................................13 Table 3.5. TMDS Input DC Specifications – HDMI Mode ....................................................................................................14 Table 3.6. TMDS Input DC Specifications – MHL Mode ......................................................................................................14 Table 3.7. TMDS Output DC Specifications .........................................................................................................................14 Table 3.8. Single Mode Audio Return Channel DC Specifications .......................................................................................14 Table 3.9. CBUS DC Specifications ......................................................................................................................................14 Table 3.10. TMDS Input Timing AC Specifications – HDMI Mode .......................................................................................15 Table 3.11. TMDS Input Timing AC Specifications – MHL Mode.........................................................................................15 Table 3.12. TMDS Output Timing AC Specifications ...........................................................................................................15 Table 3.13. Single Mode Audio Return Channel AC Specifications .....................................................................................15 Table 3.14. S/PDIF Input Port AC Specifications .................................................................................................................16 Table 3.15. CBUS AC Specifications ....................................................................................................................................16 Table 3.16. Miscellaneous Timing .......................................................................................................................................16 Table 5.1. Description of Power Modes ..............................................................................................................................22 Table 5.2. Built-in Pattern List .............................................................................................................................................24 Table 5.3. Supported 3D Video Formats .............................................................................................................................25 2 Table 5.4. I C Register Address Groups...............................................................................................................................29 © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 4 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 1. General Description The Lattice Semiconductor SiI9589 HDMI® port processor delivers five HDMI inputs with fast InstaPort™ S port switching to DTVs and other consumer electronic devices. One HDMI input can automatically detect and switch between HDMI and Mobile High-definition Link (MHL®) mode. MHL technology is available on any one input port. MHL allows consumers to attach their mobile devices to the television and view high definition content while the television charges the mobile device battery. In Port Power-only mode, the SiI9589 port processor does not require initialization and does not consume any system power. The 5 V provided by the HDMI source device powers the EDID circuitry. The EDID information is read from SRAM, which loads from an NVRAM that can be reprogrammed multiple times by system firmware. The SiI9589-3 version is rated at 300 MHz, which enables 4K x 2K, 1080p 60 Hz 3D and 1080p 120 Hz resolution. This part supports the single-mode Audio Return Channel (ARC) described in the HDMI 1.4 Specification. ARC transmits an S/PDIF audio signal from an HDMI sink to an HDMI source in the opposite direction of the TMDS data flow. ARC simplifies audio connectivity and switching for the consumer. The SiI9589 port processor enables 3D television design with three essential features: Vendor Specific InfoFrame (VSIF) extraction that recognizes 3D video; VSYNC insertion to convert frame-packed 3D video into 1080p, 120 Hz, 1080p, 48 Hz, or 720p, 100/120 Hz video which can be used by an SoC; and Left/Right markers sent in-band over TMDS to identify left and right video frames. The left marker can also optionally be sent on the GPIO0 pin. 1.1. Features Adaptive equalizer provides long cable support Built-in pattern generator to speed design, test, and manufacturing 1.2. HDMI Inputs and Output Five HDMI input ports and one output port HDMI, HDCP, and DVI compatible TMDS™ cores run at 300 MHz (SiI9589-3 device only) Supports video resolutions up to 4K x 2K, 1080p 120 Hz, and 1080P 3D, 60 Hz (SiI9589-3 device only) MHL support up to 1080p @ 30 Hz Pre-programmed with HDCP keys Repeater function supports up to 127 devices 1.3. Performance Improvement Features InstaPort™ S viewing technology allows manufacturers to build TVs which switch HDMI input ports in one second AVI, Audio InfoFrame, and video input resolution detection for all input ports, accessible port-byport Hardware-based HDCP error detection and recovery minimizes firmware intervention Automatic output mute and unmute based on link stability, such as cable connect/detach 1.4. Control Capability Integrated EDID and DDC support for the HDMI/VGA ports using a 512-byte NVRAM shared between ports. Individual control of Hot Plug Detect (HPD) for each port 2 Controllable by the local I C bus 1.5. Packaging 100-pin, 14 mm x 14 mm, 0.5 mm pitch TQFP package with exposed pad (ePad) © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 5 SiI9589 Port Processor Data Sheet Figure 1.1. Port Processor Application © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 6 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 2. Functional Description Figure 2.1 shows the block diagram of the SiI9589 port processor. Tie one CD_SENSE line to MHL CD_SENSE, the rest to ground Alwys-On Section CD_SENSE0–4 5 CBUS_HPD0–4 MHL Control 5 Serial Ports DDC I2C R0X R1X R2X R3X DDC0 DDC1 DDC2 DDC3 DDC4 DDC5 EDID SRAM HDCP Registers Local I2 C Booting Sequencer OTP Configuration, Status, and Interrupt Control Registers INT Power- Down Section TMDS Rx (Port 0) A DPLL TMDS Rx (Port 1) TMDS Rx (Port 4) HDCP Authentication MHL Demux TMDS Rx (Port 2) TMDS Rx (Port 3) C Packet Analyzer Repeater SHA Packet Analyzer B DPLL R4X NVRAM D HDMI Data Path and HDCP Unmask AV Mute TMDS Tx TX MHL Demux ARC ARC SPDIF Connect to any one input port Note: MHL input can be assigned to any port during design but is hardwired and cannot be selected using firmware. Figure 2.1. Functional Block Diagram 2.1. Always-on Section 2 The Always-on section contains the low speed control parts of the HDMI connection, and includes the I C interfaces, internal memory blocks, and the registers that control the blocks of the Power-down section. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 7 SiI9589 Port Processor Data Sheet 2.1.1. Serial Ports Block 2 The Serial Ports Block provides seven I C serial interfaces: 5 DDC ports to communicate with the HDMI or DVI hosts, 2 one VGA DDC port, and one local I C port for initialization and control by a local microcontroller in the display. Each 2 interface is 5 V tolerant. Figure 2.2 shows the connection of the local I C port to the system microcontroller. VDD33 CSDA SiI9589 Port Processor System Microcontroller CSCL INT 2 Figure 2.2. I C Control Mode Configuration The six DDC interfaces (DDC 0–5) on the SiI9589 port processor are slave interfaces that can run up to 400 kHz. Each interface connects to one E-DDC bus and is used to read the integrated EDID and HDCP authentication information. The port is accessible on the E-DDC bus at device addresses 0xA0 for the EDID and 0x74 for HDCP control. This feature complies with the HDCP 1.4 Specification. 2 Refer to the Local I2C section on page 29 for information about the I C addresses and the use of the CI2CA pin. 2.1.2. Static RAM Block The EDID Static RAM (SRAM) Block contains 2176 bytes of RAM. Each port is allocated a 256-byte block for DDC; this allows all ports to be read simultaneously from five different sources connected to the SiI9589 device. A 128-byte block is available for VGA DDC, 640 bytes are available for KSVs, 64 bytes are used for the Auto-boot feature, and 64 bytes are 2 reserved. Every EDID and SHA KSV has an offset location. The SRAM can be written to and read from using the local I C interface and it can be read through the DDC interface. The memory can be read without main TV power (VCC33), using 5 V power from the HDMI connector. See the EDID Memory section on page 28 for information about how the SRAM and NVRAM work together. 2.1.3. NVRAM Block The port processor contains 512 bytes of NVRAM, 256 of which is used to store common EDID data used by each of the ports, 128 of which is used for VGA DDC, and 64 of which is used by the Auto-boot feature. (64 bytes are unused.) Both 2 the NVRAM EDID data and NVRAM Auto-boot data should be initialized by software using the local I C bus at least once during the time of manufacture. 2.1.4. HDCP Register Block The HDCP Register Block controls the necessary logic to decrypt the incoming audio and video data. The decryption process is controlled entirely by the host side microcontroller using a set sequence of register reads and writes through the DDC channel. The decryption process uses pre-programmed HDCP keys and Key Selection Vector (KSV) stored in the on-chip non-volatile memory. 2.1.5. OTP ROM Block The OTP ROM Block is programmed at the factory and contains the pre-programmed HDCP keys. System manufacturers do not need to purchase key sets from the Digital Content Protection LLC. All purchasing, programming, and security for the HDCP keys is handled by Lattice Semiconductor. The preprogrammed HDCP keys provide the highest level of security, as keys cannot be read out of the device after they are programmed. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 8 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 2.1.6. Booting Sequencer The Booting Sequencer boots up the required data, such as EDID, initial HPD status, and MHL port selection from NVRAM during power-on. 2.1.7. Configuration, Status, and Interrupt Control Registers Blocks The Configuration, Status, and Interrupt Control Registers blocks incorporate the registers required for configuring and managing the features of the SiI9589 port processor. These registers are used to perform audio/video/auxiliary format 2 processing, CEA-861E InfoFrame Packet format, and power-down control. The registers are accessible from the local I C port. This block also handles interrupt operation. 2.1.8. MHL Control Block The MHL Control Block handles CBUS conversion of RCP and DDC signals for the HDCP interface and EDID blocks. 2.2. Power-down Section The Power-down section contains HDMI high-speed data paths, including the analog TMDS input and output blocks and the digital logic for HDMI data and HDCP processing. 2.2.1. TMDS Receiver Blocks The receiver ports, defined as Port 0, Port 1, Port 2, Port 3, and Port 4 are terminated separately, equalized under the 2 control of the receiver digital block, and controlled by the local I C bus. 2.2.2. 5:1 Input Multiplexer Blocks 5:1 Input Multiplexer Blocks A and B select one of the five inputs. Multiplexer Block A sequentially selects one of the four inactive inputs and sends its data over the roving pipe to the DPLL block and the MHL demux block. Multiplexer Block B selects the active input and sends its data over the main pipe to be processed. 2.2.3. MHL Demultiplexer Blocks If the signal received from the DPLL block only appears in one of the three lanes, the input is an MHL signal. The Demultiplexer block distributes the single-lane RGB serial data blocks over the three parallel RGB lanes of video data. 2.2.4. 2:1 HDMI/MHL Multiplexer Blocks 2:1 HDMI/MHL Multiplexer Blocks C and D select either the HDMI from the DPLL block or the MHL converted to HDMI by the MHL Demultiplexer. Block C transfers data from the roving pipe, and block D transfers data from the main pipe. 2.2.5. Packet Analyzer Blocks The Packet Analyzer blocks extract the control signals from the HDMI control packets that are needed to control the HDCP decryption process in the main and the roving pipe. HDCP decryption is controlled by register information. 2.2.6. HDCP Authentication Block The active receiver port switched to the main pipe is permanently connected to its HDCP decryption block. The remaining four ports share the roving pipe. Each of the decryption blocks are sequentially switched to its input port for a period long enough to get the control information from the HDMI packets needed for the preauthentication process. There is a small probability of missing important information in the roving process because of the unpredictable occurrence of control packets. The missed information is detected and leads to a full reauthentication of the corresponding HDCP path. 2.2.7. MP and RP HDMI Receive Data Path and HDCP Unmask Blocks HDMI data from the Main Pipe (MP) and Roving Pipe (RP) are sent to and processed by the respective HDMI Receive Data Path and HDCP Unmask blocks. The appropriate decryption key for the main port and the input port currently © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 9 SiI9589 Port Processor Data Sheet connected to the roving pipe is applied to the XOR mask in these blocks to descramble the video, audio, and auxiliary packets. 2.2.8. Repeater SHA Block The Repeater Secured Hash Algorithm (SHA) Block is used only when the port processor is configured as a repeater, in which HDMI receiver and transmitter connections are cascaded. In this case each transmitter has to ensure that all downstream receivers are HDCP-compliant. To make sure that all receivers in the downstream path are protected by HDCP, the downstream transmitters propagate a ready signal to the final upstream source transmitter. 2.2.9. AV Mute Block The AV Mute Block controls audio and video mute, using two methods. Software mute is controlled by register settings. When hardware mute is enabled, audio and video are automatically muted and un-muted if an ECC error occurs. 2.2.10. TMDS Transmitter Block The Transmitter Block delivers an HDMI content stream, based on the content of the original stream from the selected source. Internal source termination eliminates the need to use external R-C components for signal shaping. The internal source termination can be disabled. 2.3. ARC Block The Audio Return Channel (ARC) Block allows digital S/PDIF data received from the sink device to be transmitted in the direction opposite to the TMDS input port signal. The block embeds the audio data, in single mode format, in the same lines connected to the Utility pin of the HDMI connector. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 10 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 3. Electrical Specifications 3.1. Absolute Maximum Conditions Table 3.1. Absolute Maximum Conditions Symbol Parameter Min Typ Max Unit Notes VDD33 Supply voltage −0.3 — 4.0 V 1, 2 SBVCC5 Supply voltage −0.3 — 5.7 V 1, 2 RnPWR5V 5 V input from power pin of HDMI connector −0.3 — 5.7 V 1, 2 R5PWR5V 5 V input from power pin of VGA connector −0.3 — 5.7 V 1, 2 LPSBV Low-power Standby voltage −0.3 — 4.0 V 1, 2 AVDD12 TMDS receiver core supply voltage −0.3 — 1.5 V 1, 2 VDD12 Digital core supply voltage −0.3 — 1.5 V 1, 2 TCVDD12 TMDS transmitter core supply voltage −0.3 — 1.5 V 1, 2 TPVDD12 TMDS transmitter PLL supply voltage −0.3 — 1.5 V 1, 2 VI Input voltage −0.3 — VDD33 + 0.3 V 1, 2, 3 VO Output voltage −0.3 — VDD33 + 0.3 V 1, 2, 4 TJ Junction temperature 0 — 125 C — TSTG Storage temperature −65 — 150 C — VESD ESD voltage per IEC 61000-4-2 (Contact) 8 — — kV 5 ESD voltage per IEC 61000-4-2 (Air) 8 — — kV 5 Notes: 1. Permanent device damage can occur if absolute maximum conditions are exceeded. 2. Functional operation should be restricted to the conditions described in the Normal Operating Conditions section below. 3. 5 V tolerant input signals. 4. 5 V output signals. 5. System-level tests at HDMI connectors. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 11 SiI9589 Port Processor Data Sheet 3.2. Normal Operating Conditions Table 3.2. Normal Operating Conditions Symbol Parameter Min Typ Max Unit Notes VDD33 Supply voltage 3.14 3.3 3.46 V — SBVCC5 Supply voltage 4.3 5.0 5.5 V 2 RnPWR5V 5 V input from power pin of HDMI connector 4.3 5.0 5.5 V 2 R5PWR5V 5 V input from power pin of VGA connector 4.3 5.0 5.5 V 2 LPSBV Low-power Standby voltage 3.14 3.3 3.46 V 7 AVDD12 TMDS receiver core supply voltage 1.08 1.2 1.32 V 5 1.14 1.2 1.26 V 6 VDD12 Digital core supply voltage 1.08 1.2 1.32 V 5 1.14 1.2 1.26 V 6 TCVDD12 TMDS transmitter core supply voltage 1.08 1.2 1.32 V 5 1.14 1.2 1.26 V 6 1.08 1.2 1.32 V 5 TPVDD12 TMDS transmitter PLL supply voltage 1.14 1.2 1.26 V 6 VDD12N Supply voltage noise for 1.2V power — — 75 mVP-P 1 VDD33N Supply voltage noise for 3.3V power — — 100 mVP-P 1 TA Ambient temperature (with power applied) 0 +25 +70 C — ja Ambient thermal resistance (Theta JA) — — 29.3 C/W 3,4 jc Junction to case resistance (Theta JC) — — 12.6 C/W 4 Notes: 1. The supply voltage noise is measured at test point VDDTP shown in Figure 3.1. The ferrite bead provides filtering of power supply noise. The figure is representative and applies to other VDD pins as well. 2. The MHL VBUS voltage requirements may be more stringent than the 5 V power supply requirements for the port processor itself. 3. Airflow at 0 m/s. 4. The thermal resistance figures are based on a 4-layer PCB. 5. SiI9589 device. 6. SiI9589-3 device. 7. Voltage listed is supplied to the required 5.1 kΩ series resistor. Actual voltage measured at the LPSBV pin is approximately 2.4 V. VDDTP Ferrite VDD 10 F 10 F 0.1 F 0.1 F SiI9589 GND Figure 3.1. Test Point VDDTP for VDD33 Noise Tolerance Specification © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 12 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 3.3. DC Specifications Table 3.3. Digital I/O Specifications Symbol VIH Parameter HIGH-level Input Voltage Pin Type LVTTL VIL Vth+ RESET# LOW-level Input Voltage LOW-to-HIGH Threshold RESET # pin HIGH-to-LOW Threshold RESET# pin Vth-RESET# VTH+DDC VTH-DDC VTH+I2C LOW-to-HIGH Threshold DDC Bus HIGH-to-LOW Threshold DDC Bus LOW-to-HIGH Threshold 2 I C Bus 1 Conditions — Min 2.0 Typ — Max — Units V Notes 1 LVTTL — — — 0.8 V Schmitt — 2.0 — 1 — Schmitt — — — 0.8 V Schmitt — 3.0 — — V Schmitt — — — 1.5 V Schmitt — 2.0 — — V Schmitt — — — 0.8 V LVTTL IOH = 8 mA 2.4 — — V 4 LVTTL Opendrain Opendrain IOL = –8 mA — — 0.4 V IOL = –3 mA — — 0.4 V 4 3 IOL = –3 mA — — 0.4 V V — 3 3 — VOH HIGH-to-LOW Threshold 2 I C Bus HIGH-level Output Voltage VOL LOW-level Output Voltage VOL_DDC LOW-level Output Voltage VOL_I2C LOW-level Output Voltage IIL Input Leakage Current LVTTL High-impedance −10 — 10 A — IOL Output Leakage Current LVTTL High-impedance −10 — 10 — IOD8 8 mA Digital Output Drive LVTTL VOUT = 2.4 V VOUT = 0.4 V 8 8 — — — — A mA mA VTH-I2C — — 4 4 Notes: 1. Refer to the Pin Descriptions section on page 18 for pin type designations for all package pins. 2. Applies to the GPIO, SPDIF_IN, and TPWR_CI2CA signal pins. 3. Applies to the DDC interface. 4. Applies to the GPIO, INT, and TPWR_CI2CA signal pins. Table 3.4. Power Requirements Symbol Parameter IAVDD12 IVDD33 297 MHz 225 MHz Unit Notes 334 mA 1 260 mA 1 Typ Max Typ Max Supply Current for Analog VDD12 390 411 314 Supply Current for VDD33 260 260 260 IVDD12 Supply Current for Digital VDD12 240 283 201 218 mA 1 ISBVCC5SB Supply Current for SBVCC5 during standby 6 7 6 7 mA — ISBVCC5OP IRnPWR5V Supply Current for SBVCC5 during operation Supply Current for RnPWR5V during operation 8 2 9 4 8 2 9 4 mA mA 1 1, 2 ITCVDD12 Supply Current for TCVDD12 25 26 17 19 mA 1 ITPVDD12 Supply Current for TPVDD12 15 16 13 14 mA 1 ILPSBVSOP Supply Current for LPSBV during normal operation 200 210 200 210 µA 1 Total Total Power 1680 1902 1543 1722 mW 1 Notes: 1. Maximum supply currents are measured at maximum operating voltages, with all inputs and outputs switching at the measurement frequency listed. 2. The power provided by IRnPWR5V is not included in the Total Power row. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 13 SiI9589 Port Processor Data Sheet Table 3.5. TMDS Input DC Specifications – HDMI Mode Symbol Parameter Conditions Min Typ Max Units VID Differential-mode Input Voltage — 150 — 1200 mV VICM Common-mode Input Voltage — AVDD33 – 400 — AVDD33 – 37.5 mV Table 3.6. TMDS Input DC Specifications – MHL Mode Symbol Parameter Conditions Min Typ Max Units VIDC Single-ended Input DC Voltage — AVDD33 – 1200 — AVDD33 – 300 mV VIDF Differential-mode Input Swing Voltage — 200 — mV VICM Common-mode Input Swing Voltage — 170 — 1000 Min (720, 0.85 VIDF) mV Table 3.7. TMDS Output DC Specifications Symbol Parameter Conditions Min Typ Max Units VSWING VH Single-ended Output Swing Voltage Single-ended High-level Output Voltage RLOAD = 50 Ω — 400 AVDD33 – 200 — — 600 AVDD33 + 10 mV mV VL Single-ended Low-level Output Voltage — AVDD33 – 700 — AVDD33 – 400 mV Table 3.8. Single Mode Audio Return Channel DC Specifications Symbol Parameter Vel Vel swing Operating DC Voltage Swing Amplitude Conditions Min Typ Max Units Notes — — 0 400 — — 5 600 V mV — — Table 3.9. CBUS DC Specifications Symbol Parameter Conditions Min Typ Max Units Notes VIH_CBUS VIL_CBUS VOH_CBUS High-level Input Voltage Low-level Input Voltage High-level Output Voltage — — IO = 100 µA 1.0 — 1.5 — — — — 0.6 — V V V — — — VOL_CBUS ZDSC_CBUS Low-level Output Voltage Pull-down Resistance – Discovery IO = 100 µA — — 800 — 1000 0.2 1200 V Ω — — ZON_CBUS Pull-down Resistance – Active Input Leakage Current — High-impedance 90 — 100 — 110 1 kΩ IIL_CBUS — — CCBUS Capacitance Power Off — — 30 A pF — © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 14 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 3.4. AC Specifications Table 3.10. TMDS Input Timing AC Specifications – HDMI Mode Symbol Parameter TINTRA-PAIR_SKEW Input Intrapair Skew TINTER-PAIR_SKEW Input Interpair Skew FRXC Differential Input Clock Frequency TRXC Differential Input Clock Period TIJIT Differential Input Clock Jitter Tolerance Notes: 1. SiI9589 device. 2. SiI9589-3 device. Conditions — Min — Typ — Max 0.4 TBIT Units ps Notes 1 — — — — — 25 — — — 112 + 0.15 TBIT 0.2TPIXEL + 1.78 225 ps ns MHz 2 — — 25 4.44 — — 300 40 MHz ns 2 1 — 300 MHz 3.33 — — — 40 0.3 ns TBIT 2 — 1 Table 3.11. TMDS Input Timing AC Specifications – MHL Mode Symbol Parameter Conditions Min Typ Max Units TSKEW_DF TSKEW_CM Input Differential Intrapair Skew Input Common-mode Intrapair Skew — — — — — — 93 93 ps ps FRXC TRXC TCLOCK_JIT Differential Input Clock Frequency Differential Input Clock Period Common-mode Clock Jitter Tolerance — — — 25 13.33 — — — — 75 40 0.3TBIT + 200 MHz ns ps TDATA_JIT Differential Data Jitter Tolerance — — — 0.4TBIT + 88.88 ps Table 3.12. TMDS Output Timing AC Specifications Symbol TTXDPS Parameter Intrapair Differential Output Skew Conditions — Min — Typ — Max 0.15 Units TBIT Notes — TTXRT TTXFT Data/Clock Rise Time Data/Clock Fall Time 20%–80% 20%–80% 75 75 — — 144 120 ps ps — — FTXC Differential Output Clock Frequency TTXC Differential Output Clock Period — — — 25 25 4.44 — — — 225 300 40 MHz MHz ns 1 2 — TDUTY TOJIT Differential Output Clock Duty Cycle Differential Output Clock Jitter — — 40% — — — 60% 0.25 TTXC TBIT — — Min Typ Max Units Note — — — — 60 60 ns ns — — 0.05 1000 UI* ppm — — Notes: 1. SiI9589 device. 2. SiI9589-3 device. Table 3.13. Single Mode Audio Return Channel AC Specifications Symbol Parameter TASMRT TASMFT Rise Time Fall Time Conditions 10%–90% 10%–90% TASMJIT Jitter Max — — — FASMDEV Clock Frequency Deviation — –1000 — *Note: Proportional to unit time (UI), according to sample rate. Refer to the S/PDIF specification. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 15 SiI9589 Port Processor Data Sheet Table 3.14. S/PDIF Input Port AC Specifications Symbol Parameter FI_SPDIF TI_SPCYC TI_SPDUTY Sample Rate Cycle Time Duty Cycle Conditions Min Typ Max Units Note To ARC — — 32 — 90 — — — 48 1.0 110 kHz UI* %UI* — — — *Note: Proportional to unit time (UI), according to sample rate. Refer to S/PDIF specification. Table 3.15. CBUS AC Specifications Symbol Parameter Conditions TBIT_CBUS Bit Time TBJIT_CBUS Bit-to-Bit Jitter TDUTY_CBUS TR_CBUS TF_CBUS ΔTRF Duty Cycle of 1 Bit Rise Time Fall Time Rise-to-Fall Time Difference Min Typ Max Units 1 MHz clock 0.8 — –1% — 1.2 — +1% s TBIT_CBUS — 0.2 V–1.5 V 0.2 V–1.5 V 40% 5 5 — — — 60% 200 200 TBIT_CBUS ns ns — — — 100 ns 3.5. Miscellaneous Timing Table 3.16. Miscellaneous Timing Symbol Parameter Conditions Min Typ Max Unit Figure Note TRESET RESET# signal LOW time for valid reset — 1 — — ms Figure 3.2 — TSBVCC5RT Rise Time 10%–90% — — 1 ms — — 2 THDDAT I C data hold time 0–400 KHz 0 — — ns — 1 2 Note: This minimum hold time is required by CSCL and CSDA pins as an I C slave. The 300 ns internal delay for CSDA can be enabled by NVRAM configuration 3.6. Reset Timing RESET# TRESET RESET# must be pulled LOW for TRESET before accessing registers. This is done by pulling RESET# LOW from a HIGH state (shown above) for at least TRESET. Figure 3.2. RESET# Minimum Timing © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 16 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 4. Pin Diagram and Pin Descriptions 4.1. Pin Diagram R1X0N R1X0P R1X1N R1X1P R1X2N R1X2P AVDD12 VDD12 R2XCN R2XCP R2X0N R2X0P R2X1N R2X1P R2X2N R2X2P VDD33 R3XCN R0X2P R0X2N R0X1P R0X1N R0X0P R0X0N R0XCP R0XCN TPVDD12 TCVDD12 TXCN TXCP TX0N TX0P TX1N TX1P TX2N TX2P ARC VDD12 100 96 95 86 85 81 99 98 97 94 93 92 91 90 89 88 87 84 83 82 80 79 78 77 RSVDL R1XCP R1XCN VDD33 AVDD12 Figure 4.1 shows the pin assignments of the SiI9589 port processor. Individual pin functions are described in the Pin Descriptions section on the next page. The package is a 14 mm x 14 mm 100-pin TQFP with an ePad, which must be connected to ground. 76 SPDIF_IN INT CSCL CSDA 1 75 2 74 3 73 4 72 5 71 6 70 7 69 8 68 CD_SENSE4 9 67 10 66 11 65 RESET_N TPWR_CI2CA GPIO0 62 CD_SENSE3 CD_SENSE2 CD_SENSE1 CD_SENSE0 RSVD LPSBV 15 61 PWRMUX_OUT 16 60 17 59 18 58 R3XCP R3X0N R3X0P R3X1N R3X1P R3X2N 19 57 20 56 21 55 SBVCC5 R5PWR5V(VGA) DSCL5 (VGA) DSDA5(VGA) R2PWR5V CBUS_HPD2 22 54 23 53 24 52 R3X2P 25 51 12 64 SiI9589 Top View 13 14 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 DSCL2 DSDA2 R4PWR5V CBUS_HPD4 50 AVDD12 VDD33 R4XCN R4XCP R4X0N R4X0P R4X1N R4X1P R4X2N R4X2P VDD12 DSDA0 DSCL0 CBUS_HPD0 R0PWR5V DSDA1 DSCL1 CBUS_HPD1 R1PWR5V DSDA3 DSCL3 CBUS_HPD3 R3PWR5V DSDA4 DSCL4 26 63 Figure 4.1. Pin Diagram (Top View) © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 17 SiI9589 Port Processor Data Sheet 4.2. Pin Descriptions 4.2.1. HDMI and MHL Receiver Port Pins Pin Name R0X0P Pin 92 R0X0N 91 R0X1P 94 R0X1N 93 R0X2P 96 R0X2N 95 Type TMDS Dir Input Description TMDS input Port 0 data pairs. R0XCP 90 TMDS Input TMDS input Port 0 clock pair. R0XCN R1X0P 89 2 TMDS Input TMDS input Port 1 data pairs. R1X0N 1 R1X1P 4 R1X1N 3 R1X2P 6 R1X2N 5 TMDS Input TMDS input Port 1 clock pair. TMDS Input TMDS input Port 2 data pairs. TMDS Input TMDS input Port 2 clock pair. TMDS Input TMDS input Port 3 data pairs. TMDS Input TMDS input Port 3 clock pair. TMDS Input TMDS input Port 4 data pairs. TMDS Input TMDS input Port 4 clock pair. R1XCP 100 R1XCN 99 R2X0P 12 R2X0N 11 R2X1P 14 R2X1N R2X2P 13 16 R2X2N 15 R2XCP 10 R2XCN 9 R3X0P 21 R3X0N 20 R3X1P 23 R3X1N R3X2P 22 25 R3X2N 24 R3XCP 19 R3XCN 18 R4X0P 31 R4X0N 30 R4X1P 33 R4X1N 32 R4X2P 35 R4X2N 34 R4XCP 29 R4XCN 28 Note: For the port that has been configured as a MHL input, the RnX0P and RnX0N pins carry the MHL signal. All eight TMDS lines require 5.1 Ω series resistors to meet the impedance requirements of both the MHL and HDMI Specifications. HDMI-only ports do not require 5.1 Ω series resistors on the TMDS lines. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 18 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 4.2.2. Audio Pins Pin Name Pin Type Dir ARC 78 Analog Output Description SPDIF_IN 75 LVTTL Input Audio Return Channel. This pin is used to transmit an IEC60958-1 audio stream, received on the SPDIF_IN input pin, upstream to a compatible source or repeater device, using single-mode ARC. S/PDIF input from the SoC. 4.2.3. HDMI Transmitter Port Pins Pin Name TX0P Pin 83 TX0N 84 TX1P 81 TX1N 82 TX2P 79 TX2N 80 TXCP 85 TXCN 86 Type TMDS Dir Output Description HDMI Transmitter Output Port Data. TMDS Low-voltage Differential Signal output data pairs. TMDS Output HDMI Transmitter Output Port Clock. TMDS Low-voltage Differential Signal output clock pair. 4.2.4. System Switching Pins Pin Name DSDA0 DSDA1 Pin 37 41 DSDA2 DSDA3 53 45 DSDA4 DSDA5(VGA) 49 57 DSCL0 38 DSCL1 42 DSCL2 54 DSCL3 46 DSCL4 DSCL5(VGA) 50 58 R0PWR5V R1PWR5V 40 44 R2PWR5V 56 R3PWR5V R4PWR5V 48 52 CBUS_HPD0 39 CBUS_HPD1 43 CBUS_HPD2 55 CBUS_HPD3 47 CBUS_HPD4 51 R5PWR5V(VGA) 59 Type LVTTL Schmitt Open-drain 5 V tolerant Dir Input/ Output Description 2 DDC I C Data for respective port. These signals are true open drain, and do not pull to ground when power is not applied to the device. These pins require an external pull-up resistor. LVTTL Schmitt Open-drain 5 V tolerant Input DDC I C Clock for respective port. These signals are true open drain, and do not pull to ground when power is not applied to the device. These pins require an external pull-up resistor. Power Input 5 V Port detection input for respective port. Connect to 5 V signal from HDMI input connector. These pins require a 10 Ω series resistor, a 5.1 kΩ pull-down resistor, and at least a 1 µF capacitor to ground. Schmitt 5 V tolerant Analog pad Input/ Output Power Input 2 Hot Plug Detect Output for the respective port. In MHL mode, these pins serve as the respective CTRL bus. VGA 5 V Detect. This pin provides 5 V power from VGA connector. This pin requires a 10 Ω series resistor and at least a 1 μF capacitor to ground. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 19 SiI9589 Port Processor Data Sheet 4.2.5. Control Pins Pin Name Pin Type Dir CSCL 73 LVTTL 5 V tolerant Schmitt Input Description Local Configuration/Status I C Clock. 2 Chip configuration/status is accessed using this I C port. This pin is true open drain, so it doesn’t pull to ground if power is not applied. CSDA 72 LVTTL 5 V tolerant Schmitt Input/ Output Local Configuration/Status I C Data. 2 Chip configuration/status is accessed using this I C port. This pin is true open drain, so it does not pull to ground if power is not applied. See Figure 2.2 on page 8. CD_SENSE0 64 Input CD_SENSE1 65 CD_SENSE2 66 LVTTL 5 V tolerant Schmitt CD_SENSE3 67 CD_SENSE4 68 MHL cable detection pins. Only one of these five pins should be connected to HDMI/MHL multi input port. The rest of unused pins should be tied to ground. These pins have an internal 300 kΩ pull-down resistor which is required for CD_SENSE by the MHL specification, so an external 300 kΩ pull-down resistor is not required for these pins GPIO0 69 Input/ Output RESET_N 71 LVTTL 5 V tolerant Schmitt LVTTL 5 V tolerant Schmitt 2 2 General Purpose I/O Input External reset. Active LOW. Must be pulled-up to PWRMUX_OUT. Apply external reset only when internal POR does not work properly. Refer to the Programmer’s Reference for more details about the external reset sequence. When main power is not provided to the system, the microcontroller must present a high-impedance of at least 100 kΩ to RESET_N. If this condition is not met, a circuit to block the leakage from PWRMUX_OUT to the microcontroller GPIO may be required 4.2.6. Configuration Pins Pin Name TPWR_CI2CA Pin 70 Type LVTTL 5 V tolerant Schmitt Dir Input/ Output Description 2 I C Slave Address input/Transmit Power Sense Output. During chip reset, either by internal Power-on-Reset (POR) or the 2 RESET_N signal, this pin is used as an input to latch the I C sub-address. The level on this pin is latched when the POR transitions from the asserted state to the deasserted state or on a LOW-to-HIGH transition of the RESET_N signal. After completion of reset, this pin is used as the TPWR output, showing the RnPWR status of the selected port. A register setting can change this pin to show if the active port is receiving a TMDS clock. 2 This pin must be tied to ground for the 0xB0 I C address through a 2 4.7 kΩ resistor. For the 0xB2 I C address, this pin must be pulled up to PWRMUX_OUT through a 4.7 kΩ resistor. INT 74 LVTTL 5 V tolerant Schmitt Input/ Output Interrupt Output. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 20 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 4.2.7. Power and Ground Pins Pin Name Pin Type VDD33 17, 27, 98 Power Description TMDS Core VDD. In order to prevent reverse leakage from source device through TMDS input pins, VDD33 should be isolated from other system power. Must be supplied at 3.3 V. PWRMUX_OUT 61 Output Power Output. This pin requires a 10 µF capacitor to ground. Maximum output current is 30 mA. SBVCC5 60 Power Local Power from TV. Must be set to 5 V. This pin requires a 10 Ω series resistor. AVDD12 7, 26, 97 Power TMDS Receiver Core. Must be supplied at 1.2 V. VDD12 8, 36, 77 Power Digital Core. Must be supplied at 1.2 V. TCVDD12 87 Power TMDS Transmitter Core. Must be supplied at 1.2 V. TPVDD12 88 Power TMDS Transmitter PLL. Must be supplied at 1.2 V. LPSBV 62 Power Low-power Standby Power. Always on. Must be supplied at 3.3 V. This pin requires a 5.1 kΩ series resistor. GND ePad Ground The ePad must be soldered to ground, as this is the only ground connection for the device. 4.2.8. Reserved Pins Pin Name Pin Type RSVDL RSVD 76 63 Reserved Reserved Description Reserved, must be tied to ground. Reserved, do not connect. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 21 SiI9589 Port Processor Data Sheet 5. Feature Information 5.1. Standby and HDMI Port Power Supplies The SiI9589 port processor incorporates a 5 V standby power supply pin (SBVCC5). SBVCC5 can be used to supply power to the EDID portions of the device when all other power supplies are turned off. This arrangement allows the EDID to be readable. Table 5.1 summarizes the power modes available in the processor. Figure 5.1 on the next page shows a block diagram of the standby power supply sources and the always-on power island. Table 5.1. Description of Power Modes Power mode Power-on mode 5 V Standby. ARC supported Standby power mode. ARC mode Standby power mode. 5 V standby HDMI Port only power VGA Port only power Description All power supplies to the SiI9589 chip are on. All functions are available. The standby power supply is 5 V. The always-on power domain is on, supplied from the internal power MUX; ARC is supported. The always-on power domain is on, supplied from the internal power MUX; all other supplies are off. The standby power supply is 5 V. In this mode, EDID is functional, but both video and audio processing is not performed and all outputs are off. Power is off to the device. HDMI +5 V from the HDMI cable is the only power source. For example, if the TV is unplugged from AC wall outlet, the EDID is functional in this mode. Power is off to the device. VGA +5 V from the VGA cable is the only power source. For example, if the TV is unplugged from AC power, the EDID is functional in this mode. SBVCC5 5V RnPWR5V Do not Care VDD33 3.3 V VDD12 1.2 V 5V 5 V on Port 1 Don’t Care 1.2 V 5V Don’t Care Off Off Off 5 V on any input Off Off Off 5V Off Off © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 22 SiI-DS-1097-D SiI9589 Port Processor Data Sheet HDMI/VGA Connectors n = 0 to 5 VDD33 VDD12 AVDD12 TCVDD12/ TPVDD12 VDD12 RnPWR5V SBVCC5 SiI9589 ARC ARC Block Power Multiplexer EDID RAM Video and Audio Processing Blocks Always-on Power Island Figure 5.1. Standby Power Supply Diagram If all power is off to the device (for example, if the TV is unplugged from the AC electrical outlet), the EDID can still be read from the source by using power from the HDMI connector +5 V signal. In this case, the internal power MUX will automatically switch to the HDMI connector power to use it for powering the EDID logic. In this mode, only the EDID block is functional, with all other functions of the device in power-off mode. No damage will occur to the device in this mode. 5.2. Hardware Reset Lattice Semiconductor recommends applying a hardware reset through RESET_N pin only when a POR reset problem is detected by the indicating register (Refer to the SiI9589 Programmer's Reference). The connection for RESET_N should meet the following conditions: 1. The microcontroller GPIO used to connect to RESET_N must have more than 100 kΩ impedance when the microcontroller does not have power. 2. RESET_N must be pulled HIGH at all times, except when it is necessary to be toggled. 3. The GPIO should be high-impedance by default when the microcontroller boots up, and should not toggle RESET_N. 4. There should be no leakage between PWRMUX_OUT and the microcontroller GPIO through RESET_N that might disrupt the main system or the port processor when the system is in standby mode. Ensure that PWRMUX_OUT goes HIGH earlier than the microcontroller GPIO so that the leakage from PWRMUX_OUT through RESET_N does not affect the main system. For the board design to meet the above conditions, a circuit such as the one shown in Figure 5.2 on the next page may be required. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 23 SiI9589 Port Processor Data Sheet PWRMUX_OUT 10 k To Microcontroller GPIO SiI9589 RESET_N Schottky Diode FET Main 3.3 V (Same domain as Microcontroller) Figure 5.2. External Reset Circuit 2 After a hardware reset, the SiI9589 device latches the level on the TPWR_CI2CA pin to set the device I C address, restores all registers to default values, and reloads the EDID data and Auto-boot data from NVRAM. Hardware reset also toggles Hot Plug. 5.3. Built-in Pattern Generator The SiI9589 port processor supports a built-in pattern generator that supports the eight patterns shown in Table 5.2 at 1280 x 720 resolution. Either an internal oscillator with a part-to-part accuracy of ±10% or an external 74.25 MHz clock with higher accuracy can be used as the clock source for the pattern generator. These patterns are invoked through the 2 I C interface. See the SiI9589 Programmer’s Reference for details on how to activate the pattern generator. Table 5.2. Built-in Pattern List Pattern RGB Description Solid Red 255, 0, 0 Solid Green 0, 255, 0 Solid Blue 0, 0, 255 Solid Black 0, 0, 0 Solid White 255, 255, 255 256 Grey Ramp 256 vertical bars, 5 pixels wide. RGB value of first bar: (0, 0, 0) RGB value of last bar: (255, 255, 255) Increment of each bar: One RGB value (1, 1, 1), (2, 2, 2), etc. 8 x 6 black/white squares. No border RGB value of white: (0, 0, 0) RGB value of black: (255, 255, 255) 8 vertical bars. White: 255, 255, 255; Yellow: 255, 255, 0 Cyan: 0, 255, 255; Green: 0, 255, 0 Magenta: 255, 0, 255; Red: 255, 0, 0 Blue: 0, 0, 255; Black: 0, 0, 0 Checkerboard RGB Color Bars Example Picture © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 24 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 5.4. 3D Video Formats The SiI9589 port processor supports the pass-through of 3D video modes described in the HDMI 1.4a Specification. All modes support RGB 4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 color formats and 8-, 10-, and 12-bit data-width per color component. Table 5.3 shows only the maximum possible resolution with a given frame rate; for example, Side-by-Side (Half) mode is defined for 1080p, 60 Hz, which implies that 720p, 60 Hz and 480p, 60 Hz are also supported. Furthermore, a frame rate of 24 Hz also means that a frame rate of 23.98 Hz is supported and a frame rate of 60 Hz also means a frame rate of 59.94 Hz is supported. The input pixel clock changes accordingly. Pass-through of the HDMI Vendor Specific InfoFrame, which carries 3D information to the receiver, is supported by the SiI9589 device. It also supports extraction of the HDMI Vendor-specific InfoFrame, which allows the 3D information 2 contained in the InfoFrame to be passed to the host system over the I C port. Table 5.3. Supported 3D Video Formats 3D Format Extended Definition Frame Packing Side-by-Side — full Line Alternative L+ Depth — — Frame Packing — Side-by-Side full half Resolution Frame Rate (Hz) Input Pixel Clock (MHz) 1080p 50/60 297 (Supported by 300 MHz version only) 1080p 24/30 720p/1080i 1080p 50/60 24/30 720p/1080i 1080p 50/60 50/60 Top-and-Bottom — 1080p 1080p 720p/1080i 50/60 24/30 50/60 Line Alternative — 1080p 720p/1080i 24/30 50/60 Field Alternative — L + depth — 1080i 1080p 720p/1080i 50/60 24/30 50/60 148.5 74.25 148.5 5.5. 3D Markers and VS Insertion The SiI9589 device features logic that can be used to assist the downstream SoC in processing 3D video for display. It can monitor the 3D video stream and insert a VS pulse in the VS signal during the Active space period for demarcating the L and R video frames. It can embed markers that identify the L active video region, the R active video region, and the Active space region directly in the video stream on either the CTL0 or CTL1 signals. Separately, the L active video region marker can also be sent on the GPIO0 pin. The port processor can be enabled to send the 3D markers when 3D video is detected, or the markers can be enabled by software manually. Figure 5.3 on the next page shows the VS insertion mode. The front porch, pulse width, back porch, and polarity of the inserted VS signal can be individually set. Figure 5.4 on the next page illustrates the mode that embeds 3D markers in the CTL0/CTL1 signals. The L, R, and Active space markers can be individually switched on. In addition, each marker can be embedded in CTL0, CTL1, or in both. For example, the L marker can be embedded in CTL0 and the R marker in CTL1. The polarity of the markers is also programmable. However, a delay function is not supported, nor is the pulse width of the markers adjustable; these parameters are fixed to the input timing. 3D markers are supported only for 720p frame-packed, and 1080p frame-packed video modes. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 25 SiI9589 Port Processor Data Sheet Original 3D Stream DE HS VS Vact_video Vact_space Vact_video Modified 3D Stream DE HS VS Vact_video Vfront Vsync Vback Vact_video Active video B C D E F CTL0/1 CTL0/1 CTL0/1 CTL0/1 Case A B C D E F L V A CTL0/1 H CTL0/1 Figure 5.3. VS Insertion in Active Space Active space 3D Marker State L AS R ON OFF OFF ON ON OFF OFF ON OFF OFF ON ON OFF OFF ON ON OFF ON Active video R 3D Frame Packing Video Figure 5.4. 3D Markers on CTL0/1 Signals 5.6. Input Video Resolution Detection and InfoFrame Extraction InfoFrame extraction and input video resolution detection are supported for the main and roving port and are accessible port-by-port. This feature helps microcontroller reduce switching time to predetermine resolution and InfoFrame before switching. 5.7. Repeater Support Repeater support is provided for the active port and supports up to 127 downstream devices. Repeater applications also support InstaPort S. With InstaPort S, authentication for unselected ports is accomplished in the background so when a new port that was pre-authenticated is selected, the content can be shown to the user with minimal time delay. InstaPort S can be supported when the device is used as a repeater. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 26 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 5.8. Audio Return Channel ARC is transmitted in single mode by using the ARCP (Utility) line. When using ARC single-mode transmission, a standard HDMI cable can be used. Utility is a new name for the Reserved pin described in earlier versions of the HDMI Specification (The SiI9589 port processor doesn’t support ARC common-mode.) The way the S/PDIF backchannel is used depends on the application. For example, in a TV application, an S/PDIF audio signal from the TV can be sent to an HDMI source device such as an A/V receiver over the Audio Return Channel. ARC simplifies system setup because the consumer does not need to run an S/PDIF cable from the TV to the AVR. ARC also automates connectivity. When the TV input is switched to an analog source or the TV tuner, the TV can use the CEC protocol to indicate to the AVR that it should switch to playback of the ARC input. Blu-ray Player DTV S/PDIF Out HDMI Out HDMI In HDMI S/PDIF (ARC) Active Speaker with S/PDIF Input HDMI S/PDIF HDMI In S/PDIF Out (ARC) HDMI Out S/PDIF In (ARC) DB9233 CP9589 HDMI ARC Starter Kit CP9334 HDMI ARC Starter Kit HDMI 1.4 Sink HDMI 1.4 Source HDMI 1.4 ARC Figure 5.5. Audio Return Channel Example Application © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 27 SiI9589 Port Processor Data Sheet 5.9. EDID Memory The port processor contains 512 bytes of NVRAM that stores common EDID data used by each of the ports and information used by the Auto-Boot feature. The Auto-Boot feature initializes some of the registers used to enable the EDID for the respective port, as well as asserts Hot Plug Detect (HPD) after the EDID has loaded properly into the SRAM. For example, by changing the data in the NVRAM Auto-boot portion, EDID load and HPD state can be set HIGH in 4 of the HDMI ports while disabling this feature in the fifth port. See the associated Programmer’s Reference for more detail about the format of the NVRAM Auto-boot feature. Each port has a 256-byte block of SRAM for EDID data, which allows all ports to be read simultaneously from five different sources connected to the SiI9589 device. In addition, a 128-byte block of NVRAM is reserved for the VGA EDID. Figure 5.6 shows how the NVRAM is initialized using the local 2 I C slave and the shadow SRAM during manufacture, and how data is loaded into the SRAM blocks from the NVRAM during normal operation. I2C Local I2C SLAVE R/W SRAM0/ Shadow SRAM 256 byte EDID R/W 64 Byte Booting NVRAM READ NVRAM 256 bytes HDMI EDID 128 bytes VGA EDID 64 bytes Booting SRAM1 R/W EDID/ NVRAM CONTROL REGISTER R/W 256 byte EDID SRAM2 256 byte EDID R/W SRAM3 R/W 256 byte EDID SRAM4 R/W 256 byte EDID SRAM5 R/W 256 byte EDID Figure 5.6. EDID Block Diagram © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 28 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 5.10. Local I2C Port 2 The local I C slave port on the SiI9589 port processor (pins CSCL and CSDA) is capable of running up to 400 kHz. This port is used to configure the port processor by reading from and writing to necessary registers. 2 2 The local I C port consists of ten separate I C slave addresses. Therefore, the port processor appears as ten separate 2 devices on the I C local bus. The address for accessing the system control registers is fixed, and can only be set to one 2 of two values by using the CI2CA pin. The remaining nine addresses have an I C register-programmable address mapped into the system control register space so that they can be changed to any free addresses in the system. Refer to the Programmer’s Reference for complete information. 2 Table 5.4. I C Register Address Groups 2 I C Slave Address 0x74 Through DDC Register Programmable No Blocks HDCP 0xA0 0x64 DDC 2 Local I C No Yes EDID Rx TMDS – Rx0, Rx1 0x50 0x52 0x54 Local I C 2 Local I C 2 Local I C 2 Yes Yes Yes Preauthentication, page 0 Preauthentication, page 1 Preauthentication, page 2 0x66 0x68 Local I C 2 Local I C 2 Yes Yes Rx TMDS – Rx2, Rx3 Rx TMDS – Rx4 0x90 0xB0 / 0xB2 0xE0 Local I C 2 Local I C 2 Local I C 2 Yes No Yes Tx TMDS /ARC System Control EDID/NVRAM/MHL 0xE6 Local I C 2 Yes CBUS © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 29 SiI9589 Port Processor Data Sheet 6. Design Recommendations 6.1. Audio Return Channel Design Figure 6.1 shows a sample design circuit for using the Audio Return Channel feature. Any one of the five input ports can be wired for ARC use; connection to Port 1 for ARC is shown in the figure. 5V SiI9589 Port Processor 1 k HDMI Port 1 Connector +5V An external DC bias network is required on ARC signal 18 10 4 k R1PWR5V 5.1k 1 F 1 H HP_DET UTILITY CKCK+ D0D0+ D1D1+ D2D2+ CBUS_HPD1* 19 14 1 F ARC R1XCN 12 10 R1XCP 9 R1X0N 7 R1X0P R1X1N 6 R1X1P 4 R1X2N 3 R1X2P 1 S/PDIF Input (required for ARC) SPDIF_IN Figure 6.1. Connection of ARC to HDMI Port © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 30 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 6.2. MHL Power and Cable Detect Design Figure 6.2 shows a sample design circuit for MHL Power and Cable Detect. All eight TMDS connections require 5.1 Ω series resistors for ports that are wired for both MHL and HDMI. Any one of the input ports can be wired for MHL; connection to Port 4 for combined HDMI and MHL is shown in the figure. Power Switch IN SiI9589 Port Processor Power Switch should provide reverse current blocking when off +5V(VBUS) R4PWR5V 10 1 F 5.1 k OUT ENABLE HDMI/MHL Port 4 CKCK+ D0D0+ D1D1+ D2D2+ 12 10 9 7 6 4 3 1 R4XCN R4XCP R4X0N R4X0P R4X1N R4X1P R4X2N R4X2P 5.1 +5V (Always on) RPWR4/VBUS4 47 k 47 k 19 HP_DET 16 DDC_DATA 15 DDC_CLK BAV74 CBUS_HPD4 DSDA4 DSCL4 CD_SENSE0 +5V D2_Shield 18 CD_SENSE1 RPWR4/VBUS4 CD_SENSE2 CD_SENSE3 2 CD_SENSE4 Varistor For optional ESD protection 0.047 F Not all connector pins shown Series resistors required on TMDS lines of port wired for both MHL and HDMI Tie CD_SENSE corresponding to the enabled MHL port line to MHL Connector pin 2. Tie the remaining CD_SENSE lines to ground. In this case, Port 4 is used for MHL. Figure 6.2. Connection of MHL Power and Cable Detect 6.3. Power Supply Decoupling Designers should include decoupling and bypass capacitors at each power signal in the layout. These are shown schematically in Figure 6.3. Connections in one group (such as VDD33) can share C2, C3, and the ferrite, with each pin having a separate C1 placed as close to the pin as possible. Figure 6.4 on the next page is representative of the various types of power connections on the port processor. +3.3 V L1 VDD Pin C1 C2 C3 GND Figure 6.3. Decoupling and Bypass Schematic © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 31 SiI9589 Port Processor Data Sheet VDD C1 C2 L1 VDD Ferrite C3 Via to GND Figure 6.4. Decoupling and Bypass Capacitor Placement 6.4. Power Supply Sequencing All power supplies in the SiI9589 port processor are independent, but identical supplies must come on at the same time; for example, power to all VDD33 pins must come on together. During power up, the SBVCC5 rise time (from 10% to 90% of 5 V) should be less than 1 ms. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 32 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 7. Package Information 7.1. ePad Requirements The SiI9589 port processor chip is packaged in a 100-pin, 14 mm x 14mm TQFP package with an exposed pad (ePad) that is used for the electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are 5 mm x 5 mm ±0.15 mm. Soldering the ePad to the ground plane of the PCB is required to meet package power dissipation requirements at full speed operation, and to correctly connect the chip circuitry to electrical ground. A clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of the lead pads to avoid the possibility of electrical shorts. The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The solder mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter. Package stand-off when mounting the device also needs to be considered. For a nominal stand-off of approximately 0.1 mm the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal land. Figure 7.1 on the next page shows the package dimensions of the SiI9589 port processor. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 33 SiI9589 Port Processor Data Sheet 7.2. Package Dimensions These drawings are not to scale. D D1 5.00 ± 0.20 100 76 R1 75 R2 GAGE PLANE .25 5.00 ± 0.20 PIN 1 IDENTIFIER E1 E S L L1 Detail A 51 25 26 e b 50 See Detail A A A2 A1 ccc C C Figure 7.1. Package Diagram JEDEC Package Code MS-026 Item A Description Thickness Min — Typ — Max 1.20 Item C A1 A2 Stand-off Body thickness 0.05 0.95 — 1.00 0.15 1.05 D E D1 Footprint Footprint Body size E1 b Body size Lead width 0.17 Description Lead thickness Min 0.09 Typ — Max 0.20 e L Lead pitch Lead foot length 0.45 0.50 BSC 0.60 0.75 16.00 BSC 16.00 BSC 14.00 BSC L1 R1 R2 Total lead length Lead radius, inside Lead radius, outside 0.08 0.08 1.00 REF — — — 0.20 14.00 BSC 0.22 S ccc Lead horizontal run Lead coplanarity 0.27 0.20 — 0.08 — © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 34 SiI-DS-1097-D SiI9589 Port Processor Data Sheet 7.3. Marking Specification Figure 7.2 shows the markings of the SiI9589 port processor package. This drawing is not to scale. Silicon Image Logo InstaPort Logo SiI9589CTUC-3 LLLLLL.LL-L YYWW XXXXXXX Pin 1 location Silicon Image Part Number Lot # (= Job#) Date code Trace code SiIxxxxrpppp-sXXXX Product Designation Special Designation Revision Package Type Speed Figure 7.2. Marking Diagram 7.4. Ordering Information Production Part Numbers: Device Part Number Port processor with ARC and InstaPort S SiI9589CTUC Port processor with ARC and InstaPort S, 300 MHz SiI9589CTUC-3 © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 35 SiI9589 Port Processor Data Sheet References Standards Documents This is a list of standards abbreviations appearing in this document, and references to their respective specifications documents. Abbreviation Standards publication, organization, and date HDMI HCTS HDCP High Definition Multimedia Interface, Revision 1.4, Licensing, LLC, June 2009 HDMI Compliance Test Specification, Revision 1.4, Licensing, LLC, November 2009 High-bandwidth Digital Content Protection, Revision 1.3, Digital Content Protection, LLC, December 2006 DVI E-EDID Digital Visual Interface, Revision 1.0, Digital Display Working Group, April 1999 Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA, Feb. 2000 E-DID IG CEA-861-E VESA EDID Implementation Guide, VESA, June 2001 A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA, March 2008 EDDC MHL Enhanced Display Data Channel Standard, Version 1.1, VESA, September 1999 MHL (Mobile High-definition Link) Specification, Version 1.0, MHL, LLC, June 2010 Standards Groups For information on the specifications that apply to this document, contact the responsible standards groups appearing on this list. Standards Group ANSI/EIA/CEA Web URL http://global.ihs.com VESA HDCP DVI http://www.vesa.org http://www.digital-cp.com http://www.ddwg.org MHL http://www.mhlconsortium.org Lattice Semiconductor Documents This is a list of the related documents that are available from your Lattice Semiconductor sales representative. The Programmer Reference requires an NDA with Lattice Semiconductor. Document SiI-PR-1058 Title SiI9587 and SiI9589 Port Processor Programmer’s Reference Technical Support For assistance, submit a technical support case at www.latticesemi.com/techsupport. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 36 SiI-DS-1097-D SiI9589 Port Processor Data Sheet Revision History Revision D, March 2016 Updated to latest template. Revision D, September 2013 Updated Table 3.3. Digital I/O Specifications and Table 3.16. Miscellaneous Timing. Revision C, June 2012 Updated Figure 6.2. Connection of MHL Power and Cable Detect. Revision B, January 2012 Updated Table 3.4. Power Requirements. Revision A, October 2011 First production release. © 2010-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. SiI-DS-1097-D 37 th th 7 Floor, 111 SW 5 Avenue Portland, OR 97204, USA T 503.268.8000 www.latticesemi.com