SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output

SiI9233 HDMI Receiver with Repeater, Multichannel Audio, and Deep Color Output
Data Sheet
SiI-DS-1032-A
March 2016
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Contents
1.
General Description ......................................................................................................................................................6
1.1.
Features ...............................................................................................................................................................6
1.2.
Important Information ........................................................................................................................................6
1.3.
Overview .............................................................................................................................................................7
1.4.
Additional Features .............................................................................................................................................7
2. System Applications ......................................................................................................................................................9
2.1.
Comparing SiI9233 with SiI9127, SiI9125 and SiI9135 ........................................................................................9
3. Functional Description ................................................................................................................................................10
3.1.
TMDS Digital Cores ............................................................................................................................................11
3.1.1. Active Port Detection and Selection .............................................................................................................11
3.2.
HDCP Decryption Engine/XOR Mask .................................................................................................................11
3.2.1. HDCP Embedded Keys ...................................................................................................................................11
3.3.
Data Input and Conversion ................................................................................................................................12
3.3.1. Mode Control Logic .......................................................................................................................................12
3.3.2. Video Data Conversion and Video Output ....................................................................................................12
3.3.3. Deep Color Support.......................................................................................................................................13
3.3.4. x.v.Color Support ..........................................................................................................................................13
3.3.5. Automatic Video Configuration ....................................................................................................................15
3.4.
Audio Data Capture Logic ..................................................................................................................................16
3.4.1. S/PDIF ............................................................................................................................................................16
2
3.4.2. I S ..................................................................................................................................................................16
3.4.3. One-Bit Audio Input (DSD/SACD) ..................................................................................................................16
3.4.4. High-Bitrate Audio on HDMI .........................................................................................................................16
3.4.5. Auto Audio Configuration .............................................................................................................................18
3.4.6. Soft Mute ......................................................................................................................................................18
3.5.
Control and Configuration .................................................................................................................................19
3.5.1. Register/Configuration Logic ........................................................................................................................19
2
3.5.2. I C Serial Ports ...............................................................................................................................................19
3.5.3. EDID FLASH and RAM Block ..........................................................................................................................19
3.5.4. CEC Interface .................................................................................................................................................19
3.5.5. Standby and HDMI Port Power Supplies .......................................................................................................20
4. Electrical Specifications ..............................................................................................................................................21
4.1.
Absolute Maximum Conditions .........................................................................................................................21
4.2.
Normal Operating Conditions ...........................................................................................................................22
4.3.
DC Specifications ...............................................................................................................................................23
4.3.1. Digital I/O Specifications ...............................................................................................................................23
4.3.2. DC Power Supply Pin Specifications ..............................................................................................................24
4.4.
AC Specifications ...............................................................................................................................................25
4.4.1. TMDS Input Timings ......................................................................................................................................25
4.4.2. Video Output Timings ...................................................................................................................................26
4.4.3. Audio Output Timings ...................................................................................................................................26
4.4.4. Miscellaneous Timings ..................................................................................................................................28
4.4.5. Interrupt Timings ..........................................................................................................................................28
4.5.
Timing Diagrams ................................................................................................................................................29
4.5.1. TMDS Input Timing Diagrams .......................................................................................................................29
4.5.2. Power Supply Control Timings ......................................................................................................................30
4.5.3. Reset Timings ................................................................................................................................................30
4.5.4. Digital Video Output Timing Diagrams ..........................................................................................................31
4.5.5. Digital Audio Output Timings ........................................................................................................................32
4.6.
Calculating Setup and Hold Times for Video Bus ..............................................................................................33
4.6.1. 24/30/36-Bit Mode .......................................................................................................................................33
4.6.2. 12/15/18-Bit Dual-Edge Mode ......................................................................................................................34
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
2
4.7.
Calculating Setup and Hold Times for I S Audio Bus ......................................................................................... 35
5. Pin Diagram and Descriptions ..................................................................................................................................... 36
5.1.
Pin Descriptions................................................................................................................................................. 37
5.1.1. Digital Video Output Pins .............................................................................................................................. 37
5.1.2. Digital Audio Output Pins.............................................................................................................................. 38
5.1.3. Configuration/Programming Pins ................................................................................................................. 39
5.1.4. HDMI Control Signal Pins .............................................................................................................................. 40
5.1.5. Differential Signal Data Pins.......................................................................................................................... 41
5.1.6. Power and Ground Pins ................................................................................................................................ 42
6. Video Path .................................................................................................................................................................. 43
6.1.
HDMI Input Modes to SiI9233 Receiver Output Modes.................................................................................... 44
6.1.1. HDMI RGB 4:4:4 Input Processing................................................................................................................. 45
6.1.2. HDMI YCbCr 4:4:4 Input Processing .............................................................................................................. 46
6.1.3. HDMI YCbCr 4:2:2 Input Processing .............................................................................................................. 47
6.2.
SiI9233 Receiver Output Mode Configuration .................................................................................................. 48
6.2.1. RGB and YCbCr 4:4:4 Formats with Separate Syncs ..................................................................................... 49
6.2.2. YC 4:2:2 Formats with Separate Syncs .......................................................................................................... 51
6.2.3. YC 4:2:2 Formats with Embedded Syncs ....................................................................................................... 54
6.2.4. YC Mux (4:2:2) Formats with Separate Syncs ............................................................................................... 57
6.2.5. YC Mux 4:2:2 Formats with Embedded Syncs ............................................................................................... 59
6.2.6. 12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs ................................................................ 61
2
7. I C Interfaces............................................................................................................................................................... 63
2
7.1.
HDCP E-DDC / I C Interface ............................................................................................................................... 63
2
7.2.
Local I C Interface ............................................................................................................................................. 64
2
7.3.
Video Requirement for I C Access ..................................................................................................................... 64
2
7.4.
I C Registers ...................................................................................................................................................... 64
8. Hot Plug Detect CTS Requirement .............................................................................................................................. 65
9. Design Recommendations .......................................................................................................................................... 66
9.1.
Power Control ................................................................................................................................................... 66
9.1.1. Power Pin Current Demands......................................................................................................................... 66
9.2.
HDMI Receiver DDC Bus Protection .................................................................................................................. 67
9.3.
Decoupling Capacitors ...................................................................................................................................... 67
9.4.
ESD Protection .................................................................................................................................................. 67
9.5.
HDMI Receiver Layout ....................................................................................................................................... 68
9.6.
EMI Considerations ........................................................................................................................................... 69
9.7.
XTALIN Clock Required in All Designs ................................................................................................................ 70
9.7.1. Description .................................................................................................................................................... 70
9.7.2. Recommendation ......................................................................................................................................... 70
9.8.
Typical Circuit .................................................................................................................................................... 70
9.8.1. Power Supply Decoupling ............................................................................................................................. 70
9.8.2. HDMI Port Connections ................................................................................................................................ 71
9.8.3. Digital Video Output Connections ................................................................................................................ 72
9.8.4. Digital Audio Output Connections ................................................................................................................ 73
9.8.5. Control Signal Connections ........................................................................................................................... 73
9.9.
Layout................................................................................................................................................................ 74
9.9.1. TMDS Input Port Connections ...................................................................................................................... 74
10.
Packaging ................................................................................................................................................................ 75
10.1. ePad Enhancement ........................................................................................................................................... 75
10.2. PCB Layout Guidelines ...................................................................................................................................... 75
10.3. 144-pin TQFP Package Dimensions ................................................................................................................... 76
10.4. Marking Specification ........................................................................................................................................ 77
10.5. Ordering Information ........................................................................................................................................ 77
Revision History .................................................................................................................................................................. 78
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
3
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Figures
Figure 1.1. A/V Receiver Block Diagram ...............................................................................................................................6
Figure 3.1. Functional Block Diagram .................................................................................................................................10
Figure 3.2. Default Video Processing Path ..........................................................................................................................14
Figure 3.3: High Speed Data Transmission..........................................................................................................................16
Figure 3.4: High-Bitrate Stream Before and After Reassembly and Splitting .....................................................................17
Figure 3.5. High-Bitrate Stream After Splitting ...................................................................................................................17
2
Figure 3.6. I C Register Domains ........................................................................................................................................19
Figure 4.1. Audio Crystal Schematic for the SiI9233 Receiver ............................................................................................27
Figure 4.2. SCDT and CKDT Timing from DE or RXC Inactive/Active ...................................................................................29
Figure 4.3. TMDS Channel-to-Channel Skew Timing ..........................................................................................................29
Figure 4.4. Power Supply Sequencing .................................................................................................................................30
Figure 4.5. RESET# Minimum Timings.................................................................................................................................30
Figure 4.6. Video Digital Output Transition Times ..............................................................................................................31
Figure 4.7. Receiver Clock-to-Output Delay and Duty Cycle Limits ....................................................................................31
2
Figure 4.8. I S Output Timings ............................................................................................................................................32
Figure 4.9. S/PDIF Output Timings ......................................................................................................................................32
Figure 4.10. MCLK Timings ..................................................................................................................................................32
Figure 4.11. 24/30/36-Bit Mode Receiver Output Setup and Hold Times ..........................................................................33
Figure 4.12. 12/15/18-Bit Mode Receiver Output Setup and Hold Times ..........................................................................34
Figure 5.1. Pin Diagram .......................................................................................................................................................36
Figure 5.2. Test Point VCCTP for VCC Noise Tolerance Spec ..............................................................................................42
Figure 6.1. Receiver Video and Audio Data Processing Paths ............................................................................................43
Figure 6.2. HDMI RGB 4:4:4 Input to Video Output Transformations ................................................................................45
Figure 6.3. HDMI YCbCr 4:4:4 Input to Video Output Transformations .............................................................................46
Figure 6.4. HDMI YCbCr 4:2:2 Input to Video Output Transformations .............................................................................47
Figure 6.5. 4:4:4 Timing Diagram ........................................................................................................................................50
Figure 6.6. YC Timing Diagram ............................................................................................................................................53
Figure 6.7. YC 4:2:2 Embedded Sync Timing Diagram ........................................................................................................56
Figure 6.8. YC Mux 4:2:2 Timing Diagram ...........................................................................................................................58
Figure 6.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram .................................................................................60
Figure 6.10. 18-Bit Output 4:4:4 Timing Diagram ...............................................................................................................61
Figure 6.11. 15-Bit Output 4:4:4 Timing Diagram ...............................................................................................................62
Figure 6.12. 12-Bit Output 4:4:4 Timing Diagram ...............................................................................................................62
2
Figure 7.1. I C Byte Read .....................................................................................................................................................63
2
Figure 7.2. I C Byte Write ....................................................................................................................................................63
Figure 7.3. Short Read Sequence ........................................................................................................................................63
Figure 8.1: HPD CTS Compliance Requirement Schematic .................................................................................................65
Figure 9.1. Decoupling and Bypass Capacitor Placement ...................................................................................................67
Figure 9.2. Cut-out Reference Plane Dimensions ...............................................................................................................68
Figure 9.3. HDMI to Receiver Routing – Top View ..............................................................................................................69
Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic ....................................................................................70
Figure 9.5. HDMI Port Connections Schematic ...................................................................................................................71
Figure 9.6. Digital Display Schematic ..................................................................................................................................72
Figure 9.7. Audio Output Schematic ...................................................................................................................................73
Figure 9.8. Controller Connections Schematic ....................................................................................................................73
Figure 9.9. TMDS Input Signal Assignments .......................................................................................................................74
Figure 10.1. ePad Diagram ..................................................................................................................................................75
Figure 10.2. 144-Pin TQFP Package Diagram ......................................................................................................................76
Figure 10.3. Marking Diagram ............................................................................................................................................77
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Tables
Table 2.1. Summary of Features ........................................................................................................................................... 9
Table 3.1. Digital Video Output Formats ............................................................................................................................ 12
Table 3.2. Default Video Processing ................................................................................................................................... 14
Table 3.3. AVI InfoFrame Video Path Details ...................................................................................................................... 15
Table 3.4. Digital Output Formats Configurable through Auto Output Format Register ................................................... 15
Table 3.5. Supported MCLK Frequencies ............................................................................................................................ 16
Table 3.6. Maximum Audio Sampling Frequency for All Video Format Timings ................................................................ 18
Table 4.1. Calculation of 24/30/36-Bit Output Setup and Hold Times ............................................................................... 33
Table 4.2. Calculation of 12/15/18-Bit Output Setup and Hold Times ............................................................................... 34
2
Table 4.3. I S Setup and Hold Time Calculations ................................................................................................................ 35
Table 6.1. Translating HDMI Formats to Output Formats .................................................................................................. 44
Table 6.2. Output Video Formats ....................................................................................................................................... 48
Table 6.3. 4:4:4 Mappings .................................................................................................................................................. 49
Table 6.4. YC 4:2:2 Separate Sync Pin Mappings ................................................................................................................ 51
Table 6.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping ............................................................................... 52
Table 6.6. YC 4:2:2 Embedded Sync Pin Mappings ............................................................................................................. 54
Table 6.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping ............................................................................. 55
Table 6.8. YC Mux 4:2:2 Mappings ..................................................................................................................................... 57
Table 6.9. YC Mux 4:2:2 Embedded Sync Pin Mapping ...................................................................................................... 59
Table 6.10. 12/15/18-Bit Output 4:4:4 Mappings .............................................................................................................. 61
2
Table 7.1. Control of the Default I C Addresses with the CI2CA Pin ................................................................................... 64
Table 9.1. Maximum Power Domain Currents versus Video Mode.................................................................................... 66
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
5
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
1.1.
1. General Description
The SiI9233 from Lattice Semiconductor is a 4-port
receiver that is fully compliant with the HDMI 1.3
standard. AV receivers that output to DTVs displaying
10/12-bit color depth can now provide the highest
quality protected digital audio/video over a single
cable. The SiI9233 receiver can receive deep color
video up to 12-bit, 1080p at 60 Hz. Efficient color space
conversion receives RGB or YCbCr video data and
outputs either standard-definition or high-definition
RGB or YCbCr formats.
Features

4-Port HDMI 1.3, HDCP 1.3, and DVI 1.0 compliant
Receiver

Integrated TMDS® core running at 25–225 MHz

36-bit digital video interface supports video
processors:
The Sil9233 receiver adds support for the extended
gamut YCC or x.v.Color color space, which supports
approximately 1.8 times the number of colors as the
RGB color space. The x.v.Color color space also makes
full use of the range on the standard 8-bit resolution
per pixel.

x.v.Color to extended RGB

36-bit RGB / YCbCr 4:4:4

16/20/24-bit YCbCr 4:2:2

8/10/12-bit YCbCr 4:2:2 (ITU BT.656)

Color Space Conversion for both RGB-to-YCbCr
and YCbCr-to-RGB (both 601 and 709)

True 12-bit accurate output data using an
internal14-bit wide processing path

Programmable drive strength from 2 mA to
14 mA.

Programmable output delay control to
prevent simultaneous switching
1.2.

Important Information
See the Hot Plug Detect CTS Requirement sections
for important information regarding HDMI
compliance testing
HDMI Port3
Connector
RPWR3 (5V)
TMDS3
DDC3
HPD3
HDMI Port2
Connector
Digital Video
RPWR2(5V)
Video
Processor
TMDS2
SiI9134
Transmitter
DDC2
CEC
HPD2
SiI9233
Receiver
I2 S/
DSD
RPWR1(5V)
HDMI Port1
Connector
SPDIF
MCLK
TMDS1
DDC1
HPD1
2
IC
CEC
HDMI Port0
Connector
RPWR0 (5V)
TMDS0
DDC0
HPD0
Microcontroller
I2S
Audio DSP
Other Audio Sources
Audio
DAC
Speakers
Figure 1.1. A/V Receiver Block Diagram
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
1.3.
Overview
The SiI9233 HDMI Receiver can send and receive up to two channels of uncompressed digital audio at 192 kHz.
2
Compressed streams are also supported through either the S/PDIF port or over I S for DTS-HD and Dolby TrueHD. An
2
industry-standard I S port allows direct connection to low-cost audio DACs at up to 192 kHz. An S/PDIF port supports
up to 192 kHz audio. Audio down-sampling allows the SiI9233 receiver to share the audio bus with a high-sample-rate
audio DAC while down-sampling audio for an attached display that supports only lower rates.
The SiI9233 receiver provides additional integrated features to help lower system cost and provide enhanced features
to the end consumer. The SiI9233 receiver integrates the Extended Display Identification Data (EDID) block, which is
stored in embedded Non-Volatile Memory (NVM). This memory can be programmed at the time of manufacture using
2
the local I C bus, similar to how existing EEPROMs are programmed today. On board RAM can also be loaded with EDID
data from the system microcontroller during power up or initialization if the NVM is not used. The EDID is reflected on
each of the four HDMI ports through the DDC bus. Flexibility is built in to allow mixing different EDID formats in an
application. This feature can eliminate up to four EDID ROMs while also saving board space.
The SiI9233 receiver provides a complete, simple solution to enabling Consumer Electronics Control (CEC) in a DTV. CEC
is a single-wire bus that transmits remote control commands throughout a home network. The SiI9233 receiver
integrates both an HDMI-compliant I/O and Lattice Semiconductor’s CEC API. The CEC I/O meets all HDMI compliance
tests and eliminates the need for additional external components, again saving board space and reducing DTV BOM
cost. The CEC API manages reception and transmission of all CEC signals according to the CEC protocol and makes the
information available to the system microcontroller. This significantly lowers the system-level control by the system
microcontroller, simplifying firmware overhead.
The SiI9233 receiver also incorporates a very robust standby power scheme. The standby power plane of the device is
isolated from the rest of the device, and can be powered locally from an external +5 V standby power supply input to
the device, or from the +5 V signal from one of the four HDMI connectors. This feature results in extremely low power
consumption of the device when in standby mode, while both CEC and EDID are fully operational. Additionally, if using
the NVM feature to store the EDID, only the +5 V power from the source device is needed to read the EDID, and the
display can be completely unplugged from the AC power outlet.
The SiI9233 receiver also comes pre-programmed with HDCP keys. This set of keys simplifies the manufacturing process
and lowers costs, while providing the highest level of HDCP key security.
Lattice Semiconductor’s HDMI Receivers use the latest generation of TMDS core technology, supporting dynamic cable
equalization that automatically detects the appropriate equalization required for the incoming signal, offering the best
support for long cable connections. These TMDS cores pass all HDMI compliance tests.
1.4.






Additional Features
Digital audio interface supports high-end audio systems:
 DTS-HD and DolbyTrueHD high bit rate audio support
2
 I S output with 4 data signals for multi-channel formats
 S/PDIF output supports PCM, Dolby Digital, DTS digital audio transmission (32-192 kHz Fs sample rate)
 IEC60958 or IEC61937 compatible
2
 Flexible, programmable I S channel mapping
 2:1 and 4:1 down-sampling to handle 96-kHz and 192-kHz audio streams.
Intelligent audio mute capabilities avoids pops and noise with automatic soft mute and unmute.
Integrated HDCP decryption engine for receiving protected audio and video content:
 Pre-programmed HDCP keys provide highest level of key security and simplify manufacturing
 Full support for HDCP repeaters (up to 16 attached downstream devices)
 Built in HDCP self-test (BIST).
HDCP Repeater support.
Built-in Consumer Electronics Control (CEC)
 HDMI-compliant CEC I/O simplifies design and lowers cost
 Integrated CEC Programming Interface (CPI) lowers software overhead
 Automatic Feature Abort response for unsupported commands
 Automatic message retry on transmit.
Integrated EDID in non-volatile memory with optional registers to override EDID for each port.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
7
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet


Flexible power management
 Separate Standby power pin
 Standby power can be from HDMI +5V signal or locally
 Extremely low standby power.
20 mm x 20 mm 144-pin TQFP package with ePad.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
2. System Applications
The SiI9233 HDMI Receiver is designed for digital televisions that require support for HDMI v1.3 Deep Color. The
SiI9233 receiver supports the HDMI v1.3 specification and allows receipt of 10/12-bit color depth up to 1080p
resolutions. A single SiI9233 receiver provides four HDMI input ports. The video output interfaces to a video processor
and the audio output can interface directly to an audio DAC or an audio DSP for further processing as shown in Figure
1.1.
2.1.
Comparing SiI9233 with SiI9127, SiI9125 and SiI9135
Table 2.1 summarizes the functional differences among the SiI9127, SiI9125, the SiI9135, and the SiI9233.
Table 2.1. Summary of Features
Feature
SiI9125
SiI9127
SiI9135
SiI9223
SiI9233
HDMI Input Connections
TMDS Input Ports
2
2
2
4
4
Color Depth
8/10/12-bit
8/10/12-bit
8/10/12-bit
8/10/12-bit
8/10/12-bit
DDC Input Ports
2
2
2
4
4
Maximum TMDS Input Clock
Video Output
225 MHz
225 MHz
225 MHz
225 MHz
225 MHz
Digital Video Output Ports
1
1
1
1
1
Maximum Output Pixel Clock
Maximum Output Bus Width
Audio Formats
165 MHz.
36
165 MHz.
36
165 MHz.
36
165 MHz.
36
165 MHz.
36
S/PDIF Output Ports
I2S Output
1
2 channel
1
2 channel
1
8 channel
1
2 channel
1
8 channel
DSD Output
High Bit Rate Audio Support
Compressed DTS-HD and Dolby
True-HD
2 channel
No
NA
No
6 channel
Yes
NA
No
8 channel
Yes
Maximum Audio Sample Rate (Fs)
192 kHz
192 kHz
192 kHz
192 kHz
192 kHz
RGB to/from
YCbCr
RGB to/from
YCbCr
x.v.Color to RGB
RGB to/from
YCbCr
RGB to/from
YCbCr
x.v.Color to RGB
RGB to/from
YCbCr
x.v.Color to RGB
Video Processing
Color Space Converter
Pixel Clock Divider
Digital Video Bus Mapping
Other Features
÷ 4, ÷ 2
swap Cb, Cr pins
÷ 4, ÷ 2
swap Cb, Cr pins
÷ 4, ÷ 2
swap Cb, Cr pins
Local fixed I2C Device Address
0x60/0x68 or
0x62/0x6A
0x60/0x68 or
0x62/0x6A
Programmable I2C Device
Address
NA
0x60/0x68 or
0x62/0x6A
0x64, 0xC0,
0xE0, 0xE6,
0x90
CEC
No
Yes
EDID
HDCP Repeater Support
Interlaced Format Detection Pin
No
No
Yes
144-pin TQFP
ePad
NVRAM
No
Yes
128-pin TQFP
ePad
Package
÷ 4, ÷ 2
swap Cb, Cr pins
÷ 4, ÷ 2
swap Cb, Cr pins
0x60/0x68 or
0x62/0x6A
0x64, 0xC0, 0xE0,
0xE6, 0x90
0x60/0x68 or
0x62/0x6A
0x64, 0xC0,
0xE0, 0xE6,
0x90
No
Yes
Yes
No
Yes
Yes
144-pin TQFP
ePad
NVRAM
No
Yes
144-pin TQFP
ePad
NVRAM
Yes
Yes
144-pin TQFP
ePad
NA
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
9
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3. Functional Description
The SiI9233 receiver provides a complete solution for receiving HDMI-compliant digital audio and video. Specialized
audio and video processing is available within the HDMI Receiver to add HDMI capability to consumer electronics such
as DTVs. Figure 3.1 shows the functional blocks of the chip.
CEC_A
DSDA0
DSDA1
DSDA2
DSDA3
DSCL0
DSCL1
DSCL2
DSCL3
CSDA
CSCL
CI2CA
CEC
Serial
Host
Interface
(DDC)
R0XC+
R0XCR0X0+
R0X0R0X1+
R0X1R0X2+
R0X2R0XC+
R0XCR0X0+
R0X0R0X1+
R0X1R0X2+
R0X2R0XC+
R0XCR0X0+
R0X0R0X1+
R0X1R0X2+
R0X2-
HDCP
Registers
SRAM
Serial
Host
Interface
(local)
CEC_D
RPI
Registers
and State
Machine
HDCP
Engine
EDID
NVRAM
Embedded
HDCP Keys
HPD0
HPD1
HPD2
HPD3
Hot Plug
Controller
Configuration
and Status
Registers
INT
Video Processing
Video
HDCP
Unmask
Color
Space
Converter
Deep
Color
Video
Output
Format
Up/Down
Sampling
HDMI
Receiver
Mux
A/V Split
HDMI
Decode
Auto Video Configuration
Audio Processing
Audio Clock
Regeneration
R0XC+
R0XCR0X0+
R0X0R0X1+
R0X1R0X2+
R0X2-
ODCK
Q[35:0]
DE
HSYNC
VSYNC
EVNODD
SCDT
Logic
Audio
HDCP
Unmask
APLL
Auto
Audio/
Exception
Audio Output
S/PDIF
Output
I2S/
DSD
Output
SPDIF
SCK/DCLK
WS
SD[3:0]
DR[3:0]
DR[3:0]
MUTEOUT
XTALIN
XTALOUT
MCLK
SCDT
R0PWR5V
R1PWR5V
R2PWR5V
R3PWR5V
RESET#
Reset
Logic
Figure 3.1. Functional Block Diagram
The SiI9233 receiver supports four HDMI input ports. Only one port can be active at any time.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.1.
TMDS Digital Cores
The TMDS Digital core is the latest generation core that supports HDMI v1.3 and the ability to carry 10/12-bit color
depth. The core can receive TMDS data at up to 225 MHz. Each core performs 10-to-8-bit TMDS decoding on the video
data and 10-to-4 bit TMDS decoding on the audio data received from the three TMDS differential data lines along with
a TMDS differential clock. The TMDS core can sense a stopped clock or stopped video and software can put the HDMI
receiver into power-down mode.
3.1.1. Active Port Detection and Selection
Only one port can be active at a time, under control of the HDMI Receiver’s firmware. Active TMDS signaling can arrive
at all ports, but only one has internal circuitry enabled. The firmware in the display controls these states using register
settings.
Other control signals are associated with the TMDS signals on each HDMI port. The HDMI Receiver can monitor the +5V
supply from each attached host. The firmware can poll registers to check on which ports are connected. The firmware
also controls functional connection to one of the four E-DDC buses, enabling one while disabling the others. An
attached host determines the active status of an attached HDMI device by polling the E-DDC bus to the HDMI Receiver.
Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for a complete description of
port detection and selection.
3.2.
HDCP Decryption Engine/XOR Mask
The HDCP decryption engine contains all the necessary logic to decrypt the incoming audio and video data. The
decryption process is entirely controlled by the host side microcontroller/microprocessor through a set sequence of
register reads and writes through the DDC channel. Pre-programmed HDCP keys and a Key Selection Vector (KSV)
stored in the on-chip non-volatile memory are used in the decryption process. A resulting calculated value is applied to
an XOR mask during each clock cycle to decrypt the audio/video data.
The SiI9233 also contains all the necessary logic to support full HDCP repeaters. The KSV values of downstream devices
2
(up to 16 total) are written to the HDMI receiver through the local I C bus (CSDA/CSCL). As defined in the HDCP
specification, Vi’ is calculated and made available to the host on the DDC bus (DSDA/DSCL).
3.2.1. HDCP Embedded Keys
The SiI9233 HDMI Receiver comes pre-programmed with a set of production HDCP keys stored on-chip in non-volatile
memory. System manufacturers do not need to purchase key sets from the Digital-Content LLC. All purchasing,
programming, and security for the HDCP keys is handled by Lattice Semiconductor. The pre-programmed HDCP keys
provide the highest level of security, as keys cannot be read out of the device after they are programmed. Before
receiving samples of the SiI9233 receiver, customers must sign the HDCP license agreement (www.digital-cp.com) or a
special NDA with Lattice Semiconductor.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
11
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.3.
Data Input and Conversion
3.3.1. Mode Control Logic
The mode control logic determines if the decrypted data is video, audio, or auxiliary information and directs it to the
appropriate logic block.
3.3.2. Video Data Conversion and Video Output
The HDMI Receiver can output video in many different formats (see examples in Table 3.1) and can process the video
data before it is sent, as shown in Figure 3.2. It is possible to bypass each of the processing blocks by setting the
appropriate register bits.
Table 3.1. Digital Video Output Formats
Color
Space
Video
Format
Bus
Width
HSYNC/
VSYNC
RGB
4:4:4
36
Separate
480i/576i
27
30
24
12/15/18
Separate
Separate
Separate
36
30
24
YCbCr
4:4:4
4:2:2
Notes:
1.
2.
3.
4.
Output Clock (MHz)
2, 3
Notes
480p
27
XGA
65
720p
74.25
1080i
74.25
SXGA
108
1080p
148.5
UXGA
162
27
27
27
27
27
27
65
65
65
74.25
74.25
74.25
74.25
74.25
74.25
108
108
—
148.5
148.5
—
162
162
—
—
4
Separate
Separate
Separate
27
27
27
27
27
27
65
65
65
74.25
74.25
74.25
74.25
74.25
74.25
108
108
108
148.5
148.5
148.5
162
162
162
—
—
—
12/15/18
16/20/24
Separate
Separate
27
27
27
27
65
—
74.25
74.25
74.25
74.25
—
—
—
148.5
162
4
—
16/20/24
8/10/12
8/10/12
Embedded
Separate
Embedded
27
27
27
27
54
54
—
—
—
74.25
148.5
148.5
74.25
148.5
148.5
—
—
—
148.5
—
—
162
—
1
—
1
Embedded syncs use SAV/EAV coding.
480i and 576i modes can output a 13.25 MHz clock using the internal clock divider.
Output clock frequency depends on programming of internal registers. Differential TMDS clock is always 25 MHz or faster.
Output clock supports 12/15/18-bit mode by using both edges.
3.3.2.1. Color Range Scaling
The color range depends on the video format, according to the CEA-861D specification. In some applications the 8-bit
input range uses the entire span of 0x00 (0) to 0xFF (255) values. In other applications the range is scaled narrower.
The HDMI Receiver cannot detect the incoming video data range and there is no required range specification in the
HDMI AVI packet. The HDMI Receiver chooses scaling depending on the detected video format. 10 and 12-bit color
range scaling are both handled the same way. Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference
(SiI-PR-1019) for more details.
When the HDMI Receiver outputs embedded syncs (SAV/EAV codes), it also limits the YCbCr data output values to 1 to
254.
3.3.2.2. Up Sample / Down Sample
Additional logic can convert from 4:2:2 to 4:4:4 (8/10/12-bit) or from 4:4:4 (8/10/12-bit) to 4:2:2 YCbCr format. All
processing is done with 14 bits of accuracy for true 12-bit data.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.3.3. Deep Color Support
The HDMI v1.3 specification introduces color depth modes greater than 24 bits, known as Deep Color modes, to the
HDMI system architecture. The Deep Color modes employ a new pixel packing scheme to enable the extra bits of
higher color depth data to be carried over the existing TMDS data encoding scheme. Currently, three Deep Color
modes are defined: 30-bit, 36-bit and 48-bit. The SiI9233 HDMI Receiver supports two of these three Deep Color
modes: 30 and 36-bit modes. In addition, each Deep Color mode is supported to 1080p HD format.
For Deep Color modes, the TMDS clock is run faster than the pixel clock in order to create extra bandwidth for the
additional bits of the higher color depth data. The increase in the TMDS clock is by the ratio of the pixel size to 24 bits,
as follows:
30-bit mode: TMDS clock = 1.25x pixel clock (5:4)
36-bit mode: TMDS clock = 1.5x pixel clock (3:2)
Because the SiI9233 receiver supports 36-bit mode at 1080p, the highest TMDS clock rate it supports is 225 MHz. When
in Deep Color mode, the transmitter periodically sends a General Control Packet with the current color depth and pixel
packing phase information to the receiver. The SiI9233 receiver captures the color depth information in a register,
which the firmware can then use to set the appropriate clock divider to recover the pixel clock and data.
3.3.4. x.v.Color Support
The SiI9233 receiver adds support for the extended gamut x.v.Color color space; this extended format has roughly 1.8
times more colors than the RGB color space. The use of the x.v.Color color space is made possible because of the
availability of LED and laser-based light sources for the next generation displays. This format also makes use of the full
range of values (1 to 254) in an 8-bit space instead of 16 to 235 in the RGB format. The use of x.v.Color along with Deep
Color helps in reducing color banding and allows the display of a larger range of colors than is currently possible.
3.3.4.1. Color Space Conversion
Color space converter (CSC) blocks are provided to convert RGB data to Standard-Definition (ITU.601) or HighDefinition (ITU.709) YCbCr formats, and vice-versa. To support the latest extended-gamut x.v.Color displays, the Sil9233
implements color space converter blocks to convert RGB data to extended-gamut Standard-Definition (ITU.601) or
High-Definition (ITU.709) x.v.Color formats, and vice-versa.
RGB to YCbCr
The RGBYCbCr color space converter (CSC) can convert from video data RGB to standard definition
(ITU.601) or to high definition (ITU.709) YCbCr formats. The HDMI AVI packet defines the color space of the incoming
video.
YCbCr to RGB
The YCbCrRGB color space converter is available to interface to MPEG decoders with RGB-only
inputs. The CSC can convert from YCbCr in standard-definition (ITU.601) or high-definition (ITU.709) to RGB.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
13
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.3.4.2. Default Video Configuration
After hardware RESET, the HDMI Receiver chip is configured in its default mode. This mode is summarized in Table 3.2.
For more details and for a complete register listing, refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s
Reference (SiI-PR-1019).
Table 3.2. Default Video Processing
Video Control
Default after Hardware Reset
Note
HDCP Decryption
Color Space Conversion
Color Space Selection
HDCP decryption is OFF
No color space conversion
BT.601 selected
1
1
—
Color Range Scaling
Upsampling/Downsampling
HSYNC & VSYNC Timing
No range scaling
No upsampling or downsampling
No inversions of HSYNC or VSYNC
1
—
—
Data Bit Width
Pixel Clock Replication
Uses 8-bit data
No pixel clock replication
1
1
Power Down
Everything is powered down
—
Notes:
1. The HDMI Receiver assumes DVI mode after reset, which is RGB 24-bit 4:4:4 video with 0–255 range.
TMDS
HDCP
RGB to
YCbCr
YCbCr
Range
Reduce
bypass
bypass
Upsample
4:2:2 to
4:4:4
xvYCC/
YCbCr to
RGB
Widen to
14-Bits
Down
Sample
4:4:4 to
4:2:2
bypass
bypass
bypass
RGB
Range
Expand
DE
Dither
Module
Mux
656
Video
Timing
HSYNC
bypass
VSYNC
ODCK
Q[35:0]
Figure 3.2. Default Video Processing Path
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.3.5. Automatic Video Configuration
The SiI9233 receiver adds automatic video configuration to simplify the firmware’s task of updating the video path
whenever the incoming video changes format. Bits in the HDMI Auxiliary Video Information (AVI) InfoFrame are used to
reprogram the registers in the video path.
Table 3.3. AVI InfoFrame Video Path Details
AVI Byte 1 Bits [6:5]
AVI Byte 2 Bits [7:6]
AVI Byte 5 Bits [3:0]
Y[1:0]
00
Color Space
RGB 4:4:4
C[1:0]
00
Colorimetric
No Data
PR[3:0]
0000
Pixel Repetition
No repetition
01
10
11
YCbCr 4:2:2
YCbCr 4:4:4
Future
01
10
11
ITU 601
ITU 709
Extended Colorimetry
Information Valid
0001
0010
0011
Pixel sent 2 times
Pixel sent 3 times
Pixel sent 4 times
0100
Pixel sent 5 times
0101
0110
0111
Pixel sent 6 times
Pixel sent 7 times
Pixel sent 8 times
1000
1001
Pixel sent 9 times
Pixel sent 10 times
Notes on Table 3.3
1.
2.
3.
The Auto Video Configuration assumes that the AVI information is
accurate. If information is not available, then the SiI9233 receiver must
choose the video path based on measurement of the incoming
resolution.
Refer to EIA/CEA-861D Specification for details.
The SiI9233 receiver can support only pixel replication modes 0b0000,
0b0001, and 0b0011. Other modes are unsupported and can result in
unpredictable behavior.
The format of the digital video output bus can be automatically configured to many different formats by programming
the Auto Output Format Register. The available formats are listed in the table below. For detailed definitions of how to
set this register, refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019).
Table 3.4. Digital Output Formats Configurable through Auto Output Format Register
Digital Output Formats
Color
Width
MUX
Sync
RGB
YCbCr
4:4:4
4:4:4
N
N
Sep.
Sep.
YCbCr
YCbCr
YCbCr
4:2:2
4:2:2
4:2:2
N
Y
Y
Sep.
Sep.
Emb.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
15
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.4.
Audio Data Capture Logic
2
The SiI9233 receiver can output digital audio over S/PDIF, four I S outputs, or eight one-bit audio outputs.
3.4.1. S/PDIF
The S/PDIF stream can carry 2-channel uncompressed PCM data (IEC 60958) or a compressed bit stream for multichannel (IEC 61937) formats. The audio data capture logic forms the audio data into packets according to the HDMI
specification. The S/PDIF output supports audio sampling rates from 32 to 192 kHz. A separate master clock output
(MCLK), coherent with the S/PDIF output, is provided for time-stamping purposes. Coherent means that the MCLK and
S/PDIF must have been created from the same clock source. This is typically done by using the original MCLK to strobe
out the S/PDIF from the sourcing chip. There is no setup or hold timing requirement on an output with respect to
MCLK.
3.4.2. I2S
2
2
2
The I S bus format is programmable through registers, to allow interfacing with I S audio DACs or audio DSPs with I S
2
inputs. Refer to the Programmer’s Reference for the different options on the I S bus. Additionally, the MCLK (audio
master clock) frequency is selectable to be an integer multiple of the audio sample rate F s.
MCLK frequencies support various audio sample rates as shown in Table 3.5.
Table 3.5. Supported MCLK Frequencies
2
Multiple of Fs
Audio Sample Rate, Fs : I S and S/PDIF Supported Rates
128
32 kHz
4.096 MHz
44.1 kHz
5.645 MHz
48 kHz
6.144 MHz
88.2 kHz
11.290 MHz
96 kHz
12.288 MHz
176.4 kHz
22.579 MHz
192 kHz
24.576 MHz
192
256
384
6.144 MHz
8.192 MHz
12.288 MHz
8.467 MHz
11.290 MHz
16.934 MHz
9.216 MHz
12.288 MHz
18.432 MHz
16.934 MHz
22.579 MHz
33.864 MHz
18.432 MHz
24.576 MHz
36.864 MHz
33.868 MHz
45.158 MHz
36.864 MHz
49.152 MHz
512
768
16.384 MHz
24.576 MHz
22.579 MHz
33.869 MHz
24.576 MHz
36.864 MHz
45.158 MHz
49.152 MHz
1024
1152
32.768 MHz
36.864 MHz
45.158 MHz
49.152 MHz
3.4.3. One-Bit Audio Input (DSD/SACD)
DSD (direct stream digital) is an audio data format defined for SACD (Super Audio CD) applications. It consists of four
data outputs for the left channel, four data outputs for the right channel, and a clock for up to 8-channel support. Onebit Audio supports 64*Fs, with Fs being either 44.1 kHz or 88.2 kHz.
The one bit audio outputs are synchronous to the positive edge of the DSD Clock. For one bit audio, the sampling
information is carried in the Audio InfoFrame, instead of the Channel Status bits.
3.4.4. High-Bitrate Audio on HDMI
The new high-bitrate compressed standards such as DTS-HD and Dolby TrueHD transmit data at bitrates as high as 18
to 24 Mbps. Because these bitrates are so high, DVD decoders and HDMI transmitters (as source devices), and DSP and
2
HDMI receivers (as sink devices) must carry the data using four I S lines rather than using a single very-high-speed
2
S/PDIF or I S bus (see Figure 3.3).
Four I2S
Data Lines
MPEG
Four I2S
Data Lines
Tx
Rx
DSP
Figure 3.3: High Speed Data Transmission
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
2
The high-bitrate audio stream is originally encoded as a single stream. To send it over four I S lines, the DVD decoder
needs to split this single stream into four streams. Because the single stream of data is being sent over four lines, the
programmable ACR (Audio Clock Regeneration) rate is now four times the 96-kHz (384-kHz) or four times the 192-kHz
(768-kHz) sample rate.
2
Figure 3.4 shows the high-bitrate stream before it has been split into four I S lines, and after it has been reassembled.
0
1
2
3
4
……….
5
N-1
N
16-Bits
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Figure 3.4: High-Bitrate Stream Before and After Reassembly and Splitting
2
Figure 3.5 shows the same high-bitrate audio stream after being split into four I S lines:
WS
Left
Right
Left
Right
SD0
Sample 0
Sample 1
Sample 8
Sample 9
SD1
Sample 2
Sample 3
Sample 10
Sample 11
SD2
Sample 4
Sample 5
Sample 12
Sample 13
SD3
Sample 6
Sample 7
Sample 14
Sample 15
Figure 3.5. High-Bitrate Stream After Splitting
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
17
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Table 3.6. Maximum Audio Sampling Frequency for All Video Format Timings
Description
Format
Timing
Pixel
Repetition
Vertical Freq.
(Hz)
60 Hz Formats
Max fs
8 ch (kHz)
4:2:2 and 4:4:4
24-bit
Max fs
2 ch (kHz)
4:4:4 Deep Color
(depth in bits)
Standard
10
12
VGA
480i
640x480p
1440x480i
none
2
59.94/60
59.94/60
48
48
48
48
48
48
192
192
480i
240p
240p
2880x480i
1440x240p
2880x240p
4
2
4
59.94/60
59.94/60
59.94/60
192
48
192
192
48
192
192
48
192
192
192
192
480p
480p
720x480p
1440x480p
none
2
59.94/60
59.94/60
48
96
48
96
48
96
192
192
480p
720p
1080i
2880x480p
1280x720p
1920x1080i
4
none
none
59.94/60
59.94/60
59.94/60
192
192
192
192
192
192
192
192
192
192
192
192
1080p
50 Hz Formats
576i
1920x1080p
none
59.94/60
2
50
192
10
48
192
12
48
192
1440x576i
192
Standard
48
576i
288p
2880x576i
1440x288p
4
2
50
50
192
48
192
48
192
48
192
192
288p
576p
576p
2880x288p
720x576p
1440x576p
4
none
2
50
50
50
192
48
96
192
48
96
192
48
96
192
192
192
576p
720p/50
2880x576p
1280x720p
4
none
50
50
192
192
192
192
192
192
192
192
1080i/50
1920x1080i
1080p/50
1920x1080p
1080p @ 24-30 Hz
none
none
50
50
192
192
Standard
192
192
10
192
192
12
192
192
1080p
1080p
1080p
none
none
none
24
25
29.97/30
192
192
192
192
192
192
192
192
192
192
192
192
1920x1080p
1920x1080p
1920x1080p
192
3.4.5. Auto Audio Configuration
The SiI9233 receiver can control the audio output based on the current states of CablePlug, FIFO, Video, ECC, ACR, PLL,
InfoFrame, and HDMI. Audio output is enabled only when all necessary conditions are met. If any critical condition is
missing, then the audio output is disabled automatically.
3.4.6. Soft Mute
On command from a register bit or when automatically triggered with Automatic Audio Control (AAC), the SiI9233
receiver progressively reduces the audio data amplitude to mute the sound in a controlled manner. This feature is
useful when there is an interruption to the HDMI audio stream (or an error) to prevent any audio pop from being sent
2
to the I S or S/PDIF outputs.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
3.5.
Control and Configuration
3.5.1. Register/Configuration Logic
The register/configuration logic block incorporates all the
registers required for configuring and managing the
features of the SiI9233 HDMI Receiver. These registers are
used to perform HDCP authentication,
audio/video/auxiliary format processing, CEA-861B
InfoFrame Packet format, and power-down control.
The registers are accessible from one of two serial ports.
The first port is the DDC port, which is connected through
the HDMI cable to the HDMI host. It is used to control the
SiI9233 receiver from the host device for HDCP operation.
2
The second port is the local I C port, which is used to
control the SiI9233 receiver from the display device. This
is shown in Figure 3.6. The Local Bus accesses the General
Registers and the Common Registers. The DDC Bus
accesses the HDCP Operation registers and the Common
Registers.
HDCP Operation
Accessible
from DDC
I2C Bus
Common Registers
General Registers
Video Processing
Audio Processing
Accessible
from Local
I2C Bus
InfoFrames
Repeater
Interrupts
2
Figure 3.6. I C Register Domains
3.5.2. I2C Serial Ports
2
2
The SiI9233 provides 5 I C serial interfaces: 4 DDC ports to communicate back to the HDMI or DVI hosts; one I C port
for initialization and control by a local microcontroller in the display. Each interface is 5-V tolerant.
3.5.2.1. E-DDC Bus Interface to HDMI Host
The four DDC interfaces (DSDA0-3 and DSCL0-3) on the SiI9233 receiver are slave interfaces that can run up to 100 kHz.
Each interface is connected to one E-DDC bus and is used for reading the integrated EDID in addition to HDCP
authentication.
The SiISiI9233 receiver is accessible on the E-DDC bus at device addresses 0xA0 for the EDID, and 0x74 for HDCP
control. This feature is compliant with the HDCP 1.1 Specification.
3.5.3. EDID FLASH and RAM Block
The EDID block consists of 1024 bytes of RAM. Each port has a block of 256 bytes of RAM for EDID data. This feature
allows simultaneous reads of all ports from four different source devices that are connected to the SiI9233 receiver. In
addition to the RAM, the EDID block contains 256 bytes of FLASH that is shared by all ports. As a result, the timing
information must be identical among all the ports if the internal EDID is used. An additional area of FLASH contains
unique CEC physical address and checksum values for each of the four ports. This feature allows simultaneous reads of
all ports from four different source devices if they are connected and attempt an EDID read at the same time. If
independent EDIDs are required on any of the ports, a CPU can externally load the 256 bytes of RAM for that port, by
2
using the local I C bus.
2
The internal EDID can be selected on a per-port basis using registers on the local I C bus. For example, Port 0 and Port 1
can use the internal EDID, and Port 2 and Port 3 can use a discrete EEPROM for the EDID.
3.5.4. CEC Interface
The Consumer Electronics Control (CEC) Interface block provides CEC electrically compliant signals between CEC
devices and a CEC master. It allows products to meet the electrical specifications of CEC signaling by translating the
LVTTL signals of an external microcontroller (CEC host-side or Tx-side) to CEC signaling levels for CEC devices at the Rxside, and vice versa.
Additionally, a CEC controller compatible with the Lattice Semiconductor CEC Programming Interface (CPI) is included
2
on-chip. This CEC controller has a high-level register interface accessible through the I C interface which can be used to
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
19
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
send and receive CEC commands. This controller makes CEC control very easy and straightforward, and removes the
burden of having a host CPU perform these low-level transactions on the CEC bus.
2
3.5.4.1. I C Interface to Display Controller
2
The Controller I C interface (CSDA, CSCL) on the SiI9233 receiver is a slave interface capable of running up to 400 kHz.
This bus is used to configure the SiI9233 by reading/writing to the appropriate registers. The SiI9233 receiver is
2
accessible on the local I C bus at two device addresses. Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s
Reference (SiI-PR-1019) for more information.
3.5.5. Standby and HDMI Port Power Supplies
The SiI9233 receiver incorporates a 5-volt standby power supply pin (SBVCC5) that can be used to supply power to the
EDID and CEC portions of the device when all other power supplies are turned off. This results in an extremely low
power mode, but allows the EDID to be readable, and the CEC controller to be functional in this low power standby
mode. No damage will occur to the device when in this mode.
If all power is off for the device, such as the TV being unplugged from the AC electrical outlet, the EDID can still be read
from the source by using power from the HDMI connector +5V signal. In this case, an internal power MUX will
automatically switch to the HDMI connector power to use for powering the EDID logic. In this mode, only the EDID
block is functional, with all other functions of the device in power off mode. No damage will occur to the device in this
mode.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4. Electrical Specifications
4.1.
Absolute Maximum Conditions
Symbol
IOVCC33
AVCC12
Parameter
I/O Pin Supply Voltage
TMDS Analog Supply Voltage
Min
–0.3
–0.3
Typ
—
—
Max
4.0
1.9
Units
V
V
Note
1, 2, 3
1, 2
AVCC33
APVCC12
TMDS Analog Supply Voltage
Audio PLL Supply Voltage
–0.3
–0.3
—
—
4.0
1.9
V
V
1, 2
1, 2
CVCC12
XTALVCC33
SBVCC5
Digital Core Supply Voltage
ACR PLL Crystal Oscillator Supply Voltage
Standby Supply Voltage
–0.3
–0.3
–0.3
—
—
—
1.9
4.0
5.7
V
V
V
1, 2
1, 2
1,2
VI
V5V-Tolerant
Input Voltage
Input Voltage on 5-V tolerant Pins
–0.3
–0.3
—
—
IOVCC33 + 0.3
5.5
V
V
1, 2
5
TJ
Junction Temperature
—
—
125
C
—
TSTG
Storage Temperature
–65
—
150
C
—
Notes:
1.
2.
3.
4.
5.
Permanent device damage can occur if absolute maximum conditions are exceeded.
Functional operation should be restricted to the conditions described under Normal Operating Conditions.
Voltage undershoot or overshoot cannot exceed absolute maximum conditions.
Refer to the SiI9233 Qualification Report for information on ESD performance.
All VCCs must be powered to the device. If the device is unpowered and 5V is applied to these inputs, damage can occur.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
21
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.2.
Normal Operating Conditions
Symbol
IOVCC33
AVCC12
Parameter
I/O Pin Supply Voltage
TMDS Analog Supply Voltage
Min
3.13
1.14
Typ
3.3
1.2
Max
3.47
1.26
Units
V
V
Note
1, 4
1, 6
AVCC33
APVCC12
TMDS Analog Supply Voltage
Audio PLL Supply Voltage
3.13
1.14
3.3
1.2
3.47
1.26
V
—
3
—
CVCC12
XTALVCC33
SBVCC5
Digital Core Supply Voltage
ACR PLL Crystal Oscillator Supply Voltage
Standby Supply Voltage
1.14
3.13
4.75
1.2
3.3
5.0
1.26
3.47
5.25
V
V
V
2
4
—
RxPWR5V
DIFF33
DIFF12
DDC I C I/O Reference Voltage
Difference between two 3.3-V Power Pins
Difference between two 1.2-V Power Pins
4.75
—
—
5.00
—
—
5.25
1.0
1.0
V
V
V
—
DIFF3312
VCCN
Difference between any 3.3-V and 1.2-V Pin
Supply Voltage Noise
–1.0
—
—
2.6
100
V
mVP-P
4, 5
7
TA
Ambient Temperature (with power applied)
0
25
70
C
—
Ambient Thermal Resistance (Theta JA)
—
—
27
C/W
—
ja
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
2
4
4
IOVCC33 and AVCC33 pins should be controlled from one power source.
CVCC12 should be controlled from one power source.
AVCC12 pin should be regulated.
Power supply sequencing must guarantee that power pins stay within these limits of each other. See Figure 4.4.
No 1.2 V pin can be more than DIFF3312[min] higher than any 3.3 V pin. No 3.3 V pin can be more than DIFF3312[max]
higher than any 1.2 V pin.
The HDMI 1.0 Specification requires termination voltage (AVCC33) to be controlled to 3.3 V ±5%. The SiI9233 tolerates a
wider range of ±300 mV.
The supply voltage noise is measured at test point VCCTP in Figure 5.2 on page 42. The ferrite bead provides filtering of
power supply noise. The figure is representative and applies to other VCC pins as well.
Airflow at 0 m/s.
The schematics on page 70 show decoupling and power supply regulation.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
DC Specifications
4.3.
4.3.1. Digital I/O Specifications
Symbol
VIH
VIL
Parameter
High-level Input Voltage
Low-level Input Voltage
Pin Type
LVTTL
LVTTL
VTH+
Low to HIGH Threshold
RESET # Pin
HIGH to Low Threshold
RESET# Pin
Schmitt
DDC VTH+
DDC VTH-
3
2
Min
2.0
Typ
—
—
Max
—
0.8
Units
V
V
Note
—
—
—
1.46
—
—
V
5
Schmitt
—
—
—
0.96
V
5
Low to HIGH Threshold
DSDA0, DSDA1, DSCL0 and
DSCL1 pins.
Schmitt
—
3.0
—
V
—
HIGH to Low Threshold
DSDA0, DSDA1, DSCL0 and
DSCL1 pins.
Schmitt
—
—
—
1.5
V
—
Local I C VTH+
2
Low to HIGH Threshold
CSCL and CSDA pins
Schmitt
—
2.1
—
—
V
11, 13
Local I C VTH-
2
HIGH to Low Threshold
CSCL and CSDA pins
Schmitt
—
—
—
0.86
V
11, 13
VOH
High-level Output Voltage
LVTTL
—
2.4
—
V
10
VOL
IOL
Low-level Output Voltage
Output Leakage Current
LVTTL
—
—
High Impedance
—
–10
—
—
0.4
10
V
10
—
VID
Differential Input Voltage
—
—
75
250
780
A
mV
IOD4
4mA Digital Output Drive
Output
VOUT = 2.4 V
VOUT = 0.4 V
4
4
—
—
—
—
mA
mA
1, 6, 7
1, 6, 7
IOD8
8mA Digital Output Drive
Output
IOD12
12mA Digital Output Drive
Output
VOUT = 2.4 V
VOUT = 0.4 V
VOUT = 2.4 V
8
8
12
—
—
—
—
—
—
mA
mA
mA
1, 6, 8
1, 6, 8
1, 6, 9
RPD
IOPD
Internal Pull Down Resistor
Output Pull Down Current
Outputs
Outputs
VOUT = 0.4 V
IOVCC33=3.3 V
IOVCC33=3.6 V
12
25
—
—
50
60
—
110
90
mA
kΩ
A
1, 6, 9
1, 12
1, 12
IIPD
Input Pull Down Current
Input
IOVCC33=3.6 V
—
60
90
A
1
VTH-
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Conditions
—
—
4
These limits are guaranteed by design.
Under normal operating conditions unless otherwise specified, including output pin loading C L = 10 pF.
Refer to Pin Descriptions (beginning on page 21) for pin type designations for all package pins.
Differential input voltage is a single-ended measurement, according to DVI Specification.
Schmitt trigger input pin thresholds VTH+ and VTH- correspond to VIH and VIL, respectively.
Minimum output drive specified at ambient = 70 C and IOVCC33 = 3.0 V. Typical output drive specified at ambient = 25 C
and IOVCC33 = 3.3 V. Maximum output drive specified at ambient = 0 C and IOVCC33 = 3.6 V.
IOD4 Output applies to pins SPDIF, SCK, WS, SD[3:0], DCLK, INT, and CSDA.
IOD8 Output applies to pins DE, HSYNC, VSYNC, Q[35:0].and MCLK.
IOD12 Output applies to pin ODCK.
Note that the SPDIF output drives LVTTL levels, not the low-swing levels defined by IEC958.
The SCL and SDA pins are not true open-drain buffers. When no VCC is applied to the chip, these pins can continue to draw
2
a small current, and prevent the master IC from communicating with other devices on the I C bus. Therefore, do not
2
power-down the SiI9233 (remove VCC) unless the attached I C bus is completely idle.
The chip includes an internal pull-down resistor on many of the output pins. When tri-stated, these pins draw a pull down
current according to this specification when the signal is driven HIGH by another source device.
2
With –10% IOVCC33 supply, the HIGH-to-LOW threshold on DDC and I C bus is marginal. A –5% tolerance on the IOVCC33
power supply is recommended.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
23
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.3.2. DC Power Supply Pin Specifications
4.3.2.1. Total Power versus Power-Down Modes
3
Symbol
IPDQ3
IPDS
ISTBY
IUNS
ICCTD
Typ
3.3V
4
SBVCC5
Units
Notes
Mode
Frequency
A
X
4
0
—
mA
1, 6
B
27 MHz
5
4
5
mA
2, 7
74.25 MHz
150 MHz
225 MHz
6
4
7
4
4
5
5
5
5
mA
mA
mA
Standby
Current
C
27 MHz
74.25 MHz
0
0
0
0
5
5
mA
mA
150 MHz
225 MHz
27 MHz
15
25
5
0
0
19
0
0
33
5
5
5
mA
mA
mA
74.25 MHz
150 MHz
225 MHz
17
16
18
27
28
30
5
5
5
21
18
23
34
36
39
5
5
5
mA
mA
mA
27 MHz
74.25 MHz
81
100
76
160
5
5
105
165
88
181
5
5
mA
mA
150 MHz
225 MHz
123
139
279
394
5
5
247
316
337
472
5
5
mA
mA
D
Full Power
Digital Out
Current
E
SBVCC5
1.2V
Parameter
Complete
Power-Down
Current
Sleep Powerdown Current
Unselected
Current
1.2V
Max
3.3V
2, 8
2, 8
2, 10
Notes:
1.
2.
3.
Power is not related to input TMDS clock (RxC) frequency because the selected TMDS port is powered down.
Power is related to input TMDS clock (RxC) frequency at the selected TMDS port. Only one port can be selected.
Typical power specifications measured with supplies at typical normal operating conditions; and a video pattern that
combines gray scale, checkerboard and text.
4. Maximum power limits measured with supplies at maximum normal operating conditions, minimum normal operating
ambient temperature, and a video pattern with single-pixel vertical lines.
2
5. Registers are always accessible on local I C (CSDA/CSCL) without active link clock.
6. Power Down Mode A: Minimum power. Everything is powered off. Host sees no termination of TMDS signals on any of the
2
four TMDS ports. I C access is still available.
7. Power Down Mode B: Powers down as in Mode C, but also powers down SCDT logic. CKDT state can be polled in register,
but interrupts and the INT output pin are inactive. Host device can sense TMDS termination.
8. Power Down Mode C: Power off to 3.3 V and 1.2 V supplies. Power on to SBVCC5 standby supply.
9. Power Down Mode D: Monitor SCDT on selected TMDS port with outputs tri-stated. HDCP continues in the selected port,
but the output of the HDMI Receiver can be connected to a shared bus.
10. Digital Functional Mode E: Full Operation on one port with digital outputs
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.3.2.2. Power-Down Mode Definitions
Mode
A
B
C
D
Power
Down
Sleep
Mode
Power
Standby
Power
Unselected
Power
3.3V
supply
1.2v
supply
SBVCC5
Description
ON
ON
ON
ON
ON
ON
OFF
OFF
ON
ON
ON
ON
Minimum power. Everything is powered off. Host sees no termination of
2
TMDS signals on any of the four TMDS ports. I C access is still available.
Powers down as in Mode C, but also powers down SCDT logic. CKDT
state can be polled in register, but interrupts and the INT output pin are
inactive. Host device can sense TMDS termination.
Power off to 3.3 V and 1.2 V supplies. Power on to SBVCC5 standby
supply.
Monitor SCDT on selected TMDS port with outputs tri-stated. HDCP
continues in the selected port, but the output of the HDMI Receiver can
be connected to a shared bus.
E
Digital
ON
ON
ON
Full operation on one port with digital outputs.
Notes:
1. PD Clks include PD_MCLK#, PD_XTAL#, PD_APLL# and PD_PCLK# all set to zero.
2. PD Outs include PD_AO#, and PD_VO# all set to zero.
4.4.
AC Specifications
4.4.1. TMDS Input Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TDPS
Intra-Pair Differential Input Skew
—
—
—
TBIT
ps
TCCS
Channel to Channel Differential
Input Skew
—
—
—
TCIP
ns
Figure 4.3
2, 3
FRXC
Differential Input Clock Frequency
—
25
—
225
MHz
—
—
TRXC
Differential Input Clock Period
—
4.44
—
40
ns
—
—
TIJIT
Differential Input Clock Jitter
tolerance (0.3Tbit)
74.25 MHz
—
—
400
ps
—
2, 5, 6
Notes:
1.
2.
3.
4.
5.
6.
Figure
Notes
2, 4
Under normal operating conditions unless otherwise specified, including output pin loading of C L = 10 pF.
Guaranteed by design.
IDCK Period (refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet).
1/10 of IDCK Period (refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet).
Jitter defined per HDMI Specification.
Jitter measured with Clock Recovery Unit per HDMI Specification. Actual jitter tolerance can be higher depending on the
frequency of the jitter.
Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for more details on controlling
timing modes.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
25
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.4.2. Video Output Timings
4.4.2.1. 12/15/18-Bit Data Output Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
DLHT
Low-to-High Rise Time Transition
CL = 10 pF
—
—
3
ns
Figure 4.6
2
DHLT
High-to-Low Fall Time Transition
CL = 10 pF
—
—
3
ns
Figure 4.6
2
RCIP
ODCK Cycle Time
CL = 10 pF
13
—
40
ns
Figure 4.7
8
FCIP
ODCK Frequency
CL = 10 pF
25
—
82.5
MHz
—
5
TDUTY
ODCK Duty Cycle
CL = 10 pF
40%
—
60%
RCIP
Figure 4.7
3
TCK2OUT
Clock-to-Output Delay
CL = 10 pF
0.8
—
3.8
ns
Figure 4.7
—
4.4.2.2. 16/20/24/30/36-Bit Data Output Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
DLHT
Low-to-High Rise Time Transition
CL = 10 pF
—
—
3
ns
Figure 4.6
2
DHLT
High-to-Low Fall Time Transition
CL = 10 pF
—
—
3
ns
Figure 4.6
2
TDUTY
ODCK Duty Cycle
CL = 10 pF
40%
—
60%
RCIP
Figure 4.7
3
TCK2OUT
ODCK-to-Output Delay
CL = 10 pF
0.92
—
2.9
ns
Figure 4.7
—
RCIP
Output Clock
Cycle Time
SiI9233CTU
CL = 10 pF
6.06
—
40
ns
Figure 4.7
5, 8
FCIP
Output Clock
Frequency
SiI9233CTU
CL = 10 pF
25
—
165
MHz
Figure 4.7
5
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Under normal operating conditions unless otherwise specified, including output pin loading of C L=10 pF.
Rise time and fall time specifications apply to HSYNC, VSYNC, DE, ODCK, EVNODD and Q[35:0].
Output clock duty cycle is independent of the differential input clock duty cycle. Duty cycle is a component of output setup
and hold times.
See Table 4.2 on page 34 for calculation of worst case output setup and hold times.
All output timings are defined at the maximum operating ODCK frequency, FCIP, unless otherwise specified.
FCIP can be the same as FRXC or one-half of FRXC, depending on OCLKDIV setting. FCIP can also be FRXC /1.25 or FRXC /1.5 if deep
color mode is being transmitted.
RCIP is the inverse of FCIP and is not a controlling specification.
Output skew specified when ODCK is programmed to divide-by-two mode.
4.4.3. Audio Output Timings
2
4.4.3.1. I S Output Port Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
Ttr
SCK Clock Period (TX)
CL = 10 pF
1.00
—
—
Ttr
Figure 4.8
1
THC
SCK Clock HIGH Time
CL = 10 pF
0.35
—
—
Ttr
1
TLC
SCK Clock LOW Time
CL = 10 pF
0.35
—
—
Ttr
1
TSU
Setup Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
1
THD
Hold Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
1
TSCKDUTY
SCK Duty Cycle
CL = 10 pF
40%
—
60%
Ttr
1
TSCK2SD
SCK to SD or WS Delay
CL = 10 pF
–5
—
+5
ns
2
TAUDDLY
Audio Pipeline Delay
—
—
40
80
µs
Notes:
1.
2.
—
—
2
Refer to Figure 4.8. Meets timings in Philips I S Specification.
Applies also to SDC-to-WS delay.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.4.3.2. S/PDIF Output Port Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
TSPCYC
SPDIF Cycle Time
CL = 10 pF
—
1.0
—
UI
Figure 4.9
1, 2
FSPDIF
SPDIF Frequency
—
4
—
24
MHz
3
TSPDUTY
SPDIF Duty Cycle
CL = 10 pF
90%
—
110%
UI
2, 5
TMCLKCYC
MCLK Cycle Time
CL = 10 pF
20
—
250
ns
FMCLK
MCLK Frequency
CL = 10 pF
4
—
50
MHz
TMCLKDUTY
MCLK Duty Cycle
CL = 10 pF
40%
—
60%
TMCLKCYC
TAUDDLY
Audio Pipeline Delay
—
—
40
80
µs
Notes:
1.
2.
3.
4.
5.
Figure
4.10
1, 2, 4
1, 2, 4
2, 4
—
—
Guaranteed by design.
Proportional to unit time (UI), according to sample rate.
SPDIF is not a true clock, but is generated from the internal 128Fs clock, for Fs from 128 to 512 kHz.
MCLK refers to MCLKOUT.
Intrinsic jitter on S/PDIF output can limit its use as an S/PDIF transmitter. The S/PDIF intrinsic jitter is approximately 0.1UI.
4.4.3.3. Audio Crystal Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
FXTAL
External Crystal Freq.
—
—
27
—
MHz
Figure 4.1
1, 2
3.3 V
3
5
27MHz
18 pF
XTALVCC
XTALIN
SiI9233
1 M
4
XTALOUT
18pF
Figure 4.1. Audio Crystal Schematic for the SiI9233 Receiver
Notes:
1.
2.
The HDMI Receiver has been fully characterized for optimum audio quality and CEC timing calibration using 27.000 MHz.
Use Citizen part number CSA309-27.000MABJ crystal or equivalent. A less expensive, but not fully characterized circuit, can
use a TTL level clock source.
The XTALIN/XTALOUT pin pair must be driven with a clock in all applications.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
27
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.4.4. Miscellaneous Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
TI2CDVD
SDA Data Valid delay from SCL falling edge
CL = 400 pF
—
—
700
ns
—
—
FDDC
Speed on TMDS DDC Ports
CL = 400 pF
—
—
100
kHz
—
2
2
FI C
2
Speed on Local I C Port
CL = 400 pF
—
—
400
kHz
—
3
TRESET
RESET# Signal Low Time for valid reset
—
50
—
—
µs
Figure 4.5
—
TSTARTUP
Startup time from power supplies valid
—
—
—
100
ms
—
5
TBKSVINIT
HDCP BKSV Load Time
—
—
—
2.2
ms
—
4
Notes:
1.
2.
3.
4.
5.
Under normal operating conditions unless otherwise specified, including output pin loading of CL = 10 pF.
2
DDC ports are limited to 100 kHz by the HDMI Specification, and meet I C standard mode timings.
2
2
Local I C port (CSCL/CSDA) meets standard mode I C timing requirements to 400 kHz.
The time required to load the KSV values internal to the HDMI Receiver after a RESET# and the start of an active TMDS
clock. An attached HDCP host device should not attempt to read the HDMI receiver BKSV values until after this time. The
TBKSVINIT Min and Max values are based on the maximum and minimum allowable XCLK frequencies. The loading of the
BKSV values requires a valid XCLK and TMDS clock.
TSTARTUP is the startup time required for the device to be operational once power is stable. This startup time is due to the on
board voltage regulator for the EDID and CEC and a power on reset circuit.
4.4.5. Interrupt Timings
4.4.5.1. Interrupt Output Pin Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
TFSC
Link disabled (DE inactive) to SCDT LOW
—
—
0.15
40
ms
Figure 4.2
1, 2, 3, 8
THSC
Link enabled (DE active) to SCDT HIGH
—
—
—
4
DE
Figure 4.2
1, 2, 4, 8
TCICD
RXC inactive to CKDT LOW
—
—
—
100
µs
Figure 4.2
1, 2, 8
TCACD
RXC active to CKDT HIGH
—
—
—
10
µs
Figure 4.2
1, 2, 8
TINT
Response Time for INT from Input Change
—
—
—
100
µs
—
1, 5, 8
TCIOD
RXC inactive to ODCK inactive
—
—
—
100
ns
—
1, 8
TCAOD
RXC active to ODCK active and stable
—
—
—
10
ms
—
1, 6, 8
TSRRF
Delay from SCDT rising edge to Software
Reset falling edge
—
—
—
100
ms
Figure 4.5
7
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
Guaranteed by design.
SCDT and CKDT are register bits in this device.
SCDT changes to LOW after DE is HIGH for approximately 4096 pixel clock cycles, or after DE is LOW for approximately
1,000,000 clock cycles. At 27 MHz pixel clock, this delay for DE HIGH is approximately 150 µs, and the delay for DE LOW is
approximately 40 ms.
SCDT changes to HIGH when clock is active (TCACD) and at least 4 DE edges have been recognized. At 720p, the DE period is
22 µs, so SCDT responds approximately 50 µs after TCACD.
The INT pin changes state after a change in input condition when the corresponding interrupt is enabled.
Output clock (ODCK) becomes active before it becomes stable. Use the SCDT signal as the indicator of stable video output
timings, as this depends on decoding of DE signals with active RXC (see TFSC).
Software Reset must be asserted and then de-asserted within the specified maximum time after rising edge of Sync Detect
2
(SCDT). Access to both SWRST and SCDT can be limited by the speed of the I C connection.
SCDT is HIGH only when CKDT is also HIGH. When the HDMI Receiver is in a powered-down mode, the INT output pin
indicates the current state of SCDT. Thus, a power-down HDMI Receiver signals a micro connected to the INT pin whenever
SCDT changes from LOW to HIGH or HIGH to LOW.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
RXC
link clock active
link clock inactive
link clock active
CKDT
TCICD
TCACD
Do not Care
DE
TFSC
THSC
SCDT
Figure 4.2. SCDT and CKDT Timing from DE or RXC Inactive/Active
Notes:
1.
2.
3.
4.
The SCDT shown in Figure 4.2 is a register bit. SCDT remains HIGH if DE is stuck in LOW while RXC remains active, but SCDT
changes to LOW if DE is stuck HIGH while RXC remains active.
The CKDT shown in Figure 4.2 is a register bit. CKDT changes to LOW whenever RXC stops, and changes to HIGH when RXC
starts. SCDT changes to LOW when CKDT changes to LOW.
SCDT changes to LOW when CKDT changes to LOW. SCDT changes to HIGH at THSC after CKDT changes to HIGH.
The INT output pin changes state after the SCDT or CKDT register bit is set or cleared if those interrupts are enabled.
Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for more details on controlling
timing modes.
4.5.
Timing Diagrams
4.5.1. TMDS Input Timing Diagrams
RX0
RX1
RX2
TCCS
VDIFF = 0V
Figure 4.3. TMDS Channel-to-Channel Skew Timing
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
29
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.5.2. Power Supply Control Timings
Power Off Sequence
Power On Sequence
DIFF33 max
maximum 3.3 V
excursion
IOVCC33
AVCC33
XTALVCC33
minimum 3.3 V
excursion
DIFF3312 max
maximum 3.3 V
excursion
IOVCC33
AVCC33
XTALVCC33
DIFF33 max
minimum 3.3 V
excursion
maximum 1.2 V
excursion
maximum 1.2 V
excursion
minimum 1.2 V
DIFF12 max
excursion
AVCC12
CVCC12
AVCC12
CVCC12
DIFF3312 max
minimum 1.2 V
excursion
DIFF12 max
Figure 4.4. Power Supply Sequencing
4.5.3. Reset Timings
VCC max
RESET#
VCC min
TRESET
VCC
RESET#
T RESET
Note that VCC must be stable between its limits for Normal
Operating Conditions for TRESET before RESET# is HIGH.
RESET# must be pulled LOW for TRESET before accessing
registers. This can be done by holding RESET# LOW until TRESET
after stable power (at left); OR by pulling RESET# LOW from a
HIGH state (at right) for at least TRESET.
Figure 4.5. RESET# Minimum Timings
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.5.4. Digital Video Output Timing Diagrams
4.5.4.1. Output Transition Times
2.0V
2.0V
0.8V
0.8V
DLHT
DHLT
Figure 4.6. Video Digital Output Transition Times
4.5.4.2. Output Clock to Output Data Delay
T
TH
CYC
TL
OCLKINV = 0
ODCK
OCLKINV = 1
ODCK
T
CKO(max)
TCKO(min)
Q[35:0]
T CKO(max)
TCKO(min)
DE
HSYNC
VSYNC
Figure 4.7. Receiver Clock-to-Output Delay and Duty Cycle Limits
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
31
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.5.5. Digital Audio Output Timings
TTR
TSCKDUTY
SCK
TSCK2SD_MAX
WS
SD
TSU
Data Valid
THD
TSCK2SD_MIN
Data Valid
Data Valid
Figure 4.8. I2S Output Timings
TSPCYC, TSPDUTY
TSPCYC, TSPDUTY
90%
50%
SPDIF
10%
Figure 4.9. S/PDIF Output Timings
TMCLKCYC
MCLK
50%
50%
TMCLKDUTY
Figure 4.10. MCLK Timings
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.6.
Calculating Setup and Hold Times for Video Bus
4.6.1. 24/30/36-Bit Mode
Output data is clocked out on one rising (or falling) edge of ODCK, and is then captured downstream using the same
polarity ODCK edge one clock period later. The setup time of data to ODCK and hold time of ODCK to data are therefore
a function of the worst case ODCK to output delay, as shown in Figure 4.11. The active rising ODCK edge is shown with
an arrowhead. For OCK_INV=1, reverse the logic.
TCK2OUT{max}
TSU
THD
TCK2OUT{min}
ODCK
Shortest
Clk-to-Out
Longest
Clk-to-Out
Q
DE
VSYNC
HSYNC
Data Valid
Data Valid
Figure 4.11. 24/30/36-Bit Mode Receiver Output Setup and Hold Times
Table 4.1 shows minimum calculated setup and hold times for commonly used ODCK frequencies. The setup and hold
times apply to DE, VSYNC, HSYNC and Data output pins, with output load of 10pF. These are approximations. Hold time
is not related to ODCK frequency.
Table 4.1. Calculation of 24/30/36-Bit Output Setup and Hold Times
24/30/36Bit Mode
Symbol
TSU
Parameter
Setup Time to ODCK
= TODCK-TCK2OUT{max}
TODCK
27 MHz
74.25 MHz
37.0 ns
13.5 ns
Min
33.2 ns
9.7 ns
THD
Hold Time from ODCK = TCK2OUT{min}
27 MHz
37.0 ns
0.8 ns
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
33
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.6.2. 12/15/18-Bit Dual-Edge Mode
Output data is clocked out on each edge of ODCK (both rising and falling), and is then captured downstream using the
opposite ODCK edge. The setup time of data to ODCK is a function of the shortest duty cycle and the longest ODCK to
output delay. The hold time does not depend on duty cycle (since every edge is used), and is a function only of the
shortest ODCK to output delay.
TSU
THD
ODCK
TDUTY{min}
TCK2OUT{min}
TCK2OUT{max}
Q
DE
VSYNC
HSYNC
Data Valid
Data Valid
Figure 4.12. 12/15/18-Bit Mode Receiver Output Setup and Hold Times
Table 4.2 shows minimum calculated setup and hold times for commonly used ODCK frequencies, up to the maximum
allowed for 12/15/18-bit mode. The setup and hold times apply to DE, VSYNC, HSYNC and Data output pins, with
output load of 10 pF. These are approximations. Hold time is not related to ODCK frequency.
Table 4.2. Calculation of 12/15/18-Bit Output Setup and Hold Times
12/15/18Bit Mode
Symbol
TSU
THD
Parameter
Setup Time to ODCK
=TODCK•TDUTY{min}-TCK2OUT{max}
Hold Time from ODCK = TCK2OUT{min}
TODCK
27 MHz
37.0 ns
Min
34.1 ns
74.25 MHz
27 MHz
13.5 ns
37.0 ns
10.6 ns
0.8ns
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
4.7.
Calculating Setup and Hold Times for I2S Audio Bus
Valid serial data is available at Tsck2sd after the falling edge of the first SCK cycle, and then captured downstream using
the active rising edge of SCK one clock period later. The setup time of data to SCK (TSU) and hold time of SCK to data
(THD) are therefore a function of the worst case SCK-to-output data delay (Tsck2sd). Figure 4.8 illustrates this timing
relationship. Note that the active SCK edge (rising edge) is shown with an arrowhead. For a falling edge sampling clock,
the logic is reversed.
Table 4.3 shows the setup and hold time calculation examples for various audio sample frequencies. The formula used
in these examples also applies when calculating the setup and hold times for other audio sampling frequencies.
2
Table 4.3. I S Setup and Hold Time Calculations
Symbol
Parameter
FWS (kHz)
FSCLK (MHz)
Ttr
Min
TSU
Setup Time, SCK to SD/WS
= TTR – ( TSCKDUTY_WORST + TSCK2SD_MAX )
= TTR – (0.6TTR + 5ns )
= 0.4TTR – 5ns
32 kHz
2.048
488 ns
190 ns
44.1 kHz
2.822
354 ns
136 ns
48 kHz
3.072
326 ns
125 ns
96 kHz
6.144
163 ns
60 ns
192 kHz
12.288
81 ns
27 ns
32 kHz
2.048
488 ns
190 ns
44.1 kHz
2.822
354 ns
136 ns
48 kHz
3.072
326 ns
125 ns
96 kHz
6.144
163 ns
60 ns
192 kHz
12.288
81 ns
27 ns
THD
Hold Time, SCK to SD/WS
= ( TSCKDUTY_WORST - TSCK2SD_MIN )
= 0.4TTR – 5ns
Note: The sample calculations shown are based on WS=64 SCLK rising edges.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
35
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
5. Pin Diagram and Descriptions
AVCC33
R3X2+
R3X2-
R3X1+
R3X1-
R3X0+
R3X0-
R3XC+
R3XC-
AVCC12
R2X2+
R2X2-
R2X1+
R2X1-
R2X0+
R2X0-
R2XC+
R2XC-
AVCC33
R1X2+
R1X2-
R1X1+
R1X1-
R1X0+
R1X0-
R1XC+
R1XC-
AVCC12
R0X2+
R0X2-
R0X1+
R0X1-
R0X0+
R0X0-
R0XC+
R0XC-
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
Figure 5.1 shows the pin connections for the SiI9233 in the 144-pin TQFP package. Individual pin functions are
described beginning on page 36.
RSVDNC
APVCC12
1
2
108
107
AVCC 33
GPIO3 / MUTEOUT
XTALVCC33
XTALOUT
3
106
4
105
SPDIF/DL2
MCLK
XTALIN
XTALGND
5
6
104
103
SD3/DR2
102
RSVDNC
RSVDNC
7
8
9
10
100
99
SD1/DR1
SD0/DL0
SCK/DCLK
WS/DR0
RSVDL
GPIO0 /XCLKOUT
11
12
98
IOVCC 33
97
CVCC 12
GPIO 1/SCDT
GPIO2/EVNODD
13
14
96
95
Q0
Q1
RSVDNC
GPIO4
15
16
94
93
Q2
GPIO5
RSVDNC
17
92
91
Q4
Q5
90
89
Q6
21
88
22
23
24
87
86
85
Q8
IOVCC 33
25
26
84
83
27
28
82
32
33
34
77
76
75
35
74
73
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DSCL3
DSDA3
RSVDCEC
RSVDNC
RSVDNC
RSVDNC
RSVDNC
GND
Q35
Q34
Q33
Q32
Q31
Q30
Q29
Q28
Q27
CVCC12
I OVCC33
Q26
Q25
Q24
Q23
Q22
Q21
Q20
Q19
Q18
CVCC12
I OVCC33
36
HPD3
DSDA1
78
41
HPD1
DSCL1
31
R3PWR5V
DSDA0
R1 PWR5V
81
80
79
40
HPD 0
DSCL0
29
30
DSDA2
SBVCC5
R0PWR 5 V
39
CEC_ A
CEC_D
DSCL2
CI 2CA
38
CSCL
CSDA
18
19
20
37
RESET#
INT
144-pin TQFP
(Top View )
HPD2
GPIO6/DL3
GPIO7/DR3
101
R2PWR5V
IOVCC33
CVCC12
SD2/DL1
Q3
Q7
CVCC 12
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
ODCK
HSYNC
VSYNC
DE
Figure 5.1. Pin Diagram
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
5.1.
Pin Descriptions
5.1.1. Digital Video Output Pins
Pin Name
Pin #
Strength
Type
Dir
Description
Q0
96
Programmable
LVTTL
Output
Q1
95
Q2
94
Q3
93
Q4
92
Q5
91
Q6
90
Q7
89
36-Bit Output Pixel Data Bus. The Q[35:0] bus is
highly configurable using the various video
configuration registers. It supports a wide array
of output formats, including multiple RGB and
YCbCr bus formats. Using the appropriate bits in
the PD_SYS2 register, the output drivers can be
put into a high impedance (tri-state) mode. A
weak, internal pull-down device brings each
output to ground.
Q8
88
Q9
85
Q10
84
Q11
83
Q12
82
Q13
81
Q14
80
Q15
79
Q16
78
Q17
77
Q18
70
Q19
69
Q20
68
Q21
67
Q22
66
Q23
65
Q24
64
Q25
63
Q26
62
Q27
59
Q28
58
Q29
57
Q30
56
Q31
55
Q32
54
Q33
53
Q34
52
Q35
51
DE
73
Programmable
LVTTL
Output
Data Enable.
HSYNC
75
Programmable
LVTTL
Output
Horizontal Sync Output
VSYNC
74
Programmable
LVTTL
Output
Vertical Sync Output
GPIO2 / EVNODD
14
8 mA
LVTTL
Bi-Di
Programmable GPIO2 or Indicates Even or Odd
Field for Interlaced Formats.
ODCK
76
Programmable
LVTTL
Output
Output Data Clock.
Notes:
1.
HSYNC and VSYNC outputs carry sync signals for both embedded and separate sync configurations.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
37
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
2.
3.
4.
When transporting video data that uses fewer than 36 bits, the unused bits on the Q[] bus can still carry switching pixel
data signals. Unused Q[35:0] bus pins should be unconnected, masked or ignored by downstream devices. For example,
carrying YCbCr 4:2:2 data with 16-bit width (see page 51), the bits Q[0] through Q[7] output switching signals.
The output data bus, Q0 to Q35, can be wire-ORed to another device such that one device is always tri-stated. However,
the Q0-Q35 pins do not have bus hold internal pull-up or pull-down resistors, and so cannot pull the bus HIGH or LOW
when all connected devices are tri-stated.
The drive strength of these pins can be programmed in 2-mA steps between 2 mA and 14 mA: Q[0:35], DE, HSYNC, VSYNC,
and ODCK.
5.1.2.
Digital Audio Output Pins
Pin Name
Pin #
Strength
Type
XTALIN
5
—
5-V tolerant In
LVTTL
Dir
Description
Crystal Clock Input. Also allows LVTTL input.
Frequency required: 26-28.5 MHz
XTALOUT
4
4 mA
LVTTL
Out
Crystal Clock Output
GPIO0 /
XCLKOUT
12
4 mA
LVTTL
Bi-Di
Programmable GPIO0 or additional Clock Output
from crystal oscillator circuit
MCLK
105
8 mA
LVTTL
Bi-Di
SCK/DCLK
100
4 mA
LVTTL
Out
Audio Master Clock Output.
2
I S Serial Clock Output.
SD3/DR2
SD2/DL1
SD1/DR1
SD0/DL0
104
103
102
101
4 mA
LVTTL
Out
I S Serial Data Output / DSD Audio Output
Configurable to be shared with DSD.
SD0 = DSD Serial Left Ch0 Data Output
SD1 = DSD Serial Right Ch1 Data Output
SD2 = DSD Serial Left Ch1 Data Output
SD3 = DSD Serial Right Ch2 Data Output
WS/DR0
99
4 mA
LVTTL
Out
I S Word Select Output. DSD Serial Right Ch0
SPDIF/DL2
106
4 mA
LVTTL
Out
S/PDIF Audio Output. DSD Serial Left Channel 2
data output.
GPIO6/DL3
19
4 mA
LVTTL
Bi-Di
Programmable GPIO6. DSD Serial Left Channel 3
data output.
GPIO7/DR3
20
4 mA
LVTTL
Bi-Di
Programmable GPIO7. DSD Serial Right Channel 3
data output.
GPIO3/
MUTEOUT
107
4 mA
LVTTL
Bi-Di
Programmable GPIO3 or Mute Audio Output.
Signal to the external downstream audio device,
audio DAC, etc. to mute audio output.
2
2
Data Output.
Note: The XTALIN pin can either be driven at LVTTL levels by a clock (leaving XTALOUT unconnected), or connected through a crystal
to XTALOUT. Refer to the schematic on page 73.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
5.1.3. Configuration/Programming Pins
Pin Name
Pin #
Strength
Type
Dir
Description
INT
22
4 mA
LVTTL
Out
Interrupt Output. Configurable polarity and push-pull
output. Multiple sources of interrupt can be enabled
through the INT_EN register.
See Note 1.
RESET#
21
—
Schmitt
In
Reset Pin. Active LOW. 5-V tolerant
CSCL
23
—
Schmitt
In
Configuration/Status I C Clock. 5-V tolerant. Chip
configuration/status, CEA-861 support and
downstream HDCP repeater-specific registers are
2
accessed via this I C port. True open drain, so does
not pull to GND if power is not applied.
CSDA
24
3 mA
Schmitt
Bi-Di
Configuration/Status I C Data. 5-V tolerant. Chip
configuration/status, CEA-861 support and
downstream HDCP repeater-specific registers are
2
accessed via this I C port. True open drain, so does
not pull to GND if power is not applied.
CI2CA
25
—
LVTTL
In
Local I C Address Select. 5-V tolerant
Low = Addresses 0x60/0x68
High = Addresses 0x62/0x6A
GPIO1/SCDT
13
4 mA
LVTTL
Out
Programmable GPIO1 or SCDT. Indicates Active Video
at HDMI Input Port. Sync detection indicator.
GPIO4
16
4 mA
LVTTL
Bi-Di
Programmable GPIO4
GPIO5
17
4 mA
LVTTL
Bi-Di
Programmable GPIO5
RSVDNC
1, 9, 10, 15, 18,
46–49
—
—
—
Reserved, must be left unconnected
RSVDL
11
—
—
In
Reserved, must be tied to ground
2
2
2
Note: The INT pin can be programmed to be either a push-pull LVTTL output or an open-drain output.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
39
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
5.1.4. HDMI Control Signal Pins
Pin Name
Pin #
Strength
Type
Dir
Description
DSCL0
DSCL1
DSCL2
DSCL3
31
35
39
43
—
SchmittOD
In
DDC I2C Clock for respective port. 5-V tolerant.
HDCP KSV, An and Ri values are exchanged over an
I2C port during authentication. True open drain, so
does not pull to GND if power is not applied.
DSDA0
DSDA1
DSDA2
DSDA3
32
36
40
44
3 mA
SchmittOD
Bi-Di
DDC I2C Data for respective port. 5-V tolerant.
HDCP KSV, An and Ri values are exchanged over an
I2C during authentication. True open drain, so does
not pull to GND if power is not applied.
HPD0
HPD1
HPD2
HPD3
30
34
38
42
4 mA
LVTTL
Out
Hotplug output signal to HDMI connector for
respective port. Indicates EDID is readable. See the
Hot Plug Detect CTS Requirement section for
important information.
R0PWR5V
R1PWR5V
R2PWR5V
R3PWR5V
29
33
37
41
—
LVTTL
In
5V power and port detection input for respective
port. 5-V tolerant. Used to power internal EDID
when device is not powered. See Note 1,2
CEC_A
26
—
CEC compliant
5-V tolerant
Bi-Di
HDMI compliant CEC I/O used to interface to CEC
devices. This pin connects to the CEC signal of all
HDMI connectors in the system.
This pin has an internal pull-up resistor.
CEC_D
27
—
LVTTL
Schmitt
Bi-Di
CEC interface to local system. True open-drain. An
external pull-up is required. This pin typically
connects to the local CPU.
RSVDCEC
45
—
—
—
Reserved
Note:
1.
2.
There is no power sequence requirement on RxPWR5V pins.
The operation condition of the RxPWR5V pins is 5 V ±5%.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
5.1.5. Differential Signal Data Pins
Pin Name
Pin #
Type
Description
R0XC+
110
Analog
TMDS Input Clock Pair.
R0XC-
109
R0X0+
112
Analog
TMDS Input Data Pairs.
R0X0-
111
R0X1+
114
R0X1-
113
R0X2+
116
R0X2-
115
R1XC+
119
Analog
TMDS Input Clock Pair.
R1XC-
118
R1X0+
121
Analog
TMDS Input Data Pairs.
R1X0-
120
R1X1+
123
R1X1-
122
R1X2+
125
R1X2-
124
R2XC+
128
Analog
TMDS Input Clock Pair.
R2XC-
127
R2X0+
130
Analog
TMDS Input Data Pairs.
R2X0-
129
R2X1+
132
R2X1-
131
R2X2+
134
R2X2-
133
R3XC+
137
Analog
TMDS Input Clock Pair.
R3XC-
136
R3X0+
139
Analog
TMDS Input Data Pairs.
R3X0-
138
R3X1+
141
R3X1-
140
R3X2+
143
R3X2-
142
HDMI Port 0
HDMI Port 1
HDMI Port 2
HDMI Port 3
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
41
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
5.1.6. Power and Ground Pins
Pin Name
Pin #
Type
Description
Supply
CVCC12
IOVCC33
8, 60, 71, 86, 97
7, 61, 72, 87, 98
Power
Power
Digital Logic VCC
Input/Output Pin VCC
1.2 V
3.3 V
AVCC33
AVCC12
APVCC12
108, 126, 144
117, 135
2
Power
Power
Power
TMDS Analog VCC 3.3V
TMDS Analog VCC 1.2V
Audio Clock Regeneration PLL Analog
VCC. Must be connected to 1.2V
3.3 V
1.2 V
1.2 V
XTALVCC33
3
Power
Audio Clock Regeneration PLL Crystal
3.3 V
Oscillator Power. Must be connected to
3.3V
XTALGND
6
Ground
28
Power
Audio Clock Regeneration ground
Standby power supply. All other
supplies can be off with SBVCC5 on
Ground
SBVCC5
GND
50, ePad (bottom of package)
Ground
ePad must be soldered to ground
Ground
5V
VCCTP
Parasitic
Resistor
Ferrite
AVCC12
0.56 
0.1 F
0. 82 H,
150 mA
+
10 F
0.1 F
1 nF
SiI9233
GND
Figure 5.2. Test Point VCCTP for VCC Noise Tolerance Spec
Notes:
1. The Ferrite (0.82 H, 150 mA) attenuates the PLL power supply noise at 10’s of KHz and above.
The optional parasitic resistor minimizes the peaking. The typical value used here is 0.56 . 1 is the maximum
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6. Video Path
The SiI9233 receiver accepts all valid HDMI input formats and can transform that video in a variety of ways to produce
the proper video output format. The following pages describe how to control the video path formatting and how to
assign output pins for each video output format.
MCLK
SPDIF
Audio
Processing
TMDS
I2S Outputs
HDCP
WS
Widen to
14-Bits
InfoFrame
Packet
Processing
SD[3:0]
DSD Outputs
YCbCr
Range
Reduce
Down
Sample
4:4:4 to
4:2:2
bypass
bypass
bypass
Upsample
4:2:2 to
4:4:4
xvYCC/
YCbCr to
RGB
RGB
Range
Expand
RGB to
YCbCr
bypass
SCK
bypass
Note: DSD outputs are
shared with SPDIF and
I2S signals
DCLK
DR[3:0]
DL[3:0]
DE
Dither
Module
Mux
656
Video
Timing
HSYNC
bypass
VSYNC
ODCK
Q[35:0]
Figure 6.1. Receiver Video and Audio Data Processing Paths
The processing blocks in the figure above correspond to those shown in Figure 6.2 through Figure 6.4.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
43
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.1.
HDMI Input Modes to SiI9233 Receiver Output Modes
The HDMI link supports transport of video in any of three modes: RGB 4:4:4, YCbCr 4:4:4 or YCbCr 4:2:2. The flexible
video path in the SiI9233 allows reformatting of video data to a set of output modes. Table 6.1 lists the supported
transformations and points to the figure for each. In every case, the HDMI link itself carries separate syncs.
Table 6.1. Translating HDMI Formats to Output Formats
Output Format
Digital
HDMI Input
Mode
Output
Syncs
RGB 4:4:4
YCbCr
4:4:4
YCbCr
4:2:2
RGB 4:4:4
Separate
YCbCr 4:4:4
Separate
YCbCr 4:2:2
Separate
YCbCr 4:2:2
Embedded
YC Mux
Separate
YC Mux
Embedded
Figure 6.2A
Figure 6.3A
Figure 6.2B
Figure 6.3B
Figure 6.2C
Figure 6.3C
Figure 6.2D
Figure 6.3D
Figure 6.2E
Figure 6.3E
Figure 6.2F
Figure 6.3F
Figure 6.4A
Figure 6.4B
Figure 6.4C
Figure 6.4D
Figure 6.4E
Figure 6.4F
Note
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
RGB 4:4:4
TMDS and
HDCP
Decoding
RGBtoYCbCr
RGB 4:4:4
TMDS and
HDCP
Decoding
RGBtoYCbCr
Color Range
Scaling
DownSampling
RGB 4:4:4
TMDS and
HDCP
Decoding
RGBtoYCbCr
Color Range
Scaling
DownSampling
Embedded
Syncs
YCbCr 4:2:2
Emb. Syncs
RGB 4:4:4
TMDS and
HDCP
Decoding
RGBtoYCbCr
Color Range
Scaling
DownSampling
MUX YC
MUX YC 4:2:2
Separate Syncs
TMDS and
HDCP
Decoding
Color Range
Scaling
Down
Sampling
Embedded
Syncs
YCbCr 4:2:2
Separate Syncs
Color Range
Scaling
MUX YC
MUX YC 4:2:2
Emb. Syncs
RGBtoYCbCr
YCbCr 4:4:4
Separate Syncs
RGB 4:4:4
TMDS and
HDCP
Decoding
RGB 4:4:4
RGB 4:4:4
6.1.1. HDMI RGB 4:4:4 Input Processing
Digital Out
A
Digital Out
B
Digital Out
C
Digital Out
D
Digital Out
E
Digital Out
F
Figure 6.2. HDMI RGB 4:4:4 Input to Video Output Transformations
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
45
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
DownSampling
Embedded
Syncs
MUX YC
MUX YC
RGB 4:4:4
TMDS and
HDCP
Decoding
DownSampling
Embedded
Syncs
YCbCr 4:4:4
YCbCr 4:4:4
TMDS and
HDCP
Decoding
DownSampling
YCbCr 4:2:2
YCbCr 4:4:4
TMDS and
HDCP
Decoding
DownSampling
Digital Out
YCbCr 4:2:2
Emb. Syncs
YCbCr 4:4:4
TMDS and
HDCP
Decoding
Digital Out
Digital Out
MUX YC 4:2:2
YCbCr 4:4:4
TMDS and
HDCP
Decoding
YCbCr to RGB
Digital Out
MUX YC 4:2:2
Emb. Syncs
YCbCr 4:4:4
TMDS and
HDCP
Decoding
YCbCr 4:4:4
6.1.2. HDMI YCbCr 4:4:4 Input Processing
A
B
C
D
Digital Out
E
Digital Out
F
Figure 6.3. HDMI YCbCr 4:4:4 Input to Video Output Transformations
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Embedded
Syncs
RGB 4:4:4
TMDS and
HDCP
Decoding
YCbCr 4:4:4
YCbCr 4:2:2
TMDS and
HDCP
Decoding
Embedded
Syncs
Digital Out
YCbCr 4:2:2
YCbCr 4:2:2
TMDS and
HDCP
Decoding
UpSampling
Digital Out
YCbCr 4:2:2
Emb. Syncs
YCbCr 4:2:2
TMDS and
HDCP
Decoding
YCbCr to RGB
Digital Out
MUX YC
MUX YC 4:2:2
YCbCr 4:2:2
TMDS and
HDCP
Decoding
Upsampling
Digital Out
MUX YC
MUX YC 4:2:2
Emb. Syncs
YCbCr 4:2:2
TMDS and
HDCP
Decoding
YCbCr 4:2:2
6.1.3. HDMI YCbCr 4:2:2 Input Processing
A
B
C
D
Digital Out
E
Digital Out
F
Figure 6.4. HDMI YCbCr 4:2:2 Input to Video Output Transformations
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
47
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.2.
SiI9233 Receiver Output Mode Configuration
The SiI9233 receiver supports multiple output data mappings. Some have separate control signals while some have
embedded control signals. The selection of data mapping mode should be consistent at the pins and in the
corresponding register settings. Refer to the SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019)
for more details.
Table 6.2. Output Video Formats
Output Mode
Data Widths
Pixel Replication
Syncs
Page
Notes
RGB 4:4:4
24, 30, 36
1x
Separate
49
3, 7
YCbCr 4:4:4
24, 30, 36
1x
Separate
49
1. 3. 7
YC 4:2:2 Sep. Syncs
16, 20, 24
1x
Separate
51
2, 3
YC 4:2:2 Sep. Syncs
16, 20, 24
2x
Separate
51
2, 3, 8
YC 4:2:2 Emb. Syncs
16, 20, 24
1x
Embedded
54
2, 5
YC MUX 4:2:2
8, 10, 12
2x
Separate
57
2, 4, 8
YC MUX 4:2:2 Emb. Syncs
8, 10, 12
2x
Embedded
59
2, 5, 6, 8, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
YC 4:4:4 data contains one Cr, one Cb and one Y value for every pixel.
YC 4:2:2 data contains one Cr and one Cb value for every two pixels; and one Y value for every pixel.
These formats can be carried across the HDMI link. Refer to the HDMI Specification, Section 6.2.3. The link clock must be
within the specified range of the SiI9233 receiver.
In YC MUX mode data is sent to one or two 8/10/12-bit channels.
YC MUX with embedded SAV/EAV signal.
Syncs are embedded using SAV/EAV codes.
A 2x clock can also be sent with 4:4:4 data.
When sending a 2x clock the HDMI source must also send AVI InfoFrames with an accurate pixel replication
field. Refer to HDMI Spec 1.0, Section 6.4.
2x clocking does not support YC 4:2:2 embedded Sync timings for 720p or 1080i, as the output clock frequency would
exceed the range allowed for the SiI9233 receiver.
The SiI9233 receiver can output video in various formats on its parallel digital output bus. Some transformation of the
data received over HDMI is necessary in some modes. Digital output is used with either 4:4:4 or 4:2:2 data.
The diagrams do not include separation of the audio and InfoFrame packets from the HDMI stream, which occurs
immediately after the TMDS and (optional) HDCP decoding. The HDMI link always carries separate HSYNC and VSYNC
and DE. Therefore the SAV/EAV sync encoder must be used whenever the output mode includes embedded sync.
The timing diagrams in Figure 6.5 through Figure 6.9 show only a representation of the DE, HSYNC and VSYNC timings.
These timings are specific to the video resolution, as defined by EIA/CEA-861B and other specs. The number of pixels
shown per DE HIGH time is representative, to show the data formatting.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.2.1. RGB and YCbCr 4:4:4 Formats with Separate Syncs
The pixel clock runs at the pixel rate and a complete definition of each pixel is output on each clock. Figure 6.5 shows
RGB data. The same timing format is used for YCbCr 4:4:4 as listed in Table 6.3. Figure 6.5 shows timings with OCLKDIV
= 0 and OCKINV = 1.
Table 6.3. 4:4:4 Mappings
Pin
36-bit
36-bit
30-bit
30-bit
24-bit
24-bit
Name
Q0
RGB
B0
YCbCr
Cb0
RGB
NC
YCbCr
NC
RGB
NC
YCbCr
NC
Q1
Q2
Q3
B1
B2
B3
Cb1
Cb2
Cb3
NC
B0
B1
NC
Cb0
Cb1
NC
NC
NC
NC
NC
NC
Q4
Q5
B4
B5
Cb4
Cb5
B2
B3
Cb2
Cb3
B0
B1
Cb0
Cb1
Q6
Q7
Q8
B6
B7
B8
Cb6
Cb7
Cb8
B4
B5
B6
Cb4
Cb5
Cb6
B2
B3
B4
Cb2
Cb3
Cb4
Q9
Q10
Q11
B9
B10
B11
Cb9
Cb10
Cb11
B7
B8
B9
Cb7
Cb8
Cb9
B5
B6
B7
Cb5
Cb6
Cb7
Q12
Q13
G0
G1
Y0
Y1
NC
NC
NC
NC
NC
NC
NC
NC
Q14
Q15
Q16
G2
G3
G4
Y2
Y3
Y4
G0
G1
G2
Y0
Y1
Y2
NC
NC
G0
NC
NC
Y0
Q17
Q18
G5
G6
Y5
Y6
G3
G4
Y3
Y4
G1
G2
Y1
Y2
Q19
Q20
Q21
G7
G8
G9
Y7
Y8
Y9
G5
G6
G7
Y5
Y6
Y7
G3
G4
G5
Y3
Y4
Y5
Q22
Q23
G10
G11
Y10
Y11
G8
G9
Y8
Y9
G6
G7
Y6
Y7
Q24
Q25
Q26
R0
R1
R2
Cr0
Cr1
Cr2
NC
NC
R0
NC
NC
Cr0
NC
NC
NC
NC
NC
NC
Q27
Q28
Q29
R3
R4
R5
Cr3
Cr4
Cr5
R1
R2
R3
Cr1
Cr2
Cr3
NC
R0
R1
NC
Cr0
Cr1
Q30
Q31
R6
R7
Cr6
Cr7
R4
R5
Cr4
Cr5
R2
R3
Cr2
Cr3
Q32
Q33
Q34
R8
R9
R10
Cr8
Cr9
Cr10
R6
R7
R8
Cr6
Cr7
Cr8
R4
R5
R6
Cr4
Cr5
Cr6
Q35
R11
Cr11
R9
Cr9
R7
Cr7
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
49
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel n
blank
blank
blank
Q[35:24]
val
R0
R1
R2
R3
R4
Rn
val
val
val
Q[23:12]
val
G0
G1
G2
G3
G4
Gn
val
val
val
Q[11:0]
val
B0
B1
B2
B3
B4
Bn
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 6.5. 4:4:4 Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the
appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.2.2. YC 4:2:2 Formats with Separate Syncs
The YC 4:2:2 formats output one pixel for every pixel clock period. A luminance (Y) value is sent for every pixel, but the
chrominance values (Cb and Cr) are sent over two pixels. Pixel data can be 24-bit, 20-bit or 16-bit. HSYNC and VSYNC
are output separately on their own pins. The DE HIGH time must contain an even number of pixel clocks. Figure 6.6
shows timings with OCLKDIV = 0 and OCKINV = 1.
Table 6.4. YC 4:2:2 Separate Sync Pin Mappings
Pin
Name
16-bit YC
Pixel #0
Pixel #1
20-bit YC
Pixel #0
Pixel #1
24-bit YC
Pixel #0
Q0
Q1
Q2
NC
NC
NC
NC
NC
NC
NC
NC
NC
Pixel #1
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q3
Q4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q5
Q6
Q7
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q8
Q9
Q10
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q11
Q12
NC
NC
NC
NC
NC
NC
NC
NC
NC
Y0
NC
Y0
Q13
Q14
Q15
NC
NC
NC
NC
NC
NC
NC
Y0
Y1
NC
Y0
Y1
Y1
Y2
Y3
Y1
Y2
Y3
Q16
Q17
Y0
Y1
Y0
Y1
Y2
Y3
Y2
Y3
Y4
Y5
Y4
Y5
Q18
Q19
Q20
Y2
Y3
Y4
Y2
Y3
Y4
Y4
Y5
Y6
Y4
Y5
Y6
Y6
Y7
Y8
Y6
Y7
Y8
Q21
Q22
Y5
Y6
Y5
Y6
Y7
Y8
Y7
Y8
Y9
Y10
Y9
Y10
Q23
Q24
Q25
Y7
NC
NC
Y7
NC
NC
Y9
NC
NC
Y9
NC
NC
Y11
Cb0
Cb1
Y11
Cr0
Cr1
Q26
Q27
Q28
NC
NC
Cb0
NC
NC
Cr0
Cb0
Cb1
Cb2
Cr0
Cr1
Cr2
Cb2
Cb3
Cb4
Cr2
Cr3
Cr4
Q29
Q30
Cb1
Cb2
Cr1
Cr2
Cb3
Cb4
Cr3
Cr4
Cb5
Cb6
Cr5
Cr6
Q31
Q32
Q33
Cb3
Cb4
Cb5
Cr3
Cr4
Cr5
Cb5
Cb6
Cb7
Cr5
Cr6
Cr7
Cb7
Cb8
Cb9
Cr7
Cr8
Cr9
Q34
Q35
Cb6
Cb7
Cr6
Cr7
Cb8
Cb9
Cr8
Cr9
Cb10
Cb11
Cr10
Cr11
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
51
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Table 6.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping
Pin
16-bit YC
20-bit YC
24-bit YC
Name
Q0
Q1
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Q2
Q3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q4
Q5
Q6
NC
NC
NC
NC
NC
NC
NC
NC
Y0
NC
NC
Y0
Y0
Y1
Y2
Y0
Y1
Y2
Q7
Q8
Q9
NC
NC
NC
NC
NC
NC
Y1
NC
NC
Y1
NC
NC
Y3
Cb0
Cb1
Y3
Cr0
Cr1
Q10
Q11
NC
NC
NC
NC
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Q12
Q13
Q14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q15
Q16
NC
Y0
NC
Y0
NC
Y2
NC
Y2
NC
Y4
NC
Y4
Q17
Q18
Q19
Y1
Y2
Y3
Y1
Y2
Y3
Y3
Y4
Y5
Y3
Y4
Y5
Y5
Y6
Y7
Y5
Y6
Y7
Q20
Q21
Q22
Y4
Y5
Y6
Y4
Y5
Y6
Y6
Y7
Y8
Y6
Y7
Y8
Y8
Y9
Y10
Y8
Y9
Y10
Q23
Q24
Y7
NC
Y7
NC
Y9
NC
Y9
NC
Y11
NC
Y11
NC
Q25
Q26
Q27
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q28
Q29
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Cb4
Cb5
Cr4
Cr5
Q30
Q31
Q32
Cb2
Cb3
Cb4
Cr2
Cr3
Cr4
Cb4
Cb5
Cb6
Cr4
Cr5
Cr6
Cb6
Cb7
Cb8
Cr6
Cr7
Cr8
Q33
Q34
Cb5
Cb6
Cr5
Cr6
Cb7
Cb8
Cr7
Cr8
Cb9
Cb10
Cr9
Cr10
Q35
Cb7
Cr7
Cb9
Cr9
Cb11
Cr11
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
DE
DE
DE
DE
DE
DE
Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video
format is YC 4:2:2 also. No video processing block should be enabled when this
pin mapping is used.
DE
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
blank
Pixel0
Pixel1
Pixel2
Pixel3 Pixel n-1
Q[35:28]
val
Cb0[11:4]
Cr0[11:4]
Cb2[11:4]
Cr2[11:4]
Cbn-1[11:4]
Q[23:16]
val
Y0[11:4]
Y1[11:4]
Y2[11:4]
Y3[11:4]
Yn-1[11:4]
Q[27:24]
val
Cb0[3:0]
Cr0[3:0]
Cb2[3:0]
Cr2[3:0]
Cbn-1[3:0]
Q[15:12]
val
Y0[3:0]
Y1[3:0]
Y2[3:0]
Y3[3:0]
Yn-1[3:0]
Pixel n
Crn-1[11:4]
val
val
Yn[11:4]
val
val
Crn-1 [3:0]
val
val
Yn[3:0]
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 6.6. YC Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the
appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
53
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.2.3. YC 4:2:2 Formats with Embedded Syncs
The YC 4:2:2 embedded sync format is identical to the previous format (YC 4:2:2), except that the syncs are embedded and
not separate. Pixel data can be 24-bit, 20-bit or 16-bit. DE is always output. Figure 6.7 shows the Start of Active Video
(SAV) preamble, the End of Active Video” (EAV) suffix, and shows timings with OCLKDIV = 0 and OCKINV = 1.
Table 6.6. YC 4:2:2 Embedded Sync Pin Mappings
Pin
16-bit YC
20-bit YC
24-bit YC
Name
Q0
Q1
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Q2
Q3
Q4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q5
Q6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q7
Q8
Q9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q10
Q11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q12
Q13
Q14
NC
NC
NC
NC
NC
NC
NC
NC
Y0
NC
NC
Y0
Y0
Y1
Y2
Y0
Y1
Y2
Q15
Q16
Q17
NC
Y0
Y1
NC
Y0
Y1
Y1
Y2
Y3
Y1
Y2
Y3
Y3
Y4
Y5
Y3
Y4
Y5
Q18
Q19
Y2
Y3
Y2
Y3
Y4
Y5
Y4
Y5
Y6
Y7
Y6
Y7
Q20
Q21
Q22
Y4
Y5
Y6
Y4
Y5
Y6
Y6
Y7
Y8
Y6
Y7
Y8
Y8
Y9
Y10
Y8
Y9
Y10
Q23
Q24
Y7
NC
Y7
NC
Y9
NC
Y9
NC
Y11
Cb0
Y11
Cr0
Q25
Q26
Q27
NC
NC
NC
NC
NC
NC
NC
Cb0
Cb1
NC
Cr0
Cr1
Cb1
Cb2
Cb3
Cr1
Cr2
Cr3
Q28
Q29
Q30
Cb0
Cb1
Cb2
Cr0
Cr1
Cr2
Cb2
Cb3
Cb4
Cr2
Cr3
Cr4
Cb4
Cb5
Cb6
Cr4
Cr5
Cr6
Q31
Q32
Cb3
Cb4
Cr3
Cr4
Cb5
Cb6
Cr5
Cr6
Cb7
Cb8
Cr7
Cr8
Q33
Q34
Q35
Cb5
Cb6
Cb7
Cr5
Cr6
Cr7
Cb7
Cb8
Cb9
Cr7
Cr8
Cr9
Cb9
Cb10
Cb11
Cr9
Cr10
Cr11
HSYNC
VSYNC
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
54
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Table 6.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping
Pin
16-bit YC
20-bit YC
24-bit YC
Name
Q0
Q1
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Q2
Q3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q4
Q5
Q6
NC
NC
NC
NC
NC
NC
NC
NC
Y0
NC
NC
Y0
Y0
Y1
Y2
Y0
Y1
Y2
Q7
Q8
Q9
NC
NC
NC
NC
NC
NC
Y1
NC
NC
Y1
NC
NC
Y3
Cb0
Cb1
Y3
Cr0
Cr1
Q10
Q11
NC
NC
NC
NC
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Q12
Q13
Q14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q15
Q16
NC
Y0
NC
Y0
NC
Y2
NC
Y2
NC
Y4
NC
Y4
Q17
Q18
Q19
Y1
Y2
Y3
Y1
Y2
Y3
Y3
Y4
Y5
Y3
Y4
Y5
Y5
Y6
Y7
Y5
Y6
Y7
Q20
Q21
Q22
Y4
Y5
Y6
Y4
Y5
Y6
Y6
Y7
Y8
Y6
Y7
Y8
Y8
Y9
Y10
Y8
Y9
Y10
Q23
Q24
Y7
NC
Y7
NC
Y9
NC
Y9
NC
Y11
NC
Y11
NC
Q25
Q26
Q27
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q28
Q29
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Cb4
Cb5
Cr4
Cr5
Q30
Q31
Q32
Cb2
Cb3
Cb4
Cr2
Cr3
Cr4
Cb4
Cb5
Cb6
Cr4
Cr5
Cr6
Cb6
Cb7
Cb8
Cr6
Cr7
Cr8
Q33
Q34
Cb5
Cb6
Cr5
Cr6
Cb7
Cb8
Cr7
Cr8
Cb9
Cb10
Cr9
Cr10
Q35
Cb7
Cr7
Cb9
Cr9
Cb11
Cr11
HSYNC
VSYNC
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video
format is YC 4:2:2 also. No video processing block should be enabled when this
pin mapping is used.
Embedded
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
55
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
SAV
Pixel0
Pixel1
Pixel2
Pixel3
Pixel n-1
Q[35:28]
val
FF
00
00
XY
Cb0[11:4]
Cr0[11:4]
Cb2[11:4]
Cr2[11:4]
Q[23:16]
val
FF
00
00
XY
Y0[11:4]
Y1[11:4]
Y2[11:4]
Y3[11:4]
Yn-1[11:4]
Q[27:24]
val
X
X
X
X
Cb0[3:0]
Cr0[3:0]
Cb2[3:0]
Cr2[3:0]
Q[15:12]
val
X
X
X
X
Y0[3:0]
Y1[3:0]
Y2[3:0]
Y3[3:0]
EAV
Pixel n
Cbn-1[11:4] Crn-1[11:4]
FF
00
00
XY
val
Yn[11:4]
FF
00
00
XY
val
Cbn-1[3:0]
Crn-1[3:0]
X
X
X
X
val
Yn-1[3:0]
Yn[3:0]
X
X
X
X
val
ODCK
Active
Video
Figure 6.7. YC 4:2:2 Embedded Sync Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the
appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking. SAV/EAV codes appear as an 8bit field on both Q[35:28] (per SMPTE) and Q[23:16].
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
56
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.2.4. YC Mux (4:2:2) Formats with Separate Syncs
The video data is multiplexed onto fewer pins than the mapping in Table 6.8, but complete luminance (Y) and
chrominance (Cb and Cr) data is still provided for each pixel because the output pixel clock runs at twice the pixel rate.
Figure 6.8 shows the 24-bit mode. The 16- and 20-bit mappings use fewer output pins for the pixel data. Note the
separate syncs. Figure 6.8 shows OCLKDIV = 0 and OCKINV = 1.
Table 6.8. YC Mux 4:2:2 Mappings
Pin
Name
8-bit
YCbCr
10-bit
YCbCr
12-bit
YCbCr
Q0
Q1
Q2
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q3
Q4
NC
NC
NC
NC
NC
NC
Q5
Q6
Q7
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q8
Q9
Q10
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q11
Q12
NC
NC
NC
NC
NC
D0
Q13
Q14
Q15
NC
NC
NC
NC
D0
D1
D1
D2
D3
Q16
Q17
D0
D1
D2
D3
D4
D5
Q18
Q19
Q20
D2
D3
D4
D4
D5
D6
D6
D7
D8
Q21
Q22
D5
D6
D7
D8
D9
D10
Q23
Q24
Q25
D7
NC
NC
D9
NC
NC
D11
NC
NC
Q26
Q27
Q28
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q29
Q30
NC
NC
NC
NC
NC
NC
Q31
Q32
Q33
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q34
Q35
NC
NC
NC
NC
NC
NC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
57
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Pixel0
Pixel1
Pixel2
Pixel3
Q[35:24]
Q[11:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
Q[23:16]
val
val
val
val
val
Cb0[11:4]
Y0[11:4]
Cr0[11:4]
Y1[11:4]
Cb2[11:4]
Y2[11:4]
Cr2[11:4]
Y3[11:4]
Q[15:12]
val
val
val
val
val
Cb0[3:0]
Y0[3:0]
Cr0[3:0]
Y1[3:0]
Cb2[3:0]
Y2[3:0]
Cr2[3:0]
Y3[3:0]
ODCK
DE
HSYNC
VSYNC
Figure 6.8. YC Mux 4:2:2 Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the
appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
58
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.2.5. YC Mux 4:2:2 Formats with Embedded Syncs
This mode is similar to that on page 57, but with embedded syncs. It is similar to YC 4:2:2 with embedded syncs, but
also multiplexes the luminance (Y) and chrominance (Cb and Cr) onto the same pins on alternating pixel clock cycles.
Normally this mode is used only for 480i, 480p, 576i and 576p modes. Output clock rate is half the pixel clock rate on
the link. SAV code is shown before rise of DE. EAV follows the falling edge of DE. See the ITU-R BT.656 Specification.
480p, 54-MHz output can be achieved if the input differential clock is 54 MHz. Figure 6.9 shows OCLKDIV = 0 and
OCKINV = 1.
Table 6.9. YC Mux 4:2:2 Embedded Sync Pin Mapping
Pin
Name
Q0
8-bit
YCbCr
NC
10-bit
YCbCr
NC
12-bit
YCbCr
NC
Q1
Q2
NC
NC
NC
NC
NC
NC
Q3
Q4
Q5
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q6
Q7
NC
NC
NC
NC
NC
NC
Q8
Q9
Q10
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q11
Q12
Q13
NC
NC
NC
NC
NC
NC
NC
D0
D1
Q14
Q15
NC
NC
D0
D1
D2
D3
Q16
Q17
Q18
D0
D1
D2
D2
D3
D4
D4
D5
D6
Q19
Q20
D3
D4
D5
D6
D7
D8
Q21
Q22
Q23
D5
D6
D7
D7
D8
D9
D9
D10
D11
Q24
Q25
Q26
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q27
Q28
NC
NC
NC
NC
NC
NC
Q29
Q30
Q31
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q32
Q33
NC
NC
NC
NC
NC
NC
Q34
Q35
HSYNC
NC
NC
Embedded
NC
NC
Embedded
NC
NC
Embedded
VSYNC
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
59
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Pixel0
SAV
Pixel1
Pixel2
Pixel3
Q[35:24]
val
X
X
X
X
X
X
X
X
X
X
X
X
Q[23:16]
val
FF
00
00
XY
Cb0[ 11:4]
Y0[11:4]
Cr0[11:4]
Y1[11:4]
Cb2[11:4]
Y2[11:4]
Cr2[11:4]
Y3[11:4]
Q[15:12]
val
X
X
X
X
Cb0[3:0]
Y0[3:0]
Cr0[3:0]
Y1[3:0]
Cb2[3:0]
Y2[3:0]
Cr2[3:0]
Y3[3:0]
Q[11:0]
ODCK
Active
Video
Figure 6.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the
appropriate SiI9233 registers, because no pixel data is carried on HDMI during blanking. Refer to the
SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for details.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
60
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
6.2.6. 12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs
The output clock runs at the pixel rate and a complete definition of each pixel is output on each clock. One clock edge
drives out half the pixel data on 12/15/18 pins. The opposite clock edge drives out the remaining half of the pixel data
on the same 12/15/18 pins. Figure 6.10 shows RGB data. The same timing format is used for YCbCr 4:4:4 as listed in the
columns of Table 6.10. Control signals (DE, HSYNC and VSYNC) change state with respect to the first edge of ODCK.
Table 6.10. 12/15/18-Bit Output 4:4:4 Mappings
24-bit
30-bit
YCbCr
36-bit
Pin
RGB
Name
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
Q0
Q1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B0
B1
G6
G7
Cb0
Cb1
Y6
Y7
Q2
Q3
NC
NC
NC
NC
NC
NC
NC
NC
NC
B0
NC
G5
NC
Cb0
NC
Y5
B2
B3
G8
G9
Cb2
Cb3
Y8
Y9
Q4
Q5
Q6
NC
NC
B0
NC
NC
G4
NC
NC
Cb0
NC
NC
Y4
B1
B2
B3
G6
G7
G8
Cb1
Cb2
Cb3
Y6
Y7
Y8
B4
B5
B6
G10
G11
R0
Cb4
Cb5
Cb6
Y10
Y11
Cr0
Q7
Q8
B1
B2
G5
G6
Cb1
Cb2
Y5
Y6
B4
B5
G9
R0
Cb4
Cb5
Y9
Cr0
B7
B8
R1
R2
Cb7
Cb8
Cr1
Cr2
Q9
Q10
Q11
B3
B4
B5
G7
R0
R1
Cb3
Cb4
Cb5
Y7
Cr0
Cr1
B6
B7
B8
R1
R2
R3
Cb6
Cb7
Cb8
Cr1
Cr2
Cr3
B9
B10
B11
R3
R4
R5
Cb9
Cb10
Cb11
Cr3
Cr4
Cr5
Q12
Q13
B6
B7
R2
R3
Cb6
Cb7
Cr2
Cr3
B9
G0
R4
R5
Cb9
Y0
Cr4
Cr5
G0
G1
R6
R7
Y0
Y1
Cr6
Cr7
Q14
Q15
Q16
G0
G1
G2
R4
R5
R6
Y0
Y1
Y2
Cr4
Cr5
Cr6
G1
G2
G3
R6
R7
R8
Y1
Y2
Y3
Cr6
Cr7
Cr8
G2
G3
G4
R8
R9
R10
Y2
Y3
Y4
Cr8
Cr9
Cr10
Q17
G3
R7
Y3
Cr7
G4
R9
Y4
Cr9
G5
R11
Y5
Cr11
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
DE
blank
Pixel 0
RGB
Pixel 1
YCbCr
Pixel 2
RGB
Pixel 3
YCbCr
blank
blank
blank
Q[17:12]
val
G0[5:0]
R0[11:6]
G1[5:0]
R1[11:6]
G2[5:0]
R2[11:6]
G3[5:0]
R3[11:6]
val
val
val
val
val
val
Q[11:6]
val
B0[11:6]
R0[5:0]
B1[11:6]
R1[5:0]
B2[11:6]
R2[5:0]
B3[11:6]
R3[5:0]
val
val
val
val
val
val
Q[5:0]
val
B0[5:0]
G0[11:6]
B1[5:0]
G1[11:6]
B2[5:0]
G2[11:6]
B3[5:0]
G3[11:6]
val
val
val
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 6.10. 18-Bit Output 4:4:4 Timing Diagram
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
61
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
blank
blank
blank
Q[17:13]
val
G0[4:0]
R0[9:5]
G1[4:0]
R1[9:5]
G2[4:0]
R2[9:5]
G3[4:0]
R3[9:5]
val
val
val
val
val
val
Q[12:8]
val
B0[9:5]
R0[4:0]
B1[9:5]
R1[4:0]
B2[9:5]
R2[4:0]
B3[9:5]
R3[4:0]
val
val
val
val
val
val
Q[7:3]
val
B0[4:0]
G0[9:5]
B1[4:0]
G1[9:5]
B2[4:0]
G2[9:5]
B3[4:0]
G3[9:5]
val
val
val
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 6.11. 15-Bit Output 4:4:4 Timing Diagram
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
blank
blank
blank
Q[17:14]
val
G0[3:0]
R0[7:4]
G1[3:0]
R1[7:4]
G2[3:0]
R2[7:4]
G3[3:0]
R3[7:4]
val
val
val
val
val
val
Q[13:10]
val
B0[7:4]
R0[3:0]
B1[7:4]
R1[3:0]
B2[7:4]
R2[3:0]
B3[7:4]
R3[3:0]
val
val
val
val
val
val
Q[9:6]
val
B0[3:0]
G0[7:4]
B1[3:0]
G1[7:4]
B2[3:0]
G2[7:4]
B3[3:0]
G3[7:4]
val
val
val
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 6.12. 12-Bit Output 4:4:4 Timing Diagram
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
62
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
7. I2C Interfaces
7.1.
HDCP E-DDC / I2C Interface
Stop
S
Register Address
Slave Address
S
P
A
C
K
A
C
K
A
C
K
Data
Data
Stop
DSDA Line
Slave Address
Start
Bus Activity :
Master
Start
The HDCP protocol requires values to be exchanged between the video transmitter and video receiver. These values
2
are exchanged over the DDC channel of the DVI interface. The E-DDC channel follows the I C serial protocol. In a system
design using an SiI9233 receiver, the SiI9233 device is the video Receiver and has a connection to the E-DDC bus with a
2
slave address of 0x74 The I C read operation is shown in Figure 7.1, and the write operation in Figure 7.2.
No
A
C
K
2
Bus Activity :
Master
Start
Figure 7.1. I C Byte Read
DSDA Line
S
Slave Address
Register Address
P
A
C
K
A
C
K
A
C
K
2
Figure 7.2. I C Byte Write
Multiple bytes can be transferred in each transaction, regardless of whether they are reads or writes. The operations
are similar to those in Figure 7.1 and Figure 7.2 except that there is more than one data phase. An ACK follow each byte
except the last byte in a read operation. Byte addresses increment, with the least significant byte transferred first, and
2
the most significant byte last. See the I C specification for more information.
DSDA Line
S
Slave Address
Ri Lsb
Ri Msb
Stop
Bus Activity:
Master
Start
There is also a “Short Read” format, designed to improve the efficiency of Ri register reads (which must be done every
two seconds while encryption is enabled). This transaction is shown in Figure 7.3. Note that there is no register address
phase (only the slave address phase), because the register address is reset to 0x08 (Ri) after a hardware or software
2
reset, and after the STOP condition on any preceding I C transaction.
P
A
C
K
A
C
K
No
A
C
K
Figure 7.3. Short Read Sequence
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
63
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
7.2.
Local I2C Interface
2
The SiI9233 HDMI Receiver has a second I C port accessible only to the controller in the display device. It is separate
2
from the E-DDC bus. The HDMI Receiver is a slave device that responds to six binary I C device addresses of seven bits
2
each. This I C interface only supports the read operation in Figure 7.1, and the write operation in Figure 7.2. It does not
2
2
support the short read operation shown in Figure 7.3. Note that the I C data pin for the local I C bus is CSDA, instead of
the DSDA pin shown in these figures.
2
The local I C interface on the SiI9233 receiver (pins CSCL and CSDA) is a slave interface that can run up to 400 kHz. This
bus is used to configure and control the SiI9233 receiver by reading/writing to necessary registers.
2
2
The local I C interface of the SiI9233 receiver consists of 6 separate I C slave addresses. The SiI223 receiver will
2
therefore appear as 6 separate devices on the I C local bus. The first two of these addresses, used for HDMI Control
and general low level register control, are fixed, and can only be set to one of two values by using the CI2CA pin. The
2
other 3 addresses (used for CEC, EDID, and x.v.Color) have an I C register programmable address mapped into the
HDMI Control register space, so the default value can be changed if there is a bus conflict with another device.
2
Table 7.1. Control of the Default I C Addresses with the CI2CA Pin
CI2CA=LOW
Ci2CA=HIGH
HDMI Control and low level registers
(fixed)
0x60 & 0x68
X.V.Color Registers (programmable)
0x64
EDID Registers (programmable)
0xE0
0xE4
CEC Registers (programmable)
0xC0
0xC4
0x62 & 0x6A
2
The HDMI Control and low level registers are fixed after reset based on CI2CA pin and cannot be changed. The I C slave
address for the x.v.Color registers, EDID Control registers, and the CEC Control registers each have a register associated
with them that allows the address to be changed. See the SiI9223/9233/9127 HDMI Receivers Programmer’s
Reference (SiI-PR-1019) for more information.
7.3.
Video Requirement for I2C Access
The SiI9233 receiver does not require an active video clock to access its registers from either the E-DDC port or the
2
local I C port. Read-Write registers can be written and then read back. Read-only registers that provide values for an
active video or audio stream return indeterminate values if there is no video clock and no active syncs.
Use the SCDT and CKDT register bits to determine when active video is being received by the chip.
7.4.
I2C Registers
2
The register values that are exchanged over the HDMI DDC I C serial interface with the SiI9233 for HDCP are described
in the HDCP 1.0 Specification (February 2000) in Section 2.6 – HDCP Port. Refer to the SiI9223/9233/9127 HDMI
Receivers Programmer’s Reference (SiI-PR-1019) for details on these and all other SiI9233 registers.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
64
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
8. Hot Plug Detect CTS Requirement
To comply with with HDMI Compliance Test Specification Test ID 8-11, HPD Output Resistance, the circuit shown in
Figure 8.1 must be added to each SiISiI9233 input port that is used in the design.
SiI9233
RnPWR5V
18
4.7 k
+5V
HDMI
connector
Port n
1 k
19
HPD
MMBT3904
HPDn
10 k
MMBT3904
Figure 8.1: HPD CTS Compliance Requirement Schematic
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
65
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
9. Design Recommendations
The following information is provided as recommendations that are based on the experience of Lattice Semiconductor
engineers and customers. If you choose to deviate from these recommendations for a particular application, Lattice
Semiconductor strongly suggests that you contact one of its technical representatives for an evaluation of the change.
9.1.
Power Control
The low-power standby state feature of the SiI9233 receiver provides a design option of leaving the chip always
powered, as opposed to powering it on and off. Leaving the chip powered and using the PD# register bit to put it in a
lower power state can result in faster system response time, depending on the system Vcc supply ramp-up delay.
9.1.1. Power Pin Current Demands
The limits shown in Table 9.1 indicate the current demanded by each group of power pins on the SiI9233 device. These
limits were characterized at maximum VCC, 0 °C ambient temperature and for fast-fast silicon. Actual application
current demands can be lower than these figures, and varies with video resolution and audio clock frequency.
Table 9.1. Maximum Power Domain Currents versus Video Mode
Mode
ODCK (MHz)
3.3V Power Domain Currents (mA)
480p
27.0
IOVCC33
39
AVCC33
51
XTALVCC33
7
1080i
1080p
1
1080p@12-bit
74.25
148.5
225
100
182
252
51
51
51
7
7
7
Mode
ODCK (MHz)
1.2V Power Domain Currents (mA)
AVCC12
CVCC12
APVCC12
480p
27.0
1080i
74.25
36
54
84
129
1080p
148.5
1080p@12-bit
Notes:
1.
2.
3.
4.
1
225
52
127
253
343
5
5
5
5
Measured with 12-bits/pixel video data.
Measured with 192 kHz, 8-channel audio, except for 480p mode which used 48 kHz, 8-channel audio.
Measured with RGB input, vertical black-white/1-pixel stripe (Moire2) pattern, converting to YCbCr output (digital for
IOVCC33).
Only one core can be selected at a time. The TMDSxSEL register bit turns off the unselected core, except for the
termination to AVCC33.
AVCC33 current includes 40 mA for the unselected TMDS core. Only 5 mA of this current is dissipated as power in the
HDMI Receiver; the remainder is dissipated in the HDMI transmitter. The AVCC33 current on the unselected core can
be reduced to 5 mA by asserting the corresponding PD_TERMx# register bit.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
66
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
9.2.
HDMI Receiver DDC Bus Protection
2
The I C pins on the VESA DDC Specification (available at www.vesa.org) defines the DDC interconnect bus to be a 5-V
2
signaling path. The I C pins on the HDMI Receiver chip are 5-V tolerant. And these pins are true open-drain I/O. The
pull-up resistors on the DDC bus should be pulled up using the 5-V supply from the HDMI connector. Refer to Figure 9.9
on page 74.
9.3.
Decoupling Capacitors
Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown
schematically in Figure 9.4 on page 71. Place these components as closely as possible to the SiI9233 pins and avoid
routing through vias. Figure 9.1 shows the various types of power pins on the HDMI Receiver.
VCC
C1
C2
L1
VCC
Ferrite
GND
C3
Via to GND
Figure 9.1. Decoupling and Bypass Capacitor Placement
9.4.
ESD Protection
The HDMI Receiver chip is designed to withstand electrostatic discharge to 2 kV. In applications where higher
protection levels are required, ESD limiting components can be placed on the differential lines coming into the chip.
These components typically have a capacitive effect, reducing the signal quality at higher clock frequencies on the link.
Use of the lowest capacitance devices is suggested; in no case should the capacitance value exceed 5 pF.
Series resistors can be included on the TMDS lines (see Figure 9.9 on page 74) to counteract the impedance effects of
ESD protection diodes. The diodes typically lower the impedance because of their capacitance. The resistors raise the
impedance to stay within the HDMI specification centered on a 100-Ω differential.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
67
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
HDMI Receiver Layout
9.5.
The HDMI Receiver chip should be placed as closely as possible to the input connectors that carry the TMDS signals. For
a system using industry-standard HDMI connectors (see www.hdmi.org), the differential lines should be routed as
directly as possible from connector to HDMI Receiver. Lattice Semiconductor HDMI receivers are tolerant of skews
between differential pairs, so spiral skew compensation for path length differences is not required. Each differential
pair should be routed together, minimizing the number of vias through which the signal lines are routed. The distance
separating the two traces of the differential pair should be kept to a minimum.
In order to achieve the optimal input TMDS signal quality, please follow the layout guidelines below:
1.
Lay out all differential pairs with controlled impedance of 100  differential.
2.
Cut out all copper planes (ground and power) that are less than 45 mils underneath the TMDS traces near
the HDMI receiver with dimensions as shown below.
0.3 inch
> 0.1 inch
HDMI
Connectors
HDMI Receiver
> 0.1 inch
Ground and Power plane cut-out for copper planes <45 mil separation from TMDS traces
Figure 9.2. Cut-out Reference Plane Dimensions
3.
If ESD suppression devices or common mode chokes are used, place them near the HDMI connector, away
from the HDMI Receiver IC. Do not place them over the ground and power plane cutout near the HDMI
receiver.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
68
SiI-DS-1032-A
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
DDC#0
+5V
PIN 19
DDC#1
text
text
R1PWR5V
text
text
text
text
text
text
text
text
text
text
text
R0PWR5V
text
text
text
10
text
text
text
text
text
text
text
text
text
text
text
text
text
text
text
text
text
text
19
PIN 1
text
text
text
text
HDMI Port
#0
Connector
text
text
text
text
DDC#1
text
SiI9233
text
+5V
HDMI Port
#1
Connector
text
text
text
text
text
text
text
PIN 19
text
text
text
text
text
text
text
text
text
text
text
text
text
10
text
text
text
text
text
text
text
text
text
text
text
text
text
text
text
text
PIN 1
19
Drawing is not to exact scale. Refer to
HDMI connector specification for exact
dimensions.
Figure 9.3. HDMI to Receiver Routing – Top View
Note the sixteen TMDS traces connected directly from the HDMI connectors (left) to the pins on the SiI9233 receiver
(right). Trace impedance should be 100  differential in each pair and 50  single-ended if possible. Trace width and
pitch depends on the PCB construction. Not all connections are shown — the drawing demonstrates routing of TMDS
lines without crossovers, vias, or ESD protection. Refer also to Figure 9.9.
9.6.
EMI Considerations
Electromagnetic interference is a function of board layout, shielding, HDMI Receiver component operating voltage, and
frequency of operation, among other factors. When attempting to control emissions, do not place any passive
components on the differential signal lines (aside from any essential ESD protection as described earlier). The
differential signaling used in HDMI is inherently low in EMI as long as the routing recommendations noted in the
Receiver Layout section are followed.
The PCB ground plane should extend unbroken under as much of the HDMI Receiver chip and associated circuitry as
possible, with all ground pins of the chip using a common ground.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
9.7.
XTALIN Clock Required in All Designs
9.7.1. Description
The SiI9233 receiver uses the clock at the XTALIN/XTALOUT pin pair to control the internal audio pipeline. This clock is
also used to control the interrupt processing, the internal reading of HDCP keys and internal CEC timing calibration.
The XTALIN/XTALOUT pin pair must be driven with a clock in all applications, even when the design does not support
audio processing. The clock frequency must be 27.000 MHz.
9.7.2. Recommendation
For designs that do not support audio, the XTALIN pin can be connected to an ordinary 27-MHz LVTTL clock source,
which is commonly available on HDMI sink designs. There is no requirement that this clock source be low jitter. The
XTALOUT pin can be left unconnected when XTALIN is driven with a LVTTL clock.
9.8.
Typical Circuit
Representative circuits for application of the SiI9233 HDMI Receiver chip are shown in Figure 9.4 through Figure 9.8.
For a detailed review of your intended circuit implementation, contact your Lattice Semiconductor representative.
9.8.1. Power Supply Decoupling
AVCC_3. 3V
Ferrite
220 @100MHz
AVCC33
0.1uF
10uF
0.1uF
0.1uF
0.1uF
1nF
1nF
1nF
GND
+3.3V
Place ceramic capacitors
close to VCC pins .
IOVCC33
10uF
10uF
0.1uF
0. 1uF
0.1uF
0.1uF
1nF
1nF
1nF
1nF
1nF
1nF
1nF
GND
+1. 2V
Place ceramic capacitors
close to VCC pins .
CVCC 12
10uF
10uF
0.1uF
0. 1uF
0.1uF
0.1uF
1nF
1nF
1nF
1nF
1nF
1nF
1nF
GND
SiI9233
+1.2V
0.56 
1%
Ferrite
0.82uH, 150 mA
AVCC12
10uF
0.1uF
0. 1uF
0.1uF
1nF
1nF
1nF
AGND
+1.2V
Ferrite
220@100 MHz
+3.3V
Ferrite
220@100 MHz
APVCC12
XTALVCC33
+5V
SBVCC 5
Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
70
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
The ferrite on AVCC33 attenuates noise above 10 kHz. A parasitic resistor helps to minimize the peaking. An example
device (surface mount, 0805 package) is part number MLF2012DR82 from TDK. A data sheet is available at
www.tdk.co.jp
9.8.2. HDMI Port Connections
RX2+ n
RX2- n
RnX2+
RnX2-
RX1+ n
RnX1+
RX1- n
RnX1-
RX0+ n
RX0- n
RnX0+
RnX0-
RXC+ n
RnXC+
RXC- n
RnXC-
HDMI
Connector
Port n
SiI9233
CEC_A
CEC n
HPD n
HPDn
+5V n
47 k
47 k
See the Hot Plug Detect CEC
Requirement section for
important information.
SCL n
DSCLn
SDA n
DSDAn
Figure 9.5. HDMI Port Connections Schematic
Note: Repeat the schematic for each HDMI input port on the SiI9233 receiver.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
9.8.3. Digital Video Output Connections
SiI9233
INT
102
Micro
19
DE
20
HSYNC
21
VSYNC
5
ODCK
16
Q0
15
Q1
14
Q2
13
Q3
10
Q4
9
Q5
8
Q6
7
Q7
3
Q8
2
Q9
1
Q10
144
Q11
141
Q12
140
Q13
139
Q14
138
Q15
135
Q16
134
Q17
133
Q18
132
Q19
129
Q20
128
Q21
127
Q22
126
Q23
33
33
33
33
33
33
33
123
Q24
122
Q25
121
Q26
120
Q27
117
Q28
116
Q29
115
Q30
114
Q31
111
Q32
110
Q33
109
Q34
108
Q35
33
33
33
Figure 9.6. Digital Display Schematic
The 3.3V to the level-shifters and pull-up resistors should be powered-down whenever the 3.3 V is powered-down on
the HDMI Receiver itself.
The HDMI Receiver’s INT output can be connected as an interrupt to the microcontroller, or the microcontroller can
poll register 0x70 (INTR_STATE) to determine if any of the enabled interrupts have occurred. Refer to the
SiI9223/9233/9127 HDMI Receivers Programmer’s Reference (SiI-PR-1019) for details. The HDMI Receiver’s VSYNC
output can be connected to the micro if it is necessary to monitor the vertical refresh rate of the incoming video.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
72
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
9.8.4. Digital Audio Output Connections
+3.3V
SiI9233
Ferrite
XTALVCC
SCK
WS
SD[3:0]
SPDIF
DCLK
DR[2:0]
0.01 F
0.1F
DL[2:0]
18 pF
MCLKOUT
XTALIN
MUTEOUT
33
1 M
18 pF
28.322
MHz
XTALOUT
Place crystal circuit as
closely to package as
possible.
Figure 9.7. Audio Output Schematic
9.8.5. Control Signal Connections
+3.3V
SiI9233
4.7
k
4.7
k
CSDA
CSDA
CSCL
CSCL
EVEN/ODD Field
EVNODD
RSVDL
4.7 k
Microcontroller
GPIO
SCDT and INT outputs to micro are optional
.
Sync status and interrupt bits may be polled
2
through CSDA/CSCL I C port.
RESET#
GPIO
SCDT
GPIO
INT
GPIO
Firmware monitors Hot Plug Detect signal
to trigger EDID re-read and inhibit HDCP
authentication attempts.
HPD
HDMI
Connector
Figure 9.8. Controller Connections Schematic
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
9.9.
Layout
Figure 9.9 shows an example of routing TMDS lines between the SiI9233 and the HDMI connector.
9.9.1. TMDS Input Port Connections
DDC SCL
TMDS Data 2+
DDC SDA
TMDS Data 2-
Hot Plug
Detect
TMDS Data 1+
Connector
Shell
TMDS Data 1TMDS Data 0+
+5V Power
DDC Ground
TMDS Data 0-
Reserved NC
TMDS Clock
Shield
CEC
TMDS Clock-
TMDS
Clock+
TMDS Data Shield
TMDS Data Shield
TMDS Data Shield
Figure 9.9. TMDS Input Signal Assignments
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
74
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
10. Packaging
10.1. ePad Enhancement
The SiI9233 receiver is packaged in a TQFP package with ePad that must be soldered to ground. The ePad dimensions
are shown in Figure 10.1.
T1
ePad Dimensions
typ
max
T1
T2
ePad Height
4.064
4.214
ePad Width
4.445
4.595
ΔT
ePad tolerance
±.15
T2
All dimensions are in millimeters.
Center the ePad on the package center lines with the
tolerance shown.
A clearance of at least 0.25mm should be designed on
the PCB between the edge of the ePad and the inner
edges of the lead pads to avoid any electrical shorts.
Tabs may have smaller dimensions than the maximums
shown above, and may not appear at all, because
minimum width and height are 0.0 mm.
Lattice Semiconductor requires that the ePad be soldered to the PCB
and electrically grounded on the PCB. The ePad must not be
electrically connected to any other voltage level except ground (GND).
Figure 10.1. ePad Diagram
10.2. PCB Layout Guidelines
Refer to Lattice Semiconductor document PCB Layout Guidelines: Designing with Exposed Pads (SiI-AN-0129) for basic
PCB design guidelines when designing with thermally enhanced packages using the exposed pad. This application note
is intended for use by PCB layout designers.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
10.3. 144-pin TQFP Package Dimensions
typ
max
A
Thickness
1.10
1.20
A1
A2
Stand-off
0.10
0.15
Body Thickness
1.00
1.05
D1
E1
D
Body Size
20.00
20.00
Body Size
20.00
20.00
Footprint
22.00
22.00
E
D2
E2
Footprint
22.00
22.00
Lead Row Width
17.50
17.50
Lead Row Width
17.50
17.50
Lead Count
144
L1
Lead Length
1.00
L
b
c
Lead Foot
0.60
0.75
Lead Width
0.20
0.27
e
aaa
Lead Pitch
0.50
0.50
Form Tolerance
0.20
0.20
bbb
ccc
ddd
Form Tolerance
0.20
0.20
Position Tolerance
0.08
0.08
Position Tolerance
0.08
0.08
JEDEC Package Code MS-026-AFB
Lead Thickness
0.20
Dimensions in millimeters.
Overall thickness A=A1+A2.
Figure 10.2. 144-Pin TQFP Package Diagram
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
76
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SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
10.4. Marking Specification
Drawing is not to scale and pin count shown is representative. Refer to specifics in Figure 10.2 on page 76.
Logo
Product Line
SiI9233CTU
LLLLLL.LL-L
YYWW
TTTTTTmmmr
Silicon Image Part Number
Lot # (= Job#)
Date code
Trace code
Pin 1 location
Figure 10.3. Marking Diagram
10.5. Ordering Information
Production Part Numbers:
TMDS Input Clock Range
Part Number
SiI9233
25–225 MHz
SiI9233CTU
The universal package may be used in lead-free and ordinary process lines.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1032-A
77
SiI9233 HDMI Receiver with Repeater, Multi-channel Audio, and Deep Color Output
Data Sheet
Revision History
Revision A, March 2016
Updated to latest template.
Revision A, August 2008
First production release.
© 2008-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
78
SiI-DS-1032-A
th
th
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