SiI9127A/SiI1127A HDMI Receiver with Deep Color Output

SiI9127A/SiI1127A HDMI Receiver with Deep
Color Output
Data Sheet
SiI-DS-1059-C
February 2016
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Contents
Acronyms in This Document .................................................................................................................................................6
1. General Description ......................................................................................................................................................7
1.1.
Inputs ..................................................................................................................................................................7
1.2.
Digital Video Output ............................................................................................................................................7
1.3.
Digital Audio Interface.........................................................................................................................................8
1.4.
Consumer Electronic Control ..............................................................................................................................8
1.5.
System Applications ............................................................................................................................................8
1.6.
Package ...............................................................................................................................................................8
2. Product Family ..............................................................................................................................................................9
3. Functional Description ................................................................................................................................................10
3.1.
TMDS Digital Cores ............................................................................................................................................10
3.1.1. Active Port Detection and Selection .............................................................................................................10
3.2.
HDCP Decryption Engine/XOR Mask .................................................................................................................11
3.2.1. HDCP Embedded Keys ...................................................................................................................................12
3.3.
Data Input and Conversion ................................................................................................................................12
3.3.1. Mode Control Logic .......................................................................................................................................12
3.3.2. Video Data Conversion and Video Output ....................................................................................................12
3.3.3. Deep Color Support.......................................................................................................................................13
3.3.4. xvYCC .............................................................................................................................................................13
3.4.
3D Video Formats ..............................................................................................................................................13
3.4.1. Automatic Video Configuration ....................................................................................................................15
3.5.
Audio Data Output Logic ...................................................................................................................................15
3.5.1. S/PDIF ............................................................................................................................................................15
2
3.5.2. I S ..................................................................................................................................................................15
3.6.
Control and Configuration .................................................................................................................................16
3.6.1. Register/Configuration Logic ........................................................................................................................16
2
3.6.2. I C Serial Ports ...............................................................................................................................................16
3.6.3. EDID FLASH and RAM Block ..........................................................................................................................17
3.6.4. CEC Interface .................................................................................................................................................17
3.6.5. Standby and HDMI Port Power Supplies .......................................................................................................17
4. Electrical Specifications ..............................................................................................................................................19
4.1.
Absolute Maximum Conditions .........................................................................................................................19
4.2.
Normal Operating Conditions ...........................................................................................................................20
4.3.
DC Specifications ...............................................................................................................................................21
4.3.1. Digital I/O Specifications ...............................................................................................................................21
4.3.2. DC Power Supply Pin Specifications ..............................................................................................................22
4.4.
AC Specifications ...............................................................................................................................................24
4.4.1. Video Output Timings ...................................................................................................................................24
4.4.2. Audio Output Timings ...................................................................................................................................25
4.4.3. Miscellaneous Timings ..................................................................................................................................26
4.4.4. Interrupt Timings ..........................................................................................................................................26
5. Timing Diagrams .........................................................................................................................................................28
TMDS Input Timing Diagrams ............................................................................................................................28
5.1.
5.2.
Power Supply Control Timings ..........................................................................................................................28
5.2.1. Power Supply Sequencing .............................................................................................................................28
5.3.
Reset Timings ....................................................................................................................................................29
5.4.
Digital Video Output Timing Diagrams ..............................................................................................................29
5.4.1. Output Transition Times ...............................................................................................................................29
5.4.2. Output Clock to Output Data Delay ..............................................................................................................30
5.5.
Digital Audio Output Timings ............................................................................................................................30
5.6.
Calculating Setup and Hold Times for Video Bus ..............................................................................................32
5.6.1. 24/30/36-Bit Mode .......................................................................................................................................32
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
2
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
5.6.2. 12/15/18-Bit Dual-Edge Mode ...................................................................................................................... 33
2
5.7.
Calculating Setup and Hold Times for I S Audio Bus ......................................................................................... 34
6. Pin Diagram and Descriptions ..................................................................................................................................... 35
6.1.
Pin Diagram ....................................................................................................................................................... 35
6.2.
Pin Descriptions................................................................................................................................................. 36
6.2.1. Digital Video Output Data Pins ..................................................................................................................... 36
6.2.2. Digital Video Output Control Pins ................................................................................................................. 37
6.2.3. Digital Audio Output Pins.............................................................................................................................. 37
6.2.4. Configuration/Programming Pins ................................................................................................................. 38
6.2.5. HDMI Control Signal Pins .............................................................................................................................. 38
6.2.6. TMDS Differential Signal Pins........................................................................................................................ 39
6.2.7. Power and Ground Pins ................................................................................................................................ 39
6.2.8. Reserved and Not Connected Pins ................................................................................................................ 39
7. Video Path .................................................................................................................................................................. 40
7.1.
HDMI Input Modes to SiI9127A/SiI1127A Output Modes ................................................................................ 41
7.1.1. HDMI RGB 4:4:4 Input Processing................................................................................................................. 41
7.1.2. HDMI YCbCr/xvYCC 4:4:4 Input Processing................................................................................................... 42
7.1.3. HDMI YCbCr/xvYCC 4:2:2 Input Processing................................................................................................... 43
7.2.
SiI9127A/SiI1127A Output Mode Configuration ............................................................................................... 44
7.2.1. RGB and YCbCr 4:4:4 Formats with Separate Syncs ..................................................................................... 45
7.2.2. YC 4:2:2 Formats with Separate Syncs .......................................................................................................... 47
7.2.3. YC 4:2:2 Formats with Embedded Syncs ....................................................................................................... 50
7.2.4. YC Mux (4:2:2) Formats with Separate Syncs ............................................................................................... 53
7.2.5. YC Mux 4:2:2 Formats with Embedded Syncs ............................................................................................... 55
7.2.6. 12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs ................................................................ 57
2
8. I C Interfaces............................................................................................................................................................... 59
2
8.1.
HDCP E-DDC / I C Interface ............................................................................................................................... 59
2
8.2.
Local I C Interface ............................................................................................................................................. 60
2
8.3.
Video Requirement for I C Access ..................................................................................................................... 60
2
8.4.
I C Registers ...................................................................................................................................................... 60
9. Design Recommendations .......................................................................................................................................... 61
9.1.
Power Control ................................................................................................................................................... 61
9.2.
Power-on Sequencing ....................................................................................................................................... 61
9.2.1. Power Pin Current Demands......................................................................................................................... 61
9.3.
HDMI Receiver DDC Bus Protection .................................................................................................................. 62
9.4.
Decoupling Capacitors ...................................................................................................................................... 62
9.5.
ESD Protection .................................................................................................................................................. 62
9.6.
HDMI Receiver Layout ....................................................................................................................................... 63
9.7.
EMI Considerations ........................................................................................................................................... 64
9.8.
Typical Circuit .................................................................................................................................................... 65
9.8.1. Power Supply Decoupling ............................................................................................................................. 65
9.8.2. HDMI Port Connections ................................................................................................................................ 66
9.8.3. Digital Video Output Connections ................................................................................................................ 67
9.8.4. Digital Audio Output Connections ................................................................................................................ 68
9.8.5. Control Signal Connections ........................................................................................................................... 69
9.9.
Layout................................................................................................................................................................ 70
9.9.1. TMDS Input Port Connections ...................................................................................................................... 70
10.
Package Information ............................................................................................................................................... 71
10.1. ePad Requirements ........................................................................................................................................... 71
10.2. PCB Layout Guidelines ...................................................................................................................................... 71
10.3. Package Dimensions .......................................................................................................................................... 72
10.4. Marking Specification ........................................................................................................................................ 73
10.5. Ordering Information ........................................................................................................................................ 73
References .......................................................................................................................................................................... 74
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
3
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Standards Documents .....................................................................................................................................................74
Standards Groups ...........................................................................................................................................................74
Lattice Semiconductor Documents .................................................................................................................................74
Technical Support ...........................................................................................................................................................74
Revision History ..................................................................................................................................................................75
Figures
Figure 1.1. Digital Television System Diagram ......................................................................................................................7
Figure 3.1. Digital Television Receiver Block Diagram ........................................................................................................10
Figure 3.2. Functional Block Diagram .................................................................................................................................11
Figure 3.3. Default Video Processing Path ..........................................................................................................................14
2
Figure 3.4. I C Register Domains .........................................................................................................................................16
Figure 3.5. Power Island .....................................................................................................................................................18
Figure 4.1. Test Point VCCTP for VCC Noise Tolerance Specification .................................................................................20
Figure 4.2. Audio Crystal Schematic ...................................................................................................................................25
Figure 4.3. SCDT and CKDT Timing from DE or RXC Inactive/Active ...................................................................................27
Figure 5.1. TMDS Channel-to-Channel Skew Timing ..........................................................................................................28
Figure 5.2. Power Supply Sequencing .................................................................................................................................28
Figure 5.3. RESET# Minimum Timings.................................................................................................................................29
Figure 5.4. Video Digital Output Transition Times ..............................................................................................................29
Figure 5.5. Receiver Clock-to-Output Delay and Duty Cycle Limits ....................................................................................30
2
Figure 5.6. I S Output Timings ............................................................................................................................................30
Figure 5.7. S/PDIF Output Timings ......................................................................................................................................31
Figure 5.8. MCLK Timings ....................................................................................................................................................31
Figure 5.9. 24/30/36-Bit Mode Receiver Output Setup and Hold Times ............................................................................32
Figure 5.10. 12/15/18-Bit Mode Receiver Output Setup and Hold Times ..........................................................................33
Figure 6.1. Pin Diagram .......................................................................................................................................................35
Figure 7.1. Receiver Video and Audio Data Processing Paths ............................................................................................40
Figure 7.2. HDMI RGB 4:4:4 Input to Video Output Transformations ................................................................................41
Figure 7.3. HDMI YCbCr/xvYCC 4:4:4 Input to Video Output Transformations ..................................................................42
Figure 7.4. HDMI YCbCr/xvYCC 4:2:2 Input to Video Output Transformations ..................................................................43
Figure 7.5. 4:4:4 Timing Diagram ........................................................................................................................................46
Figure 7.6. YC Timing Diagram ............................................................................................................................................49
Figure 7.7. YC 4:2:2 Embedded Sync Timing Diagram ........................................................................................................52
Figure 7.8. YC Mux 4:2:2 Timing Diagram ...........................................................................................................................54
Figure 7.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram .................................................................................56
Figure 7.10. 18-Bit Output 4:4:4 Timing Diagram ...............................................................................................................57
Figure 7.11. 15-Bit Output 4:4:4 Timing Diagram ...............................................................................................................58
Figure 7.12. 12-Bit Output 4:4:4 Timing Diagram ...............................................................................................................58
2
Figure 8.1. I C Byte Read .....................................................................................................................................................59
2
Figure 8.2. I C Byte Write ....................................................................................................................................................59
Figure 8.3. Short Read Sequence ........................................................................................................................................59
Figure 9.1. Decoupling and Bypass Capacitor Placement ...................................................................................................62
Figure 9.2. Cut-out Reference Plane Dimensions ...............................................................................................................63
Figure 9.3. HDMI to Receiver Routing – Top View ..............................................................................................................64
Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic ....................................................................................65
Figure 9.5. HDMI Port Connections Schematic ...................................................................................................................66
Figure 9.6. Digital Display Schematic ..................................................................................................................................67
Figure 9.7. Audio Output Schematic ...................................................................................................................................68
Figure 9.8. Controller Connections Schematic ....................................................................................................................69
Figure 9.9. TMDS Input Signal Assignments .......................................................................................................................70
Figure 10.1. 128-Pin TQFP Package Diagram ......................................................................................................................72
Figure 10.2. Marking Diagram of SiI9127A .........................................................................................................................73
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
4
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Tables
Table 2.1. Summary of New Features ................................................................................................................................... 9
Table 3.1. Digital Video Output Formats ............................................................................................................................ 12
Table 3.2. Supported 3D Video Formats ............................................................................................................................. 14
Table 3.3. Default Video Processing ................................................................................................................................... 14
Table 3.4. AVI InfoFrame Video Path Details ...................................................................................................................... 15
Table 3.5. Digital Output Formats Configurable through Auto Output Format Register ................................................... 15
Table 3.6. Supported MCLK Frequencies ............................................................................................................................ 16
Table 5.1. Calculation of 24/30/36-Bit Output Setup and Hold Times ............................................................................... 32
Table 5.2. Calculation of 12/15/18-Bit Output Setup and Hold Times ............................................................................... 33
2
Table 5.3. I S Setup and Hold Time Calculations ................................................................................................................ 34
Table 7.1. Translating HDMI Formats to Output Formats .................................................................................................. 41
Table 7.2. Output Video Formats ....................................................................................................................................... 44
Table 7.3. 4:4:4 Mappings .................................................................................................................................................. 45
Table 7.4. YC 4:2:2 Separate Sync Pin Mappings ................................................................................................................ 47
Table 7.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping ................................................................................ 48
Table 7.6. YC 4:2:2 Embedded Sync Pin Mappings ............................................................................................................. 50
Table 7.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping ............................................................................. 51
Table 7.8. YC Mux 4:2:2 Mappings ..................................................................................................................................... 53
Table 7.9. YC Mux 4:2:2 Embedded Sync Pin Mapping ...................................................................................................... 55
Table 7.10. 12/15/18-Bit Output 4:4:4 Mappings .............................................................................................................. 57
2
Table 8.1. Control of the Default I C Addresses with the CI2CA Pin ................................................................................... 60
Table 9.1. Maximum Power Domain Currents versus Video Mode.................................................................................... 61
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
5
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Acronyms in This Document
A list of acronyms used in this document.
Acronym
ACR
AVI
CBUS
CEC
CPI
CPU
CSC
DDC
DSC
DSD
DTV
EDDC
EDID
ESD
GPIO
HDCP
HDMI
HPD
2
IC
2
IS
KSV
NVM
PCM
S/PDIF
TMDS
TQFP
Definition
Audio Clock Regeneration
Auxiliary Video Information
Control Bus
Consumer Electronics Control
CEC Programming Interface
Central Processing Unit
Color Space Converter
Display Data Channel
Display Stream Compression
Direct-Stream Digital
Digital Television
Enhanced Display Data Channel
Extended Display Identification Data
Electrostatic Discharge
General Purpose Input/Output
High-bandwidth Digital Content Protection
High-Definition Multimedia Interface
Hot Plug Detect
Inter-Integrated Circuit
Inter-IC Sound, Integrated Interchip Sound
Key Selection Vector
Non Volatile Memory
Pulse Code Modulation
Sony/Philips Digital Interface Format
Transition Minimized Differential Signaling
Thin Quad Flat Pack
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
6
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
1. General Description
The SiI9127A/SiI1127A HDMI® Receiver with Deep
Color Outputs from Lattice Semiconductor Corporation
is a 2-port receiver that allows DTVs that can display
10/12-bit color depth to provide the highest quality
protected digital audio and video over a single cable.
The SiI9127A/SiI1127A receiver can receive Deep Color
video up to 12-bit, 1080p at 60 Hz. Efficient color space
conversion receives RGB or YCbCr video data and
sends either standard-definition or high-definition RGB
or YCbCr formats.
The SiI9127A/SiI1127A receiver supports the extended
gamut YCC or xvYCC color space described in the
IEC 61966-2-4 Specification, which supports
approximately 1.8 times the number of colors as the
RGB color space. The xvYCC color space also makes full
use of the range provided by the standard 8-bit
resolution per pixel format.
The SiI9127A receiver is preprogrammed with
High-bandwidth Digital Content Protection (HDCP) keys
and contains an integrated HDCP decryption engine for
receiving protected audio and video content. This set
of keys helps reduce programming overhead, lowers
manufacturing costs, and provides the highest level of
security.
The SiI1127A receiver is functionally equivalent to the
SiI9127A receiver except that the HDCP keys are not
preprogrammed, therefore SiI1127A does not support
HDCP decryption.
An integrated Extended Display Identification Data
(EDID) block stored in non-volatile memory (NVM) can
be programmed at the time of manufacture using the
2
local I C bus. On-board RAM can also be loaded through
2
the I C bus with EDID data from the system
microcontroller during initialization if the EDID content
of the NVM is not used.
The EDID is reflected on the two HDMI ports through
the DDC bus. The device allows different EDID formats
to be mixed in an application. Having the flexibility to
provide EDID content from the sources described above
or from external ROM can eliminate up to two EDID
ROMs and save board space.
Flexible power management provides extremely low
standby power consumption. Standby power can be
supplied from an HDMI 5 V signal or from a separate
standby power pin. If the NVM stores the EDID, only
the 5 V power from the source device is needed to
read the EDID.
1.1.



1.2.






Up to 2 HDMI Sources
(DVD Player, Set Top Box, HD Camcorder,
Game Console, etc.)
Inputs
Two HDMI/DVI-compatible ports
The TMDS™ core runs at 25 MHz–225 MHz
Dynamic cable equalization automatically detects
the equalization required for the incoming signal
Digital Video Output
xvYCC to extended RGB
36-bit RGB/YCbCr 4:4:4
16/20/24-bit YCbCr 4:2:2
8/10/12-bit YCbCr 4:2:2 (ITU BT.656)
True 12-bit accurate output data using an internal
14-bit wide processing path
Drive strength is programmable from 2 mA to 14 mA
Display
(DTV, LCD, Plasma, Projector)
HD Camcorder
HDMI
SiI9127A/
SiI1127A
HDMI
Receiver
Video
Video
Processor
Audio
Blu-ray DVD
Audio
DAC/Amp
L
R
Figure 1.1. Digital Television System Diagram
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
7
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
1.3.





Sends and receives up to two channels of
uncompressed digital audio at the rate of 192 kHz.
2
I S output with one data signal for stereo formats
S/PDIF output supports PCM, Dolby Digital, DTS
digital audio transmission with a 32 kHz–192 kHz
Fs sample rate
Intelligent audio mute capability avoids pops and
noise with automatic soft mute and unmute
IEC60958 or IEC61937 compatible
1.4.




Digital Audio Interface
Consumer Electronic Control
Consumer Electronics Control (CEC) interface
incorporates an HDMI CEC I/O
An integrated CEC Programming Interface (CPI)
relieves the burden of the microcontroller having
to write low-level commands
Automatic Feature Abort response for
unsupported commands
Automatic Message Retry on transmit
1.5.
System Applications
The SiI9127A/SiI1127A receiver is designed for digital
televisions that require support for HDMI Deep Color.
The device allows receipt of 10/12-bit color depth up
to 1080p resolutions. A single receiver chip provides
two HDMI input ports. The video output interfaces to a
video processor and the audio output can interface
directly to an audio DAC or an audio DSP for further
processing as shown in Figure 3.1.
1.6.
Package
14 mm × 14 mm 128-pin TQFP package with an exposed
pad (ePad)
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
8
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
2. Product Family
Table 2.1 summarizes the functional differences among the SiI9127A/SiI1127A, SiI9125, SiI9135A, SiI9223A and the
SiI9233A receivers.
Table 2.1. Summary of New Features
Feature
SiI9125
SiI9127A/SiI1127A
SiI9135A
SiI9223A
SiI9233A
2
2
2
4
4
8/10/12-bit
8/10/12-bit
8/10/12-bit
8/10/12-bit
8/10/12-bit
2
2
2
4
4
225 MHz
225 MHz
225 MHz
225 MHz
225 MHz
1
1
1
1
1
165 MHz
36
165 MHz
36
165 MHz
36
165 MHz
36
165 MHz
36
HDMI Input Connections
TMDS Input Ports
Color Depth
DDC Input Ports
Maximum TMDS Input Clock
Video Output
Digital Video Output Ports
Maximum Output Pixel Clock
Maximum Output Bus Width
Audio Formats
S/PDIF Output Ports
1
1
1
1
1
2 channel
2 channel
2 channel
NA
8 channel
6 channel
2 channel
NA
8 channel
8 channel
No
No
Yes
No
Yes
192 kHz
192 kHz
192 kHz
192 kHz
192 kHz
RGB to/from
YCbCr
RGB to/from
YCbCr
xvYCC to RGB
RGB to/from
YCbCr
RGB to/from
YCbCr
xvYCC to RGB
RGB to/from
YCbCr
xvYCC to RGB
÷ 4, ÷ 2
swap Cb, Cr pins
÷ 4, ÷ 2
swap Cb, Cr pins
÷ 4, ÷ 2
swap Cb, Cr pins
÷ 4, ÷ 2
swap Cb, Cr pins
÷ 4, ÷ 2
swap Cb, Cr pins
0x60/0x68 or
0x62/0x6A
0x60/0x68 or
0x62/0x6A
0x60/0x68 or
0x62/0x6A
0x60/0x68 or
0x62/0x6A
0x60/0x68 or
0x62/0x6A
NA
0x64, 0xC0, 0xE0
NA
0x64, 0xC0, 0xE0
0x64, 0xC0, 0xE0
Reserved I C Device Address
3D Support
CEC
NA
No
No
0x90, 0xD0, 0xE6
Yes
Yes
NA
No
No
0x90, 0xD0, 0xE6
Yes
Yes
0x90, 0xD0, 0xE6
Yes
Yes
EDID
HDCP Repeater Support
Interlaced Format Detection
Pin
No
No
NVRAM
No
No
Yes
NVRAM
No
NVRAM
Yes
Yes
Yes
Yes
Yes
Yes
144-pin TQFP
ePad
128-pin TQFP ePad
144-pin TQFP
ePad
144-pin TQFP
ePad
144-pin TQFP
ePad
2
I S Output
DSD Output
High Bit Rate Audio Support
Compressed DTS-HD and
Dolby True-HD
Maximum Audio Sample Rate
(Fs)
Video Processing
Color Space Converter
Pixel Clock Divider
Digital Video Bus Mapping
Other Features
2
Local fixed I C Device Address
1
2
Programmable I C Device
1
Address
2
Package
Notes:
1.
2.
2
2
Refer to the SiI9223A/SiI9233A/SiI9127A/SiI1127A HDMI Receivers Programmer Reference for a description of these I C
register addresses.
2
2
These are reserved I C register addresses which are within the I C register address map of the chip. Do not access these
2
registers on the chip and do not use these addresses for other devices, in the system which use the same I C bus.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
9
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
3. Functional Description
The SiI9127A/SiI1127A receiver provides a complete solution for receiving HDMI-compliant digital audio and video.
Specialized audio and video processing is available within the receiver to add HDMI capability to consumer electronics
such as DTVs. Figure 3.1 shows the SiI9127A/SiI1127A receiver incorporated into a digital television reciever. Figure 3.2
on the next page shows the functional blocks of the chip. The receiver supports two HDMI input ports. Only one port
can be active at any time.
HDMI Port 2
Connector
System
Microcontroller
R1PWR5V
INT
TMDS2
DDC2
I 2C
CEC
HPD2
R2PWR5V
SiI9127A/
SiI1127A
36-bit Video
HDMI Port 1
Connector
Video
Processor
TMDS1
I 2 S Audio
DDC1
Audio
DAC
Speakers
HPD1
Figure 3.1. Digital Television Receiver Block Diagram
3.1.
TMDS Digital Cores
The TMDS digital core is the latest generation core that supports HDMI and the ability to carry 10/12-bit color depth.
The core can receive TMDS data at up to 225 MHz. Each core performs 10-to-8 bit TMDS decoding on the video data
and 10-to-4 bit TMDS decoding on the audio data received from the three TMDS differential data lines along with a
TMDS differential clock. The TMDS core can sense a stopped clock or stopped video and software can put the receiver
into power-down mode.
3.1.1. Active Port Detection and Selection
Only one port can be active at a time, under control of the receiver firmware. Active TMDS signaling can arrive at both
ports, but only one has internal circuitry enabled. The firmware in the display controls these states using register
settings.
Other control signals are associated with the TMDS signals on each HDMI port. The receiver can monitor the +5 V
supply from each attached host. The firmware can poll registers to check which ports are connected. The firmware also
controls functional connection to one of the two E-DDC buses, enabling one while disabling the other. An attached host
determines the active status of an attached HDMI device by polling the E-DDC bus to the device.
Refer to the SiI-PR-1033 Programmer Reference (see Lattice Semiconductor Documents on page 74) for a complete
description of port detection and selection. The Programmer Reference requires an NDA with Lattice Semiconductor.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
10
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
CEC_A
DSDA1
DSDA2
DSCL1
DSCL2
CEC
Serial
Host
Interface
(DDC)
HDCP
Registers
SRAM
CSDA
CSCL
CI2CA
Serial
Host
Interface
(local)
CEC_D
RPI
Registers
and State
Machine
HDCP
Engine
EDID
NVRAM
Embedded
HDCP Keys
Hot Plug
Controller
HPD1
HPD2
Configuration
and Status
Registers
INT
Video Processing
R1XC+
R1XCR1X0+
R1X0R1X1+
R1X1R1X2+
R1X2R2XC+
R2XCR2X0+
R2X0R2X1+
R2X1R2X2+
R2X2-
Video
HDCP
Unmask
Color
Space
Converter
Deep
Color
Video
Output
Format
Up/Down
Sampling
HDMI
Receiver
Mux
A/V Split
HDMI
Decode
ODCK
Q[35:0]
DE
HSYNC
VSYNC
EVNODD
Auto Video Configuration
Audio Processing
Audio Clock
Regeneration
SCDT
Logic
Audio
HDCP
Unmask
APLL
Auto
Audio
Audio Output
S/PDIF
Output
SPDIF
I2S
Output
SCK/DCLK
WS
SD0
MUTEOUT
XTALIN
XTALOUT
MCLK
SCDT
R1PWR5V
R2PWR5V
RESET#
Reset
Logic
Note: HDCP blocks do not apply to the SiI1127A receiver.
Figure 3.2. Functional Block Diagram
3.2.
HDCP Decryption Engine/XOR Mask
The HDCP decryption engine contains all the necessary logic to decrypt the incoming audio and video data. The
decryption process is entirely controlled by the host-side microcontroller/microprocessor through a set sequence of
register reads and writes through the DDC channel. Preprogrammed HDCP keys and Key Selection Vector (KSV) stored
in the on-chip non-volatile memory are used in the decryption process. A resulting calculated value is applied to an XOR
mask during each clock cycle to decrypt the audio and video data.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
11
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
3.2.1. HDCP Embedded Keys
The SiI9127A receiver comes preprogrammed with a set of production HDCP keys stored on-chip in non-volatile
memory. System manufacturers do not need to purchase key sets from the Digital Content Protection LLC. All
purchasing, programming, and security for the HDCP keys is handled by Lattice Semiconductor. The preprogrammed
HDCP keys provide the highest level of security, as keys cannot be read out of the device after they are programmed.
Before receiving samples of the receiver, customers must sign the HDCP license agreement available from Digital
Content Protection, LLC, or have a special NDA with Lattice Semiconductor.
The SiI1127A receiver does not come preprogrammed with a set of production HDCP keys stored on-chip in nonvolatile memory.
3.3.
Data Input and Conversion
3.3.1. Mode Control Logic
The mode control logic determines if the decrypted data is video, audio, or auxiliary information, and directs it to the
appropriate logic block.
3.3.2. Video Data Conversion and Video Output
The SiI9127A/SiI1127A receiver can output video in many different formats (see the examples in Table 3.1) and can
process the video data before it is sent, as shown in Figure 3.3. It is possible to bypass each of the processing blocks by
setting the appropriate register bits.
Table 3.1. Digital Video Output Formats
Color
Space
RGB
Video
Format
4:4:4
Bus
Width
HSYNC/
VSYNC
36
30
Separate
Separate
24
12/15/18
Separate
Separate
36
30
24
4:2:2
480i/576i
27
27
Notes
480p
27
27
XGA
65
65
720p
74.25
74.25
1080i
74.25
74.25
SXGA
108
108
1080p
148.5
148.5
UXGA
162
162
27
27
27
27
65
65
74.25
74.25
74.25
74.25
108
—
148.5
—
162
—
—
4
Separate
Separate
Separate
27
27
27
27
27
27
65
65
65
74.25
74.25
74.25
74.25
74.25
74.25
108
108
108
148.5
148.5
148.5
162
162
162
—
—
—
12/15/18
16/20/24
Separate
Separate
27
27
27
27
65
—
74.25
74.25
74.25
74.25
—
—
—
148.5
—
162
4
—
16/20/24
8/10/12
8/10/12
Embedded
Separate
Embedded
27
27
27
27
54
54
—
—
—
74.25
148.5
148.5
74.25
148.5
148.5
—
—
—
148.5
—
—
162
—
—
1
—
1
4:4:4
YCbCr
Output Clock (MHz)
2, 3
—
—
Notes:
1. Embedded syncs use SAV/EAV coding.
2. 480i and 576i modes can output a 13.25 MHz clock using the internal clock divider.
3. Output clock frequency depends on programming of internal registers. Differential TMDS clock is always 25 MHz or faster.
4. Output clock supports 12/15/18-bit mode by using both edges.
Color Range Scaling
The color range depends on the video format, according to the CEA-861D specification. In some applications the 8-bit
input range uses the entire span of 0x00 (0) to 0xFF (255) values. In other applications the range is scaled narrower.
The receiver cannot detect the incoming video data range and there is no required range specification in the HDMI AVI
packet. The device chooses scaling depending on the detected video format. 10 and 12-bit color range scaling are both
handled the same way. Refer to the SiI-PR-1033 Programmer Reference for more details.
When the receiver outputs embedded syncs (SAV/EAV codes), it also limits the YCbCr data output values to 1 to 254.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
12
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Up Sample/Down Sample
Additional logic can convert from 4:2:2 to 4:4:4 (8/10/12-bit) or from 4:4:4 (8/10/12-bit) to 4:2:2 YCbCr format. All
processing is done with 14 bits of accuracy for true 12-bit data.
3.3.3. Deep Color Support
The HDMI 1.3 Specification introduces Color Depth modes greater than 24 bits, known as Deep Color modes, to the
HDMI system architecture. The Deep Color modes employ a new pixel packing scheme to enable the extra bits of
higher color depth data to be carried over the existing TMDS data encoding scheme. Currently, three Deep Color
modes are defined: 30-bit, 36-bit, and 48-bit. The SiI9127A/SiI1127A receiver supports two of these three Deep Color
modes; 30-bit, and 36-bit modes. In addition, each Deep Color mode is supported up to 1080p HD format.
For Deep Color modes, the TMDS clock is run faster than the pixel clock in order to create extra bandwidth for the
additional bits of the higher color depth data. The increase in the TMDS clock is by the ratio of the pixel size to 24 bits,
as follows:
 30-bit mode: TMDS clock = 1.25x pixel clock (5:4)
 36-bit mode: TMDS clock = 1.5x pixel clock (3:2)
Because the receiver supports 36-bit mode at 1080p, the highest TMDS clock rate it supports is therefore 225 MHz.
When in Deep Color mode, the transmitter periodically sends a General Control Packet with the current color depth
and pixel packing phase information to the receiver. The receiver captures the color depth information in a register,
which the firmware can then use to set the appropriate clock divider to recover the pixel clock and data.
3.3.4. xvYCC
The SiI9127A/SiI1127A receiver adds support for the extended gamut xvYCC color space; this extended format has
roughly 1.8 times more colors than the RGB color space. The use of the xvYCC color space is made possible because of
the availability of LED and laser based light sources for the next generation displays. This format also makes use of the
full range of values 1 to 254 in an 8-bit space instead of 16 to 235 in the RGB format. The use of xvYCC along with Deep
Color helps in reducing color banding and allows display of a larger range of colors than is currently possible.
3.3.4.1. Color Space Conversion
Color space converter (CSC) blocks are provided to convert RGB data to Standard-Definition (ITU.601) or HighDefinition (ITU.709) YCbCr formats, and vice-versa. To support the latest extended-gamut xvYCC displays, the
SiI9127A/SiI1127A receiver implements color space converter blocks to convert RGB data to extended-gamut StandardDefinition (ITU.601) or High-Definition (ITU.709) xvYCC formats, and vice-versa.
RGB to YCbCr
The RGBYCbCr color space converter (CSC) can convert from video data RGB to standard definition (ITU.601) or to
high definition (ITU.709) YCbCr formats. The HDMI AVI packet defines the color space of the incoming video.
YCbCr to RGB
The YCbCrRGB color space converter is available to interface to MPEG decoders with RGB-only inputs. The CSC can
convert from YCbCr in standard-definition (ITU.601) or high-definition (ITU.709) to RGB.
3.4.
3D Video Formats
The SiI9127A/SiI1127A receiver has support for the 3D video modes described in the HDMI 1.4 Specification. All modes
support RGB 4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 color formats and 8-, 10-, and 12-bit data width per color component.
Table 3.2 on the next page shows only the maximum possible resolution with a given frame rate; for example, Side-bySide (Half) mode is defined for 1080p60, which implies that 720p60 and 480p60 are also supported. Furthermore, a frame
rate of 24 Hz also means that a frame rate of 23.98 Hz is supported and a frame rate of 60 Hz also means a frame rate of
59.94 Hz is supported. The input pixel clock changes accordingly.
When using Side-by-Side formats the use of 4:2:2 to 4:4:4 up-sampling and 4:4:4 to 4:2:2 down-sampling should not be
enabled as it may result in visible artifacts.
Video processing should be bypassed in the case of L + depth format.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
13
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Table 3.2. Supported 3D Video Formats
3D Format
Extended Definition
Resolution
—
Frame Packing
interlaced
L + depth
—
full
Side-by-Side
half
Frame Rate (Hz)
1080p
24
720p
50 / 60
1080i
50 / 60
1080p
24
720p
50 / 60
1080p
24
720p
50 / 60
1080p
50 / 60
1080i
50 / 60
Input Pixel Clock (MHz)
148.5
74.25
Default Video Configuration
After hardware reset, the SiI9127A/SiI1127A chip is configured in its default mode. This mode is summarized in
Table 3.3. For more details and for a complete register listing, refer to the SiI-PR-1033 Programmer Reference.
Table 3.3. Default Video Processing
Video Control
Default after Hardware Reset
HDCP Decryption
Color Space Conversion
Color Space Selection
HDCP decryption is OFF
No color space conversion
BT.601 selected
Color Range Scaling
Upsampling/Downsampling
No range scaling
No upsampling or downsampling
HSYNC & VSYNC Timing
Data Bit Width
Pixel Clock Replication
No inversions of HSYNC or VSYNC
Uses 8-bit data
No pixel clock replication
Power Down
Everything is powered down
Notes:
1. The receiver assumes DVI mode after reset, which is RGB 24-bit 4:4:4 video with a range of 0–255.
2. HDCP decryption is not supported on the SiI1127A receiver.
TMDS
HDCP
Widen to
14-Bits
bypass
RGB to
YCbCr
YCbCr
Range
Reduce
bypass
bypass
Upsample
4:2:2 to
4:4:4
xvYCC/
YCbCr to
RGB
bypass
bypass
Down
Sample
4:4:4 to
4:2:2
RGB
Range
Expand
Dither
Module
Mux
656
Video
Timing
DE
HSYNC
bypass
VSYNC
Note: HDCP decoding does not apply to the SiI1127A receiver.
ODCK
Q[35:0]
Figure 3.3. Default Video Processing Path
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
14
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
3.4.1. Automatic Video Configuration
The SiI9127A/SiI1127A receiver adds automatic video configuration to simplify the firmware task of updating the video
path whenever the incoming video changes format. Bits in the HDMI Auxiliary Video Information (AVI) InfoFrame are
used to reprogram the registers in the video path.
Table 3.4. AVI InfoFrame Video Path Details
AVI Byte 1 Bits [6:5]
AVI Byte 2 Bits [7:6]
Y[1:0]
00
Color Space
RGB 4:4:4
C[1:0]
00
01
10
YCbCr 4:2:2
YCbCr 4:4:4
01
10
11
Future
11
AVI Byte 5 Bits [3:0]
Colorimetric
No Data
ITU 601
ITU 709
Extended Colorimetry
Information Valid
Notes:
1. The Auto Video Configuration assumes that the AVI information is accurate. If
information is not available, then the receiver must choose the video path
based on measurement of the incoming resolution.
2. Refer to EIA/CEA-861D Specification for details.
3. The SiI9127A/SiI1127A device can support only pixel replication modes
0b0000, 0b0001, and 0b0011. Other modes are unsupported and can result in
an unpredictable behavior.
PR[3:0]
0000
Pixel Repetition
No repetition
0001
0010
Pixel sent 2 times
Pixel sent 3 times
0011
Pixel sent 4 times
0100
Pixel sent 5 times
0101
0110
0111
Pixel sent 6 times
Pixel sent 7 times
Pixel sent 8 times
1000
Pixel sent 9 times
1001
Pixel sent 10 times
The format of the digital video output bus can be automatically configured to many different formats by programming
the Auto Output Format Register. The available formats are listed in Table 3.5. For detailed definitions of how to set
this register, refer to the SiI-PR-1033 Programmer Reference.
Table 3.5. Digital Output Formats Configurable through Auto Output Format Register
Digital Output Formats
Color
RGB
YCbCr
Width
4:4:4
4:4:4
MUX
N
N
Sync
Separate
Separate
YCbCr
YCbCr
4:2:2
4:2:2
N
Y
Separate
Separate
YCbCr
4:2:2
Y
Embedded
3.5.
Audio Data Output Logic
2
The SiI9127A/SiI1127A receiver can send digital audio over S/PDIF and two-channel I S outputs.
3.5.1. S/PDIF
The S/PDIF stream can carry 2-channel uncompressed PCM data (IEC 60958). The audio data output logic forms the
audio data output stream from the decoded HDMI audio packets. The S/PDIF output supports audio sampling rates
from 32 kHz to 192 kHz. A separate master clock output (MCLK), coherent with the S/PDIF output, is provided for timestamping purposes. Coherent means that the MCLK and S/PDIF are created from the same clock source.
3.5.2. I2S
2
2
2
The I S bus format is programmable through registers, to allow interfacing with I S audio DACs or audio DSPs with I S
2
inputs. Refer to the SiI-PR-1033 Programmer Reference for the different options on the I S bus. Additionally, the MCLK
(audio master clock) frequency is selectable to be an integer multiple of the audio sample rate F s.
MCLK frequencies support various audio sample rates as shown in Table 3.6 on the next page.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
15
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Table 3.6. Supported MCLK Frequencies
2
Multiple of Fs
Audio Sample Rate, Fs: I S and S/PDIF Supported Rates
128
192
32 kHz
4.096 MHz
6.144 MHz
44.1 kHz
5.645 MHz
8.467 MHz
48 kHz
6.144 MHz
9.216 MHz
88.2 kHz
11.290 MHz
16.934 MHz
96 kHz
12.288 MHz
18.432 MHz
176.4 kHz
22.579 MHz
33.868 MHz
192 kHz
24.576 MHz
36.864 MHz
256
384
8.192 MHz
12.288 MHz
11.290 MHz
16.934 MHz
12.288 MHz
18.432 MHz
22.579 MHz
33.864 MHz
24.576 MHz
36.864 MHz
45.158 MHz
49.152 MHz
512
16.384 MHz
22.579 MHz
24.576 MHz
45.158 MHz
49.152 MHz
3.6.
Control and Configuration
3.6.1. Register/Configuration Logic
The Register/Configuration Logic block incorporates all the registers required for configuring and managing the
features of the SiI9127A/SiI1127A receiver. These registers are used to perform HDCP authentication; audio, video, or
auxiliary format processing; CEA-861B InfoFrame Packet format; and power-down control.
The registers are accessible from one of the two serial ports. The first port is the DDC port, which is connected through
the HDMI cable to the HDMI host. It is used to control the receiver from the host system for HDCP operation. The
2
second port is the local I C port, which is used to control the receiver from the display system. This is shown in
Figure 3.4. The Local Bus accesses the General Registers and the Common Registers. The DDC Bus accesses the HDCP
Operation registers and the Common Registers. The HDCP Operation registers are not applicable to the SiI1127A
receiver.
Accessible
from DDC
Bus
HDCP Operation
Common Registers
General Registers
Video Processing
Audio Processing
InfoFrames
Accessible
from Local
I2C Bus
Repeater
Interrupts
2
Figure 3.4. I C Register Domains
3.6.2. I2C Serial Ports
2
The SiI9127A/SiI1127A receiver provides three I C serial interfaces: two DDC ports to communicate back to the HDMI
2
or DVI hosts, along with one I C port for initialization and control by a local microcontroller in the display. Each
interface is 5 V tolerant.
E-DDC Bus Interface to HDMI Host
The two DDC interfaces, DSDA1-2 and DSCL1-2, on the receiver are slave interfaces that can run up to 100 kHz. Each
interface is connected to one E-DDC bus and is used for reading the integrated EDID in addition to HDCP
authentication.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
16
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
The SiI9127A/SiI1127A receiver is accessible on the E-DDC bus at device addresses 0xA0 for the EDID, and 0x74 for
HDCP control. This feature complies with the HDCP Specification.
3.6.3. EDID FLASH and RAM Block
The EDID block consists of 512 bytes of RAM. Each port has a block of 256 bytes of RAM for EDID data. This feature
allows simultaneous reads of both ports from two different source devices that are connected to the SiI9127A/SiI1127A
device.
In addition to the RAM, the EDID block contains 256 bytes of FLASH that is shared by both ports. As a result, the timing
information must be identical between both ports if the internal EDID is used. An additional area of FLASH contains
unique CEC physical address and checksum values for each of the ports. This feature allows simultaneous reads of both
ports from two different source devices if they are connected and attempt an EDID read at the same time. If
independent EDIDs are required on any of the ports, a CPU can externally load the 256 bytes of RAM for that port, by
2
using the local I C bus.
2
The internal EDID can be selected on a per-port basis using registers on the local I C bus. For example, Port 1 can use
the internal EDID, and Port 2 can use a discrete EEPROM for the EDID.
3.6.4. CEC Interface
The Consumer Electronics Control (CEC) Interface block provides CEC electrically compliant signals between CEC
devices and a CEC master. It allows products to meet the electrical specifications of CEC signaling by translating the
LVTTL signals of an external microcontroller (CEC host-side or transmit-side) to CEC signaling levels for CEC devices at
the receive side, and vice versa.
Additionally, a CEC controller compatible with the Lattice Semiconductor CEC Programming Interface (CPI) is included
2
on-chip. This CEC controller has a high-level register interface accessible through the I C interface which can be used to
send and receive CEC commands. This controller makes CEC control very easy and straightforward, and removes the
burden of having a host CPU perform these low-level transactions on the CEC bus. As a result, CEC pass-through mode
is neither required nor supported.
2
I C Interface to Display Controller
2
The Controller I C interface (CSDA, CSCL) on the SiI9127A/SiI1127A receiver is a slave interface capable of running up to
400 kHz. This bus is used to configure the chip by reading or writing to the appropriate registers. It is accessible on the
2
local I C bus at two device addresses. Refer to the SiI-PR-1033 Programmer Reference for more information.
3.6.5. Standby and HDMI Port Power Supplies
The receiver incorporates a power island that continues to supply power to the EDID memory, the DDC ports, and the
CEC bus when power is removed from the VCC pins, as long as power continues to be provided through at least one
connected HDMI cable or by system standby power. Refer to Figure 3.5 on the next page. The internal power
multiplexer selects power from either SBVCC5, if it is available, or from one of the RnPWR5V pins.
The power island results in an extremely low power standby mode, but allows the EDID to be readable and the CEC
controller to be functional. No damage will occur to the device when in this mode.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
17
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
System Main 5 V
System Standby 5 V
HDMI Port
RnRPWR5V
Regulator
SBVCC5
+3.3 V
Power-On
Reset
Power MUX
DDC
I2C
Logic
On-Chip Regulator
+1.2 V
+3.3 V
CEC Logic
Main Chip Logic
EDID
RAM
+3.3 V
On-Chip Regulator
NV
Memory
+1.2 V
OTP
ROM
Power Island
Figure 3.5. Power Island
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
18
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
4. Electrical Specifications
4.1.
Absolute Maximum Conditions
Symbol
IOVCC33
AVCC12
Parameter
I/O Pin Supply Voltage
TMDS Analog Supply Voltage
Min
–0.3
–0.3
Typ
—
—
Max
4.0
1.9
Units
V
V
Note
1, 2, 3
1, 2
AVCC33
APVCC12
TMDS Analog Supply Voltage
Audio PLL Supply Voltage
–0.3
–0.3
—
—
4.0
1.9
V
V
1, 2
1, 2
CVCC12
XTALVCC33
SBVCC5
Digital Core Supply Voltage
ACR PLL Crystal Oscillator Supply Voltage
Standby Supply Voltage
–0.3
–0.3
–0.3
—
—
—
1.9
4.0
5.7
V
V
V
1, 2
1, 2
1,2
VI
V5V-Tolerant
Input Voltage
Input Voltage on 5 V tolerant Pins
–0.3
–0.3
—
—
IOVCC33 + 0.3
5.5
V
V
1, 2
5
TJ
Junction Temperature
—
—
125
C
—
Storage Temperature
–65
—
150
—
C
Notes:
1. Permanent device damage can occur if absolute maximum conditions are exceeded.
2. Functional operation should be restricted to the conditions described in the Normal Operating Conditions section on page 20.
3. Voltage undershoot or overshoot cannot exceed absolute maximum conditions.
4. Refer to the SiI9127A/SiI1127A receiver Qualification Report for information on ESD performance.
5. All VCC supplies must be available to the device. If the device is not powered and 5 V is applied to these inputs, damage can
occur.
TSTG
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
19
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
4.2.
Normal Operating Conditions
Symbol
IOVCC33
AVCC12
Parameter
I/O Pin Supply Voltage
TMDS Analog Supply Voltage
Min
3.13
1.14
Typ
3.3
1.2
Max
3.47
1.26
Units
V
V
Note
1, 4
3
AVCC33
APVCC12
TMDS Analog Supply Voltage
Audio PLL Supply Voltage
3.13
1.14
3.3
1.2
3.47
1.26
V
V
1, 6
—
CVCC12
XTALVCC33
SBVCC5
Digital Core Supply Voltage
ACR PLL Crystal Oscillator Supply Voltage
Standby Supply Voltage
1.14
3.13
4.75
1.2
3.3
5.0
1.26
3.47
5.25
V
V
V
2
4
10
RnPWR5V
DIFF33
DIFF12
DDC I C I/O Reference Voltage
Difference between two 3.3-V Power Pins
Difference between two 1.2-V Power Pins
4.7
—
—
5.00
—
—
5.3
1.0
1.0
V
V
V
11
4
4
DIFF3312
VCCN
Difference between any 3.3-V and 1.2-V Pin
Supply Voltage Noise
–1.0
—
—
—
2.6
100
V
mVP-P
4, 5
7
TA
Ambient Temperature (with power applied)
0
25
70
C
—
2
—
ja
C/W
Notes:
1. IOVCC33 and AVCC33 pins should be controlled from one power source.
2. CVCC12 should be controlled from one power source.
3. AVCC12 pin should be regulated.
4. Power supply sequencing must guarantee that power pins stay within these limits of each other. See Figure 5.2.
5. No 1.2 V pin can be more than DIFF3312[min] higher than any 3.3 V pin. No 3.3 V pin can be more than DIFF3312[max] higher
than any 1.2 V pin.
6. The HDMI Specification requires termination voltage (AVCC33) to be controlled to 3.3 V±5%. The SiI9127A/SiI1127A receiver
tolerates a wider range of ±300 mV.
7. The supply voltage noise is measured at test point VCCTP in Figure 4.1. The ferrite bead provides filtering of power supply noise.
The figure is representative and applies to other VCC pins as well.
8. Airflow at 0 m/s.
9. The schematics on page 65 show decoupling and power supply regulation.
10. SBVCC5V should provide a stable 5 V before any other VCC is applied to the device; see the Power Supply Sequencing section
on page 28.
11. Maximum current draw from this source is 50 mA. There is no power-on sequence requirement for this source.
Ambient Thermal Resistance (Theta JA)
—
—
27
VCCT
P
Parasitic
Resistor
Ferrite
AVCC12
0. 56 
0.1 F
0. 82 H,
150 mA
+
10 F
0.1 F
1 nF
SiI9127A/
SiI1127A
GND
Figure 4.1. Test Point VCCTP for VCC Noise Tolerance Specification
Notes:
1. The Ferrite (0.82 H, 150 mA) attenuates the PLL power supply noise at 10 kHz and above.
2. The optional parasitic resistor minimizes the peaking. The typical value used here is 0.56 . 1  is the maximum.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
20
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
4.3.
DC Specifications
4.3.1. Digital I/O Specifications
Symbol
VIH
VIL
Parameter
HIGH-level Input Voltage
LOW-level Input Voltage
LOW to HIGH Threshold
RESET # Pin
HIGH to LOW Threshold
RESET# Pin
VTH+
VTH-
Pin Type
LVTTL
LVTTL
3
Conditions
—
—
2
Min
2.0
—
Typ
—
—
Max
—
0.8
Units
V
V
Note
—
—
Schmitt
—
1.46
—
—
V
5
Schmitt
—
—
—
0.96
V
5
DDC VTH+
LOW to HIGH Threshold
DSDA0, DSDA1, DSCL0, and
DSCL1 pins.
Schmitt
—
3.0
—
—
V
—
DDC VTH-
HIGH to LOW Threshold
DSDA0, DSDA1, DSCL0, and
DSCL1 pins.
Schmitt
—
—
—
1.5
V
—
LOW to HIGH Threshold
CSCL and CSDA pins
Schmitt
—
2.1
—
—
V
11, 13
Local I C VTH-
HIGH to LOW Threshold
CSCL and CSDA pins
Schmitt
—
—
—
0.86
V
11, 13
VOH
HIGH-level Output Voltage
LVTTL
—
2.4
—
—
V
10
VOL
LOW-level Output Voltage
LVTTL
—
—
—
0.4
V
10
IOL
Output Leakage Current
—
High Impedance
–10
—
10
—
VID
Differential Input Voltage
—
—
75
250
780
A
mV
VOUT = 2.4 V
VOUT = 0.4 V
4
4
—
—
—
—
mA
mA
1, 6, 7
1, 6, 7
VOUT = 2.4 V
VOUT = 0.4 V
VOUT = 2.4 V
8
8
12
—
—
—
—
—
—
mA
mA
mA
1, 6, 8
1, 6, 8
1, 6, 9
2
Local I C VTH+
2
4
IOD4
4 mA Digital Output Drive
Output
IOD8
8 mA Digital Output Drive
Output
IOD12
12 mA Digital Output Drive
Output
RPD
Internal Pull Down Resistor
Outputs
VOUT = 0.4 V
IOVCC33 = 3.3 V
12
25
—
50
—
110
mA
kΩ
1, 6, 9
1, 12
IOPD
Output Pull Down Current
Outputs
IOVCC33 = 3.6 V
—
60
90
A
1, 12
IIPD
Input Pull Down Current
Input
IOVCC33 = 3.6 V
—
60
90
A
1
Notes:
1. These limits are guaranteed by design.
2. Under normal operating conditions unless otherwise specified, including output pin loading CL = 10 pF.
3. See the Pin Descriptions section on page 36 for pin type designations for all package pins.
4. Differential input voltage is a single-ended measurement, according to DVI Specification.
5. Schmitt trigger input pin thresholds VTH+ and VTH- correspond to VIH and VIL, respectively.
6. Minimum output drive specified at ambient = 70 C and IOVCC33 = 3.0 V. Typical output drive specified at ambient = 25 C and
IOVCC33 = 3.3 V. Maximum output drive specified at ambient = 0 C and IOVCC33 = 3.6 V.
7. IOD4 Output applies to pins SPDIF, SCK, WS, SD[3:0], DCLK, INT, and CSDA.
8. IOD8 Output applies to pins DE, HSYNC, VSYNC, Q[35:0].and MCLK.
9. IOD12 Output applies to pin ODCK.
10. Note that the S/PDIF output drives LVTTL levels, not the low-swing levels defined by IEC958.
11. The SCL and SDA pins are not true open-drain buffers. When no VCC is applied to the chip, these pins can continue to draw a
2
small current, and prevent the master IC from communicating with other devices on the I C bus. Therefore, do not power-down
2
the SiI9127A/SiI1127A receiver (remove VCC) unless the attached I C bus is completely idle.
12. The chip includes an internal pull-down resistor on many of the output pins. When in the high-impedance state, these pins
draw a pull- down current according to this specification when the signal is driven HIGH by another source device.
2
13. With –10% IOVCC33 supply, the HIGH-to-LOW threshold on DDC and I C bus is marginal. A –5% tolerance on the IOVCC33
power supply is recommended.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
21
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
4.3.2. DC Power Supply Pin Specifications
Total Power versus Power-Down Modes
3
Symbol
Parameter
IPDQ3
Complete
Power-Down
Current
IPDS
Sleep Powerdown Current
ISTBY
Standby
Current
IUNS
Unselected
Current
ICCTD
Full Power
Digital Out
Current
Typ
1.2 V
4
Max
1.2 V
Mode
Frequency
A
—
65
3
B
C
D
E
3.3 V
SBVCC5
3.3 V
Units
Notes
8
mA
1, 6
SBVCC5
27 MHz
68
15
8
mA
74.25 MHz
150 MHz
225 MHz
85
74
74
19
19
19
8
8
8
mA
mA
mA
27 MHz
74.25 MHz
0
0
0
0
8
8
mA
mA
150 MHz
225 MHz
27 MHz
67
111
8
0
0
68
0
0
119
8
8
8
mA
mA
mA
74.25 MHz
150 MHz
225 MHz
70
75
78
173
291
313
8
8
8
72
79
79
180
299
315
8
8
8
mA
mA
mA
27 MHz
74.25 MHz
97
158
112
175
8
8
102
167
121
177
8
8
mA
mA
150 MHz
225 MHz
259
335
295
321
8
8
280
366
302
326
8
8
mA
mA
2, 7
2, 8
2, 9
2, 10
Notes:
1. Power is not related to input TMDS clock (RxC) frequency because the selected TMDS port is powered down.
2. Power is related to input TMDS clock (RxC) frequency at the selected TMDS port. Only one port can be selected.
3. Typical power specifications measured with supplies at typical normal operating conditions, and a video pattern that combines
gray scale, checkerboard and text.
4. Maximum power limits measured with supplies at maximum normal operating conditions, minimum normal operating ambient
temperature, and a video pattern with single-pixel vertical lines.
5. Registers are always accessible on local I2C (CSDA/CSCL) without active link clock.
6. Power Down Mode A: Minimum power. Everything is powered off. Host sees no termination of TMDS signals on either TMDS
port. I2C access is still available.
7. Power Down Mode B: Powers down TMDS core. CKDT remains enabled and state can be polled in register. Host device can
sense TMDS termination.
8. Power Down Mode C: Power off to 3.3 V and 1.2 V supplies. Power on to SBVCC5 standby supply.
9. Power Down Mode D: Monitor SCDT on selected TMDS port with outputs in the high-impedance state. HDCP continues in the
selected port, but the output of the receiver can be connected to a shared bus.
10. Digital Functional Mode E: Full operation on one port with digital outputs.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
22
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Power Down Mode Definitions
Mode
3.3 V
Supply
1.2 V
Supply
SBVCC5
PDTOT#
Register Bit States
PD_TMDS# PD_AO#
PD_VO#
A
Power
Down
ON
ON
ON
0
1
1
1
B
Sleep
Mode
Power
ON
ON
ON
1
0
1
1
C
Standby
Power
OFF
OFF
ON
1
1
1
1
D
Unselected
Power
ON
ON
ON
1
1
0
0
E
Digital
ON
ON
ON
1
1
1
1
Description
Minimum power. Everything is
powered off. Host sees no
termination of TMDS signals on
2
either TMDS port. I C access is
still available.
Powers down TMDS core. CKDT
remains enabled and state can
be polled in register. Host
device can sense TMDS
termination.
Power off to 3.3 V and 1.2 V
supplies. Power on to SBVCC5
standby supply.
Monitor SCDT on selected
TMDS port with outputs in the
high-impedance state. HDCP
continues in the selected port,
but the output of the receiver
can be connected to a shared
bus.
Full operation on one port with
digital outputs.
Notes:
1. PD Clks include PD_MCLK#, PD_XTAL#, PD_APLL#, and PD_PCLK# all set to zero.
2. PD Outs include PD_AO#, and PD_VO# all set to zero.
3. Refer to the SiI-PR-1033 Programmer Reference for register bit descriptions. The Programmer Reference requires an NDA with
Lattice Semiconductor.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
23
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
4.4.
AC Specifications
TMDS Input Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
TDPS
Intra-Pair Differential Input Skew
—
—
—
TBIT
ps
—
2, 4
TCCS
Channel to Channel Differential
Input Skew
—
—
—
TCIP
ns
Figure 5.1
2, 3
FRXC
Differential Input Clock Frequency
—
25
—
225
MHz
—
—
TRXC
Differential Input Clock Period
—
4.44
—
40
ns
—
—
TIJIT
Differential Input Clock Jitter
tolerance (0.3 Tbit)
74.25 MHz
—
—
400
ps
—
2, 5, 6
Notes:
1. Under normal operating conditions unless otherwise specified, including output pin loading of C L = 10 pF.
2. Guaranteed by design.
3. IDCK Period. Refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet.
4. 1/10 of IDCK Period. Refer to the applicable Lattice Semiconductor HDMI Transmitter Data Sheet.
5. Jitter as defined by the HDMI Specification.
6. Jitter measured with Clock Recovery Unit per HDMI Specification. Actual jitter tolerance can be higher depending on the
frequency of the jitter.
Refer to the SiI-PR-1033 Programmer Reference for more details on controlling timing modes.
4.4.1. Video Output Timings
12/15/18-Bit Data Output Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
DLHT
LOW-to-HIGH Rise Time Transition
CL = 10 pF
—
—
1.5
ns
Figure 5.4
2
DHLT
HIGH-to-LOW Fall Time Transition
CL = 10 pF
—
—
1.5
ns
Figure 5.4
2
RCIP
ODCK Cycle Time
CL = 10 pF
13
—
40
ns
Figure 5.5
8
FCIP
ODCK Frequency
CL = 10 pF
25
—
82.5
MHz
—
5
TDUTY
ODCK Duty Cycle
CL = 10 pF
40%
—
60%
RCIP
Figure 5.5
3
TCK2OUT
ODCK-to-Output Delay
CL = 10 pF
0.6
—
3.8
ns
Figure 5.5
—
16/20/24/30/36-Bit Data Output Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
DLHT
LOW-to-HIGH Rise Time Transition
CL = 10 pF
—
—
1.5
ns
Figure 5.4
2
DHLT
HIGH-to-LOW Fall Time Transition
CL = 10 pF
—
—
1.5
ns
Figure 5.4
2
RCIP
ODCK Cycle Time
CL = 10 pF
—
—
40
ns
Figure 5.5
5, 8
FCIP
ODCK Frequency
CL = 10 pF
—
—
165
MHz
Figure 5.5
5
TDUTY
ODCK Duty Cycle
CL = 10 pF
40%
—
60%
RCIP
Figure 5.5
3
TCK2OUT
ODCK-to-Output Delay
CL = 10 pF
0.4
—
2.5
ns
Figure 5.5
—
Notes:
1. Under normal operating conditions unless otherwise specified, including output pin loading of C L = 10 pF.
2. Rise time and fall time specifications apply to HSYNC, VSYNC, DE, ODCK, EVNODD and Q[35:0].
3. Output clock duty cycle is independent of the differential input clock duty cycle. Duty cycle is a component of output setup and
hold times.
4. See Table 5.2 on page 33 for calculation of worst case output setup and hold times.
5. All output timings are defined at the maximum operating ODCK frequency, FCIP, unless otherwise specified.
6. FCIP can be the same as FRXC or one-half of FRXC, depending on OCLKDIV setting. FCIP can also be FRXC /1.25 or FRXC /1.5 if Deep
Color mode is being transmitted.
7. RCIP is the inverse of FCIP and is not a controlling specification.
8. Output skew specified when ODCK is programmed to divide-by-two mode.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
24
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
4.4.2. Audio Output Timings
I2S Output Port Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Ttr
SCK Clock Period (TX)
CL = 10 pF
1.00
—
—
Ttr
1
THC
SCK Clock HIGH Time
CL = 10 pF
0.35
—
—
Ttr
1
TLC
SCK Clock LOW Time
CL = 10 pF
0.35
—
—
Ttr
1
TSU
Setup Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
THD
Hold Time, SCK to SD/WS
CL = 10 pF
0.4TTR – 5
—
—
ns
1
TSCKDUTY
SCK Duty Cycle
CL = 10 pF
40%
—
60%
Ttr
1
TSCK2SD
SCK to SD or WS Delay
CL = 10 pF
–5
—
+5
ns
2
TAUDDLY
Audio Pipeline Delay
—
—
40
80
µs
Figure 5.6
Notes
1
—
—
Figure
Notes
Notes:
2
1. Refer to Figure 5.6. Meets timings in Philips I S Specification.
2. Applies also to SDC-to-WS delay.
S/PDIF Output Port Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
TSPCYC
S/PDIF Cycle Time
CL = 10 pF
—
1.0
—
UI
FSPDIF
S/PDIF Frequency
—
4
—
24
MHz
TSPDUTY
S/PDIF Duty Cycle
CL = 10 pF
90%
—
110%
UI
2, 5
TMCLKCYC
MCLK Cycle Time
CL = 10 pF
20
—
250
ns
1, 2, 4
FMCLK
MCLK Frequency
CL = 10 pF
4
—
50
MHz
TMCLKDUTY
MCLK Duty Cycle
CL = 10 pF
40%
—
60%
TMCLKCYC
TAUDDLY
Audio Pipeline Delay
—
—
40
80
µs
1, 2
Figure 5.7
Figure 5.8
3
1, 2, 4
2, 4
—
—
Notes:
1. Guaranteed by design.
2. Proportional to unit time (UI), according to sample rate.
3. S/PDIF is not a true clock, but is generated from the internal 128Fs clock, for Fs from 128 to 512 kHz.
4. MCLK refers to MCLKOUT.
5. Intrinsic jitter on S/PDIF output can limit its use as an S/PDIF transmitter. The S/PDIF intrinsic jitter is approximately 0.1 UI.
Audio Crystal Timings
Symbol
Parameter
FXTAL
External Crystal Freq.
Conditions
Min
Typ
Max
Units
Figure
—
26
27
28.5
MHz
Figure 4.2
3.3 V
3
5
27 MHz
XTALVCC
XTALIN
SiI9127A/
SiI1127A
1 M
18pF
4
XTALOUT
18 pF
Figure 4.2. Audio Crystal Schematic
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
25
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
4.4.3. Miscellaneous Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
TI2CDVD
SDA Data Valid delay from SCL falling edge
CL = 400 pF
—
—
700
ns
—
—
FDDC
Speed on TMDS DDC Ports
CL = 400 pF
—
—
100
kHz
—
2
CL = 400 pF
—
—
400
kHz
—
3
FI
2
C
2
Speed on Local I C Port
TRESET
RESET# Signal LOW Time for valid reset
—
50
—
—
µs
Figure 5.3
—
TSTARTUP
Startup time from power supplies valid
—
—
—
100
ms
—
5
TBKSVINIT
HDCP BKSV Load Time
—
—
—
2.2
ms
—
4
Notes:
1. Under normal operating conditions unless otherwise specified, including output pin loading of CL = 10 pF.
2
2. DDC ports are limited to 100 kHz by the HDMI Specification, and meet I C standard mode timings.
2
2
3. Local I C port (CSCL/CSDA) meets standard mode I C timing requirements to 400 kHz.
4. The time required to load the KSV values internal to the receiver after a RESET# and the start of an active TMDS clock. An
attached HDCP host device should not attempt to read the receiver BKSV values until after this time. The TBKSVINIT Min and Max
values are based on the maximum and minimum allowable XCLK frequencies. The loading of the BKSV values requires a valid
XCLK and TMDS clock.
5. TSTARTUP is the startup time required for the device to be operational once power is stable. This startup time is due to the onboard voltage regulator for the EDID and CEC and a power-on reset circuit.
4.4.4. Interrupt Timings
Interrupt Output Pin Timings
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Figure
Notes
TFSC
Link disabled (DE inactive) to SCDT LOW
—
—
0.15
40
ms
Figure 4.3
1, 2, 3, 8
THSC
Link enabled (DE active) to SCDT HIGH
—
—
—
4
DE
Figure 4.3
1, 2, 4, 8
TCICD
RXC inactive to CKDT LOW
—
—
—
100
µs
Figure 4.3
1, 2, 8
TCACD
RXC active to CKDT HIGH
—
—
—
10
µs
Figure 4.3
1, 2, 8
TINT
Response Time for INT from Input Change
—
—
—
100
µs
—
1, 5, 8
TCIOD
RXC inactive to ODCK inactive
—
—
—
100
ns
—
1, 8
TCAOD
RXC active to ODCK active and stable
—
—
—
10
ms
—
1, 6, 8
TSRRF
Delay from SCDT rising edge to Software
Reset falling edge
—
—
—
100
ms
Figure 5.3
7
Notes:
1. Guaranteed by design.
2. SCDT and CKDT are register bits in this device.
3. SCDT changes to LOW after DE is HIGH for approximately 4096 pixel clock cycles, or after DE is LOW for approximately
1,000,000 clock cycles. At 27 MHz pixel clock, this delay for DE HIGH is approximately 150 µs, and the delay for DE LOW is
approximately 40 ms.
4. SCDT changes to HIGH when clock is active (TCACD) and at least 4 DE edges have been recognized. At 720p, the DE period is 22
µs, so SCDT responds approximately 50 µs after TCACD.
5. The INT pin changes state after a change in input condition when the corresponding interrupt is enabled.
6. Output clock (ODCK) becomes active before it becomes stable. Use the SCDT signal as an indicator of stable video output
timings, as this depends on decoding of DE signals with active RXC (see TFSC).
7. Software reset must be asserted and then de-asserted within the specified maximum time after rising edge of Sync Detect
2
(SCDT). Access to both SWRST and SCDT can be limited by the speed of the I C connection.
8. SCDT is HIGH only when CKDT is also HIGH. When the receiver is in a powered-down mode, the INT output pin indicates the
current state of SCDT. Thus, a powered-down receiver signals a microcontroller connected to the INT pin whenever SCDT
changes from LOW to HIGH or HIGH to LOW.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
26
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
RXC
link clock active
link clock inactive
link clock active
CKDT
TCICD
DE
TCACD
Do not Care
TFSC
THSC
SCDT
Figure 4.3. SCDT and CKDT Timing from DE or RXC Inactive/Active
Notes:
1. The SCDT shown in Figure 4.3 is a register bit. SCDT remains HIGH if DE is stuck in LOW while RXC remains active, but SCDT
changes to LOW if DE is stuck HIGH while RXC remains active.
2. The CKDT shown in Figure 4.3 is a register bit. CKDT changes to LOW whenever RXC stops, and changes to HIGH when RXC
starts. SCDT changes to LOW when CKDT changes to LOW.
3. SCDT changes to LOW when CKDT changes to LOW. SCDT changes to HIGH at T HSC after CKDT changes to HIGH.
4. The INT output pin changes state after the SCDT or CKDT register bit is set or cleared if those interrupts are enabled.
Refer to the SiI-PR-1033 Programmer Reference for more details on controlling timing modes. The Programmer
Reference requires an NDA with Lattice Semiconductor.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
27
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
5. Timing Diagrams
5.1.
TMDS Input Timing Diagrams
RX0
RX1
RX2
TCCS
VDIFF = 0V
Figure 5.1. TMDS Channel-to-Channel Skew Timing
5.2.
Power Supply Control Timings
5.2.1. Power Supply Sequencing
Power Off Sequence
Power On Sequence
DIFF33 max
maximum 3.3 V
excursion
IOVCC33
AVCC33
XTALVCC33
minimum 3.3 V
excursion
DIFF3312 max
maximum 3.3 V
excursion
IOVCC33
AVCC33
XTALVCC33
maximum 1.2 V
excursion
maximum 1.2 V
excursion
minimum 1.2 V
DIFF12 max
excursion
AVCC12
CVCC12
AVPCC12
DIFF33 max
minimum 3.3 V
excursion
DIFF3312 max
AVCC12
minimum 1.2 V
CVCC12
excursion
AVPCC12
To ensure proper power-on reset, 5 V should be provided to the SBVCC5 pin before
the power-on sequence shown here begins.
DIFF12 max
Figure 5.2. Power Supply Sequencing
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
28
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
5.3.
Reset Timings
VCCmax
RESET#
VCCmin
TRESET
VCC
RESET#
TRESET
Note that VCC must be stable between its limits for
Normal Operating Conditions for TRESET before RESET# is
HIGH.
RESET# must be pulled LOW for TRESET before accessing
registers. This can be done by holding RESET# LOW until
TRESET after stable power (at left), or by pulling RESET#
LOW from a HIGH state (at right) for at least TRESET.
Figure 5.3. RESET# Minimum Timings
5.4.
Digital Video Output Timing Diagrams
5.4.1. Output Transition Times
2.0 V
0.8 V
DLHT
2.0 V
0.8 V
DHLT
Figure 5.4. Video Digital Output Transition Times
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
29
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
5.4.2. Output Clock to Output Data Delay
T
CYC
TH
TL
OCLKINV = 0
ODCK
OCLKINV = 1
ODCK
T
CKO(max)
TCKO(min)
Q[35:0]
T CKO(max)
TCKO(min)
DE
HSYNC
VSYNC
Figure 5.5. Receiver Clock-to-Output Delay and Duty Cycle Limits
5.5.
Digital Audio Output Timings
TTR
TSCKDUTY
SCK
TSCK2SD_MAX
WS
SD
Data Valid
TSU
THD
Data Valid
TSCK2SD_MIN
Data Valid
Figure 5.6. I2S Output Timings
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
30
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
TSPCYC
T SPDUTY
50%
SPDIF
Figure 5.7. S/PDIF Output Timings
TMCLKCYC
MCLK
50%
50%
TMCLKDUTY
Figure 5.8. MCLK Timings
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
31
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
5.6.
Calculating Setup and Hold Times for Video Bus
5.6.1. 24/30/36-Bit Mode
Output data is clocked out on one rising or falling edge of ODCK, and is then captured downstream using the same
polarity ODCK edge one clock period later. The setup time of data to ODCK and hold time of ODCK to data are therefore
a function of the worst case ODCK to output delay, as shown in Figure 5.9. The active rising ODCK edge is shown with
an arrowhead. For OCK_INV = 1, reverse the logic.
TCK2OUT{max}
TSU
THD
TCK2OUT{min}
ODCK
Shortest
Clk-to-Out
Longest
Clk-to-Out
Q
DE
VSYNC
HSYNC
Data Valid
Data Valid
Figure 5.9. 24/30/36-Bit Mode Receiver Output Setup and Hold Times
Table 5.1 shows minimum calculated setup and hold times for commonly used ODCK frequencies. The setup and hold
times apply to DE, VSYNC, HSYNC, and Data output pins, with an output load of 10 pF. These are approximations. Hold
time is not related to ODCK frequency.
Table 5.1. Calculation of 24/30/36-Bit Output Setup and Hold Times
Mode
Symbol
Parameter
24/30/36Bit Mode
TSU
Setup Time to ODCK = TODCK – TCK2OUT{max}
THD
Hold Time from ODCK = TCK2OUT{min}
TODCK
Min
27 MHz
37.0 ns
34.5 ns
74.25 MHz
13.5 ns
11.0 ns
27 MHz
37.0 ns
0.4 ns
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
32
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
5.6.2. 12/15/18-Bit Dual-Edge Mode
Output data is clocked out on both the rising and falling edges of ODCK, and is then captured downstream using the
opposite ODCK edge. This is shown in Figure 5.10. The setup time of data to ODCK is a function of the shortest duty
cycle and the longest ODCK to output delay. The hold time does not depend on duty cycle since every edge is used, and
is a function only of the shortest ODCK to output delay.
TSU
THD
ODCK
TDUTY{min}
TCK2OUT{min}
TCK2OUT{max}
Q
DE
VSYNC
HSYNC
Data Valid
Data Valid
Figure 5.10. 12/15/18-Bit Mode Receiver Output Setup and Hold Times
Table 5.2 shows minimum calculated setup and hold times for commonly used ODCK frequencies, up to the maximum
allowed for 12/15/18-bit mode. The setup and hold times apply to DE, VSYNC, HSYNC, and Data output pins, with
output load of 10 pF. These are approximations. Hold time is not related to ODCK frequency.
Table 5.2. Calculation of 12/15/18-Bit Output Setup and Hold Times
Mode
12/15/18Bit Mode
Symbol
Parameter
TSU
Setup Time to ODCK
= TODCK • TDUTY{min} – TCK2OUT{max}
THD
Hold Time from ODCK = TCK2OUT{min}
TODCK
Min
27 MHz
37.0 ns
11 ns
74.25 MHz
13.5 ns
1.6 ns
27 MHz
37.0 ns
0.4 ns
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
33
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
5.7.
Calculating Setup and Hold Times for I2S Audio Bus
Valid serial data is available at Tsck2sd after the falling edge of the first SCK cycle, and then captured downstream using
the active rising edge of SCK one clock period later. The setup time of data to SCK (TSU) and hold time of SCK to data
(THD) are therefore a function of the worst case SCK-to-output data delay (Tsck2sd). Figure 5.6 illustrates this timing
relationship. The active SCK edge (rising edge) is shown with an arrowhead. For a falling edge sampling clock, the logic
is reversed.
Table 5.3 shows the setup and hold time calculation examples for various audio sample frequencies. The formula used
in these examples also applies when calculating the setup and hold times for other audio sampling frequencies.
2
Table 5.3. I S Setup and Hold Time Calculations
Symbol
TSU
THD
Parameter
Setup Time, SCK to SD/WS
= TTR – ( TSCKDUTY_WORST + TSCK2SD_MAX )
= TTR – (0.6TTR + 5 ns )
= 0.4TTR – 5 ns
Hold Time, SCK to SD/WS
= ( TSCKDUTY_WORST – TSCK2SD_MIN )
= 0.4TTR – 5 ns
FWS (kHz)
FSCLK (MHz)
Ttr
Min
32 kHz
2.048
488 ns
190 ns
44.1 kHz
2.822
354 ns
136 ns
48 kHz
3.072
326 ns
125 ns
96 kHz
6.144
163 ns
60 ns
192 kHz
12.288
81 ns
27 ns
32 kHz
2.048
488 ns
190 ns
44.1 kHz
2.822
354 ns
136 ns
48 kHz
3.072
326 ns
125 ns
96 kHz
6.144
163 ns
60 ns
192 kHz
12.288
81 ns
27 ns
Note: The sample calculations shown are based on WS = 64 SCLK rising edges.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
34
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
6. Pin Diagram and Descriptions
6.1.
Pin Diagram
CEC_D
25
26
27
SBVCC5
28
R1PWR5V
HPD1
29
30
DSCL1
DSDA1
NC
AVCC33
NC
NC
NC
NC
101
100
99
R1XC+
R1XCAVCC12
104
103
102
107
106
105
R1X1+
R1X1R1X0+
R1X0-
110
109
108
AVCC33
R1X2+
R1X2-
114
113
112
111
R2X0+
R2X0R2XC+
R2XC-
118
117
116
115
R2X2+
R2X2R2X1+
R2X1-
NC
NC
AVCC12
121
120
119
98
97
SD0
SCK
WS
IOVCC33
CVCC12
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
IOVCC33
CVCC12
Q9
Q10
Q11
CVCC12
IOVCC33
VSYNC
HSYNC
Q18
Q19
Q20
Q22
Q23
Q25
63
64
ODCK
60
61
62
65
DE
32
56
57
58
59
Q16
Q17
Q21
31
53
54
55
Q15
67
66
Q24
68
51
52
Q12
Q13
Q14
Q26
70
69
CVCC12
CEC_A
73
72
71
IOVCC33
CSDA
C12CA
48
49
50
INT
CSCL
77
76
75
74
21
22
23
24
Q27
RESET#
Q28
RSVDNC
Q29
RSVDNC
80
79
78
18
19
20
Q30
GPIO7
RSVDNC
43
44
45
46
47
GPIO6
84
83
82
81
SiI9127A/SiI1127A
(Top View)
Q31
GPIO5
14
15
16
17
Q32
GPIO4
Q33
GPIO2/EVNODD
11
12
13
40
41
42
GPIO1/SCDT
Q34
GPIO0/XCLKOUT
87
86
85
Q35
RSVDL
GND
RSVDL
90
89
88
8
9
10
RSVDNC
RSVDNC
91
RSVDNC
CVCC12
RSVDNC
RSVDNC
RSVDNC
DSCL2
IOVCC33
MCLK
93
92
DSDA2
XTALGND
94
4
5
6
7
33
34
35
36
37
38
39
XTALIN
96
95
HPD2
XTALOUT
GPIO3/MUTEOUT
SPDIF
1
2
3
R2PWR5V
APVCC12
XTALVCC33
124
123
122
RSVDNC
128
127
126
125
AVCC33
NC
NC
NC
Figure 6.1 shows the pin connections for the SiI9127A/SiI1127A receiver in the 128-pin TQFP package. Individual pin
functions are described in the Pin Descriptions section on the next page.
Figure 6.1. Pin Diagram
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
35
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
6.2.
Pin Descriptions
6.2.1. Digital Video Output Data Pins
Pin Name
Pin
Type
Q0
85
Q1
84
LVTTL
2 mA to 14 mA
Q2
83
Q3
82
Q4
81
Q5
80
Q6
79
Q7
78
Q8
77
Q9
74
Q10
73
Q11
72
Q12
71
Q13
70
Q14
69
Q15
68
Q16
67
Q17
66
Q18
59
Q19
58
Q20
57
Q21
56
Q22
55
Q23
54
Q24
53
Q25
52
Q26
51
Q27
48
Q28
47
Q29
46
Q30
45
Q31
44
Q32
43
Q33
42
Q34
41
Q35
40
Dir
Description
Output 36-Bit Output Pixel Data Bus.
Q[35:0] is highly configurable using the various video configuration registers. It
supports a wide array of output formats, including multiple RGB and YCbCr bus
formats. Using the appropriate bits in the PD_SYS2 register, the output drivers
can be put into a high impedance state.
Notes:
1. When transporting video data that uses fewer than 36 bits, the unused bits on the Q[] bus can still carry switching pixel data
signals. Unused Q[35:0] bus pins should be unconnected, masked, or ignored by downstream devices. For example, carrying
YCbCr 4:2:2 data with 16-bit width (see page 47), the bits Q[0] through Q[7] output switching signals.
2. The output data bus, Q[35:0], can be wire-ORed to another device so one device is always in high impedance state. However,
these pins do not have internal pull-up or pull-down resistors, and so cannot pull the bus HIGH or LOW when all connected
devices are in the high-impedance state.
3. The drive strength of Q[0:35] can be programmed in 2 mA steps between 2 mA and 14 mA.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
36
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
6.2.2. Digital Video Output Control Pins
Pin Name
Pin
Type
DE
60
LVTTL
2 mA to 14 mA
Output Data Enable.
HSYNC
62
LVTTL
2 mA to 14 mA
Output Horizontal Sync Output.
VSYNC
61
LVTTL
2 mA to 14 mA
Output Vertical Sync Output.
13
LVTTL
8 mA
GPIO2/
EVNODD
GPIO2/
EVNODD
ODCK
65
LVTTL
2 mA to 14 mA
Dir
Description
Input
Programmable GPIO2.
Output
Output Indicates Even or Odd Field for Interlaced Formats.
Output Output Data Clock.
Notes:
1. HSYNC and VSYNC outputs carry sync signals for both embedded and separate sync configurations.
2. The drive strength of DE, HSYNC, VSYNC, and ODCK can be programmed in 2 mA steps between 2 mA and 14 mA.
6.2.3. Digital Audio Output Pins
Pin Name
Pin
Type
Dir
XTALIN
4
5 V tolerant
LVTTL
Input
XTALOUT
3
LVTTL
4 mA
Output
Crystal Clock Output.
Input
Output
Programmable GPIO0.
11
LVTTL
4 mA
Output
Additional Clock Output from crystal oscillator circuit.
GPIO0/
XCLKOUT
GPIO0/
XCLKOUT
Description
Crystal Clock Input.
Also allows LVTTL input. Frequency required: 26–28.5 MHz.
MCLK
94
LVTTL
8 mA
Output
Audio Master Clock Output.
SCK
89
LVTTL
4 mA
Output
I S Serial Clock Output.
WS
88
LVTTL
4 mA
Output
I S Word Select Output.
SD0
90
LVTTL
4 mA
Output
I S Serial Data Output.
SPDIF
95
LVTTL
4 mA
Output
S/PDIF Audio Output.
Input
Output
Programmable GPIO3.
Output
Mute Audio Output.
Signal to the external downstream audio device, audio DAC, etc. to mute audio
output.
GPIO3/
MUTEOUT
GPIO3/
MUTEOUT
96
LVTTL
4 mA
2
2
2
Note: The XTALIN pin can either be driven at LVTTL levels by a clock (leaving XTALOUT unconnected), or connected through a crystal
to XTALOUT. Refer to the schematic on page 68.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
37
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
6.2.4. Configuration/Programming Pins
Pin Name
Pin
Type
INT
22
LVTTL
4 mA
RESET#
21
Schmitt
5 V tolerant
Dir
Description
Interrupt Output.
Configurable polarity and push-pull output. Multiple sources of interrupt can be
Output
enabled through the INT_EN register.
See note below.
Input
Reset Pin.
Active LOW.
Input
Configuration/Status I C Clock.
Chip configuration/status, CEA-861 support and downstream HDCP registers are
2
accessed via this I C port. True open drain, so does not pull to GND if power is
not applied.
2
23
Schmitt
5 V tolerant
24
Schmitt
5 V tolerant
3 mA
25
LVTTL
5 V tolerant
13
LVTTL
4 mA
Programmable GPIO1.
Output Sync Detection Indicator.
Indicates Active Video at HDMI Input Port.
GPIO4
14
LVTTL
4 mA
Input
Programmable GPIO4.
Output
GPIO5
15
LVTTL
4 mA
Input
Programmable GPIO5.
Output
GPIO6
16
LVTTL
4 mA
Input
Programmable GPIO6.
Output
GPIO7
17
LVTTL
4 mA
Input
Programmable GPIO7.
Output
CSCL
2
CSDA
Configuration/Status I C Data.
Input Chip configuration/status, CEA-861 support and downstream HDCP registers are
Output accessed via this I2C port. True open drain, so does not pull to GND if power is
not applied.
2
CI2CA
GPIO1/SCDT
GPIO1/SCDT
Input
Local I C Address Select.
LOW = Addresses 0x60/0x68
HIGH = Addresses 0x62/0x6A
Note: The INT pin can be programmed to be either a push-pull LVTTL output or an open-drain output.
6.2.5. HDMI Control Signal Pins
Pin Name
Pin
Type
Dir
DSCL1
DSCL2
31
35
Schmitt
Open drain
5 V tolerant
DSDA1
DSDA2
32
36
Schmitt
Open drain
5 V tolerant
3 mA
HPD1
HPD2
30
34
LVTTL
4 mA
Output
R1PWR5V
R2PWR5V
29
33
LVTTL
5 V tolerant
Input
CEC_A
26
CEC compliant
5 V tolerant
CEC_D
27
Schmitt
5 V tolerant
Description
2
Input
DDC I C Clock for respective port.
2
HDCP KSV, An and Ri values are exchanged over an I C port during
authentication. True open drain, so does not pull to GND if power is not applied.
2
DDC I C Data for respective port.
Input
2
HDCP KSV, An and Ri values are exchanged over an I C port during
Output
authentication. True open drain, so does not pull to GND if power is not applied.
Hot plug output signal to HDMI connector for respective port.
Indicates EDID is readable.
5 V power and port detection input for respective port.
Used to power internal EDID when device is not powered.
These pins require a 10 F capacitor to ground.
HDMI compliant CEC I/O used to interface to CEC devices.
Input
This pin connects to the CEC signal of all HDMI connectors in the system.
Output
This pin has an internal pull-up resistor.
Input CEC interface to local system. True open-drain. An external pull-up is required.
Output This pin typically connects to the local CPU.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
38
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
6.2.6. TMDS Differential Signal Pins
Pin Name
R1X0+
R1X0−
R1X1+
R1X1−
R1X2+
R1X2−
R1XC+
R1XC−
R2X0+
R2X0−
R2X1+
R2X1−
R2X2+
R2X2−
R2XC+
R2XC−
Pin
107
106
109
108
111
110
105
104
116
115
118
117
120
119
114
113
Type
Dir
Description
TMDS analog
Input
Port 1 TMDS input data pairs.
TMDS analog
Input
Port 1 TMDS input clock pair.
TMDS analog
Input
Port 2 TMDS input data pairs.
TMDS analog
Input
Port 2 TMDS input clock pair.
6.2.7. Power and Ground Pins
Pin Name
CVCC12
Pin
7, 49, 63, 75, 86
Type
Power
Description
Digital Logic VCC.
IOVCC33
AVCC33
AVCC12
6, 50, 64, 76, 87
97, 112, 127
103, 121
Power
Power
Power
Input/Output Pin VCC.
TMDS Analog VCC 3.3 V.
TMDS Analog VCC 1.2 V.
APVCC12
1
Power
XTALVCC33
2
Power
XTALGND
5
Ground
SBVCC5
28
Power
39, ePad (bottom of package)
Ground
GND
Audio Clock Regeneration PLL Analog VCC.
Must be connected to 1.2 V.
Audio Clock Regeneration PLL crystal oscillator
power.
Must be connected to 3.3 V.
Supply
1.2 V
3.3 V
3.3 V
1.2 V
1.2 V
3.3 V
Audio Clock Regeneration ground.
Standby power supply.
All other supplies can be off with SBVCC5 on.
This pin requires a 10 F capacitor to ground.
Ground
Ground. The ePad must be soldered to ground.
Ground
Description
Supply
5V
6.2.8. Reserved and Not Connected Pins
Pin Name
RSVDNC
RSVDL
NC
Pin
Type
8, 18–20, 37, 38, 91, 92, 93,
128
Reserved
Reserved, must be left unconnected.
9, 10
Reserved
Reserved, must be tied to ground.
98–102, 122–126
Not
Must be left unconnected.
connected
No
connection
Ground
No
connection
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
39
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7. Video Path
The SiI9127A/SiI1127A receiver accepts all valid HDMI input formats and can transform that video in a variety of ways
to produce the proper video output format. The following pages describe how to control the video path formatting and
how to assign output pins for each video output format. The processing blocks in Figure 7.1 correspond to those shown
in Figure 7.2 through Figure 7.4.
MCLK
SPDIF
Audio
Processing
TMDS
I2S Outputs
HDCP
WS
Widen to
14-Bits
InfoFrame
Packet
Processing
SD[3:0]
DSD Outputs
YCbCr
Range
Reduce
Down
Sample
4:4:4 to
4:2:2
bypass
bypass
bypass
Upsample
4:2:2 to
4:4:4
xvYCC/YCbCr
to
RGB
RGB
Range
Expand
RGB to YCbCr
bypass
SCK
bypass
Note: DSD outputs are
shared with SPDIF and I2S
signals
DCLK
DR[3:0]
DL[3:0]
DE
Dither
Module
Mux
656
Video
Timing
HSYNC
bypass
VSYNC
ODCK
Note: HDCP decoding does not apply to the SiI1127A receiver.
Q[35:0]
Figure 7.1. Receiver Video and Audio Data Processing Paths
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
40
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.1.
HDMI Input Modes to SiI9127A/SiI1127A Output Modes
The HDMI link supports transport of video in any of the three modes; RGB 4:4:4, YCbCr/xvYCC 4:4:4, or YCbCr/xvYCC
4:2:2. The flexible video path in the SiI9127A/SiI1127A receiver allows reformatting of video data to a set of output
modes. Table 7.1 lists the supported transformations and points to the figure for each. In every case, the HDMI link
itself carries separate syncs.
Table 7.1. Translating HDMI Formats to Output Formats
Digital Output Format
YCbCr 4:2:2
YCbCr 4:2:2
Separate Sync
Embedded Sync
HDMI Input Mode
RGB 4:4:4
Separate Sync
YCbCr 4:4:4
Separate Sync
RGB 4:4:4
YCbCr/xvYCC 4:4:4
Figure 7.2A
Figure 7.3A
Figure 7.2B
Figure 7.3B
Figure 7.2C
Figure 7.3C
YCbCr/xvYCC 4:2:2
Figure 7.4A
Figure 7.4B
Figure 7.4C
YC Mux
Separate Sync
YC Mux
Embedded Sync
Figure 7.2D
Figure 7.3D
Figure 7.2E
Figure 7.3E
Figure 7.2F
Figure 7.3F
Figure 7.4D
Figure 7.4E
Figure 7.4F
RGBtoYCbCr
RGB 4:4:4
TMDS and
HDCP
Decoding
RGBtoYCbCr
Color Range
Scaling
RGB 4:4:4
TMDS and
HDCP
Decoding
RGBtoYCbCr
Color Range
Scaling
RGB 4:4:4
TMDS and
HDCP
Decoding
RGBtoYCbCr
Color Range
Scaling
TMDS and
HDCP
Decoding
RGBtoYCbCr
YCbCr 4:4:4
Separate Syncs
RGB 4:4:4
TMDS and
HDCP
Decoding
Color Range
Scaling
YCbCr 4:2:2
Separate Syncs
Color Range
Scaling
DownSampling
Embedded
Syncs
YCbCr 4:2:2
Emb. Syncs
DownSampling
MUX YC
MUX YC 4:2:2
Separate Syncs
DownSampling
Down
Sampling
Embedded
Syncs
MUX YC
MUX YC 4:2:2
Emb. Syncs
RGB 4:4:4
TMDS and
HDCP
Decoding
RGB 4:4:4
RGB 4:4:4
7.1.1. HDMI RGB 4:4:4 Input Processing
Digital Out
A
Digital Out
B
Digital Out
C
Digital Out
D
Digital Out
E
Digital Out
F
Note: HDCP decoding does not apply to the SiI1127A receiver.
Figure 7.2. HDMI RGB 4:4:4 Input to Video Output Transformations
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
41
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
DownSampling
Embedded
Syncs
MUX YC
MUX YC
RGB 4:4:4
TMDS and
HDCP
Decoding
DownSampling
Embedded
Syncs
YCbCr 4:4:4
YCbCr/xvYCC
4:4:4
TMDS and
HDCP
Decoding
DownSampling
YCbCr 4:2:2
YCbCr/xvYCC
4:4:4
TMDS and
HDCP
Decoding
DownSampling
Digital Out
Digital Out
YCbCr 4:2:2
Emb. Syncs
YCbCr/xvYCC
4:4:4
TMDS and
HDCP
Decoding
Digital Out
Digital Out
MUX YC 4:2:2
YCbCr/xvYCC
4:4:4
TMDS and
HDCP
Decoding
YCbCr/xvYCC
to RGB
MUX YC 4:2:2
Emb. Syncs
YCbCr/xvYCC
4:4:4
TMDS and
HDCP
Decoding
YCbCr/xvYCC
4:4:4
7.1.2. HDMI YCbCr/xvYCC 4:4:4 Input Processing
A
B
C
D
Digital Out
E
Digital Out
F
Note: HDCP decoding does not apply to the SiI1127A receiver.
Figure 7.3. HDMI YCbCr/xvYCC 4:4:4 Input to Video Output Transformations
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
42
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Embedded
Syncs
RGB 4:4:4
TMDS and
HDCP
Decoding
YCbCr 4:4:4
YCbCr/xvYCC
4:2:2
TMDS and
HDCP
Decoding
Embedded
Syncs
YCbCr 4:2:2
YCbCr/xvYCC
4:2:2
TMDS and
HDCP
Decoding
Digital Out
Digital Out
YCbCr 4:2:2
Emb. Syncs
YCbCr/xvYCC
4:2:2
TMDS and
HDCP
Decoding
UpSampling
Digital Out
Digital Out
MUX YC
MUX YC 4:2:2
YCbCr/xvYCC
4:2:2
TMDS and
HDCP
Decoding
Upsampling
YCbCr/xvYCC
to RGB
MUX YC
MUX YC 4:2:2
Emb. Syncs
YCbCr/xvYCC
4:2:2
TMDS and
HDCP
Decoding
YCbCr/xvYCC
4:2:2
7.1.3. HDMI YCbCr/xvYCC 4:2:2 Input Processing
A
B
C
D
Digital Out
E
Digital Out
F
Note: HDCP decoding does not apply to the SiI1127A receiver.
Figure 7.4. HDMI YCbCr/xvYCC 4:2:2 Input to Video Output Transformations
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
43
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.2.
SiI9127A/SiI1127A Output Mode Configuration
The SiI9127A/SiI1127A receiver supports multiple output data mappings. Some have separate control signals while
others have embedded control signals. The selection of data mapping mode should be consistent at both the pins and
in the corresponding register settings. Refer to the SiI-PR-1033 Programmer Reference for more details.
Table 7.2. Output Video Formats
Output Mode
Data Widths
Pixel Replication
Syncs
Page
Notes
RGB 4:4:4
24, 30, 36
1x
Separate
45
3, 7
YCbCr 4:4:4
24, 30, 36
1x
Separate
45
1, 3, 7
YC 4:2:2 Sep. Syncs
16, 20, 24
1x
Separate
47
2, 3
YC 4:2:2 Sep. Syncs
16, 20, 24
2x
Separate
47
2, 3, 8
YC 4:2:2 Emb. Syncs
16, 20, 24
1x
Embedded
50
2, 5
YC MUX 4:2:2
8, 10, 12
2x
Separate
53
2, 4, 8, 9
YC MUX 4:2:2 Emb. Syncs
8, 10, 12
2x
Embedded
55
2, 5, 6, 8, 9
Notes:
1.
2.
3.
4.
5.
6.
7.
8.
9.
YC 4:4:4 data contains one Cr, one Cb and one Y value for every pixel.
YC 4:2:2 data contains one Cr and one Cb value for every two pixels; and one Y value for every pixel.
These formats can be carried across the HDMI link. Refer to the HDMI Specification, Section 6.2.3. The link clock must be within
the specified range of the receiver.
In YC MUX mode data is sent to one or two 8/10/12-bit channels.
YC MUX with embedded SAV/EAV signal.
Syncs are embedded using SAV/EAV codes.
A 2x clock can also be sent with 4:4:4 data.
When sending a 2x clock the HDMI source must also send AVI InfoFrames with an accurate pixel replication
field. Refer to the HDMI Specification, Section 6.4.
2x clocking does not support YC 4:2:2 MUX timings for resolutions greater than 720p or 1080i, because the output clock
frequency would exceed the range allowed for the receiver.
The SiI9127A/SiI1127A receiver can output video in various formats on its parallel digital output bus. Some
transformation of the data received over HDMI is necessary in some modes. Digital output is used with either 4:4:4 or
4:2:2 data.
The diagrams do not show separation of the audio and InfoFrame packets from the HDMI stream, which occurs
immediately after the TMDS and optional HDCP decoding. The HDMI link always carries separate HSYNC and VSYNC
and DE. Therefore the SAV/EAV sync encoder must be used whenever the output mode includes embedded sync.
The timing diagrams in Figure 7.5 through Figure 7.9 show only a representation of the DE, HSYNC, and VSYNC timings.
These timings are specific to the video resolution, as defined by EIA/CEA-861B and other specs. The number of pixels
shown per DE HIGH time is representative, to show the data formatting.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
44
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.2.1. RGB and YCbCr 4:4:4 Formats with Separate Syncs
The pixel clock runs at the pixel rate, and a complete definition of each pixel is output on each clock. Figure 7.5 shows
RGB data. The same timing format is used for YCbCr 4:4:4 as listed in Table 7.3.
Figure 7.5 shows timings with OCLKDIV = 0 and OCKINV = 1.
Table 7.3. 4:4:4 Mappings
Pin Name
36-bit
30-bit
24-bit
Q0
RGB
B0
YCbCr
Cb0
RGB
NC
YCbCr
NC
RGB
NC
YCbCr
NC
Q1
Q2
Q3
B1
B2
B3
Cb1
Cb2
Cb3
NC
B0
B1
NC
Cb0
Cb1
NC
NC
NC
NC
NC
NC
Q4
Q5
B4
B5
Cb4
Cb5
B2
B3
Cb2
Cb3
B0
B1
Cb0
Cb1
Q6
Q7
Q8
B6
B7
B8
Cb6
Cb7
Cb8
B4
B5
B6
Cb4
Cb5
Cb6
B2
B3
B4
Cb2
Cb3
Cb4
Q9
Q10
Q11
B9
B10
B11
Cb9
Cb10
Cb11
B7
B8
B9
Cb7
Cb8
Cb9
B5
B6
B7
Cb5
Cb6
Cb7
Q12
Q13
G0
G1
Y0
Y1
NC
NC
NC
NC
NC
NC
NC
NC
Q14
Q15
Q16
G2
G3
G4
Y2
Y3
Y4
G0
G1
G2
Y0
Y1
Y2
NC
NC
G0
NC
NC
Y0
Q17
Q18
G5
G6
Y5
Y6
G3
G4
Y3
Y4
G1
G2
Y1
Y2
Q19
Q20
Q21
G7
G8
G9
Y7
Y8
Y9
G5
G6
G7
Y5
Y6
Y7
G3
G4
G5
Y3
Y4
Y5
Q22
Q23
G10
G11
Y10
Y11
G8
G9
Y8
Y9
G6
G7
Y6
Y7
Q24
Q25
Q26
R0
R1
R2
Cr0
Cr1
Cr2
NC
NC
R0
NC
NC
Cr0
NC
NC
NC
NC
NC
NC
Q27
Q28
Q29
R3
R4
R5
Cr3
Cr4
Cr5
R1
R2
R3
Cr1
Cr2
Cr3
NC
R0
R1
NC
Cr0
Cr1
Q30
Q31
R6
R7
Cr6
Cr7
R4
R5
Cr4
Cr5
R2
R3
Cr2
Cr3
Q32
Q33
Q34
R8
R9
R10
Cr8
Cr9
Cr10
R6
R7
R8
Cr6
Cr7
Cr8
R4
R5
R6
Cr4
Cr5
Cr6
Q35
R11
Cr11
R9
Cr9
R7
Cr7
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
45
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel n
blank
blank
blank
Q[35:24]
val
R0
R1
R2
R3
R4
Rn
val
val
val
Q[23:12]
val
G0
G1
G2
G3
G4
Gn
val
val
val
Q[11:0]
val
B0
B1
B2
B3
B4
Bn
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 7.5. 4:4:4 Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate
SiI9127A/SiI1127A registers, because no pixel data is carried on HDMI during blanking.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
46
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.2.2. YC 4:2:2 Formats with Separate Syncs
The YC 4:2:2 formats output one pixel for every pixel clock period. A luminance (Y) value is sent for every pixel, but the
chrominance values Cb and Cr are sent over two pixels. Pixel data can be 24-bit, 20-bit or 16-bit. HSYNC and VSYNC are
output separately on their own pins. The DE HIGH time must contain an even number of pixel clocks. Figure 7.6 shows
timings with OCLKDIV = 0 and OCKINV = 1.
Table 7.4. YC 4:2:2 Separate Sync Pin Mappings
Pin Name
16-bit YC
20-bit YC
24-bit YC
Q0
Q1
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Q2
Q3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q4
Q5
Q6
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q7
Q8
Q9
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q10
Q11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q12
Q13
Q14
NC
NC
NC
NC
NC
NC
NC
NC
Y0
NC
NC
Y0
Y0
Y1
Y2
Y0
Y1
Y2
Q15
Q16
NC
Y0
NC
Y0
Y1
Y2
Y1
Y2
Y3
Y4
Y3
Y4
Q17
Q18
Q19
Y1
Y2
Y3
Y1
Y2
Y3
Y3
Y4
Y5
Y3
Y4
Y5
Y5
Y6
Y7
Y5
Y6
Y7
Q20
Q21
Q22
Y4
Y5
Y6
Y4
Y5
Y6
Y6
Y7
Y8
Y6
Y7
Y8
Y8
Y9
Y10
Y8
Y9
Y10
Q23
Q24
Y7
NC
Y7
NC
Y9
NC
Y9
NC
Y11
Cb0
Y11
Cr0
Q25
Q26
Q27
NC
NC
NC
NC
NC
NC
NC
Cb0
Cb1
NC
Cr0
Cr1
Cb1
Cb2
Cb3
Cr1
Cr2
Cr3
Q28
Q29
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Cb4
Cb5
Cr4
Cr5
Q30
Q31
Q32
Cb2
Cb3
Cb4
Cr2
Cr3
Cr4
Cb4
Cb5
Cb6
Cr4
Cr5
Cr6
Cb6
Cb7
Cb8
Cr6
Cr7
Cr8
Q33
Q34
Q35
Cb5
Cb6
Cb7
Cr5
Cr6
Cr7
Cb7
Cb8
Cb9
Cr7
Cr8
Cr9
Cb9
Cb10
Cb11
Cr9
Cr10
Cr11
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
47
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Table 7.5. YC 4:2:2 (Pass Through Only) Separate Sync Pin Mapping
Pin Name
16-bit YC
20-bit YC
24-bit YC
Q0
Q1
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Q2
Q3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q4
Q5
Q6
NC
NC
NC
NC
NC
NC
NC
NC
Y0
NC
NC
Y0
Y0
Y1
Y2
Y0
Y1
Y2
Q7
Q8
Q9
NC
NC
NC
NC
NC
NC
Y1
NC
NC
Y1
NC
NC
Y3
Cb0
Cb1
Y3
Cr0
Cr1
Q10
Q11
NC
NC
NC
NC
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Q12
Q13
Q14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q15
Q16
NC
Y0
NC
Y0
NC
Y2
NC
Y2
NC
Y4
NC
Y4
Q17
Q18
Q19
Y1
Y2
Y3
Y1
Y2
Y3
Y3
Y4
Y5
Y3
Y4
Y5
Y5
Y6
Y7
Y5
Y6
Y7
Q20
Q21
Q22
Y4
Y5
Y6
Y4
Y5
Y6
Y6
Y7
Y8
Y6
Y7
Y8
Y8
Y9
Y10
Y8
Y9
Y10
Q23
Q24
Y7
NC
Y7
NC
Y9
NC
Y9
NC
Y11
NC
Y11
NC
Q25
Q26
Q27
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q28
Q29
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Cb4
Cb5
Cr4
Cr5
Q30
Q31
Q32
Cb2
Cb3
Cb4
Cr2
Cr3
Cr4
Cb4
Cb5
Cb6
Cr4
Cr5
Cr6
Cb6
Cb7
Cb8
Cr6
Cr7
Cr8
Q33
Q34
Cb5
Cb6
Cr5
Cr6
Cb7
Cb8
Cr7
Cr8
Cb9
Cb10
Cr9
Cr10
Q35
Cb7
Cr7
Cb9
Cr9
Cb11
Cr11
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
HSYNC
VSYNC
DE
DE
DE
DE
DE
DE
DE
Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video format is YC 4:2:2 also. No video
processing blocks should be enabled when this pin mapping is used.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
48
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
blank
Pixel0
Pixel1
Pixel2
Pixel3 Pixeln-1
Pixeln
Q[35:28]
val
Cb0[11:4]
Cr0[11:4]
Cb2[11:4]
Cr2[11:4]
Cbn-1[11:4]
Crn-1[11:4]
val
val
Q[23:16]
val
Y0[11:4]
Y1[11:4]
Y2[11:4]
Y3[11:4]
Yn-1[11:4]
Yn[11:4]
val
val
Q[27:24]
val
Cb0[3:0]
Cr0[3:0]
Cb2[3:0]
Cr2[3:0]
Cbn-1[3:0]
Crn-1 [3:0]
val
val
Q[15:12]
val
Y0[3:0]
Y1[3:0]
Y2[3:0]
Y3[3:0]
Yn-1[3:0]
Yn[3:0]
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 7.6. YC Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate
SiI9127A/SiI1127A receiver registers, because no pixel data is carried on HDMI during blanking.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
49
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.2.3. YC 4:2:2 Formats with Embedded Syncs
The YC 4:2:2 embedded sync format is identical to the previous format (YC 4:2:2), except that the syncs are embedded
and not separate. Pixel data can be 24-bit, 20-bit or 16-bit. DE is always output. Figure 7.7 shows the Start of Active
Video (SAV) preamble, the End of Active Video (EAV) suffix, and shows timings with OCLKDIV = 0 and OCKINV = 1.
Table 7.6. YC 4:2:2 Embedded Sync Pin Mappings
Pin Name
16-bit YC
20-bit YC
24-bit YC
Q0
Pixel #0
NC
Pixel #1
NC
Pixel #0
NC
Pixel #1
NC
Pixel #0
NC
Pixel #1
NC
Q1
Q2
Q3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q4
Q5
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q6
Q7
Q8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q9
Q10
Q11
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q12
Q13
NC
NC
NC
NC
NC
NC
NC
NC
Y0
Y1
Y0
Y1
Q14
Q15
Q16
NC
NC
Y0
NC
NC
Y0
Y0
Y1
Y2
Y0
Y1
Y2
Y2
Y3
Y4
Y2
Y3
Y4
Q17
Q18
Y1
Y2
Y1
Y2
Y3
Y4
Y3
Y4
Y5
Y6
Y5
Y6
Q19
Q20
Q21
Y3
Y4
Y5
Y3
Y4
Y5
Y5
Y6
Y7
Y5
Y6
Y7
Y7
Y8
Y9
Y7
Y8
Y9
Q22
Q23
Y6
Y7
Y6
Y7
Y8
Y9
Y8
Y9
Y10
Y11
Y10
Y11
Q24
Q25
Q26
NC
NC
NC
NC
NC
NC
NC
NC
Cb0
NC
NC
Cr0
Cb0
Cb1
Cb2
Cr0
Cr1
Cr2
Q27
Q28
Q29
NC
Cb0
Cb1
NC
Cr0
Cr1
Cb1
Cb2
Cb3
Cr1
Cr2
Cr3
Cb3
Cb4
Cb5
Cr3
Cr4
Cr5
Q30
Q31
Cb2
Cb3
Cr2
Cr3
Cb4
Cb5
Cr4
Cr5
Cb6
Cb7
Cr6
Cr7
Q32
Q33
Q34
Cb4
Cb5
Cb6
Cr4
Cr5
Cr6
Cb6
Cb7
Cb8
Cr6
Cr7
Cr8
Cb8
Cb9
Cb10
Cr8
Cr9
Cr10
Q35
Cb7
Cr7
Cb9
Cr9
Cb11
Cr11
HSYNC
VSYNC
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
50
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Table 7.7. YC 4:2:2 (Pass Through Only) Embedded Sync Pin Mapping
Pin Name
16-bit YC
20-bit YC
24-bit YC
Q0
Q1
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Pixel #0
NC
NC
Pixel #1
NC
NC
Q2
Q3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q4
Q5
Q6
NC
NC
NC
NC
NC
NC
NC
NC
Y0
NC
NC
Y0
Y0
Y1
Y2
Y0
Y1
Y2
Q7
Q8
Q9
NC
NC
NC
NC
NC
NC
Y1
NC
NC
Y1
NC
NC
Y3
Cb0
Cb1
Y3
Cr0
Cr1
Q10
Q11
NC
NC
NC
NC
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Q12
Q13
Q14
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q15
Q16
NC
Y0
NC
Y0
NC
Y2
NC
Y2
NC
Y4
NC
Y4
Q17
Q18
Q19
Y1
Y2
Y3
Y1
Y2
Y3
Y3
Y4
Y5
Y3
Y4
Y5
Y5
Y6
Y7
Y5
Y6
Y7
Q20
Q21
Q22
Y4
Y5
Y6
Y4
Y5
Y6
Y6
Y7
Y8
Y6
Y7
Y8
Y8
Y9
Y10
Y8
Y9
Y10
Q23
Q24
Y7
NC
Y7
NC
Y9
NC
Y9
NC
Y11
NC
Y11
NC
Q25
Q26
Q27
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q28
Q29
Cb0
Cb1
Cr0
Cr1
Cb2
Cb3
Cr2
Cr3
Cb4
Cb5
Cr4
Cr5
Q30
Q31
Q32
Cb2
Cb3
Cb4
Cr2
Cr3
Cr4
Cb4
Cb5
Cb6
Cr4
Cr5
Cr6
Cb6
Cb7
Cb8
Cr6
Cr7
Cr8
Q33
Q34
Cb5
Cb6
Cr5
Cr6
Cb7
Cb8
Cr7
Cr8
Cb9
Cb10
Cr9
Cr10
Q35
Cb7
Cr7
Cb9
Cr9
Cb11
Cr11
HSYNC
VSYNC
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Note: This pin mapping is only valid when the input video format is YC 4:2:2 and the output video format is YC 4:2:2 also. No video
processing blocks should be enabled when this pin mapping is used.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
51
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
SAV
Pixel0
Pixel1
Pixel2
Pixel3
Pixel n-1
Q[35:28]
val
FF
00
00
XY
Cb0[11:4]
Cr0[11:4]
Cb2[11:4]
Cr2[11:4]
Q[23:16]
val
FF
00
00
XY
Y0[ 11: 4]
Y1[ 11:4]
Y2[11: 4]
Y3[11: 4]
Yn-1[11:4]
Q[27:24]
val
X
X
X
X
Cb0[3: 0]
Cr0[3:0]
Cb2[3: 0]
Cr2[3:0]
Q[15:12]
val
X
X
X
X
Y0[ 3:0]
Y1[3:0]
Y2[3:0]
Y3[ 3:0]
EAV
Pixel n
Cbn-1[11:4] Crn-1[11:4]
FF
00
00
XY
val
Yn[ 11:4]
FF
00
00
XY
val
Cbn-1[3:0]
Crn-1[ 3:0]
X
X
X
X
val
Yn-1[3: 0]
Yn[3:0]
X
X
X
X
val
ODCK
Active
Video
Figure 7.7. YC 4:2:2 Embedded Sync Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate
SiI9127A/SiI1127A registers, because no pixel data is carried on HDMI during blanking. SAV/EAV codes appear as an 8-bit field on
both Q[35:28] (per SMPTE) and Q[23:16].
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
52
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.2.4. YC Mux (4:2:2) Formats with Separate Syncs
The video data is multiplexed onto fewer pins than the mapping in Table 7.8, but complete luminance (Y) and
chrominance (Cb and Cr) data is still provided for each pixel because the output pixel clock runs at twice the pixel rate.
Figure 7.8 on the next page shows the 24-bit mode. The 16-bit and 20-bit mappings use fewer output pins for the pixel
data. The separate syncs. Figure 7.8 shows timings with OCLKDIV = 0 and OCKINV = 1.
Table 7.8. YC Mux 4:2:2 Mappings
Pin Name
8-bit YCbCr
10-bit YCbCr
12-bit YCbCr
Q0
Q1
Q2
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q3
Q4
NC
NC
NC
NC
NC
NC
Q5
Q6
Q7
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q8
Q9
NC
NC
NC
NC
NC
NC
Q10
Q11
Q12
NC
NC
NC
NC
NC
NC
NC
NC
D0
Q13
Q14
Q15
NC
NC
NC
NC
D0
D1
D1
D2
D3
Q16
Q17
D0
D1
D2
D3
D4
D5
Q18
Q19
Q20
D2
D3
D4
D4
D5
D6
D6
D7
D8
Q21
Q22
D5
D6
D7
D8
D9
D10
Q23
Q24
Q25
D7
NC
NC
D9
NC
NC
D11
NC
NC
Q26
Q27
NC
NC
NC
NC
NC
NC
Q28
Q29
Q30
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q31
Q32
Q33
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q34
Q35
NC
NC
NC
NC
NC
NC
HSYNC
HSYNC
HSYNC
HSYNC
VSYNC
DE
VSYNC
DE
VSYNC
DE
VSYNC
DE
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
53
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Q[35:24]
Q[11:0]
X
X
X
X
X
X
X
X
X
X
X
X
X
Q[23:16]
val
val
val
val
val
Cb0[11:4]
Y0[11:4]
Cr0[11:4]
Y1[11:4]
Cb2[11:4]
Y2[11:4]
Cr2[11:4]
Y3[11:4]
Q[15:12]
val
val
val
val
val
Cb0[3:0]
Y0[3:0]
Cr0[3:0]
Y1[3:0]
Cb2[3:0]
Y2[3:0]
Cr2[3:0]
Y3[3:0]
ODCK
DE
HSYNC
VSYNC
Figure 7.8. YC Mux 4:2:2 Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate
SiI9127A/SiI1127A registers, because no pixel data is carried on HDMI during blanking.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
54
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.2.5. YC Mux 4:2:2 Formats with Embedded Syncs
This mode is similar to that on page 53, but with embedded syncs. It is similar to YC 4:2:2 with embedded syncs, but
also multiplexes the luminance (Y) and chrominance (Cb and Cr) onto the same pins on alternating pixel clock cycles.
Normally this mode is used only for 480i, 480p, 576i and 576p modes. Output clock rate is half the pixel clock rate on
the link. SAV code is shown before rise of DE. EAV follows the falling edge of DE. See the ITU-R BT.656 Specification for
more information. 480p 54 MHz output can be achieved if the input differential clock is 54 MHz. Figure 7.9 on the next
page shows OCLKDIV = 0 and OCKINV = 1.
Table 7.9. YC Mux 4:2:2 Embedded Sync Pin Mapping
Pin Name
8-bit YCbCr
10-bit YCbCr
12-bit YCbCr
Q0
Q1
NC
NC
NC
NC
NC
NC
Q2
Q3
Q4
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q5
Q6
NC
NC
NC
NC
NC
NC
Q7
Q8
Q9
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q10
Q11
Q12
NC
NC
NC
NC
NC
NC
NC
NC
D0
Q13
Q14
NC
NC
NC
D0
D1
D2
Q15
Q16
Q17
NC
D0
D1
D1
D2
D3
D3
D4
D5
Q18
Q19
D2
D3
D4
D5
D6
D7
Q20
Q21
Q22
D4
D5
D6
D6
D7
D8
D8
D9
D10
Q23
Q24
Q25
D7
NC
NC
D9
NC
NC
D11
NC
NC
Q26
Q27
NC
NC
NC
NC
NC
NC
Q28
Q29
Q30
NC
NC
NC
NC
NC
NC
NC
NC
NC
Q31
Q32
NC
NC
NC
NC
NC
NC
Q33
Q34
Q35
NC
NC
NC
NC
NC
NC
NC
NC
NC
HSYNC
VSYNC
DE
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
Embedded
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
55
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
SAV
Pixel 0
Pixel 1
Pixel 2
Pixel 3
Q[35:24]
val
X
X
X
X
X
X
X
X
X
X
X
X
Q[23:16]
val
FF
00
00
XY
Cb0[11:4]
Y0[ 11:4]
Cr0[11: 4]
Y1[11:4]
Cb2[11:4]
Y2[11:4]
Cr2[11:4]
Y3[11:4]
Q[15:12]
val
X
X
X
X
Cb0[3:0]
Y0[3:0]
Cr0[3: 0]
Y1[3:0]
Cb2[3:0]
Y2[3:0]
Cr2[ 3:0]
Y3[3:0]
Q[11:0]
ODCK
Active
Video
Figure 7.9. YC Mux 4:2:2 Embedded Sync Encoding Timing Diagram
Note: The val data is defined in various specifications to specific values. These values are controlled by setting the appropriate
SiI9127A/SiI1127A registers, because no pixel data is carried on HDMI during blanking. Refer to the SiI-PR-1033 Programmer
Reference for details. The Programmer Reference requires an NDA with Lattice Semiconductor.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
56
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
7.2.6. 12/15/18-Bit RGB and YCbCr 4:4:4 Formats with Separate Syncs
The An output clock runs at the pixel rate, and a complete definition of each pixel is output on each clock. One clock
edge drives out half the pixel data on 12/15/18 pins. The opposite clock edge drives out the remaining half of the pixel
data on the same 12/15/18 pins. Figure 7.10 shows RGB data. The same timing format is used for YCbCr 4:4:4 as listed
in the columns of Table 7.10. Control signals (DE, HSYNC, and VSYNC) change state with respect to the first edge of
ODCK.
Table 7.10. 12/15/18-Bit Output 4:4:4 Mappings
24-bit
Pin
Name
30-bit
RGB
YCbCr
36-bit
RGB
YCbCr
RGB
YCbCr
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
First
Edge
Second
Edge
Q0
Q1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B0
B1
G6
G7
Cb0
Cb1
Y6
Y7
Q2
Q3
Q4
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
B0
B1
NC
G5
G6
NC
Cb0
Cb1
NC
Y5
Y6
B2
B3
B4
G8
G9
G10
Cb2
Cb3
Cb4
Y8
Y9
Y10
Q5
Q6
NC
B0
NC
G4
NC
Cb0
NC
Y4
B2
B3
G7
G8
Cb2
Cb3
Y7
Y8
B5
B6
G11
R0
Cb5
Cb6
Y11
Cr0
Q7
Q8
Q9
B1
B2
B3
G5
G6
G7
Cb1
Cb2
Cb3
Y5
Y6
Y7
B4
B5
B6
G9
R0
R1
Cb4
Cb5
Cb6
Y9
Cr0
Cr1
B7
B8
B9
R1
R2
R3
Cb7
Cb8
Cb9
Cr1
Cr2
Cr3
Q10
Q11
Q12
B4
B5
B6
R0
R1
R2
Cb4
Cb5
Cb6
Cr0
Cr1
Cr2
B7
B8
B9
R2
R3
R4
Cb7
Cb8
Cb9
Cr2
Cr3
Cr4
B10
B11
G0
R4
R5
R6
Cb10
Cb11
Y0
Cr4
Cr5
Cr6
Q13
Q14
B7
G0
R3
R4
Cb7
Y0
Cr3
Cr4
G0
G1
R5
R6
Y0
Y1
Cr5
Cr6
G1
G2
R7
R8
Y1
Y2
Cr7
Cr8
Q15
Q16
Q17
G1
G2
G3
R5
R6
R7
Y1
Y2
Y3
Cr5
Cr6
Cr7
G2
G3
G4
R7
R8
R9
Y2
Y3
Y4
Cr7
Cr8
Cr9
G3
G4
G5
R9
R10
R11
Y3
Y4
Y5
Cr9
Cr10
Cr11
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
HSYNC
VSYNC
DE
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
blank
blank
blank
Q[17:12]
val
G0[5:0]
R0[11:6]
G1[5:0]
R1[11:6]
G2[5:0]
R2[11:6]
G3[5:0]
R3[11:6]
val
val
val
val
val
val
Q[11:6]
val
B0[11:6]
R0[5:0]
B1[11:6]
R1[5:0]
B2[11:6]
R2[5:0]
B3[11:6]
R3[5:0]
val
val
val
val
val
val
Q[5:0]
val
B0[5:0]
G0[11:6]
B1[5:0]
G1[11:6]
B2[5:0]
G2[11:6]
B3[5:0]
G3[11:6]
val
val
val
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 7.10. 18-Bit Output 4:4:4 Timing Diagram
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
57
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
blank
blank
blank
Q[17:13]
val
G0[4:0]
R0[9:5]
G1[4:0]
R1[9:5]
G2[4:0]
R2[9:5]
G3[4:0]
R3[9:5]
val
val
val
val
val
val
Q[12:8]
val
B0[9:5]
R0[4:0]
B1[9:5]
R1[4:0]
B2[9:5]
R2[4:0]
B3[9:5]
R3[4:0]
val
val
val
val
val
val
Q[7:3]
val
B0[4:0]
G0[9:5]
B1[4:0]
G1[9:5]
B2[4:0]
G2[9:5]
B3[4:0]
G3[9:5]
val
val
val
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 7.11. 15-Bit Output 4:4:4 Timing Diagram
blank
Pixel 0
Pixel 1
Pixel 2
Pixel 3
blank
blank
blank
Q[17:14]
val
G0[3:0]
R0[7:4]
G1[3:0]
R1[7:4]
G2[3:0]
R2[7:4]
G3[3:0]
R3[7:4]
val
val
val
val
val
val
Q[13:10]
val
B0[7:4]
R0[3:0]
B1[7:4]
R1[3:0]
B2[7:4]
R2[3:0]
B3[7:4]
R3[3:0]
val
val
val
val
val
val
Q[9:6]
val
B0[3:0]
G0[7:4]
B1[3:0]
G1[7:4]
B2[3:0]
G2[7:4]
B3[3:0]
G3[7:4]
val
val
val
val
val
val
ODCK
DE
HSYNC,
VSYNC
Figure 7.12. 12-Bit Output 4:4:4 Timing Diagram
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
58
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
8. I2C Interfaces
8.1.
HDCP E-DDC / I2C Interface
Stop
S
Register Address
Slave Address
S
P
A
C
K
A
C
K
A
C
K
Data
Data
Stop
DSDA Line
Slave Address
Start
Bus Activity :
Master
Start
For the SiI9127A device, the HDCP protocol requires values to be exchanged between the video transmitter and the
video receiver. These values are exchanged over the DDC channel of the DVI interface. The E-DDC channel follows the
2
I C serial protocol. The SiI9127A/SiI1127A device is the video receiver in a system design using the SiI9127A/SiI1127A
2
receiver and it has a connection to the E-DDC bus with a slave address of 0x74. The I C read operation is shown in
Figure 8.1, and the write operation is shown in Figure 8.2.
No
A
C
K
2
Bus Activity :
Master
Start
Figure 8.1. I C Byte Read
DSDA Line
S
Slave Address
Register Address
P
A
C
K
A
C
K
A
C
K
2
Figure 8.2. I C Byte Write
Multiple bytes can be transferred in each transaction, regardless of whether they are reads or writes. The operations
are similar to those in Figure 8.1 and Figure 8.2 except that there is more than one data phase. An ACK follows each
byte except the last byte in a read operation. Byte addresses increment, with the least significant byte transferred first,
2
and the most significant byte last. See the I C specification for more information.
DSDA Line
S
Slave Address
Ri Lsb
Ri Msb
Stop
Bus Activity:
Master
Start
There is also a Short Read format, designed to improve the efficiency of Ri register reads, which must be done every
two seconds while encryption is enabled. This transaction is shown in Figure 8.3. With this format, there is only the
slave address phase, and no register address phase, because the register address is reset to 0x08 (Ri) after a hardware
2
or software reset, and after the STOP condition on any preceding I C transaction.
P
A
C
K
A
C
K
No
A
C
K
Figure 8.3. Short Read Sequence
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
59
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
8.2.
Local I2C Interface
2
The SiI9127A/SiI1127A receiver has a second I C port accessible only to the controller in the display device. It is
2
separate from the E-DDC bus. The receiver is a slave device that responds to the six binary I C device addresses of
2
seven bits each. This I C interface only supports the read operation shown in Figure 8.1, and the write operation shown
2
2
in Figure 8.2. It does not support the short read operation shown in Figure 8.3. The I C data pin for the local I C bus is
CSDA, instead of the DSDA pin shown in these figures.
2
The local I C interface on the receiver (pins CSCL and CSDA) is a slave interface that can run up to 400 kHz. This bus is
used to configure and control the SiI9127A/SiI1127A device by reading or writing to necessary registers.
2
2
2
The local I C interface consists of 5 separate I C slave addresses. Therefore, it appears as 5 separate devices on the I C
local bus. The first two of these addresses, used for HDMI Control and general low level register control, are fixed and
can only be set to one of two values by using the CI2CA pin. Table 8.1 shows the address selected for each state of the
2
CI2CA pin at reset. The other 3 addresses, used for CEC, EDID and xvYCC, have an I C register-programmable address
mapped into the HDMI Control register space, so the default value can be changed if there is a bus conflict with
another device.
2
Table 8.1. Control of the Default I C Addresses with the CI2CA Pin
Register Group
HDMI Control and low level registers (fixed)
CI2CA = LOW
0x60 & 0x68
CI2CA = HIGH
0x62 & 0x6A
2
The HDMI Control and low level registers are fixed after a reset based on CI2CA pin and cannot be changed. The I C
slave address for the xvYCC registers, EDID Control registers, and the CEC Control registers each have a register
associated with them that allows the address to be changed. Refer to the SiI-PR-1033 Programmer Reference for more
information.
8.3.
Video Requirement for I2C Access
The SiI9127A/SiI1127A receiver does not require an active video clock to access its registers from either the E-DDC port
2
or the local I C port. Read-Write registers can be written and then read back. Read-only registers that provide values
for an active video or audio stream return indeterminate values if there is no video clock and no active syncs.
Use the SCDT and CKDT register bits to determine when active video is being received by the chip.
8.4.
I2C Registers
2
The register values that are exchanged over the HDMI DDC I C serial interface with the receiver for HDCP are described
in the HDCP Specification in Section 2.6 – HDCP Port. Refer to the SiI-PR-1033 Programmer Reference for details on
these and all other SiI9127A/SiI1127A registers.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
60
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9. Design Recommendations
The following information is provided as recommendations that are based on the experience of Lattice Semiconductor
engineers and customers. If you choose to deviate from these recommendations for a particular application, Lattice
Semiconductor strongly suggests that you contact one of its technical representatives for an evaluation of the change.
9.1.
Power Control
The low-power standby state feature of the SiI9127A/SiI1127A receiver provides a design option of leaving the chip
always powered, as opposed to powering it on and off. Leaving the chip powered and using the PD# register bit to put
it in a lower power state can result in faster system response time, depending on the system Vcc supply ramp-up delay.
9.2.
Power-on Sequencing
Due to timing considerations with the power-on reset circuits within the chip, Lattice Semiconductor recommends that
5 V power is available to the device before the 3.3 V and 1.2 V VCC supplies are enabled. If the 3.3 V and 1.2 V supplies
reach their operating levels before the 5 V power supply to the power island, the chip may not reset properly.
9.2.1. Power Pin Current Demands
The limits shown in Table 9.1 indicate the current demanded by each group of power pins on the device. These limits
were characterized at maximum VCC, 0 °C ambient temperature and for fast-fast silicon. Actual application current
demands can be lower than these figures and vary with video resolution and audio clock frequency.
Table 9.1. Maximum Power Domain Currents versus Video Mode
3.3 V Power Domain Currents (mA)
AVCC33
XTALVCC33
Mode
ODCK (MHz)
480p
1080i
1080p
27.0
74.25
148.5
39
104
217
62
62
62
2
2
2
225
302
62
2
1080p@12-bit
1
Mode
ODCK (MHz)
480p
27.0
1080i
74.25
1080p
1080p@12-bit
148.5
1
225
IOVCC33
1.2 V Power Domain Currents (mA)
AVCC12
CVCC12
APVCC12
79
86
118
95
40
88
158
191
3
3
3
3
Notes:
1. Measured with 12 bits/pixel video data.
2. Measured with 192 kHz, 8-channel audio, except for 480p mode which used 48 kHz, 8-channel audio.
3. Measured with RGB input, vertical black-white/1-pixel stripe (Moire2) pattern, converting to YCbCr output (digital for IOVCC33).
4. Only one core can be selected at a time. The TMDSxSEL register bit turns off the unselected core, except for the termination to
AVCC33.
AVCC33 current includes 40 mA for the unselected TMDS core. Only 5 mA of this current is dissipated as power in the
receiver; the remainder is dissipated in the HDMI transmitter. The AVCC33 current on the unselected core can be
reduced to 5 mA by asserting the corresponding PD_TERMx# register bit.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
61
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.3.
HDMI Receiver DDC Bus Protection
2
The VESA DDC Specification (see Standards Groups on page 74) defines the DDC I C interconnect bus to be a 5 V
2
signaling path. The I C pins on the SiI9127A/SiI1127A chip are 5 V tolerant and are true open-drain I/O. The pull-up
resistors on the DDC bus should be pulled up using the 5 V supply from the HDMI connector. See Figure 9.9 on page 70.
9.4.
Decoupling Capacitors
Designers should include decoupling and bypass capacitors at each power pin in the layout. These are shown
schematically in Figure 9.4 on page 65. Place these components as close as possible to the SiI9127A/SiI1127A pins and
avoid routing through vias. Figure 9.1 shows various types of power pins on the receiver.
VCC
C1
C2
L1
VCC
Ferrite
GND
C3
Via to GND
Figure 9.1. Decoupling and Bypass Capacitor Placement
9.5.
ESD Protection
The SiI9127A/SiI1127A chip is designed to withstand an electrostatic discharge up to 2 kV. In applications where higher
protection levels are required, ESD limiting components can be placed on the differential lines coming into the chip.
These components typically have a capacitive effect, reducing the signal quality at higher clock frequencies on the link.
Use of the lowest capacitance devices is suggested; the capacitance value should not exceed 5 pF in any case.
Series resistors can be included on the TMDS lines (see Figure 9.9 on page 70) to counteract the impedance effects of
ESD protection diodes. The diodes typically lower the impedance because of their capacitance. The resistors raise the
impedance to stay within the HDMI Specification, centered on a 100 Ω differential.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
62
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.6.
HDMI Receiver Layout
The SiI9127A/SiI1127A chip should be placed as close as possible to the input connectors that carry the TMDS signals.
For a system using industry-standard HDMI connectors (see Standards Groups on page 74), the differential lines should
be routed as directly as possible from the connector to the receiver. Lattice Semiconductor receivers are tolerant of
skews between differential pairs, so spiral skew compensation for path length differences is not required. Each
differential pair should be routed together, minimizing the number of vias through which the signal lines are routed.
The distance separating the two traces of the differential pair should be kept to a minimum.
In order to achieve optimal input TMDS signal quality, follow the layout guidelines below:
 Lay out all differential pairs with a controlled differential impedance of 100 .
 Cut out all ground and power copper planes that are less than 45 mils underneath the TMDS traces near the
receiver with the dimensions shown in Figure 9.2.
 If ESD suppression devices or common mode chokes are used, place them near the HDMI connector, away from
the SiI9127A/SiI1127A package. Do not place them over the ground and power plane cutout near the receiver.
0.3 inch
> 0.1 inch
HDMI Connectors
HDMI Receiver
> 0.1 inch
Ground and Power plane cut-out for copper planes <45 mil separation from TMDS traces
Figure 9.2. Cut-out Reference Plane Dimensions
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
63
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
In Figure 9.3, which is a representation of a PCB containing HDMI connectors and the receiver, the sixteen TMDS traces
are connected directly from the HDMI connectors (shown on the left in the figure) to the pins on the SiI9127A/SiI1127A
receiver (shown on the right). Trace differential impedance should be 100  for each pair and 50  single-ended if
possible. Trace width and pitch depends on the PCB construction. Not all connections are shown; the drawing
demonstrates routing of TMDS lines without crossovers, vias, or ESD protection. Refer also to Figure 9.9.
DDC#0
+5V
PIN 19
R1PWR5V
text
SiI9127A/
SiI1127A
text
text
PIN 1
t
tex
t
tex
t
tex
t
tex
t
tex
t
19
text
t
tex
t
tex
text
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
10
tex
t
tex
text
PIN 19
+5V
text
DDC#1
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
text
R0PWR5V
text
t
tex
t
tex
t
tex
t
tex
t
10
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
tex
t
19
HDMI Port
#0
Connector
HDMI Port
#1
Connector
DDC#1
text
PIN 1
tex
t
tex
t
tex
t
tex
Drawing is not to exact. scale.
Refer to HDMI connector specification for
.
exact dimensions
Figure 9.3. HDMI to Receiver Routing – Top View
9.7.
EMI Considerations
Electromagnetic interference is a function of the board layout, shielding, receiver component operating voltage, and
frequency of operation, among other factors. When attempting to control emissions, do not place any passive
components on the differential signal lines other than the essential ESD protection described earlier. The differential
signaling used in HDMI is inherently low in EMI as long as the routing recommendations noted in the Receiver Layout
section are followed.
The PCB ground plane should extend unbroken under as much of the SiI9127A/SiI1127A chip and associated circuitry as
possible, with all ground pins of the chip using a common ground.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
64
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.8.
Typical Circuit
Representative circuits for application of the SiI9127A/SiI1127A receiver chip are shown in Figure 9.4 through
Figure 9.8. For a detailed review of your intended circuit implementation, contact your Lattice Semiconductor
representative.
9.8.1. Power Supply Decoupling
AVCC_3. 3V
Ferrite
220 @100MHz
AVCC33
0.1 F
10 F
0.1 F
0.1 F
0.1 F
1 nF
1 nF
1 nF
GND
+3.3 V
Place ceramic capacitors
close to VCC pins .
IOVCC33
10 F
10 F
0.1 F
0.1 F
0.1 F
0.1 F 1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
GND
+1.2 V
Place ceramic capacitors
close to VCC pins .
CVCC 12
10 F
10 F
0.1 F
0.1 F
0.1 F
0.1 F
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
1 nF
GND
SiI9127A/
SiI1127A
+1.2 V
0.56 
1%
Ferrite
0.82 H, 150 mA
AVCC12
10 F
0.1 F
0.1 F
0.1 F
1 nF
1 nF
1 nF
AGND
+1.2 V
Ferrite
220@100 MHz
+3.3 V
Ferrite
220@100 MHz
APVCC12
XTALVCC33
+5 V
SBVCC 5
Figure 9.4. Power Supply Decoupling and PLL Filtering Schematic
The ferrite on AVCC33 attenuates noise above 10 kHz. A parasitic resistor helps to minimize the peaking. An example of
a surface mount device is the MLF2012 Series SMD inductors from TDK.
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trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
65
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.8.2. HDMI Port Connections
RX2+ n
RX2- n
RnX2+
RnX2-
RX1+ n
RnX1+
RX1- n
RnX1-
RX0+ n
RX0- n
RnX0+
RnX0-
RXC+ n
RnXC+
RXC- n
RnXC-
HDMI
Connector
Port n
SiI9127A/SiI1127A
CEC n
CEC_A
HPD n
HPDn
+5V n
47 k
47 k
SCL n
DSCLn
SDA n
DSDAn
Figure 9.5. HDMI Port Connections Schematic
Note: Repeat the schematic for each HDMI input port on the receiver.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
66
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.8.3. Digital Video Output Connections
SiI9127A/SiI1127A
INT
22
Microcontroller
60
DE
HSYNC 62
61
VSYNC
65
ODCK
85
Q0
84
Q1
83
Q2
82
Q3
81
Q4
80
Q5
79
Q6
78
Q7
77
Q8
74
Q9
73
Q10
72
Q11
33
33
33
33
71
Q12
70
Q13
69
Q14
68
Q15
67
Q16
66
Q17
59
Q18
58
Q19
57
Q20
56
Q21
55
Q22
54
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
Q33
Q34
Q35
33
33
33
53
52
51
48
33
47
46
45
44
43
33
42
41
40
33
Figure 9.6. Digital Display Schematic
The 3.3 V to the level-shifters and pull-up resistors should be powered-down whenever the 3.3 V is powered-down on
the receiver itself.
The receiver INT output can be connected as an interrupt to the microcontroller, or the microcontroller can poll
register 0x70 (INTR_STATE) to determine if any of the enabled interrupts have occurred. Refer to the SiI-PR-1033
Programmer Reference for details. The receiver VSYNC output can be connected to the microcontroller if it is necessary
to monitor the vertical refresh rate of the incoming video.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
67
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.8.4. Digital Audio Output Connections
+3.3 V
SiI9127A/SiI1127A
Ferrite
XTALVCC
SCK
WS
0.1F
SD0
0.01 F
SPDIF
DCLK
DR[ 2:0]
DL[ 2:0]
MCLKOUT
XTALIN
18 pF
MUTEOUT
33
1 M
27.00
MHz
XTALOUT
18 pF
Place crystal circuit as
closely to package as
possible.
Figure 9.7. Audio Output Schematic
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
68
SiI-DS-1059-C
SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.8.5. Control Signal Connections
+3.3 V
SiI9127A/
Si1127A
4.7
k
4.7
k
CSDA
CSDA
CSCL
CSCL
EVEN/ODD Field
EVNODD
RSVDL
4.7 k
Microcontroller
GPIO
SCDT and INT outputs to micro are optional
.
Sync status and interrupt bits may be polled
through CSDA/ CSCL I2C port
.
RESET#
GPIO
SCDT
GPIO
INT
GPIO
Firmware monitors Hot Plug Detect signal
to trigger EDID re
- read and inhibit HDCP
authentication attempts
.
HPD
HDMI
Connector
Figure 9.8. Controller Connections Schematic
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
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SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
9.9.
Layout
Figure 9.9 shows an example of routing TMDS lines between the SiI9127A/SiI1127A device and the HDMI connector.
9.9.1. TMDS Input Port Connections
DDC SCL
TMDS Data 2+
DDC SDA
TMDS Data 2-
Hot Plug
Detect
TMDS Data 1+
Connector
Shell
TMDS Data 1TMDS Data 0+
+5V Power
DDC Ground
Reserved NC
CEC
TMDS Clock-
TMDS Data 0TMDS Clock
Shield
TMDS
Clock+
TMDS Data Shield
TMDS Data Shield
TMDS Data Shield
Figure 9.9. TMDS Input Signal Assignments
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Data Sheet
10. Package Information
10.1. ePad Requirements
The SiI9127A/SiI1127A receiver is packaged in a 128-pin, 14 mm x 14 mm TQFP package with an ePad that is used for
the electrical ground of the device and for improved thermal transfer characteristics. The ePad dimensions are 4.445
mm x 4.0604 mm ±0.15 mm. Soldering the ePad to the ground plane of the PCB is required to meet package power
dissipation requirements at full speed operation, and to correctly connect the chip circuitry to electrical ground. A
clearance of at least 0.25 mm should be designed on the PCB between the edge of the ePad and the inner edges of the
lead pads to avoid the possibility of electrical shorts.
The thermal land area on the PCB may use thermal vias to improve heat removal from the package. These thermal vias
also double as the ground connections of the chip and must attach internally in the PCB to the ground plane. An array
of vias should be designed into the PCB beneath the package. For optimum thermal performance, the via diameter
should be 12 mils to 13 mils (0.30 mm to 0.33 mm) and the via barrel should be plated with 1-ounce copper to plug the
via. This design helps to avoid any solder wicking inside the via during the soldering process, which may result in voids
in solder between the pad and the thermal land. If the copper plating does not plug the vias, the thermal vias can be
tented with solder mask on the top surface of the PCB to avoid solder wicking inside the via during assembly. The
solder mask diameter should be at least 4 mils (0.1 mm) larger than the via diameter.
Package stand-off when mounting the device also needs to be considered. For a nominal stand-off of approximately
0.1 mm the stencil thickness of 5 mils to 8 mils should provide a good solder joint between the ePad and the thermal
land.
Figure 10.1 on the next page shows the package dimensions of the SiI9127A/SiI1127A receiver.
10.2. PCB Layout Guidelines
Refer to Lattice Semiconductor application note PCB Layout Guidelines: Designing with Exposed Pads (see Lattice
Semiconductor Documents on page 74) for basic PCB design guidelines when designing with thermally enhanced
packages using the exposed pad. This application note is intended for use by PCB layout designers.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
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SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
10.3. Package Dimensions
Figure 10.1 shows the layout and dimensions of the 128-pin TQFP package. Package drawings are not to scale.
D
D1
D2
4.064 ± 0.15
96
65
R1
97
64
R2
A
A
GAGE PLANE
.25
A
4.445 ± 0.15
S
B
L
E2 E1 E
L1
SECTION A-A
33
128
Pin 1
Identifier
1
e
32
b
0.07
M
CA B
S
A BD
A BD
0.20 C
0.20 H
DS
TOP VIEW
0.05
S
0.08
A A2
A1
L1
C
c
Seating Plane
C
SIDE VIEW
JEDEC Package Code MS-026-AFB
Item
Description
Typ
Max
Item
Description
Typ
Max
A
A1
Thickness
Stand-off
1.10
0.10
1.20
0.15
b
c
Lead width
Lead thickness
0.16
—
0.23
0.20
A2
D
E
Body thickness
Footprint
Footprint
1.00
1.05
e
L
L1
Lead pitch
Lead foot length
Lead length
0.60
D1
E1
D2
Body size
Body size
Lead Row Width
14.00
14.00
12.40
E2
Lead Row Width
12.40
16.00
16.00
0.40
0.75
1.00
Dimensions are in millimeters.
Overall thickness A = A1 + A2.
Figure 10.1. 128-Pin TQFP Package Diagram
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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Data Sheet
10.4. Marking Specification
Figure 10.2 shows the markings of the SiI9127A package. This drawing is not to scale. Refer to the specifics in
Figure 10.1 on the previous page.
Logo
Product Line
SiI9127ACTU
LLLLLL.LL-L
YYWW
TTTTTTmmmr
Part Number
Lot # (= Job#)
Date code
Trace code
Pin 1
location
Figure 10.2. Marking Diagram of SiI9127A
10.5. Ordering Information
Production Part Numbers:
TMDS Input Clock Range
Part Number
25 MHz–225 MHz
SiI9127ACTU
25 MHz–225 MHz
SiI1127ACTU
The universal package may be used in lead-free and ordinary process lines.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
SiI-DS-1059-C
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SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
References
Standards Documents
This is a list of standards abbreviations appearing in this document, and references to their respective specifications
documents.
Abbreviation
Standards publication, organization, and date
HDMI
High-Definition Multimedia Interface, Revision 1.4b, HDMI Consortium; October 2011
High-Definition Multimedia Interface, Revision 1.4a, HDMI Consortium; March 2010
HCTS
High Definition Multimedia Interface, Revision 1.3, HDMI Consortium; June 2006
HDMI Compliance Test Specification, Revision 1.2a, HDMI Consortium; December 2005
HDCP
E-EDID
E-DID IG
High-bandwidth Digital Content Protection, Revision 1.3, Digital Content Protection, LLC; December 2006
Enhanced Extended Display Identification Data Standard, Release A Revision 1, VESA; Feb. 2000
VESA EDID Implementation Guide, VESA; June 2001
CEA-861
CEA-861-B
CEA-861-D
A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA; January 2001
A DTV Profile for Uncompressed High Speed Digital Interfaces, Draft 020328, EIA/CEA; March 2002
A DTV Profile for Uncompressed High Speed Digital Interfaces, EIA/CEA; July 2006
EDDC
Enhanced Display Data Channel Standard, Version 1.1, VESA; March 2004
Standards Groups
For information on the specifications that apply to this document, contact the responsible standards groups appearing
on this list.
Standards Group
Web URL
ANSI/EIA/CEA
VESA
DVI
http://global.ihs.com
http://www.vesa.org
http://www.ddwg.org
HDCP
HDMI
http://www.digital-cp.com
http://www.hdmi.org
Lattice Semiconductor Documents
This is a list of the related documents that are available from your Lattice Semiconductor sales representative. The
Programmer Reference requires an NDA with Lattice Semiconductor.
Document
Title
SiI-PR-1033
SiI-PR-0041
SiI9127A/SiI1127A HDMI Receiver with Deep Color Outputs Programmer Reference
CEC Programming Interface (CPI) Programmer Reference
SiI-AN-0129
PCB Layout Guidelines: Designing with Exposed Pads Application Note
Technical Support
For assistance, submit a technical support case at www.latticesemi.com/techsupport.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
74
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SiI9127A/SiI1127A HDMI Receiver with Deep Color Output
Data Sheet
Revision History
Revision C, February 2016
Added SiI1127A receiver support. Updated to latest template.
Revision B, December 2012
2
Added local I C device addresses and 3D video format support.
Revision A03, September 2010
Removed Patent information from DB, rolled the revision for DS.
Revision A02, May 2010
Rewrite page 1; minor content corrections; light copyedit; update package drawing; prepare Data Brief.
Revision A01, April 2009
Removed audio downsampling, output delay control, video output pull-down information; updated specifications and
layout.
Revision A, October 2008
First production release.
© 2009-2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are
trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
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