CD40105BMS CMOS FIFO Register December 1992 Features Description • 4 Bits x 16 Words CD40105BMS is a low-power first-in-first-out (FIFO) “elastic” storage register that can store 16 4-bit words. It is capable of handling input and output data at different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. • High Voltage Type (20V Rating) • Independent Asynchronous Inputs and Outputs • 3-State Outputs • Expandable in Either Direction • Status Indicators on Input and Output • Reset Capability • Standardized Symmetrical Output Characteristics • 100% Tested for Quiescent Current at 20V • 5V, 10V and 15V Parametric Ratings • Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices” Each word position in the register is clocked by a control flipflop, which stores a marker bit. A “1” signifies that the position’s data is filled and a “0” denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the “0” state and sees a “1” in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to “0”. The first and last control flip-flops have buffered outputs. Since all empty locations “bubble” automatically to the input end, and all valid data ripple through to the output end, the status of the first control flip-flop (DATA-IN READY) indicates if the FIFO is full, and the status of the last flip-flop (DATAOUT READY) indicates if the FIFO contains data. As the earliest data are removed from the bottom of the data stack (the output end), all data entered later will automatically propagate (ripple) toward the output. Loading Data - Data can be entered whenever the DATA-IN READY (DIR) flag is high, by a low to high transition on the SHIFT-IN (SI) input. This input must go low momentarily before the next word is accepted by the FIFO. The DIR flag will go low momentarily, until that data have been transferred to the second location. The flag will remain low when all 16word locations are filled with valid data, and further pulses on the SI input will be ignored until DIR goes high. Applications • Bit Rate Smoothing • CPU/Terminal Buffering • Data Communications • Peripheral Buffering • Line Printer Input Buffers Continued on next page • Auto Dialers • CRT Buffer Memories • Radar Data Acquisition Pinout Functional Diagram CD40105BMS TOP VIEW 3 - STATE CONTROL 1 DIR SI 2 3 3-STATE CONTROL 16 VDD 15 SO D0 14 DOR D1 D0 4 13 Q0 D1 5 12 Q1 D2 6 11 Q2 D3 7 10 Q3 VSS 8 9 MR D2 D3 SHIFT IN SHIFT OUT MASTER RESET CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 7-1317 1 4 13 5 12 6 11 7 10 3 14 15 2 9 Q0 Q1 Q2 Q3 DATA-OUT READY DATA-IN READY VDD = 16 VSS = 8 File Number 3353 CD40105BMS be gated together with AND gates. Their outputs drive the SI and SO inputs in parallel, if expanding is done in both directions (see Figures 9 and 11). Unloading Data - As soon as the first word has rippled to the output, DATA-OUT READY (DOR) goes high, and data can be removed by a falling edge on the SO input. This falling edge causes the DOR signal to go low while the word on the output is dumped and the next word moves to the output. As long as valid data are available in the FIFO, the DOR signal will go high again signifying that the next word is ready at the output. When the FIFO is empty, DOR will remain low, and any further commands will be ignored until a “1” marker ripples down to the last control register, when DOR goes high. Unloading of data is inhibited while the 3-state control input is high. The 3-state control signal should not be shifted from high to low (data outputs turned on) while the SHIFTOUT is at logic 0. This level change would cause the first word to be shifted out (unloaded) immediately and the data to be lost. 3-State Outputs - In order to facilitate data busing, 3-state outputs are provided on the data output lines, while the load condition of the register can be detected by the state of the DOR output. Master Reset - A high on the MASTER RESET (MR) sets all the control logic marker bits to “0”. DOR goes low and DIR goes high. The contents of the data register are not changed, only declared invalid, and will be superseded when the first word is loaded. The shift-in must be low during Master Reset. The CD40105BMS is supplied in these 16-lead outline packages: Cascading - The CD40105BMS can be cascaded to form longer registers simply by connecting the DIR to SO and DOR to SI. In the cascaded mode, a MASTER RESET pulse must be applied after the supply voltage is turned on. For words wider than 4 bits, the DIR and the DOR outputs must Braze Seal DIP Frit Seal DIP Ceramic Flatpack H4X H1F H6W Logic Diagram 2 MASTER RESET * SHIFT OUT DATA IN READY (DIR) * 15 1 * 9 3 - STATE CONTROL (OUTPUT ENABLE) SHIFT IN DATA READY 3 POSITIONS * R R Q R 1 S *D0 Q S Q R Q S 16 Q S Q 13 Q0 CL 5 *D2 6 D3 S R 4 - 15 2 4 *D1 * Q Q 14 (DOR) CL CL 4 LATCHES CL CL 4 LATCHES CL 4 LATCHES CL CL 3 STATE OUTPUT BUFFERS 4 LATCHES 12 Q1 11 Q2 10 Q3 7 POS 1 *ALL INPUTS PROTECTED BY POS 2 POS 3 POS 16 CL DETAIL OF LATCHES VDD p COS/MOS PROTECTION NETWORK n CL CL p n CL VSS 7-1318 Specifications CD40105BMS Absolute Maximum Ratings Reliability Information DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Thermal Resistance . . . . . . . . . . . . . . . . θja θjc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W Maximum Package Power Dissipation (PD) at +125oC For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K). . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Supply Current SYMBOL IDD CONDITIONS (NOTE 1) VDD = 20V, VIN = VDD or GND GROUP A SUBGROUPS LIMITS TEMPERATURE o 1 +25 C o 2 Input Leakage Current IIL IIH Output Voltage VOL15 - 10 µA - 1000 µA 3 -55 C - 10 µA 1 +25oC -100 - nA 2 +125oC -1000 - nA 3 -55oC -100 - nA 1 +25oC - 100 nA 2 +125oC - 1000 nA 3 -55oC VDD = 20 VIN = VDD or GND VDD = 20 VDD = 15V, No Load - 100 nA 1, 2, 3 +25oC, +125oC, -55oC - 50 mV 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA 1 +25oC 3.5 - mA IOL15 VDD = 15V, No Load (Note 3) o Output Current (Sink) Output Current (Sink) VOH15 UNITS VIN = VDD or GND VDD = 18V Output Voltage MAX VDD = 18V, VIN = VDD or GND VDD = 18V Input Leakage Current +125 C MIN VDD = 15V, VOUT = 1.5V Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA 1 +25oC - -1.4 mA 1 +25oC - -3.5 mA -2.8 -0.7 V 0.7 2.8 V Output Current (Source) Output Current (Source) IOH10 IOH15 VDD = 10V, VOUT = 9.5V VDD = 15V, VOUT = 13.5V N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC VDD = 2.8V, VIN = VDD or GND 7 +25oC VDD = 20V, VIN = VDD or GND 7 +25oC VDD = 18V, VIN = VDD or GND 8A +125oC VDD = 3V, VIN = VDD or GND 8B Functional (Note 4) F Input Voltage Low (Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage High (Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 Input Voltage Low (Note 2) VIL VDD = 15V, VOH > 13.5V, VOL < 1.5V Input Voltage High (Note 2) VIH VDD = 15V, VOH > 13.5V, VOL < 1.5V Tri-State Output Leakage IOZL VIN = VDD or GND VOUT = 0V VDD = 18V 7-1319 V -55oC +25oC, VDD = 20V VOH > VOL < VDD/2 VDD/2 +125oC, -55oC - 1.5 V +25oC, +125oC, -55oC 3.5 - V 1, 2, 3 +25oC, +125oC, -55oC - 4 V 1, 2, 3 +25oC, +125oC, -55oC 11 - V 1 +25oC -0.4 - µA 2 +125oC -12 - µA 3 -55oC -0.4 - µA Specifications CD40105BMS TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER Tri-State Output Leakage SYMBOL CONDITIONS (NOTE 1) IOZH VIN = VDD or GND VOUT = VDD LIMITS GROUP A SUBGROUPS TEMPERATURE MIN MAX UNITS 1 +25oC - 0.4 µA 2 +125oC - 12 µA 3 -55oC - 0.4 µA VDD = 20V VDD = 18V NOTES: 1. All voltages referenced to device GND, 100% testing being implemented. 2. Go/No Go test with limits applied to inputs. 3. For accuracy, voltage is measured differentially to VDD. Limit is 0.050V max. 4. VDD = 2.8V/3.0V, RL = 100K to VDD VDD = 20V/18V, RL = 10K to VDD TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS PARAMETER SYMBOL Propagation Delay Shift Out or Reset to Data-Out Ready TPHL1 Propagation Delay Shift In to Data-In Ready TPHL2 Propagation Delay Ripple through Delay Input to Output TPLH3 Propagation Delay 3-State Control to Data Out TPZH Transition Time TTHL TTLH Maximum Shift-In or Shift-Out Rate CONDITIONS (NOTE 1) GROUP A SUBGROUPS TEMPERATURE VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 1, 2) VDD = 5V, VIN = VDD or GND (Note 2, 3) VDD = 5V, VIN = VDD or GND (Note 1, 2) FCL VDD = 5V (Note 1, 2), VIN = VDD or GND 9 10, 11 9 10, 11 +25oC +125oC, -55oC +25oC +125oC, -55oC LIMITS MIN MAX UNITS - 370 ns - 500 ns - 320 ns - 432 ns 9 +25oC - 4 µs 10, 11 +125oC, -55oC - 5.4 µs 9 +25oC - 280 ns - 378 ns - 200 ns 10, 11 9 10, 11 +125oC, -55oC +25oC +125oC, -55oC - 270 ns 9 +25oC 1.5 - MHz 10, 11 +125oC, -55oC 1.11 - MHz MIN MAX UNITS µA NOTES: 1. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 2. -55oC and +125oC limits guaranteed, 100% testing being implemented. 3. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL IDD CONDITIONS NOTES VDD = 5V, VIN = VDD or GND VDD = 10V, VIN = VDD or GND VDD = 15V, VIN = VDD or GND Output Voltage VOL VDD = 5V, No Load 1, 2 1, 2 1, 2 1, 2 TEMPERATURE -55oC, +25oC - 5 +125oC - 150 µA -55oC, +25oC - 10 µA +125oC - 300 µA - 10 µA +125oC - 600 µA +25oC, +125oC, - 50 mV -55oC, +25oC -55oC Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC - 50 mV Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC, -55oC 4.95 - V Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC, -55oC 9.95 - V 7-1320 Specifications CD40105BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER Output Current (Sink) SYMBOL IOL5 CONDITIONS VDD = 5V, VOUT = 0.4V NOTES TEMPERATURE MIN MAX UNITS 1, 2 +125oC 0.36 - mA o Output Current (Sink) Output Current (Sink) Output Current (Source) IOL10 IOL15 IOH5A VDD = 10V, VOUT = 0.5V VDD = 15V, VOUT = 1.5V VDD = 5V, VOUT = 4.6V 1, 2 1, 2 1, 2 -55 C 0.64 - mA +125oC 0.9 - mA -55oC 1.6 - mA +125oC 2.4 - mA -55oC 4.2 - mA +125oC - -0.36 mA - -0.64 mA - -1.15 mA - -2.0 mA - -0.9 mA - -1.6 mA -55o Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 -55 Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 C +125oC oC +125oC o -55 C Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125o - -2.4 mA -55oC C - -4.2 mA Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC - 3 V Input Voltage High VIH VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC, -55oC 7 - V 1, 2, 3 +25oC - 180 ns Propagation Delay Shift or Reset to Data Out Ready TPHL1 Propagation Delay Ripple through Delay Input to Output TPLH3 Propagation Delay Shift-In to Data-In Ready TPHL2 Propagation Delay Shift Out to QN Out TPHL4 TPLH4 VDD = 10V o VDD = 15V 1, 2, 3 +25 C - 130 ns VDD = 10V 1, 2, 3 +25oC - 2 µs VDD = 15V 1, 2, 3 +25 oC - 1.4 µs VDD = 10V 1, 2, 3 +25oC - 130 ns VDD = 15V 1, 2, 3 +25oC - 90 ns 1, 2, 3 +25 oC - 420 ns VDD = 10V 1, 2, 3 +25oC - 380 ns VDD = 15V 1, 2, 3 +25oC - 250 ns 1, 2, 4 +25 oC - 120 ns - 80 ns VDD = 5V Propagation Delay 3-State Control to Data Out TPZH TPZL VDD = 10V VDD = 15V 1, 2, 4 +25oC Propagation Delay 3-State Control to Data Out TTHZ TPLZ VDD = 10V 1, 2, 3 +25oC - 100 ns VDD = 15V 1, 2, 3 +25oC - 80 ns FCL VDD = 10V 1, 2 +25oC 3 - MHz 1, 2 +25oC 4 - MHz VDD = 5V 3 +25oC - 15 µs VDD = 10V 3 +25oC - 15 µs VDD = 15V 3 +25oC - 15 µs VDD = 5V 3 +25oC - 15 µs 3 +25oC - 15 µs VDD = 15V 3 +25oC - 15 µs VDD = 5V 3 +25oC - 15 µs 3 +25oC - 5 µs 3 +25oC - 5 µs Maximum Shift-In or Shift-Out Rate Maximum Shift-In or Shift-Out Rise Time Maximum Shift-In Fall Time Maximum Shift-Out Fall Time VDD = 15V TR TF VDD = 10V TF VDD = 10V VDD = 15V 7-1321 Specifications CD40105BMS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued) LIMITS PARAMETER SYMBOL Minimum Master Reset Pulse Width TWH Data-In Ready Pulse Width TWL Data-Out Ready Pulse Width TWL Minimum Shift Out Pulse Width TWL CONDITIONS VDD = 5V TSU TH TW CIN UNITS 1, 2, 3 - 200 ns o +25 C - 90 ns 1, 2, 3 +25oC - 60 ns 1, 2, 3 +25 oC - 520 ns VDD = 10V 1, 2, 3 +25oC - 200 ns VDD = 15V 1, 2, 3 +25oC - 140 ns 1, 2, 3 +25 oC - 440 ns VDD = 10V 1, 2, 3 +25o C - 180 ns VDD = 15V 1, 2, 3 +25oC - 130 ns VDD = 5V 1, 2, 3 +25 oC - 180 ns VDD = 10V 1, 2, 3 +25oC - 75 ns 1, 2, 3 o +25 C - 55 ns VDD = 5V 1, 2, 3 +25o C - 0 ns VDD = 10V 1, 2, 3 +25oC - 0 ns 1, 2, 3 +25oC - 0 ns VDD = 5V 1, 2, 3 +25 oC - 350 ns VDD = 10V 1, 2, 3 +25oC - 150 ns 1, 2, 3 o +25 C - 120 ns VDD = 5V 1, 2, 3 +25 oC - 200 ns VDD = 10V 1, 2, 3 +25oC - 80 ns 1, 2, 3 oC - 60 ns +25oC - 7.5 pF VDD = 5V VDD = 5V VDD = 15V Input Capacitance MAX +25oC 1, 2, 3 VDD = 15V Minimum Shift In Pulse Width MIN VDD = 15V VDD = 15V Minimum Data Hold Time TEMPERATURE VDD = 10V VDD = 15V Minimum Data Setup Time NOTES Any Input +25 1, 2 NOTES: 1. All voltages referenced to device GND. 2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial design release and upon design changes which would affect these characteristics. 3. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. CL = 50pF, RL = 1K, Input TR, TF < 20ns. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS LIMITS PARAMETER Supply Current SYMBOL CONDITIONS NOTES TEMPERATURE MIN MAX UNITS IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC - 25 µA 1, 4 +25oC -2.8 -0.2 V 1, 4 +25oC - ±1 V N Threshold Voltage VNTH N Threshold Voltage Delta ∆VTN P Threshold Voltage P Threshold Voltage Delta Functional VDD = 10V, ISS = -10µA VDD = 10V, ISS = -10µA VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC - ±1 V 1 +25oC VOH > VDD/2 VOL < VDD/2 V 1, 2, 3, 4 +25oC - 1.35 x +25oC Limit ns F VDD = 18V, VIN = VDD or GND VDD = 3V, VIN = VDD or GND Propagation Delay Time TPHL TPLH VDD = 5V 3. See Table 2 for +25oC limit. NOTES: 1. All voltages referenced to device GND. 2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 4. Read and Record 7-1322 Specifications CD40105BMS TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC PARAMETER SYMBOL DELTA LIMIT Supply Current - MSI-2 IDD ± 1.0µA Output Current (Sink) IOL5 ± 20% x Pre-Test Reading IOH5A ± 20% x Pre-Test Reading Output Current (Source) TABLE 6. APPLICABLE SUBGROUPS MIL-STD-883 METHOD GROUP A SUBGROUPS Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A 100% 5004 1, 7, 9, Deltas 100% 5004 1, 7, 9 100% 5004 1, 7, 9, Deltas CONFORMANCE GROUP PDA (Note 1) Interim Test 3 (Post Burn-In) PDA (Note 1) Final Test Group B IDD, IOL5, IOH5A 100% 5004 2, 3, 8A, 8B, 10, 11 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11 Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroup B-6 Sample 5005 1, 7, 9 Sample 5005 1, 2, 3, 8A, 8B, 9 Group A Group D READ AND RECORD Subgroups 1, 2, 3, 9, 10, 11 Subgroups 1, 2 3 NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION CONFORMANCE GROUPS TEST READ AND RECORD MIL-STD-883 METHOD PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD 5005 1, 7, 9 Table 4 1, 9 Table 4 Group E Subgroup 2 TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS OSCILLATOR FUNCTION OPEN GROUND VDD Static Burn-In 1 Note 1 2, 10 - 14 1, 3 - 9, 15 16 Static Burn-In 2 Note 1 2, 10 - 14 8 1, 3 - 7, 9, 15, 16 Dynamic Burn-In Note 1 - 1, 8, 9 16 2, 10 - 14 8 1, 3 - 7, 9, 15, 16 Irradiation Note 2 9V ± -0.5V 50kHz 25kHz 2, 10 - 14 3, 15 4-7 NOTES: 1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V 2. Each pin except VDD and GND will have a series resistor of 47K ± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V ± 0.5V 7-1323 CD40105BMS 30 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 25 20 15 10V 10 5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) AMBIENT TEMPERATURE (TA) = +25oC 15.0 GATE-TO-SOURCE VOLTAGE (VGS) = 15V 12.5 10.0 10V 7.5 5.0 2.5 5V 0 5 10 15 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT CHARACTERISTICS DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 DRAIN-TO-SOURCE VOLTAGE (VDS) (V) -15 -10 -5 AMBIENT TEMPERATURE (TA) = +25oC GATE-TO-SOURCE VOLTAGE (VGS) = -5V 0 -5 -10 -15 -10V -20 -25 -15V -30 -5 -10V POWER DISSIPATION PER GATE (PD) (µW) (ALL Q OUTPUTS LOADED) TRANSITION TIME (tTHL, tTLH) (ns) SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 106 8 6 4 AMBIENT TEMPERATURE (TA) = +25oC 2 SUPPLY VOLTAGE (VDD) = 15V 105 8 6 4 104 10V 2 8 6 4 103 102 20 -15 FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 200 0 0 -10 -15V AMBIENT TEMPERATURE (TA) = +25oC 50 0 GATE-TO-SOURCE VOLTAGE (VGS) = -5V FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS 150 0 AMBIENT TEMPERATURE (TA) = +25oC OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) 0 OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA) AMBIENT TEMPERATURE (TA) = +25oC OUTPUT LOW (SINK) CURRENT (IOL) (mA) OUTPUT LOW (SINK) CURRENT (IOL) (mA) Typical Performance Characteristics 10V 5V 2 8 6 4 CL = 50pF 2 CL = 15pF 2 40 60 80 100 LOAD CAPACITANCE (CL) (pF) 1 FIGURE 6. TYPICAL TRANSITION TIME AS A FUNCTION OF LOAD CAPACITANCE 4 68 2 4 68 2 4 68 2 4 68 103 10 102 INPUT FREQUENCY (fIN) (kHz) 2 4 68 104 FIGURE 7. TYPICAL DYNAMIC POWER DISSIPATION AS A FUNCTION OF FREQUENCY 7-1324 CD40105BMS INPUT BUFFERS D0 4 D1 5 D2 6 D3 7 OUTPUT BUFFERS 13 Q0 12 Q1 4 x 16 DATA REGISTER 11 Q2 SI DOR D0 Q0 D1 Q1 D2 Q2 D3 Q3 DIR MR SO 10 Q3 1 DATA-IN READY (DIR) 2 SI DOR D0 Q0 D1 Q1 D2 Q2 D3 Q3 DIR MR SO 3-STATE CONTROL 14 CONTROL LOGIC DATA-OUT READY (DOR) 3 15 SHIFT IN (SI) 9 MASTER RESET (MR) SHIFT OUT (SO) FIGURE 8. CD40105BMS FUNCTIONAL BLOCK DIAGRAM FIGURE 9. EXPANSION, 4-BITS WIDE-BY-16 N-BITS LONG MASTER RESET SHIFT IN (DATA VALID) INPUTS SHIFT-IN PULSES HAVE NO EFFECT ≈ 2µs* SHIFT OUT SHIFT-OUT PULSES HAVE NO EFFECT ≈ 2µs** INPUT READY (CLEAR OUT) OUTPUTS OUTPUT READY (CLEAR OUT) DATA IN (Dn) INPUTS 3-STATE (OUTPUT ENABLE) DATA OUT*** 1 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 HIGH Z (UNKNOWN) *AT VDD =5V - RIPPLE TIME FROM POSITION 1 TO POSITION 16 **AT VDD = 5V - RIPPLE TIME FROM POSITION 16 TO POSITION 1 ***DATA VALID goes to high level in advance of the DATA OUT 1 0 by maximum of 50ns at VDD = 5V, 25ns at VDD = 10V, and 20ns at VDD = 15V for CL = 50pF and TA = 25oC FIGURE 10. TIMING DIAGRAM FOR THE CD40105BMS 7-1325 1 1 1 0 INVALID CD40105BMS DATA OUT READY SHIFT IN SI DOR D0 Q0 SI DOR D0 Q0 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D3 Q3 D3 Q3 MR DIR SO MR DIR SO 8 BIT DATA 8 BIT DATA SI DOR D0 Q0 SI DOR D0 Q0 D1 Q1 D1 Q1 D2 Q2 D2 Q2 D3 Q3 D3 Q3 MR DIR SO MR DIR SO SHIFT OUT DATA IN READY *MASTER RESET *Pulse must be applied for cascading by 16 N bits. FIGURE 11. EXPANSION, 8-BITS-WIDE-BY-16 N-BITS LONG USING CD40105BMS Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: PASSIVATION: BOND PADS: Thickness: 11kÅ − 14kÅ, AL. 10.4kÅ - 15.6kÅ, Silane 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 1326