Freescale Semiconductor Advance Information Document Number: MC33789 Rev. 4.0, 9/2014 Airbag System Basis Chip (SBC) with Power Supply and PSI5 Sensor Interface 33789 AUTO RESTRAINT The 33789, a SafeAssure SMARTMOS solution, is a mixed signal IC for airbag safety applications. The 33789 provides a cost effective and flexible system IC solution across the range of airbag partitions used in cars and other vehicles. The 33789 connects to the 12 V vehicle battery and supplies the multiple voltages of a typical airbag system. The 33789 can detect switched input states, communicate with both local and remote crash sensors. It offers an industry standard interface (SPI) and four PSI5 master interfaces. The 33789 has a AE SUFFIX (PB-FREE) dedicated safing state machine that complements the airbag’s MCU hardware/ EXPOSED PAD software safing approach. Also included are a diagnostic - self protection 98ASA10763D capability and a programmable analog interface accessible by the system MCU. 64-PIN LQFP The 33789 is well suited for use in low to high end airbag systems by allowing the designer to scale a design for the number of firing loops needed while providing enhanced safety and system reliability. Applications Features • Airbag safety • Designed to operate 5.2 V VPWR 20 V, up to a 40 V transient • Safing state machine with programmable sensing thresholds • Two configurable high-side/low-side drivers with PWM capability • Four PSI5 satellite sensor master interfaces • Self-protected and diagnostic capability • Watchdog and system Power ON Reset (POR) • Supports complete airbag system power supply architecture, including system power mode control, supplies for squib firing (33 V), satellite sensors (6.3 V), and local ECU sensors and ECU logic circuits (5.0 V) • Nine configurable switch input monitors for simple switch and Hall- effect sensor interfaces with internal power supply • 16-bit SPI interface • LIN 2.1 physical layer interface 33789 VBAT IN1 IN2 9 Input Monitors IN8 IN9 LIN PSI5_1 4 Satellite Sensor Interfaces Wake Up WAKE BSTSW 33 V VBST VER PSI5_2 PSI5_3 VBAT VPWR ERSW PSI5_4 VPWR OUT1_D OUT1_S 5.0 V X/Y Axis Accel. Sensor Sensor SPI 5.0 V VFIRE_x SQB_H1 SQB_H1 BUCKSW VBUCK VCCDRI SPI 5.0 V Energy Storage 9.0 V 5.0 V Output Squib Driver 1 VCC SQB_L1 5.0 V SPI_A VDD AIN SQB_L1 AOUT ARM RESET RESET SPI_B MCU Squib Driver 2 FEN_1 FEN_2 Squib Driver SPI RESET SPI 2 ARM_X and ARM_Y for Squib Driver 2 FENs Figure 1. 33789 Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010-2014. All rights reserved. Cross-coupled Squib Connections ORDERABLE PARTS ORDERABLE PARTS This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://www.freescale.com and perform a part number search for the following device numbers. Table 1. Orderable Part Variations Part Number MCZ33789BAE Notes Temperature (TA) (1) -40 °C to 125 °C Package 64 LQFP EP Notes 1. To order parts in Tape & Reel, add the R2 suffix to the part number. 33789 2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM INTERNAL BLOCK DIAGRAM SI Power Mode Control SPI Interface SO SCK VREF WAKE VPWR CS BSTSW CS_A CS_B CS_C Boost Converter SPI Monitor DISARM VBST Safing A_SENSOR ARM BSTGND BSTCOMP1 BSTCOMP2 Safing Logic ASST Configurable Drivers OUT1_D OUT1_S VER Energy Reserve Control SCRAP ERSW VERDIAG OUT2_D VBUCK OUT2_S CLK PSI5 Satellite Sensor Interfaces SATSYNC PSI5_1 PSI5_2 BUCKSW Buck Converter BUCKGND VBUCK_R BUCKCOMP1 BUCKCOMP2 PSI5_3 PSI5_4 CPC1 GND_PSI IN1 Analog Multiplexer IN2 IN3 Quad Bias Voltage Regulator CPC2 Sync Supply VSYNC CPGND IN4 IN5 IN6 IN7 Linear Regulator & Watchdog IN8 IN9 Analog Multiplexer AOUT VREF LIN Interface Power Supply I/O Monitor GNDA VCC VDD RESET PPT Analog Multiplexer Driver Output OUTx Monitor VCCDRI VSS TXD LIN RXD GND_LIN Figure 2. 33789 Simplified Internal Block Diagram 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 3 PIN CONNECTIONS VERDIAG BUCKGND BUCKSW VBST ERSW BSTGND BSTSW VER WAKE VPWR VSYNC CPC2 CPC1 CPGND Transparent Top View VBUCK_R VBUCK PIN CONNECTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ASST 1 48 BUCKCOMP1 CS_C 2 47 BUCKCOMP2 CS_B 3 46 BSTCOMP1 CS_A 4 45 BSTCOMP2 SCRAP 5 44 VDD PSI5_1 6 43 VSS PSI5_2 7 42 VCC PSI5_3 8 41 GNDA PSI5_4 9 40 VCCDRI GND_PSI 10 39 DISARM SO 11 38 ARM SI 12 37 RESET SCK 13 36 AOUT CLK 14 35 RXD CS 15 34 TXD SATSYNC 16 33 A_SENSOR IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 IN9 GND_LIN LIN OUT1_D OUT1_S PPT OUT2_S OUT2_D 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 3. 33789 Pin Connections A functional description of each pin can be found in the Functional Pin Description section beginning on page 26. Table 2. 33789 Pin Definitions Pin Number Pin Name Pin Function Formal Name 1 ASST Input Analog Sensor Self-test 2 CS_C Input Chip Select C Active low SPI monitor chip select input dedicated for on-board sensor C. 3 CS_B Input Chip Select B Active low SPI monitor chip select input dedicated for on-board sensor B 4 CS_A Input Chip Select A Active low SPI monitor chip select input dedicated for on-board sensor A 5 SCRAP Input Scrap 6 PSI5_1 Input/Output PSI5 Interface 1 PSI5 standard interface 1 as satellite sensor channel 1 7 PSI5_2 Input/Output PSI5 Interface 2 PSI5 standard interface 2 as satellite sensor channel 2 8 PSI5_3 Input/Output PSI5 Interface 3 PSI5 standard interface 3 as satellite sensor channel 3 9 PSI5_4 Input/Output PSI5 Interface 4 PSI5 standard interface 4 as satellite sensor channel 4 10 GND_PSI Ground PSI Ground 11 SO Output SPI Data Out 12 SI Input SPI Data In SPI data input 13 SCK Input SPI Clock SPI clock input 14 CLK Input Satellite Sensor Clock 15 CS Input SPI Chip Select Definition Active high input to initiate analog sensor self-test Scrap command input Dedicated ground point for PSI5 sensor SPI data output Clock input for the PSI5 sensor interface(s) running in synchronous operation mode Active low SPI chip select input from MCU, also used for satellite channels on SPI monitor 33789 4 Analog Integrated Circuit Device Data Freescale Semiconductor PIN CONNECTIONS Table 2. 33789 Pin Definitions (continued) Pin Number Pin Name Pin Function Formal Name 16 SATSYNC Input Satellite Sync-pulse Trigger Satsync command input from MCU to trigger PSI5 Sync-pulse 17 OUT2_D Output Output Driver2 Drain Drain pin of the configurable driver2 outputs 18 OUT2_S Output Output Driver2 Source 19 PPT Input Production Programming and Testing 20 OUT1_S Output Output Driver1 Source 21 OUT1_D Output Output Driver1 Drain 22 LIN Input/output LIN Interface LIN interface. It can be configured as a bi-directional pin which represents the singlewire bus transmitter and receiver 23 GND_LIN Ground LIN Ground Dedicated ground point for a bi-directional pin which represents the single-wire bus transmitter and receiver 24 IN9 Input Input Monitor Port 9 Port 9 of input monitor for DC sensor 25 IN8 Input Input Monitor Port 8 Port 8 of input monitor for DC sensor 26 IN7 Input Input Monitor Port 7 Port 7 of input monitor for DC sensor 27 IN6 Input Input Monitor Port 6 Port 6 of input monitor for DC sensor 28 IN5 Input Input Monitor Port 5 Port 5 of input monitor for DC sensor 29 IN4 Input Input Monitor Port 4 Port 4 of input monitor for DC sensor 30 IN3 Input Input Monitor Port 3 Port 3 of input monitor for DC sensor 31 IN2 Input Input Monitor Port 2 Port 2 of input monitor for DC sensor 32 IN1 Input Input Monitor Port 1 Port 1 of input monitor for DC sensor 33 A_SENSOR Input Analog Sensor Input Analog sensor input for safing 34 TXD Input Data Input from UART Logic-level data input from MCU UART transmitter for LIN/K-line 35 RXD Output Data Output to UART Logic-level data output to MCU UART receiver for LIN/K-line 36 AOUT Output Analog Output 37 RESET Output Reset 38 ARM Output Arm Enable Active high safing enable signal to squib driver 39 DISARM Output Arm Disable Active low safing enable signal to squib driver 40 VCCDRI Output VCC Bypass Transistor Drive 41 GNDA Ground Analog Ground 42 VCC Input VCC Input 43 VSS Ground Digital Ground 44 VDD Output Digital Power Supply Output 45 BSTCOMP2 Input Boost Compensation pin2 Connection 2 to the boost converter compensation network 46 BSTCOMP1 Input Boost Compensation pin1 Connection 1 to the boost converter compensation network 47 BUCKCOM P2 Input Buck Compensation pin2 Connection 2 to the buck converter compensation network 48 BUCKCOM P1 Input Buck Compensation pin1 Connection 1 to the buck converter compensation network Definition Source pin of the configurable driver2 outputs Active high input to enable test-mode for production programming and testing. Not for application Source pin of the configurable driver1 outputs Drain pin of the configurable driver1 outputs Analog output to send MCU scaled, multiplexed and buffered analog signals for diagnosis Active low reset output Linear regulator drive output to control an external PNP transistor for 5.0 V VCC output Analog ground 5.0 V VCC input for monitoring and internal supply Digital ground 2.5 V linear regulator output for output capacitor connection. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 5 PIN CONNECTIONS Table 2. 33789 Pin Definitions (continued) Pin Number Pin Name Pin Function Formal Name 49 VERDIAG Input Energy Reserve Diagnosis 50 BUCKGND Ground Buck Converter Ground 51 BUCKSW Output Buck Switch 52 VBST Input Boost Voltage Input 53 ERSW Output Energy Reserve Switch Storage driver output to control the energy reserve capacitor charging 54 BSTGND Ground Boost Converter Ground Ground return of the boost converter, buck switch ground 55 BSTSW Output Boost Switch 56 VER Input Energy Reserve Voltage 57 WAKE Input Wake-up 58 VPWR Input Power Supply 59 VSYNC Input/output Sensor Sync Power Supply 60 CPC2 Output Charge Pump Capacitor Pin2 Charge pump capacitor pin2 61 CPC1 Output Charge Pump Capacitor Pin1 Charge pump capacitor pin1 62 CPGND Ground Charge Pump Ground 63 VBUCK_R Input Buck Converter Redundant Input 64 VBUCK Input Buck Converter Input Definition AC coupled energy reserve diagnostic input Ground return of the buck converter, buck switch ground Buck switch driver output to connect buck inductor Boost voltage input for boost loop feedback and source of buck converter, same voltage as boost output Boost switch driver output to connect boost inductor Energy reserve voltage input for the storage capacitor charge control and energy reserve monitor Wake-up signal input to start-up boost and buck converters Battery voltage power supply input Satellite sensor sync voltage supply charge/discharge connection Charge pump ground Redundant buck converter input to supply current for charge pump Buck converter input for buck loop feedback and current source of charge pump 33789 6 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit Supply Input Voltage VPWR -0.3 to 40 V Wake-up Input Voltage VWAKE -16 to 40 V Supply Voltage - 1 VBST, VBSTSW, VBUCKSW, VERSW, VER -0.3 to 40 V Supply Voltage - 2 VSYNC, VCPC2 -0.3 to 20 V Supply Voltage - 3 VCPC1, VBUCK, VBUCK_R, VCCDRI -0.3 to 10 V Supply Voltage - 4 VERDIAG -0.3 to 7 V Supply Voltage - 5 VCC -0.3 to 5.5 V Supply Voltage - 6 VDD, VBSTCOMP1, VBSTCOMP2, VBUCKCOMP1, VBUCKCOMP2 -0.3 to 3 V ELECTRICAL RATINGS LIN Interface Voltage VLIN -27 to 40 V I/O Voltage - 1 VOUT1_D, VOUT1_S, VOUT2_D, VOUT2_S -1 to 40 V I/O Voltage - 2 VIN1 ~ VIN9, VPSI5_1 ~ VPSI5_4 -1 to 20 V I/O Voltage - 3 VARM, VDISARM, VPPT -0.3 to 10 V I/O Voltage - 4 VA_SENSOR, VAOUT, VASST, VSCRAP, VRESET, VTXD, VRXD, VSI, VSO, VSCK, VCLK, VCS, VCS_A, VCS_B, VCS_C, VSATSYNC -0.3 to 5.5 V VSS, VGND_LIN, VCPGND, VGND_PSI -0.3 to 0.3 V GND Shift LIN Bus Voltage(2) Normal Operation (DC) Transient (Coupled Through 1.0 nF Capacitor, according to ISO7637-2 & ISO7637-3) (See Table 4 and Figure 4) - Pulse 1 (test up to the limit for Damage - Class C(1)) - Pulse 2a (test up to the limit for Damage - Class C(1)) - Pulse 3a (test up to the limit for Damage - Class C(1)) - Pulse 3b (test up to the limit for Damage - Class C(1)) VBUS(SS) -27 to 40 VBUS(S1) -100 VBUS(S2A) +75 VBUS(S3A) -150 VBUS(S3B) +100 V Notes 1. Class C: At least one function of the transceiver stops working properly during the test, and will return to the proper operation automatically when the exposure to the disturbance has ended. No physical damage of the IC occurs. 2. The LIN bus voltage is applied on the LIN pin as VLIN during tests. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 7 ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings Symbol Value Unit ESD Capability AECQ100 Human Body Model - JESD22/A114(3) All pins VESD1-1 Charge Device Model - JESD22/C101(3) Corner pins VCCDRI pin All other pins VESD2-1 VESD2-2 VESD2-3 ± 2.0 k ± 750 ± 400 V ±500 Additional for LIN Conformance Contact Discharge, Unpowered(4) LIN pin without capacitor LIN pin with 220 pF capacitor LIN pin with 220 pF capacitor and indirect ESD coupling (according to ISO10605 - Annex F) VLIN_ESD1-1 VLIN_ESD1-2 VLIN_ESD1-3 ± 6.0 k ± 6.0 k ± 8.0 k THERMAL RATINGS Operating Temperature Junction Temperature Case (Exposed Pad) Temperature TJ TC -40 to 150 -40 to 125 °C TSTG -65 to +150 °C TPPRT Note 6 °C Junction to Ambient (Natural Convection) JA 26 °C/W Junction to Case (Exposed Pad) JC 1.5 °C/W Storage Temperature Peak Package Reflow Temperature During (6) Reflow(5), THERMAL RESISTANCE Notes 3. ESD testing is performed in accordance with the Human Body Model (HBM) (CZAP = 100 pF, RZAP = 1500 ), and the Charge Device Model (CDM) (CZAP = 4.0 pF). 4. According to “Hardware Requirements for LIN, CAN, and Flexray Interfaces in Automotive Applications” specification Rev. 1.1/December 2, 2009 (CZAP = 150 pF, RZAP = 330 ). 5. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics. 6. 33789 8 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 4. Limits / Maximum Test Voltage for LIN Pin Transient Immunity Tests Test Pulse VS [V] Pulse Repetition Frequency [Hz] (1/T1) Test Duration [min] Ri [W] Remarks 1 -100 2 10 10 t2 = 0s 2a +75 2 10 2 3a -150 10 10 50 3b +100 10 10 50 Notes 7. VSUP is applied on the VPWR pin as a test condition. The I/V characteristic and leakage of the pin is performed before and after the test. The supply pins and LIN must pass the VS voltage level specified in Table 4 without damage. The failure validation during test is evaluated at RxD. Tests perform in Normal mode on LIN (Failure on RxD), VSUP (Failure on LIN)(7). The voltage level found is for information only. Failure criteria on RxD in Normal Mode: 0.9 V and 7.5 µs DUT 1.0 nF LIN Transient Pulse Generator (Note) GND DUT GND Note Waveform per ISO 7637-2. Test Pulses 1, 2, 3a, 3b,. Figure 4. Test Circuit for Transient Test Pulses (LIN) 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 9 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes POWER MANAGEMENT VPWR Power Supply Input Voltage Normal Operation 5.2 - 20 VWAKE_TH Wake-up Threshold Voltage Normal VPWR Range 0.3* VPWR 0.5* VPWR 0.7* VPWR V V RWAKE Wake-up Input Internal Pull-down Resistance 120 200 320 VBST Boost Converter Output Voltage Normal VPWR Range, 0 IBST Max. IBST 31.6 33.3 35 Boost Overvoltage Threshold 36 38 40 V VBST_OV_CLMP Boost Overvoltage Clamping Boost operating with active clamping 40 43 46 V VBST_OV_HYS Boost Overvoltage Hysteresis 2.2 2.6 3.0 V Low VPWR as Boost Undervoltage Lockout Threshold and IGNSTAT Detect Threshold 4.7 4.95 5.2 V Boost Undervoltage Hysteresis 0.3 0.5 0.8 V - - 550 m VBST_OV VBST_UV VBST_UV_HYS k V RBSTSW_ON Boost Switch Transistor On Resistance IBSTSW_LMT Boost Switch Current Limit 1.3 1.5 1.8 A TSW_SHDN Power Switch Thermal Shutdown 155 175 195 °C TSW_HYST Power Switch Thermal Shutdown Hysteresis 15 - 30 °C ESRCERM Energy Reserve Capacitor ESR Measurement Range 200 - 600 m - CER ESR Measurement Tolerance -50 - 50 m - CER Capacitance Measurement Tolerance -15 - 15 % CER Charge Transistor On Resistance 3.0 10 14 CER Charge Transistor Overcurrent Shutdown Threshold 400 550 800 mA CER Discharge Transistor On Resistance 2.0 5.5 8.0 CER Discharge Transistor Overcurrent Shutdown Threshold 350 450 800 mA ERSW Pin Leakage Current - - 250 nA IVER_LEAK VER Pin Leakage Current - - 200 µA VER_RESD CER Residual Voltage after 10 s Discharge - - 2.5 V Buck Converter Output Voltage 10 V VBST 40 V, 100 mA IBUCK IBUCK_C 8.73 9.0 9.27 V Buck Converter Output Overvoltage Shutdown Threshold 9.6 10 10.8 V Low VBST as Buck Converter Start-up Threshold 13.5 15.5 17.5 V - - 460 mVPP RERSW_CH_ON IERSW_CH_SHDN RERSW_DISCH_ON IERSW_DISCH_SHDN IERSW_LEAK VBUCK VBUCK_OV_SHDN VBUCK_UV VBUCK_RIPL Buck Converter Output Ripple Voltage 6.0 V VPRW 40 V, 100 mA IBUCK IBUCK_C Notes 8. VSUP is applied on the VPWR pin as a test condition. 33789 10 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Buck Converter Output Current Capability 400 - - mA - 5.0 4.0 8.0 6.0 mV Buck High-side Switch Current Limit 500 800 1100 mA Sync Supply Output Voltage 6.0 V VPRW 40 V 15 - 2x VBUCK V - - 300 mVPP Sync Supply Output Current Capability 20 - - mA Sync Switch Overcurrent Protection Limit 65 - 150 mA Notes POWER MANAGEMENT (CONTINUED) IBUCK_C Buck Converter Load Regulation VBUCK_LOAD IBUCKSW_HS_LMT VSYNC VSYNC_RIPL ISYNC_C ISYNC_OC IBUCK = 100 mA, IBUCK = 100 mA IBUCK = 300 mA, IBUCK = 100 mA Sync Supply Output Ripple Voltage 6.0 V VPRW 40 V VCC VCC Supply Output Voltage 6.0 V VBUCK 9.5 V, 0 ICC 200 mA 4.85 5.0 5.15 V - VCC Supply Line Regulation VPWR-AC = 200 mVPP, f PWR-AC 500 kHz 20 - - dB - - 10 mV - 5.0 20 mVPP 9.0 13.5 22 mA VCC_NOISE VCC Supply Load Regulation ICC-DC = 0.8* ICC_MAX, ICC = 50 mA VCC Supply Noise Voltage IVCCDRI_LMT VCC Base Driver Current Limit TA = 25°C, Temperature coefficient = 300 ppm/ °C (typ.) VBUCK_VCC Minimum VBUCK Voltage for VCC Operation - - 6.0 V Minimum VBST Voltage for VCC Operation - - 7.0 V VDD Supply Voltage - 2.5 - V VBST_VCC VDD RESET AND WATCHDOG VRESET_H Reset Output High IRESET = -2.0 mA VCC - 0.4 - VCC VRESET_L Reset Output Low IRESET = 2.0 mA 0.0 - 0.4 V V VCC_OP Rising VCC Threshold for Reset Operation - - 1.5 V VCC_OV VCC Overvoltage for Reset 5.2 - 5.5 V VCC_UV VCC Undervoltage for Reset 4.5 - 4.80 V VCC Voltage Monitor Threshold Hysteresis 30 - - mV VDD_OV VDD Overvoltage for Reset 2.7 - 3.0 V VDD_UV VDD Undervoltage for Reset 1.85 1.90 2.10 V 0.3 - 0.8 V VCC_VM_HYS GNDA to GND_LIN Voltage Difference to Activate Open GNDA VGNDA_GND_LIN_TH Detection 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 11 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SATELLITE SENSOR INTERFACE ISAT_BUS_SUP_Q Satellite Bus Supply Quiescent Current - - 2.2 mA ISAT_BUS_SUP Satellite Bus Supply Operation Current - - 4.0 mA ISAT_SYNC_SUP_Q Sync Supply Quiescent Current - - 1.0 mA ISAT_SYNC_SUP Sync Supply Operation Current - - 1.0 mA ISAT_VCC_Q Satellite Logic Supply Quiescent Current - - 1.0 mA ISAT_VCC Satellite Logic Supply Operation Current - - 3.0 mA VSAT_OUT Satellite Interface DC Output Operation Voltage 0 ISAT_OUT 65 mA 5.8 6.3 6.7 - - 0.5 30 20 - - dB - - 200 mVPP 10 - 12 V VSAT_OUT + 4.3 - VSAT_OUT + 5.5 V VSAT_OUT_DIS PSRRSAT_BUS_SUP VSAT_RIPL Satellite Interface DC Output Disable Voltage ISAT_OUT = 0 mA Satellite Interface Ripple Rejection from Bus Supply 50 kHz fRIPL 280 kHz 280 kHz fRIPL 560 kHz Satellite Interface Ripple Voltage due to Current Modulation (typical application configuration) VSAT_SYNC_ABS Sync Pulse Absolute Voltage VSAT_SYNC_STEP Sync Pulse Voltage Step V V VSATSYNC_L SATSYNC Input Low Voltage -0.3 - 1.0 V VSATSYNC_H SATSYNC Input High Voltage 2.0 - VCC+0.3 V SATSYNC Input Pull-down Current 10 - 50 µA Satellite Interface Operational Current Range 0.0 - 65 mA Satellite Interface Pull-down Current Limit 27 - 60 mA Satellite Interface Overcurrent Limit 70 - 120 mA Minimum Satellite Quiescent Current Adaptation Level 1.9 - 3.8 mA ISAT_Q_RANGE_MAX Maximum Satellite Quiescent Current Adaptation Level 35 - 50 mA Satellite Quiescent Current for Single Satellite Synchronous Satsync-steered Mode 4.0 - 18.5 mA ISAT_Q_DUAL Satellite Quiescent Current for Dual Satellite Synchronous Satsync-steered Mode 8.0 - 26.5 mA ISAT_Q_TOTAL Total Bus Quiescent Current Synchronous TDM Mode 4.0 - 35 mA -10 -6.0 - 10 6.0 % 20 - 30 mA ISATSYNC_PULLDN ISAT ISAT_PD_LIM ISAT_OC ISAT_Q_RANGE_MIN ISAT_Q_SINGLE ISAT_MOD Satellite Quiescent Current Detect Accuracy 4.0 mA = Current Threshold = 14 mA 14 mA = Current Threshold = 35 mA Satellite Sensor Modulation Current ISAT_TH_RANGE Satellite Data Comparator Current Threshold Range 15.75 - 48.25 mA ISAT_TH_OFS Satellite Data Comparator Threshold Current Offset 11.25 12.5 13.75 mA ISAT_TH_HYST Satellite Data Detection Current Threshold Hysteresis 2.0 - 3.5 mA 33789 12 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SYNC PULSE LIMITS FOR SYNCHRONOUS TDM MODE (SEE Figure 5. SYNCHRONOUS TDM MODE SYNC PULSE TIMING) Vt0 Sync Slope Reference Voltage Vt2 Sync Signal Sustain Voltage - 0.5 - V 4.3 - 5.5 V DC Sensor Supply Regulator Current Limit 30 - 55 mA Current Difference Between the Regulator Overcurrent Detection Threshold and the Regulator Current Limit IDCREG_OC_DIFF = IDCREG_LMT - IDCREG_OC 1.0 9.0 18 V1 Regulated Output Voltage 1 1.35 1.5 1.73 V V2 Regulated Output Voltage 2 2.25 2.5 2.75 V V3 Regulated Output Voltage 3 4.5 5.0 5.5 V V4 Regulated Output Voltage 4 5.85 6.5 7.15 V - - 25 % DC SENSOR INTERFACE IDCREG_LMT IDCREG_OC_DIFF - Output Voltage Overshoot When Changing the Setting Measured as Percentage of the Voltage Step RDCREG_FBK Regulator Feedback Load Resistance 100 200 300 k ThDCREG_SD Regulator Thermal Shutdown Temperature 155 175 195 °C ThDCREG_HYS Regulator Thermal Shutdown Hysteresis 15 - 30 °C INx Load Capacitance 12.5 - 220 nF KCONV DC Sensor Interface Current to Voltage Conversion Factor (See Figure 21) IINx: 2.5 mA ~ 25 mA 0.163 0.177 0.190 VCONV_NLIN DC Sensor Interface Current to Voltage Conversion Nonlinearity - - 20 mVRMS 0.0 0.0 0.0 0.0 28 29 33 38 50 55 60 65 mV - - 1.0 V -110 -85 -30 µA CINx VINx_I_OFS VINx_OFS IINx_PULLDN Current Measurement Output Offset Voltage IINx = 0, CINx = 0.22 nF, RINx = 1.0 M V1 = 1.5 V V2 = 2.5 V V3 = 5.0 V V4 = 6.5 V INx Pin Offset Voltage Voltage Source not Enable and IINx = 0 INx Active Pull-down Current 2.0 V VINx 7.15 V and INx is not selected (9) mA V/mA Notes 9. IDCREG_OC is the regulator overcurrent detection threshold to trigger the regulator switch between a voltage source and a current source. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 13 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes ANALOG OUTPUT VAOUT Analog Output Voltage GND - VCC V Analog Buffer Offset -20 - 20 mV A Analog Output Buffer Gain For Output Voltage Monitors For DC Sensor Interface INx Voltage Monitors 0.99 0.48 1.0 0.5 1.01 0.52 K1 Scale Factor of Pin VBST Monitor VBST 35 V 8.0 8.5 9.1 K2 Scale Factor of Pin VER Monitor VER 35 V 8.0 8.5 9.1 K3 Scale Factor of Pin VERDIAG Monitor 4.5 5.0 5.5 K4 Scale Factor of Pin VBUCK Monitor VBUCK 10 V 2.6 2.8 2.9 K5 Scale Factor of Pin VSYNC Monitor VSYNC 20 V 4.5 5.0 5.5 K6 Scale Factor of Pin VPWR Monitor VPWR 20 V 5.2 5.6 5.9 K7 Scale Factor of Pin OUTx_D Monitor 5.2 5.6 5.9 K8 Scale Factor of Pin OUTx_S Monitor 5.2 5.6 5.9 VAOUT_OFS CONFIGURABLE DRIVERS VOUTx_S_ON_HS Drain-Source On Voltage in High-side Driver Configuration VOUTx_D = 18 V, IOUTx_S = 70 mA VOUTx_D – 0.5 - VOUTx_D V VOUTx_D_ON_LS Drain-Source On Voltage in Low-side Driver Configuration VOUTx_S = 0 V, IOUTx_D = 70 mA VOUTx_S - VOUTx_S + 0.5 V IOUTx_S_LMT High-side Driver Current Limit VOUTx_D = 18 V, VOUTx_S = 0 V 70 - 110 mA IOUTx_D_LMT Low-side Driver Current Limit VOUTx_D = 18 V, VOUTx_S = 0 V -110 - -70 mA ThOUTx_SD Driver Thermal Shutdown Temperature 155 175 195 °C ThOUTx_HYS Driver Thermal Shutdown Hysteresis 15 - 30 °C -1.0 45 - 1.0 100 µA -1.0 -100 - 1.0 -45 µA 0.4 x VPWR - 0.6 x VPWR V -1.0 50 - 1.0 100 µA IOUTx_D_LEAK_GND Drain Leakage to GND VRESET = 0 V, or in Sleep Mode, VOUTx_D = 0 V IOUTx_D_LEAK_BAT Drain Leakage to Battery VRESET = 0 V, VOUTx_D = VPWR VOUTx_D_OPEN IOUTx_S_LEAK_GND VRESET = 5 V, VPWR = 18 V, Driver Off, VOUTx_D = 0 V VRESET = 5.0 V, VPWR =18 V, Driver Off, VOUTx_D = 18 V Open Drain Voltage VRESET = 5.0 V, Driver Off Source Leakage to GND VRESET = 0 V, or in Sleep Mode, VOUTx_S = 0 V VRESET = 5.0 V, VPWR = 18 V, Driver Off, VOUTx_S = 0 V 33789 14 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit 0.0 -100 - 300 -50 µA Open Source Voltage VRESET = 5.0 V, Driver Off 0.4 x VPWR - 0.6 x VPWR V VTH_2/3 2/3 VPWR Comparator Threshold for Diagnostics 6.0 V VPWR 18 V 0.6 x VPWR 0.666 x VPWR 0.734 x VPWR V VTH_1/3 1/3 VPWR Comparator Threshold for Diagnostics 6.0 V VPWR 18 V 0.266 x VPWR 0.333 x VPWR 0.4 x VPWR V DOUTx PWM Duty Cycle Fixed Frequency = 128 Hz, Increment step = 1.6% 0.0 - 100 % Notes CONFIGURABLE DRIVERS (CONTINUED) IOUTx_S_LEAK_BAT VOUTx_S_OPEN Source Leakage to Battery VRESET = 0 V, VOUTx_S = VPWR VRESET = 5.0 V, VPWR = 18 V, Driver Off, VOUTx_S = 18 V GENERAL LOGIC INPUTS: CS, CS_X, SCK, SI, ASST, SCRAP, CLK VLGIN_H Logic Input High 2.0 - VCC + 0.3 V VLGIN_L Logic Input Low -0.3 - 1.0 V 10 - 50 µA -2.0 - 5.0 µA ILGIN_PULLUP ILGIN_LEAK Logic Input Pull-up Current For CS: VLGIN = VCS 2.0 V For others: VLGIN 4.5 V Logic Input Leakage VLGIN = VDD SPI (OTHERS) AND SPI MONITOR INTERFACE VSO_L SO Voltage Low ISO = 0.5 mA - - 0.4 V VSO_H SO Voltage High ISO = -0.2 mA VCC - 0.4 - VCC V ANALOG SENSOR INPUT VIN_ANA Analog Sensor Input Voltage 0.0 - VCC V IIN_ANA Analog Sensor Input Pull-down Current 2.0 - 8.0 µA ARM ENABLE / DISABLE OUTPUTS VARM_H ARM / DISARM Output High VCC - 0.4 - VCC V VARM_L ARM / DISARM Output Low 0.0 - 0.4 V ARM / DISARM Output High-impedance Leakage -2.0 - 2.0 µA PPT Input Pull-down Resistance 100 230 400 k PPT Input Test Mode Enable Threshold 4.0 4.5 5.0 V IARM_LEAK PRODUCTION PROGRAM AND TEST INPUT RPPT_IN VPPT_TEST 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 15 ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes LIN TRANSCEIVER LOGIC INTERFACE VRXD_OL RXD Output Low Level Voltage IRXD_IN 1.5 mA sinking current 0.0 — 0.9 VRXD_OH RXD Output High Level Voltage IRXD_OUT 250 A source current 4.25 — 5.25 V V VTXD_IL TXD Input Low Level Voltage — — 0.8 V VTXD_IH TXD Input High Level Voltage 2.0 — — V TXD Input Threshold Voltage Hysteresis 100 300 600 mV TXD Pull-up Current Source 1.0 V < VTXD < 3.5 V - 60 - 35 - 20 VTXD_IN_HYST ITXD_PULLUP A LIN TRANSCEIVER PHYSICAL LAYER (14),(12) VBAT Operating Voltage Range 8.0 – 18 V VSUP Operating Supply Voltage Range 7.0 – 18 V Supply Voltage Range (within which the device is not destroyed) -0.3 – 40 V 40 90 200 -1.0 – – – – 20 -1.0 – 1.0 VBAT Disconnected; VSUP_DEVICE = GND; 0 V < VBUS < 18 V – – VBUSDOM Receiver Dominant State – VBUSREC Receiver Recessive State VBUS_CNT Receiver Threshold Center (VTH_DOM + VTH_REC)/2 VSUP_NON_OP IBUS_LIM Current Limitation for Driver Dominant State Driver ON, VBUS = 18 V IBUS_PAS_DOM Input Leakage Current at the Receiver Driver off; VBUS = 0 V; VBAT = 12 V IBUS_PAS_REC Leakage Output Current to GND Driver Off; 8.0 V VBAT 18 V; 8.0 V VBUS 18 V; VBUS VBAT; IBUS_NO_GND Control Unit Disconnected from Ground GNDDEVICE = VSUP; VBAT = 12 V; 0 < VBUS < 18 V IBUSNO_BAT VHYS VBUS VSUP Receiver Threshold Hysteresis (VTH_REC - VTH_DOM) mA mA µA mA (11) 100 µA (13) – 0.4* VSUP V 0.6* VSUP – – V 0.475* VSUP 0.5* VSUP 0.525* VSUP V – – 0.175* VSUP V VSERDIODE Voltage Drop at the Serial Diode in Pull-up Path 0.4 – 1.0 V VSHIFT_BAT VBAT_SHIFT 0.0 – 11.5% VBAT VSHIFT_GND GND_SHIFT 0.0 – 11.5% VBAT VUVL, VUVH LIN Undervoltage Threshold (positive and negative) 5.9 – 6.7 V – 100 – mV VUVHYST LIN Undervoltage Hysteresis (VUVL - VUVH) (10) 33789 16 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 5. Static Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(8) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes LIN TRANSCEIVER PHYSICAL LAYER (CONTINUED) (14),(12) VBUSWU LIN Wake-up Threshold from Sleep Mode – 4.3 5.0 V RSLAVE LIN Pull-up Resistor to VSUP 20 40 60 k Notes 10. Voltage range at the battery level, including the reverse battery diode. 11. Loss of local ground must not affect communication in the residual network. 12. In this LIN Physical Layer EC section, use VSUP to represent VPWR and use VBUS to represent VLIN, in order to be consistent with the LIN Protocol Specification, and other Freescale LIN product specifications. 13. Node has to sustain the current that can flow under this condition. The bus must remain operational under this condition. 14. Guaranteed by design. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 17 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics Characteristics noted under conditions 7.0 V VSUP(15) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes POWER MANAGEMENT tBSTSW Boost Switch Transistor Switching Time 20 50 150 ns tSYNCSW Sync Switch Transistor Switching Time 10 - 250 ns tVCC_RISE VCC Voltage Rise Time From 0.1xVCC to 0.9xVCC 200 - 1800 µs tVCC_VM_REJ VCC Voltage Monitor Deglitch Filter Time 45 50 55 µs tVCC_VM_RST VCC Voltage Monitor Reset Time Delay 10 - 15 ms tWDW_MIN Watchdog Refresh Window Lower Limit 275 - 400 µs tWDW_MAX Watchdog Refresh Window Upper Limit 650 - 900 µs - Reset Pin Activation Time for Watchdog Error 0.7 - 1.0 ms fBST/BUCK Boost and Buck Regulators Switch Frequency Low Speed Frequency High Speed Frequency 133 232 140 245 147 258 kHz fSYNC_CP Sync Supply Charge Pump Switch Frequency - 160 - kHz 3.92 3.98 4.00 4.00 4.08 4.02 MHz 118.75 125 131.25 kHz 45 47 - 55 53 % (16) SATELLITE SENSOR INTERFACE PSI5 fCLK Satellite Interface Input Clock Frequency Synchronous SATSYNC-steered mode Synchronous TDM mode fSAT Satellite bit Rate Operation Range DSAT_IMOD Satellite Sensor Current Modulation Duty Cycle Synchronous SATSYNC-steered mode Synchronous TDM mode tSAT_IMOD_FR Satellite Sensor Current Signal Rising and Falling Time From 10% to 90% of Modulation Amplitude 0.5 - 1.0 µs SRSAT_IMOD Satellite Sensor Current Signal Slew Rate 16 - 48 mA/µs tSAT_SYNC_FR Sync Pulse Rising and Falling Time 3.0 4.0 6.0 µs tSAT_IQ_FLT Satellite Quiescent Current Sampling Filter Time Constant - 60 - µs tSAT_IQ_DET Satellite Quiescent Current Out of Range Detection Time 3/fCLK - 4/fCLK µs tSAT_OC_DET Satellite Current Overcurrent Detection Time - 512 - µs 3.5 - 4.0 ms tSAT_OC_SDDEL Satellite Interface Overcurrent Shutdown Delay tSATSYNC_PER = 500 µs, tSAT_OC_DET = 512 µs tSAT_TH_DEL_ Satellite Data Detection Delay Difference Between Rising Edge and Falling Edge - - 250 ns tSAT_IQ_INIT_DEL Initial Satellite Quiescent Current Measurement Delay - 10 - ms tSAT_IQ_INIT_DUR Initial Satellite Quiescent Current Measurement Duration - 35 - ms Notes 15. VSUP is applied on the VPWR pin as a test condition. 16. The switching frequency used for the Boost and Buck supplies is selectable via the SPI with a LIN_CONFIG command at either a low-speed or high-speed switching mode. 33789 18 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(15) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes SATELLITE SENSOR INTERFACE PSI5 (CONTINUED) tSAT_IQ_ DEL Satellite Quiescent Current Measurement Delay - 5.0 - µs tSAT_IQ _DUR Satellite Quiescent Current Measurement Duration - 3.0 - µs Satellite Quiescent Current Measurement Delay with No Bus Activity - 120 - µs tSAT_IQ_ DEL_NA SYNC PULSE LIMITS FOR SYNCHRONOUS TDM MODE (SEE Figure 5, Synchronous TDM Mode Sync Pulse Timing) t0 Reference Time Base - 0.0 - µs t1 Sync Signal Earliest Start - -3.0 - µs t2 Sync Signal Sustain Start 0 7.0 - µs - Sync Rising Slope Slew Rate 0.43 - 1.5 V/µs - Sync Falling Slope Slew Rate -1.5 - - V/µs t3 Sync Signal Sustain Time - 16 - µs t4 Sync Discharge Time Limit - 35 - µs 44 - - µs tSLOT1_START Start of First Sensor Data Word (Remaining discharge current < 2.0 mA) SATELLITE TIMING LIMITS FOR SYNCHRONOUS TDM MODE (SEE Figure 6, Synchronous TDM Mode Satellite Interface Timing) tSYNC tSATSYNC_WIDTH Sync Pulse Period 495 500 505 µs Satsync Input Pulse Width 40 - - µs tSLOT1_START Slot1 Start Time (relative to t0) - 44 - µs tSLOT2_START Slot2Start Time (relative to t0) - 181.3 - µs tSLOT3_START Slot3 Start Time (relative to t0) - 328.9 - µs tSLOT3_END Slot3 End Time (relative to t0) - 492 - µs -2.1 - 2.1 µs tEMC Timing Variation Margin SATELLITE TIMING LIMITS FOR SYNCHRONOUS SATSYNC-STEERED MODE (SEE Figure 7, Synchronous Satsync-Steered Mode Satellite Interface Timing) PSI5_x Activation Time from Rising Edge of Chip Select (1) 1.0 - 10 µs tSATSYNC_PER Satsync Period (2) 167 - µs tSATSYNC_PH1 Satsync Phase 1 Time (3) - 200 - µs tSATSYNC_PH0 Satsync Phase 0 Time (4) - 170 - µs 250 - 750 ns tSAT_ACT tSATSYNC_S_DEL Satsync Sampling Delay Time (5) (1/ FSAT_CLK to 3/ FSAT_CLK) tSAT_SYNC_WIDTH Sync Pulse Width (6) - 32 34 µs Channel Stagger Time (7) (16/ FSAT_CLK) - 4.0 - µs tSAT_STAGGER tSAT_SYNC_GEN_DEL SYNC Pulse Generation Delay (8) - - 2.5 µs tSAT_SYNC_BLANK Sync Blanking Time (Decoder disabled) (9) - 69 - µs tSAT_PHASE_BLANK Phase Transition Blanking Time (Manchester Decoder disabled) (10) - 10 - µs 81.48 - 156.5 µs tSAT_MSG Message Time (11) 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 19 ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(15) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes DC SENSOR INTERFACE AND ANALOG OUTPUT tMEAS DC Sensor Measurement Duration 0.5 - 2.0 ms tDCREG_SET Supply Regulator Setting Time VINx = 90% x V4 = 90% x 6.5 V, - - 70 µs |dVInx/dt| Regulator Output Switch Slew Rate 0.08 5.0 7.0 V/µs - - 40 70 135 190 210 mV/µs - 248 - µs tAOUT_SETL IInx = 20 mA, CInx = 10 nF Analog Output Settling Time CL = 0.22 nF, RL = 1.0 M AOUT = 90% final value AOUT = 99% final value µs CONFIGURABLE DRIVERS |dVOUTx/dt| tLATCH_DELAY Driver Output Switching Slew Rate Control 6.0 V < VOUTx <18 V, RLOAD = 273 , CLOAD = 100 nF Delay for Comparator Latch (992/FCLK) SPI AND SPI MONITOR INTERFACE (SEE Figure 8. SPI TIMING, WITH AN EXTERNAL PULL-UP OF 47 k OR 110 ΜA ON DO) fSCK SCK Frequency - - 8.08 MHz tSCK _H SCK High Time (A) 1/2 tSCK - 13 - - ns tSCK _L SCK High Time (B) 1/2 tSCK - 13 - - ns 123.7 - - ns tSCK SCK Period (C) tFALL SCK Falling Time (D) 5.5 - 13 ns tRISE SCK Rising Time (E) 5.5 - 13 ns tSET SI Setup Time (F) 37 - - ns tHOLD SI Hold Time (G) 49 - - ns tACC SO Access Time (H) - - 43 ns SO Valid Time after SCK (I) - - 30 ns 0.0 - - ns - - 750 ns tVALID tLAG SO Lag Time (J) tDISABLE SO Disable Time (K) tCS_LEAD CS Lead Time (L) 1/2 tSCK - - ns tCS_LAG CS Lag Time (M) 1/2 tSCK - - ns Sequential Data Transfer Delay (N) 3/ FCLK - - µs tTD ADDITIONAL COMMUNICATION LINE (ACL) INPUT FOR SCRAP tKEY_TOUT Scrap KEY Timeout - - 600 µs ACL Period 180 200 220 ms tACL_H ACL Pulse High Time 126 140 154 ms tACL_L ACL Pulse Low Time 54 60 66 ms tACL 33789 20 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 6. Dynamic Electrical Characteristics (continued) Characteristics noted under conditions 7.0 V VSUP(15) 18 V, - 40 C TA 125 C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted. Symbol Characteristic Min Typ Max Unit Notes LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING TO THE LIN PHYSICAL LAYER SPECIFICATION(17), (18) D1 Duty Cycle 1: THREC(MAX) = 0.744 * VSUP THDOM(MAX) = 0.581 * VSUP % D1 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 50 µs, 7.0 V VSUP18 V D2 39.6 — — Duty Cycle 2: THREC(MIN) = 0.422 * VSUP THDOM(MIN) = 0.284 * VSUP % D2 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 50 µs, 7.6 V VSUP18 V — — 58.1 LIN PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR SLOW SLEW RATE - 10.4 KBIT/SEC ACCORDING TO LIN PHYSICAL LAYER SPECIFICATION(17), (19) D3 Duty Cycle 3: THREC(MAX) = 0.778 * VSUP THDOM(MAX) = 0.616 * VSUP % D3 = tBUS_REC(MIN)/(2 x tBIT), tBIT = 96 µs, 7.0 V VSUP18 V 41.7 — — Duty Cycle 4: THREC(MIN) = 0.389 * VSUP D4 % THDOM(MIN) = 0.251 * VSUP D4 = tBUS_REC(MAX)/(2 x tBIT), tBIT = 96 µs, 7.6 V VSUP18 V LIN PHYSICAL LAYER: RECEIVER CHARACTERISTICS t REC_PD t REC_SYM — — 59 (20) Propagation Delay and Symmetry Propagation Delay of Receiver, tREC_PD = MAX (tREC_PDR, tREC_PDF) Symmetry of Receiver Propagation Delay, tREC_PDF - tREC_PDR — — 6.0 - 2.0 — 2.0 TXD Permanent Dominant State Delay 3.75 5.0 — 50 s (21) 6.25 ms (22) 80 s (23) TXD TIMING t TXDDOM t LIN_1STDOM First Dominant bit Delay The transmitter delay before sending the first dominant bit, after the transceiver is activated Notes 17. Bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 9. In Figure 9, use VSUP to represent the VPWR pin, and use GND to represent both the GND and GND_LIN VLIN pins, in order to be consistent with LIN Protocol Specification, and other Freescale LIN product specifications. 18. See Figure 10. 19. See Figure 11. 20. VSUP from 7.0 to 18 V, bus load RBUS and CBUS 1.0 nF / 1.0 k, 6.8 nF / 660 , 10 nF / 500 . Measurement thresholds: 50% of TXD signal to LIN signal threshold defined at each parameter. See Figure 9. 21. See Figure 12. 22. The LIN is in Recessive state and the receiver is still active. 23. The First Dominant bit delay normally has no impact to LIN communication, but may need additional care on the software for ISO 9141 (K-line) communication initialization. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 21 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TIMING DIAGRAMS Figure 5. Synchronous TDM Mode Sync Pulse Timing tSAT_SYNC Figure 6. Synchronous TDM Mode Satellite Interface Timing 33789 22 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS Voltages SPI CS Satsync Satsync (Internal) PSI5_1 Current PSI5_2 Figure 7. Synchronous Satsync-Steered Mode Satellite Interface Timing Figure 8. SPI Timing 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 23 ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS VSUP VSUP TXD R0 LIN RXD GND C0 Note R0 and C0: 1.0 k/1.0 nF, 660 /6.8 nF, and 500 /10 nF. Figure 9. Test Circuit for Timing Measurements TXD TBIT VLIN_REC TBIT tBUS_DOM(MAX) tBUS_REC(MIN) THREC(MAX) 74.4% VSUP Thresholds of receiving node 1 THDOM(MAX) 58.1% VSUP LIN Thresholds of receiving node 2 THREC(MIN) 42.2% VSUP THDOM(MIN) 28.4% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDR(2) tREC_PDF(2) Figure 10. LIN Timing Measurements for Normal Baud Rate 33789 24 Analog Integrated Circuit Device Data Freescale Semiconductor ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD TBIT TBIT tBUS_DOM(MAX) VLIN_REC tBUS_REC(MIN) THREC(MAX) 77.8% VSUP Thresholds of receiving node 1 THDOM(MAX) 61.6% VSUP LIN Thresholds of receiving node 2 THREC(MIN) 38.9% VSUP THDOM(MIN) 25.1% VSUP tBUS_DOM(MIN) tBUS_REC(MAX) RXD Output of receiving Node 1 tREC_PDF(1) tREC_PDR(1) RXD Output of receiving Node 2 tREC_PDF(2) tREC_PDR(2) Figure 11. LIN Timing Measurements for Slow Baud Rate VLIN_REC VBUSREC 0.6% VSUP VBUSDOM 0.4% VSUP VSUP LIN BUS SIGNAL RXD tREC_PDF tREC_PDR Figure 12. LIN Receiver Timing 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 25 FUNCTIONAL DESCRIPTION INTRODUCTION FUNCTIONAL DESCRIPTION INTRODUCTION The 33789 provides an integrated solution for multiple basic functions in an air bag control module. As a system basis chip, the 33789 supplies different voltages to a complete airbag system with centralized power management. It controls the wake-up and power down of the system through the Power Mode Control function. It runs the Watchdog State Machine to respond to the MCU refresh and controls all of internal and external resets. It operates in Safing mode to prevent inadvertent deployment of the airbags, and thereby secure the occupants safety. It also operates in Scrap mode, to allow for the disposal of the unused pyrotechnic devices (squibs) at the end of vehicle life. For different voltage applications, it uses internal switches to boost battery voltage up to 33 V to supply external squib drivers and to charge the energy reserve. It then combines internal buck switches and the charge pump to create bus and sync supplies for satellite sensors, and uses an external bipolar transistor to supply VCC for all on-board IC cores. Safing is another key function of the 33789. There are four SPI5 satellite sensor interfaces, nine DC sensor inputs, and one highly accurate analog input, equipped on the 33789 for the airbag system acquiring different types of safing data. The SPI Monitor in the safing block monitors on-board sensor data and satellite sensor data read by the MCU via the SPI. The on-chip safing logic compares all of the sensor data to the configurable thresholds, and thereby determines whether a safety event (collision) is happening. Whenever a collision is detected, an arm control will be created in which complementary ARM and DISARM logic outputs are activated. The 33789 can output two PWM signals with high-side/low-side configurable drivers, which can be used to drive alert indicators. The 33789 outputs a multiplexed analog signal to the MCU for diagnostics on all DC sensors, power supplies, and configurable driver outputs. A LIN / ISO-9141 physical layer interface can be used to communicate with either LIN based Occupant Classification Systems or vehicle diagnostics. Its communication mode can be selected by the MCU through the SPI. FUNCTIONAL PIN DESCRIPTION POWER SUPPLY INPUT (VPWR) VPWR is the system power supply input. It takes a protected 12 V vehicle battery input, which should be protected for load dump and reverse battery. Additional filtering is preferred for better EMC performance. WAKE-UP INPUT (WAKE) WAKE is a battery voltage, active high logic input. When activated, it brings the system out of sleep mode by starting the boost and buck converters. Internally, the WAKE input is implemented with a 200 k pull-down resistance and a 1.0 ms glitch filter. BOOST SWITCH OUTPUT (BSTSW) BSTSW is an internal low-side switch output. When the switch is turned on, its voltage will be pulled down close to GND (VBSTGND), thus increasing the current in the boost inductor. When the switch is turned off, the un-interrupted current will charge the boost capacitor. BOOST SUPPLY INPUT (VBST) The VBST pin is externally connected to the boost capacitor. It inputs VBST as a regulated higher voltage supply, and distributes it internally for all sub-system applications. BOOST COMPENSATION CONNECTION (BSTCOMPX) The two boost compensation pins are used for connecting an external RC filter in the boost converter feedback loop. ENERGY RESERVE SWITCH OUTPUT (ERSW) ERSW is an energy reserve control output. It is connected to a charge/discharge switch pair. When the energy reserve voltage across the energy reserve capacitor CER is lower than the target value, the internal charge switch will be turned on to provide source current from the boost supply to charge CER. A short discharge pulse can be used for measuring CER capacitance and ESR. ENERGY RESERVE MONITOR (VER) VER is a voltage input for the system, to monitor the voltage across CER, to maintain enough energy storage. ENERGY RESERVE DIAGNOSTIC INPUT (VERDIAG) VER and VERDIAG both monitor the voltage across CER. However, VERDIAG only takes AC samples coupled by an external capacitor. The VERDIAG sample will be processed with 10-bit ADC and sent to the MCU for CER diagnostics. 33789 26 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION BUCK SWITCH OUTPUT (BUCKSW) BUCKSW is a synchronous half-bridge switch output for the buck converter, to create VBUCK on CBUCK. When VBUCK is below the target threshold, the high-side switch is turned on to charge CBUCK, sourcing current from the internal VBST connection. Once VBUCK has reached the threshold, the high-side switch is turned off and the low-side driver is turned on for the current circulation. BUCK SUPPLY INPUT (VBUCK, VBUCK_R) The 33789 uses two pins to input VBUCK. VBUCK provides supply source for the Sync charge pump and other internal applications, while VBUCK_R shares all applications except Sync. BUCK COMPENSATION CONNECTION (BUCKCOMPX) The two buck compensation pins are used for connecting an external RC filter in the buck converter feedback loop. CHARGE PUMP CAPACITOR CONNECTION (CPCX) A charge pump capacitor is connected between CPC1 and CPC2. SYNC SUPPLY CONNECTION (VSYNC) The internal charge pump outputs current to charge CSYNC, which is externally connected on this pin, to achieve VSYNC. The satellite sensor interface block sources VSYNC to create sync pulse internally. DEDICATED GROUND CONNECTIONS FOR SWITCHING POWER SUPPLIES (BSTGND, BUCKGND, CPGND) There are three dedicated ground connection pins designed for the boost converter, buck converter, and charge pump ground returns respectively, to shorten their own current loops for the best EMC performance. Eventually, all of ground pins, including GNDA, VSS, GND_LIN, and GND_PSI, must be connected together and terminated on the circuit board ground. ANALOG GROUND (GNDA) The ground return terminal or ground source pin for analog circuits. DIGITAL GROUND (VSS) The ground return terminal or ground source pin for logic circuits. 5.0 V VCC TRANSISTOR BASE DRIVER OUTPUT (VCCDRI) The VCCDRI pin is an internal driver output to control the base pin of an external PNP transistor to regulate 5.0 V VCC. 5.0 V VCC INPUT (VCC) The VCC pin is used to input 5.0 V VCC, which supplies the internal analog circuit and provides feedback for the linear regulator. 2.5 V VDD CONNECTION (VDD) 2.5 V VDD is converted from VPWR and VBUCK, to supply internal logic circuits. The VDD pin is the connection point between the internal VDD regulator driver and its external load capacitor. RESET (RESET) The RESET pin is the reset driver output to issue global resets to other system ICs. PRODUCTION PROGRAMMING AND TEST (PPT) The PPT pin is an active high enable input. It will be only used by manufacturers to program and test the circuit during production. It should not be connected to any application circuit externally. The PPT pin should be grounded to secure airbag system operation. LIN INTERFACE (LIN) The LIN pin is a LIN 2.1 compatible physical layer interface to communicate with devices or diagnostic systems external to the airbag ECU. LIN GROUND (GND_LIN) The dedicated ground for LIN (or K-line) interface. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 27 FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION UART CONNECTION (TXD, RXD) The 33789 uses TXD and RXD ports to receive and transmit 5.0 V logic level LIN bus data through the MCU UART interface. DC SENSOR INPUTS (INX) There are nine switch mode analog inputs, IN1 through IN9, on the 33789 to monitor the switch mode sensor status of up to 9 independent DC type sensors. The sensors can be Hall-effect sensors, resistive sensors, on/off switches, or any other regular analog sensors. The 33789 supplies one of four selectable bias voltages for each channel, multiplexes the sensor inputs, and outputs them in serial to the MCU through the AOUT pin. ANALOG DIAGNOSTIC OUTPUT (AOUT) The AOUT pin outputs multiple scanned, rescaled, and buffered analog signals to the MCU. With the AOUT signal, the MCU can read DC sensor status, and conduct diagnostics on DC sensors, configurable driver outputs, and all power supplies. CONFIGURABLE DRIVER OUTPUTS (OUTX_D, OUTX_S) The 33789 provides two general purpose low current drivers. Each one can be independently configured as either a high-side or a low-side driver by a SPI command. Both the drain and the source terminals of each driver have dedicated pins for external connections. SATELLITE SENSOR INTERFACES (PSI5_X) The four satellite sensor interface pins, PSI5_1 through PSI5_4, provide four PSI5 V 1.3 physical connections. All four channels can be enabled or disabled via SPI commands. Each channel can be used to connect up to three satellite sensors in PSI5-P10P-500/3L Synchronous TDM mode, or up to two satellite sensors in Synchronous Satsync-steered mode. The MCU can retrieve the currentmodulated sensor data and query the channel status via the SPI. SYNC-PULSE ACTIVATION SIGNAL INPUT (SATSYNC) The MCU provides a periodic Satsync signal to the 33789 at the SATSYNC pin to activate higher voltage sync pulse generation, The 33789 adds the sync pulses on each satellite channel in sequence, to synchronize the satellite data sampling. SATELLITE SENSOR INTERFACE CLOCK INPUT (CLK) The PSI5 interface block receives a 4.0 MHz clock input from the MCU at the CLK pin, and uses it for satellite sensor signal decoding and synchronizing other internal logic processing. SATELLITE GROUND (GND_PSI) GND_PSI is a dedicated common ground connection point for all PSI5 satellite sensor channels. SERIAL PERIPHERAL INTERFACE (SPI) DATA INPUT (SI) Since the 33789 is configured as a slave device connected on the Master Out Slave In (SI) line of SPI bus, the SI pin is implemented as an SPI data serial input pin. SPI DATA OUTPUT (SO) SO is a Slave Data Output pin for the 33789 to send serial data out via the SPI bus. SPI CLOCK (SCK) The 33789 uses the SCK pin to receive the SPI clock signal from the MCU. The SPI clock is used to synchronize the data transaction and the logic processing at the SPI interface block. SPI CHIP SELECTS (CS) The MCU selects to communicate with the 33789 by pulling CS pin to ground. Once the data transaction is completed, the voltage level on the CS pin will return high. 33789 28 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION CHIP SELECTS FOR SPI MONITOR (CS_X) When the MCU sends a “sensor request” over the SPI interface, the 33789 SPI Monitor listens to the sensor response and extracts valid sensor data from up to four sources using additional chip select signals on CS_x: • CS: dedicated for satellite sensors • CS_A: Intended for an on-board accelerometer • CS_B: Intended for an on-board accelerometer or an expansion satellite receiver • CS_C: Intended for an expansion satellite receiver ANALOG SENSOR INPUT (A_SENSOR) There is one analog safing sensor input on the 33789. The analog signal input from the A_SENSOR pin is processed by a 10-bit ADC and digital filters. The 10-bit sensor data result will be stored in a holding register for the SPI reading. ANALOG SENSOR SELF-TEST (ASST) The MCU can run a self-test on the on-board analog sensor without triggering Arming. The MCU would need to issue a disable signal to the safing block to ignore the analog sensor data during its self-test period. The ASST pin on the 33789 is the digital input to receive this disable signal. Once the ASST pin is pulled high by the MCU, the internal digit filter will not process the analog sensor data, and the analog sensor register will not be loaded for comparison. ARM OUTPUT (ARM, DISARM) The 33789 uses a pair of digit output pins, ARM and DISARM, with opposite logic, for the Arming output. They can be directly used by squib drivers as a squib firing enable and/or disable inputs. Both the ARM and DISARM pins are set to high-impedance under the following conditions: • During resets • Arm Lockout • While the Safing State Machine is in Start-up mode SCRAP CONTROL (SCRAP) The SCRAP pin on the 33789, is also called ACL input, for an Additional Communication Line, per the ISO-26021 standard. It is a digital signal input to receive the ACL signal from either the MCU or an external device. The ACL signal will be used by the 33789 to determine if it should stay in, or enter into Scrap mode from Arming mode during its scrap handshaking with the MCU. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 29 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION MC33789 Function Block Diagram Power Management Power Mode Control Energy Reserve Control Boost Converter Buck Converter Sync Supply Charge Pump 5V Linear Regulator 2.5V Linear Regulator Watchdog Satellite Sensor Interface PSI5 Quiescent Current Monitor Manchester Decoder PSI5 Clock Mode Control Sync Pulse Gernerator Protection & Diagnostics Signal I/Os DC Sensor Inputs Selectable Bias Supplies Analog MUX Analog Sensor Input Analog Diagnostics Output ADC Analog MUX Digital Filter Com munications SPI ACL Analog Buffer Amplifier Configurable Drivers LIN / K-Line HSD/LSD Config. PWM Protection & Diagnostics Safing Compare Logic Arm Enable Outputs Safing SPI Monitor & Decoder Safing state Safing Control Machine Counters Safing Threshold Logic Figure 13. Functional Blocks BOOST CONVERTER The boost converter uses an internal power switch combined with external passive components, to create a 33 V boost supply from the 12 V battery input. The 33 V boost output is used for: • Charging energy reserve capacitor • Firing squibs when a safing is detected and the battery input is still available • Power source for all other lower voltage supplies The boost switch is activated by a wake-up signal, and its operation is controlled by the MCU through the SPI command. ENERGY RESERVE CONTROL The energy reserve is a power backup for the air bag system. When a vehicle accident happens and the battery supply is lost, the energy reserve can provide sufficient power to support the system to continuously collect sensor information, process safing messages, and fire squibs, for a time determined by the capacity of the energy reserve. To secure the energy reserve function, the 33789 has implemented sophisticated controls: • Monitoring VBST and VER to determining when the energy reserve capacitor CER needs to be charged. • Controlling the turn on time of the high-side charge switch, to keep VER close to VBST, and limiting the inrush charge current. • Executing a MCU command to diagnose CER by momentarily turning on the low-side discharge switch (while turning off the highside charge switch), and accurately measuring the VER changes. 33789 30 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION SPI WAKE VPWR VPWR LBST Sleep Mode Control SPI Interface BSTSW BSTGND Internal Data Exchange Sleep Reset AOUT Boost Control V BST VB ST Analog MUX VBAT 33V VBST 1/ K1 CBST BSTCOMP1 BSTCOMP2 Figure 14. Boost Converter Block Diagram SPI VBST VBST 33V SPI Interface ERSW AOUT Internal Data Exchange Control through SPI Energy Reserve Control CER VER 1/K 2 Analog MUX Buffer VERDIAG K3 A D Figure 15. Energy Reserve Control Block Diagram 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 31 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION BUCK CONVERTER The buck converter creates a step-down intermediate supply voltage, VBUCK 9.0 V, from the 33 V VBST. It uses a synchronous buck structure, and controls the internal power switches running at 140 kHz, the same frequency as for the boost switch. The switches are fully protected against overvoltage, overcurrent and overtemperature. The buck converter operation is under control of the power mode signal and SPI commands from the MCU. The buck converter status can be read via the SPI, and its output voltage, VBUCK, can be monitored via AOUT by the MCU. The 33789 provides redundant pins to input VBUCK for the voltage regulation and further power conversions. SPI WAKE VBST Sleep Mode Control SPI Interface LBUCK BUCKSW AOU T Internal Data Exchange Sleep R eset Buck C ontrol BUC KGN D V BUC K V BUC K Analog MUX 1/K4 C BUC K VBUCK_R 9V VBUC K BUCKCOMP1 BUCKCOMP2 Figure 16. Buck Converter Block Diagram SYNC SUPPLY FOR PSI5 INTERFACE To create a regulated sync pulse supply with a voltage at least 5.0 V above the bus voltage for the PSI5 satellite sensor interface, the 33789 uses a charge pump to “double” VBUCK. The charge pump switches are operated at 160 kHz, with output current limitation. The MCU enables the sync supply and monitors VSYNC via the AOUT for diagnostics. LINEAR REGULATORS The 33789 drives an external PNP transistor to provide a 5.0 V VCC output. This design can reduce the IC power dissipation and offers the ECU designer system design flexibility. As the prime core power supply, VCC can be shared by the 33789 with other on-board ICs. The 2.5 V VDD used for the 33789 internal circuitry is created by an internal linear regulator, using VPWR (for start-up) and VBUCK. It utilizes an external capacitor through the VDD pin. 33789 32 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION WATCHDOG AND RESET The Watchdog State Machine monitors the system clock by reading refresh messages from the MCU via the SPI, and applies state control and power mode control accordingly. The MCU periodically sends watchdog refresh messages within the watchdog time window. If the refresh to the window watchdog has failed, a system reset will be issued. The RESET pin will be pulled low to drive external reset. The reset control is also linked to the VCC monitor and the VDD monitor to ensure their output voltages are within the defined tolerances. SPI VBUCK SPI Interface CPC1 AOUT Internal Data Exchange C ontrol through SPI Charge Pump Control CCP CPC2 Analog MUX VSYNC VSYNC C SYNC CPGND 1/K5 Figure 17. Sync Supply Block Diagram 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 33 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION SPI PPT WAKE VBU C K VBU C K Internal Data Exchange SPI Interface Sleep Reset Sleep Mode Control V DD V BG VRE F OV VPW R VBU C K OV OV VD D VD D UV UV VD D Regulator UV External Reset Driver 5V VCC VCC Reset Logic VC C VC C Watchdog Control Internal Resets RESET VCCDRI VC C Control VDD 2.5V Bandgap Figure 18. Linear Regulators and Watchdog Block Diagram SATELLITE SENSOR INTERFACE PSI5 The 33789 provides four satellite sensor interface channels to collect data from up to 12 remote satellite sensors. The physical link is a two-wire pair. The satellite sensor interface implements the P10P-500/3L mode, as defined in the PSI5 technical specification V1.3 protocol. It also supports 10-bit Synchronous Satsync-Steered mode operation. The interface receives data in synchronous mode only. In addition, a method is provided to allow implementation of the bi-directional communication feature, also defined in PSI5 V1.3, under software control. All four satellite channels can be independently enabled or disabled via SPI commands. The selection of communication mode and the status acquisition are also controlled by the MCU via the SPI. The physical layer of the PSI5 interface supplies continuous power and synchronization pulses, created from VBUCK and VSYNC respectively, to the remote satellite sensors. It senses the satellite current draw to receive the Manchester-encoded current modulation signals from the sensors. The interface converts the Satsync signal from the MCU to synchronize the sensor data transmission, and uses the CLK signal from the MCU as a time base for the Manchester decoding. Each satellite channel has three registers to store decoded messages from up to three satellite sensors. The messages are accessible to the MCU over the SPI. Each channel’s fault condition is isolated from the others. All four channels are independently protected from short to GND or battery. 33789 34 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION SPI VSYNC CLK PSI5_1 PSI5_2 PSI5_3 Two-Wire Satellite Sensor2 SPI Interface PSI5 Satellite Sensor Interfaces Internal Data Exchange Airbag Control Module Satellite Sensor1 VBUCK Manchester Decoder PSI5_4 GND_PSI Analog MUX A_SENSOR Satellite Sensor3 A D ASST Buffer ADC Control SATSYNC Safing Figure 19. Satellite Sensor Interface and Analog Sensor Input Block Diagram ANALOG SENSOR INPUT There is one analog sensor input port provided on the 33789 for a sensitive analog safing sensor signal. The analog input shares a 10-bit A/D converter with the VERDIAG input. The periodic Satsync pulses trigger the A/D conversions. The digital result of the analog sensor input is saved into a 10-bit analog sensor data register. It can then be read via the SPI and monitored by the safing logic in the same way as the satellite data from the PSI5 interface. The ASST input receives an inhibit signal from the MCU during the analog sensor self-test to stop the buffer register updating, thus avoid the Arming output triggered by an Analog Sensor Self Test fault condition. DC SENSOR INTERFACE The DC sensor interface provides 9 channels for Hall-effect sensors, resistive sensors or simple ON/OFF type switching sensors, such as seat belt buckles, seat track position sensors, etc. All nine inputs are multiplexed and buffered before they are output to the MCU through the AOUT pin. The multiplexer is controlled by SPI commands. The DC sensor interface not only monitors the voltages at each input, but also provides a bias supply with four selectable regulated voltages for each sensor output stage. The supply regulator is capable of measuring and limiting the load current. If the load current exceeds the overcurrent detection threshold, the voltage regulator will enter into a protection mode and become a current source. During the transient period, the regulator output voltage will be increased to maintain the supply current near the current limit level, which is required by the load resistance in the Hall-effect sensor, to establish a sensing signal voltage. The DC sensor load current IINx to the analog output voltage VAOUT conversion curve for the AOUT monotonic operation can be found in Figure 21. The DC sensor interface allows dual-point measurement that eliminates common-mode ground offset for implementation of sensors without a ground return to the ECU. The DC sensor interface system is capable of diagnosing whether a sensor switch is in a valid position, open circuit, short circuit to other channels, or other vehicle voltage potentials. There is a low-current active pull-down circuit at each INx input, to discharge the residual voltage after the channel is deselected. The circuit stays activated as long as the DC sensor interface block is enabled and the channel is unselected until the channel is once again selected. To prevent damage caused by external fault conditions, the interface local temperature is monitored with a safety feature of overtemperature shut down. The bias supply regulator configuration and the current limit functions are controlled by SPI commands, and the fault conditions including the overtemperature error, can be read via the SPI. An internal reset automatically deactivates the bias supply regulator and all of multiplexers and switches. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 35 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION ANALOG OUTPUT FOR DC SENSOR MONITOR AND ANALOG DIAGNOSTICS The AOUT pin is for SPI controlled multi-function analog output with an analog buffer amplifier. According to the SPI command, the instant AOUT voltage can be: • One of the DC sensor inputs with selected bias supply voltage, or the sensor load current • One of the system power supply voltages (rescaled), including the energy reserve diagnostic measurement • One of the output pin voltages from the two configurable drivers The AOUT signal provides a convenient access for the MCU to extract the DC sensor status and conduct diagnostics for all of above sub-systems. VBU CK V BUC K SPI IN1 V BAT IN2 V1 Bias V2 Voltage V3 Supply IN3 IN4 V4 IN5 9 DC Sensor Inputs IN6 IN7 IN8 IN9 Channel Select VBST 1/K1 VER SPI Interface AOU T A 1/K2 1/K7 VERDIAG OUT1_S 1/K8 1/K4 1/K7 OUT2_D 1/K5 1/K8 VPWR OUT1_D K3 VBU CK VSYNC SPI OUT2_S 1/K6 VAOUT (V) Figure 20. DC Sensor Interface and Analog Output Block Diagram IINx (mA) Figure 21. VAOUT vs. IINx Monotonic Operation 33789 36 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION SERIAL PERIPHERIAL INTERFACE (SPI) • • • • The 33789 SPI interface uses a slave configuration. It features: 16-bit data frame Up to 8.0 MHz SPI clock 5.0 or 3.3 V compatibility (receives 3.3 V SPI inputs without a level shifter) Three extra chip selects CS_A, CS_B, and CS_C to support SPI monitor extract on-board digital sensor data for up to four sensors. SI SPI Interface TXD LIN GND_LIN LIN Interface SCK CS Internal Data Exchange RXD SO SPI Monitor CS_A CS_B SCRAP Safing CS_C Figure 22. Communication Interfaces Block Diagram LIN Physical Layer The LIN physical layer is LIN 2.1 compliant, and supports three communication speeds by changing the output slew rate: • LIN: up to 10.4 kBaud • LIN: up to 20 kBaud • ISO 9141 (K-line): up to 100 kBaud This external communication interface can also be configured to directly output one of four satellite sensor channel's Manchester code. SAFING LOGIC The Safing Logic block utilizes a logic structure, which is independent of the MCU, to monitor both on-board sensors and satellite sensors, to determine the vehicle safety status, and verify the necessity to warrant Arming deployment of the airbag system. The functions of each section can be summarized as following: 1. SPI Monitor and Decoder: • Extracts all of the sensor data transferred on the SPI in responding the MCU requests • Checks the sensor data whether they are in valid ranges and in the correct sequence requested by the MCU 2. Safing State Machine: • Applies overall safing control • Supports 5 exclusive operation modes: •Start-up Mode •Diagnostic Mode •Safing Mode •Scrap Mode •Arming Mode 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 37 FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION 3. Safing Control Counters: Data Valid Counter •Incremental by each sensor message containing valid data •Read by the MCU to determine if the safing logic has sufficient sensor data Sequence Counter •Incremented by each valid sensor message •Ensures the sensor data is requested by the MCU in the correct range of values, and aligns the sensor data to the corresponding safing threshold 4. Safing Threshold Logic: • Ensures the safing threshold values can be reliably written and read through a secure protocol run by the MCU 5. • • • Safing Compare Logic: Compares sensor data with configured threshold aligned by the sequence counter Increments the incident counter (sample counter) whenever the sampled sensor data value is beyond the thresholds Checks the incident counter to determine if Arming should be asserted. 6. Arming Enable Output: • A pair of complementary logical outputs used to enable the external arm circuit and/or squib drivers for deployment. SI SO SCK Internal Data Exchange SPI Interface CS Safing State Machine SCRAP Sequence Error CS_A CS_B CS_C SPI Monitor & Decoder Valid Sensor Data Safing Threshold Logic Data Valid Counter Sensor Message Sequence Counter Safing Compare Logic ARM DISARM Decoded Sensor Data SATSYNC Figure 23. Safing Logic Block Diagram 33789 38 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DESCRIPTION FUNCTIONAL INTERNAL BLOCK DESCRIPTION CONFIGURABLE GENERAL PURPOSE DRIVERS The 33789 offers two general purpose drivers. Each one can be configured as either a high-side driver or a low-side driver via the SPI. Both drain and source terminals of each driver have connect pins on the package, for external configuration convenience. The driver output pins can withstand shorts to as low as -1.0 V, as high as VPRW + 1.0 V, and up to 27 V for 5 minutes. They will survive with 40 V load dump. The driver output current capability is 70 mA with current limitation. The driver has integrated diagnostics and short-circuit protection. The output status can be checked by the MCU via the SPI. All output pin voltages can be monitored at the multiplexed analog output pin AOUT. The driver control block has a built-in 128 Hz 6-bit PWM modulator. Thus, the driver can be used as a dimmable indicator driver (such as an LED). When this option is selected, the activation of both drivers will be logically synchronized, which means both drivers will be turned on simultaneously. This allows an application to combine both drivers in parallel to drive a single load with a doubled drive capability. The output stage has slew rate control and thermal shut down features to improve performance and reliability. VPWR VPWR Short to VPWR VBST OUT1_D PWM (128Hz) OUT1_S Control Logic Exchange Short to GND Internal Data Failure Detection VPWR OUT2_S VPWR Other Analog Diagnosis Samples OUT2_D SPI Interface Analog MUX AOUT SPI Figure 24. Configurable General Purpose Driver Block Diagram 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 39 FUNCTIONAL DEVICE OPERATION OPERATING MODES FUNCTIONAL DEVICE OPERATION OPERATING MODES POWER MODE CONTROL The 33789 Power Mode Control controls the start-up activation of both boost and buck power supplies, based on the voltages on the VPWR and WAKE pins. The Wake input is a battery voltage, active-high logic input, and the detection threshold is normally VPWR/2. When the battery input at the VPWR pin exceeds the low-voltage lockout threshold VBST_UV, and the WAKE state is active (logic high), both the boost and buck converters are started. This low-voltage lockout threshold is also used as the ignition status threshold. The MCU can receive an indication that the threshold has been exceeded, when using the SPI STATUS to read the IGNSTSAT status and receiving the signal IGN=1 (see Table 32). Hysteresis is applied to prevent inadvertent deactivation of the boost supply. Figure 25 shows the glitch suppression of the Wakeup signal. WAKE 1 VPWR/2 1.0 ms 3 6 4 2 5 1.0 ms t 1.0 ms 1.0 ms 10 ms Figure 25. Wake Glitch Suppression The suppression results of the above six marked scenarios in Figure 25 are: 1. No change of sleep mode state, but current consumption may exceed specification for sleep mode. 2. The Sleep mode current returns to within specified limits. 3. Power supply exits Sleep mode. Switches start operating if applicable voltages exceed the undervoltage lockout threshold, but the Sleep Reset is still active, because of its 10 ms delay in response to the Wake-up signal. The system stays in Sleep mode. 4. Sleep Reset is released and the entire system starts operating. After this point, a SPI command to turn off switches would not be executed, but would be latched and wait for the WAKE signal change to low. 5. The latched SPI command to turn off the switches would not be executed if the Wake signal has turned to a low less than 1.0 ms. 6. After the Wake signal stays low for more than 1.0 ms, the latched SPI command to turn off the switches is executed and the system is turned off. To simplify the power supply state diagrams, an internal active low signal Sleep Mode needs to be introduced. Figure 26 shows the logic relation between the Sleep Mode signal and the Wake signal, SPI Buck_off command, and Sleep_Reset status. Delay WAKE 1 1ms S SPI Buck_Off R SET CLR Q 0 Sleep Mode Q Sleep_Reset Figure 26. Sleep Mode Control Logic With the Sleep Mode signal, the 33789 power mode control logic can be illustrated in the following diagrams. 33789 40 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATING MODES Sleep Mode =1 Boost Thermal Shutdown =0 VPWR > VBST_UV SPI BOE =1 Internal_ Reset Boost_ON=1 Boost_ON=0 Sleep Mode =0 Boost Thermal Shutdown =1 VPWR < VBST_UV SPI BOE =0 Figure 27. Boost Control Logic Diagram Sleep Mode =1 Buck Thermal Shutdown =0 VBST > VBUCK_UV VBUCK_OV =0 VCC_OV =0 Internal_ Reset Buck_ON=0 Buck_ON=1 Sleep Mode =0 Buck Thermal Shutdown =1 VBUCK_OV =1 VCC =0 Figure 28. Buck Control Logic Diagram Sleep Mode =1 VCC Ramp up VBUCK_OK =1 Start 5ms T1 Timer with UV masking Internal_ Reset VCC_OFF Sleep Mode =0 T1 timeout VCC_UV =0 T1 timeout VCC_UV =1 VCC_OV =1 T2 timeout VCC_ON VCC_UV =1 VCC_OV =1 VCC_OPEN =1 VCC_ON =0 Start 5ms T2 Timer Sleep Mode =0 Figure 29. VCC Control Logic Diagram VBUCK DIAGNOSTIC AND VCC RESTART Figure 29 indicates “VBUCK_OK = 1” is a necessary condition for VCC start. In a specific case, it can be VCC dependent. The situation could happen during the process of an MCU read of VBUCK from the AOUT pin, via the analog MUX, when VCC is incidentally turned off and attempted to be turned back on. VBUCK AI_CONTROL: VBUCK VCC VCC AOUT VBUCK / K4 Analog MUX VREF_1V VBUCK_OK = 1 Figure 30. VBUCK Diagnostic and VCC Clamping 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 41 FUNCTIONAL DEVICE OPERATION OPERATING MODES In Figure 30, the analog MUX output is clamped to VCC, to protect the 5.0 V buffer amplifier. When VCC is turned off, both the input and output of the MUX are clamped to GND, pulling the VBUCK_OK comparator input below 1.0 V, therefore, “VBUCK_OK = 0”. This logic status will lock out VCC from a restart, as long as the MUX is not changed by an internal reset. In vehicle applications, when the battery voltage drops very low, VPWR will fluctuate near the VBST_UV threshold. This particular operation condition will cause both the boost and buck switches to oscillate, resulting in a VCC on-off restart cycle, as described in Figure 27, Figure 28, and Figure 29 respectively. Other possible conditions causing VCC to turn off, can be found in Figure 29, the VCC Control Logic Diagram. If the MCU can always read VBST and show that VBST is in the specified normal operation voltage range, just before reading VBUCK, the buck capacitor should be able to hold the valid voltage long enough to ensure that VCC will not drop off before the VBUCK diagnostic read is complete. This software implementation can avoid a VCC restart difficulty in the low VPWR fluctuation condition. Users can also find other hardware solutions, with external configurations, to prevent VCC from dropping below its threshold, flipping the VBUCK_OK comparator output. INTERNAL POWER SUPPLY The 2.5 V internal supplies are created, based on two voltages: VPRE_HIGH and VPRE_LOW. VPRE_HIGH Regulator VPRE_HIGH provides supply for the power switches. The VPRE_HIGH regulator starts operation with the VPWR input. After the VBST output reaches the normal value, it switches the source to VBST. VBST VPWR 0 1 2 8.5V VP RE_HIGH Figure 31. VPRE_HIGH to VPRE_HIGH The VPRE_HIGH switch control logic can be described with the following truth table in Table 7. Table 7. VPRE_HIGH Switch Control Internal Reset Sleep Mode Boost_OK Switch Position 1 X X 0 0 0 X 1 0 1 0 1 0 1 1 2 33789 42 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATING MODES VPRE_LOW Regulator VPRE_LOW supplies power for the logic and bandgap circuits. The VPRE_LOW regulator starts operation with the VPWR input. After the VBUCK output reaches the normal value, it switches the source to VBUCK. VBUCK VPWR 0 1 2 Bandgap Wakeup 4.5V VP RE_LOW Figure 32. VPRE_LOW Regulator The VPRE_LOW switch control logic can be described with Table 8. Table 8. VPRE_LOW Switch Control VWAKE > VPWR/2 Sleep Mode Buck_OK Switch Position 0 0 X 0 X 1 0 1 X 1 1 2 1 0 X 1 V2P5 and VDD Regulators The 4.5 V VPRE_LOW is used to create a 2.5 V internal supply V2P5, which supplies the analog circuit, and its buffered output VDD supplies digital circuit. VPRE_LOW Ban dga p 1V Ref. V2P5 VDD Figure 33. 2.5 V Internal Supply Regulators VDD Output Capacitor and Diagnostics The VDD regulator is switched off for about 6.0 µs every 200 ms. Once the capacitor is disconnected or out of tolerance, the output voltage will drop and the VDD undervoltage error can be detected. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 43 FUNCTIONAL DEVICE OPERATION OPERATING MODES WATCHDOG STATES AND RESET Types of Resets and Reset Sources The reset functions of the 33789 control both its internal resets and the external resets on all of the devices in the system equipped with a reset input. The internal reset is triggered by the VDD voltage thresholds and the internal bandgap regulator status. The external RESET pin is driven by the following reset sources: • VCC voltage monitor • Window watchdog • VDD voltage monitor • Open ground monitor (for GNDA and VSS) • Internal bandgap regulator monitor Figure 34 shows the logic relation between all of the resets and all of the reset sources. VD D_ UV Inte rnal_Re set Ba ndg ap_OK Band gap VR EF_OK WSM_Reset VCC _OV V CC_UV Delay 10 ms WDOG Er ror SSM_Reset Delay 1ms VD D_OV GNDA Lo ss WDOG Test RESET Anal og_Reset Slee p_ Rese t Figure 34. Reset Logic The functions of the reset signals are: • Internal_Reset: Resets all internal blocks except Safing and Watchdog • WSM_Reset: Resets Watchdog State Machine • SSM_Reset: Resets Safing State Machine • Analog_Reset: Arm enable for ARM / DISARM • Sleep_Reset: Resets Sleep_Mode Logic Start-up Behavior After wake-up, when VCC ramps up, the internal power supply holds the RESET pin low and keeps the watchdog in a “INITIAL” state with the 33789 status register bit WDR = 0, which indicates the reset is not caused by any watchdog error. The register is guaranteed by design to be inactive during the VCC ramp up period. When the power-on delay has elapsed and VCC has entered into the valid voltage range, the RESET pin is released and the system operation starts. The Watchdog State machine (WSM) does not start its operation until the first watchdog feed command is received. Before the first watchdog refresh, the ARM and DISARM outputs are forced to maintain their high-impedance states. Watchdog Window A watchdog window is defined as a time window between two adjacent watchdog refreshes. The 33789 uses software watchdog, it periodically receives watchdog refresh signals from the MCU through the SPI interface. A successful watchdog refresh is a SPI command, WDOG_FEED (high or low), followed by another SPI command, WDOG_FEED (low or high), within a designated watchdog window. (See Figure 35, Watchdog Windows) Once the 33789 receives the first WDOG_FEED command, the first successful refresh occurs and the watchdog transits from “INITIAL” state to “DRIVE” state. (See Figure 36, Watchdog State Diagram) 33789 44 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATING MODES WDOG Refr esh WDOG Refresh Refresh Acceptance W indow Refresh Acceptance Window Watchdog Window (WDW) t t tWD W_MIN tW DW_MIN t WDW_MAX Last Refresh tWDW_M AX Last Refresh Figure 35. Watchdog Windows Watchdog Error WDOG Error is defined as: NOT [WDOG OVERIDE] AND [WDOG_FEED with same polarity as the previous feed OR WDOG_FEED before the min. window time to the previous feed OR WDOG_FEED after the max. window time to the previous feed] WDOG Refresh OK is defined as: WDOG_FEED with opposite polarity to the previous feed AND WDOG_FEED after the min. window time to the previous feed AND WDOG_FEED before the max. window time to the previous feed If a window watchdog refresh fails, the RESET pin will be pulled down for 1.0 ms to reset the system, and the 33789 internal status register will set the Watchdog Error Status bit WDR = 1, to indicate a watchdog error is the source of the reset. The value of the WDR bit is latched and can be read by the MCU via the SPI STATUS request command. The WDR bit is cleared by either a WSM_Reset or a correct WDOG_FEED. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 45 FUNCTIONAL DEVICE OPERATION OPERATING MODES WSM_Reset (From any state) Set ARM_LOCKOUT = 0 Set WDR = 0 VPPT>VPPT_TEST AND SPI WDOG_TEST 1.0 ms INITIAL WDOG error Set WDR = 1 Set ARM_LOCKOUT = 1 WDOG OVERRIDE WDOG refresh OK Set WDR = 0 WDOG RESET WDOG error Set WDR = 1 Set ARM_LOCKOUT = 1 WDOG error Set WDR = 1 WDOG refresh OK DRIVE SPI WDOG_TEST WDOG refresh OK WDOG TEST Figure 36. Watchdog State Diagram Arm Lockout and WDOG_TEST During a system reset, both the ARM and DISARM pin outputs are forced to the high-impedance state, which is called Arm Lockout. To individually test ARM and DISARM (The tests allow both the ARM and DISARM pins to be set to “1” or “0” at same time) while the WSM is still running in the background, the WSM can be set to the WDOG OVERRIDE state after a WSM reset, or insert the SPI command of WDOG_TEST from the DRIVE state, to avoid setting ARM_LOCKOUT = 1. Though watchdog error always causes a system reset, which can be measured at the RESET pin and can be checked by using the SPI STATUS command to read the bit WDR = 1, it does not always cause an Arm Lockout, which depends on the WSM running in the DRIVE state, or in the WDOG TEST state before the watchdog error occurs. Regardless whether the watchdog error causes an Arm Lockout, the WSM_Reset always brings the WSM back to the INITIAL state, with the setting of ARM_LOCKOUT = 0 and WDR = 0 at the end of the system reset. To facilitate testing of the watchdog error function, the SPI command WDOG_TEST can be used to prevent the Arm Lockout caused by a watchdog error. This command is only valid for the next watchdog window: A WDOG_TEST command has to be inserted before a watchdog error (invalid refresh or missing refresh) within the same watchdog window. Thus, once the error occurs, the consequential resets would not cause an Arm Lockout. (See Figure 37 for some typical examples of successful and unsuccessful inserted SPI WDOG_TEST commands) 33789 46 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATING MODES WDOG Refresh Refresh Acceptance Window t Last Refresh SPI WDOG_TEST received WDOG Refresh Refresh OK Return to DRIVE Without watchdog reset SPI WDOG_TEST did nothing WDOG Refresh Refresh Acceptance Window Refresh Acceptance Window 1ms 1ms t Last Refresh Missing refresh Set WDR=1 Return to INITIAL t Last Refresh SPI WDOG_TEST received Early refresh Set WDR=1 SPI WDOG_TEST received Return to INITIAL Figure 37. Successful and Unsuccessful WDOG Test Examples Arming Logic When an internal Arm signal is created, it shall be output through the ARM and DISARM pins only when the following conditions are satisfied: While in WDOG_OVERRIDE state OR While in DRIVE state with [SSM_Reset inactive AND Arm_Lockout inactive] In any other conditions, the internal ARM / DISARM control signal shall never be sent to the output, and the output pins ARM and DISARM shall be set to high-impedance. Whenever an Analog_Reset is created, the ARM and DISARM outputs are set to high-impedance to inhibit outputs by an analog implementation, as a part of failure mode control, the Arming logic result will be ignored. DRIVE ARM_LOCKOUT SSM_Reset WDOG OVERRIDE ARM / DISARM Output Control Analog_Reset Implemented in analog (0: High Impedance 1: Enabled) Figure 38. Arming Logic 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 47 FUNCTIONAL DEVICE OPERATION OPERATING MODES SATELLITE SENSOR INTERFACE PSI5 Interface The satellite sensor interface (see Figure 19) on the 33789 serves as master interface. Each one of its channels independently supplies a regulated DC voltage VSAT_OUT to its satellite devices. At the same time, it monitors the current draw to receive the sensor signals. The output current can be limited for fault protection. The satellite sensors transmit Manchester-encoded data with current modulation. The Manchester coding uses a rising edge to represent logic “0” and a falling edge to represent logic “1”. Start bits S1 ‘0’ Logic Data bits S2 ‘0’ D0 ‘1’ D1 ‘1’ D2 ‘0’ ISAT ISAT_MOD ISAT_TH ISAT_Q ISAT_TH_OFS t Bit Time = 1/fSAT • • • • • Figure 39. Current Modulation and Manchester Bit Encoding of Satellite Sensor The PSI5-P 10P -500/3L mode of PSI5 V1.3 protocol has the following features: PSI5-P: Peripheral Sensor Interface - Parallel Bus mode 10P: 10 data bits + 1 parity bit -500: 500 µs nominal synchronization period /3: three time slots for sensor data L: 125 kbps the first transmitted bit S1 S2 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 P 0 0 1 1 1 0 0 1 1 1 1 0 1 Manchester code example to transmit 0x1E7 = 01 1110 0111b Figure 40. Satellite Data Frame Format The even parity is checked for the entire data transmission except the start bits. If a parity error is detected, an error message will be sent to the MCU. The 33789 automatically calibrates the sensor clock, to align the sampling timing of the receiver for the Manchester decoding. Each channel has implemented an input data filter to remove the glitch from the input signal and recover data from waveform distortion, to reduce the decoding error. The input data filter includes sampling / holding circuit, shift register, and majority detector. If one or more of following statements are true, a Manchester Error will be directed to the MCU: • Two valid start bits are detected, and at least one of the expected 13 mid-bit transitions are not detected. • Two valid start bits are detected, and more than 13 mid-bit transitions are detected. • Two valid start bits are detected, and the sampled logic levels before and after any of the 13 expected mid-bit transitions are the same. Synchronous Operation Modes To synchronize the sampling of satellite sensor data, the master interface circuitry on the 33789 creates a sync pulse with increased voltage added on the top of sensor supply voltage VSAT_OUT, to signal the initiation of sampling to the satellites. The MCU periodically sends a satellite synchronization signal (Satsync) to the 33789, to activate the sync pulses and controls the timing of the satellite data acquisition. When the rising edge of the Satsync signal is detected, the master interface outputs four Sync pulses, one for each channel, on channels PSI5_1 through PSI5_4, in sequence. A 4.0 µs stagger time is inserted from channel to channel, to avoid high peak current. Figure 41 illustrates the sync signals’ voltage and timing relations. 33789 48 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATING MODES V SATSYNC V CC t V PSI5_1 V SAT_OUT V PSI5_2 t V SAT_SYNC t t SAT_SYNC _STAG V PSI5_4 tSYNC t Figure 41. Satellite Synchronization Pulses The sync pulse driver can either source or sink bus current. It outputs higher charge current to increase the bus voltage VPSI5_X from VSAT_OUT to VSAT_SYNC, at the beginning of Sync pulse, and discharges the bus capacitance at the end of sync pulse, to return the bus voltage back to VSAT_OUT. The pull-down device to sink the bus current is current limited. The sync pulse output from the interface is wave-shaped to limit the slew rate for EMC improvement. In the synchronous mode operation, satellite sensors transmit data in response to Sync pulse. Each satellite has its own assigned time slot for sending data. All of the satellites need to be pre-programmed for timing order, to realize different communication start times. The 33789 PSI5 interface supports two types of synchronous operation modes for scheduling satellite data transfer. The operation mode can be selected channel-by-channel per MCU SPI commands. 1. Synchronous Time-division Multiplexed (TDM) Mode The PSI5-P 10P -500/3L mode is a synchronous TDM mode of the PSI5 protocol, which supports one to three satellites per channel. VSATSYNC tSYNC VSAT_SYNC VSAT_OUT S1 S2 S3 S1 S2 S3 Figure 42. Synchronous TDM Mode The rising edge of the Satsync signal triggers the generation of the sync pulse, the falling edge of Satsync is ignored. The time window between two Sync pulses is divided into three time slots, each slot for one of the three satellite sensor’s data. Once the three Manchester data are received and decoded in sequence at the 33789, they are stored in order into three internal registers A, B, and C. All bits of these registers are simultaneously updated upon reception of the satellite message to prevent partial frame data from being checked out via the SPI interface. A fixed blanking interval, which is triggered by the rising edge of the Satsync signal, is inserted at the receiver to avoid false triggering of the Manchester decoder. The PSI5 Sync pulse can also be used for bidirectional communication. This feature allows the 33789 to send commands to satellites, which is useful to pre-program or re-program the satellite sensors in the system. Once the PSI5 bus is set to bidirectional communication mode by the MCU via the SPI, in every fixed Satsync period, the appearance of the sync pulse represents a logic “1”, and the missing pulse represents a logic “0”. The communications between an airbag ECU (master terminal) and the PSI5 satellite sensors (slave terminals), use two different modulations: Sensors ECU: current modulation ECU Sensors: voltage modulation 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 49 FUNCTIONAL DEVICE OPERATION OPERATING MODES 2. Satsync-steered Mode The Satsync-steered mode is another type of TDM operation. It supports up to two satellites per channel. VSATSYNC VSAT_SYNC VSAT_OUT ISAT S1 S2 S1 Figure 43. Satsync-steered Mode The data from two parallel connected satellite sensors are transferred in serial, and they are time-divided with alignment to the Satsync edges. At the 33789, the logic level of the Satsync signal steers the incoming sensor data into two input data registers: • When the Satsync input is high, the received data is stored in register A • When the Satsync input is low, the received data is stored in register B. Quiescent Current Monitoring The quiescent current on the PSI5 bus has a wide tolerance range. It varies from sensor to sensor, and depends on the number of the sensors on the bus. Supply voltage and ambient temperature also have an influence on the satellite sensor quiescent current. The 33789 automatically calibrates the interface quiescent current, and resets the adaptive current detection threshold, to achieve the demodulation accuracy. The 33789 uses three different timing strategies to monitor quiescent current in different communication states: 1) During Startup The PSI5 standard V1.3 allows the sensor quiescent current settling time tSET, up to 10 ms. Figure 44. Sensor Current Consumption During Startup To ensure a proper measurement, the 33789 starts to measure the bus quiescent current 10 ms after a channel is activated, and inhibits the Sync pulse generation until the first measurement is completed. The first measurement takes 35 ms. 33789 50 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATING MODES S a ts y n c S ig n a l S ync P u ls e 500 µs 500 µs 120 µs N o S y n c p u ls e u n t il 4 5 m s S1 PSI Bus C u rre n t A d d it io n a l q u ie s c e n t c u r r e n t s e t t lin g t im e S e n s o rs p o w e r-u p Q u ie s c e n t C u rre n t M e a s u re m e n t S2 S3 S2 S3 B u s c h a rg e D is c h a r g e F ir s t q u ie s c e n t c u rre n t m e a s u re m e n t Q u ie s c e n t c u r r e n t u p d a t e 0 C h a n n e l A c t iv a t io n 5 ms 10 m s 45 m s t Figure 45. Quiescent Current Measurement Timing 2) During Run-time with First Data Frame In every Sync cycle, if there is a data transfer activity during the first time slot, and the parity bit of the first data frame is checked as correct, the receiver updates the quiescent current 2.0 µs after the end of the parity bit. 3) During Run-time without First Data Frame If there is no data transfer activity detected in the first time slot, the receiver updates quiescent current 120 µs after the rising edge of the Satsync signal. The receiver would stop the updating if there is any data bit detected during the update process. ANALOG / DIGITAL CONVERTER The 33789 uses a single analog to digital converter, ADC, to measure the two analog input signals: • A_SENSOR: On-board analog safing sensor input • VERDIAG: The voltage change across the energy reserve capacitor CER for diagnosis When the 33789 receives the falling edge of Satsync signal, the ADC Control Logic asserts Start Of Conversion (SOC) signal, which is synchronized with the analog multiplexer (MUX) input select timing, to trigger the 10-bit A/D conversions for the two input signals in sequence. When each of conversions is completed, the ADC sends an End Of Conversion (EOC) signal back to the Control Logic, to set Sensor_val or ER_Val, depending on which input is processed. Analog Sensor Data After the A_SENSOR signal conversion, the Control Logic sets Sensor_val to load the data from the ADC into a high-pass digital filter, HPF, to reduce slow offset drifts caused by aging and environment. This offset remove process is also called Zero Adjust. The output of HPF is then latched into a 10-bit holding register, ASENSOR_RG. The MCU can use Sensor Request SPI command to access the 10-bit data from ASENSOR_RG. This allows the SPI Monitor in the 33789 safing block to treat A_SENSOR data exactly same as satellite sensor data. Similar to the satellite sensor data, subsequent SPI requests of A_SENSOR data before the next Satsync falling edge will result in an error response, with the ND (No Data) bit set for Exception status. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 51 FUNCTIONAL DEVICE OPERATION OPERATING MODES SPI A_SENSOR 10-bit ADC 0 1 Digital HPF ASENSOR_RG (10-bit) En A D 1 SATSYNC ASST En Clr Read VERDIAG VERDIAG_EN Satsync Filter SOC Select ER Discharge VERDIAG_RG (8-bit) ER_Val S/H Sensor_Val K3 EOC VERDIAG Internal Data Exchange Analog MUX ASST_DIS ADC Control Logic ER Discharge Energy Reserve Control Internal Reset Figure 46. The 33789 ADC Process Diagram VERDIAG Signal Conversion To convert the VERDIAG signal, VERDIAG _EN shall be active in advance. At the next Satsync falling edge, the ADC Control Logic asserts the ER Discharge signal to turn the ER charge switch (the high-side driver) off and the ER discharge switch (the low-side driver) on, discharging the energy reserve capacitor (see Figure 15, Energy Reserve Control Block Diagram). A sampling and holding circuit catches the initial VERDIAG voltage drop to have the ER diagnostic signal ready. When the MUX Select is switched from “0” to “1” (after the A_SENSOR signal conversion), the acquired initial VERDIAG voltage drop value is passed through and loaded into the ADC. Then the Control Logic set SOC to trigger the conversion. At the end of conversion, if the VERDIAG_EN signal is still active, following EOC, the ER Discharge signal will be de-asserted to turn off the ER discharge switch and turn the ER charge switch back on. At the same time, upon receiving EOC, the Control Logic sets ER_Val to latch the 8 most significant bits (MSB) of the 10-bit ADC output into a holding register VERDIAG_RG. This register will be cleared after a SPI read. The internal VERDAIG_EN signal is activated by ESR_DIAG SPI command from the MCU with the EN bit set (EN = ’1’), and it remains set until a subsequent ESR_DIAG SPI command with EN = ’0’. With this design, the 33789 can automatically repeat the ESR test on the ER capacitor in every Satsync cycle, using only one SPI command. 33789 52 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION OPERATING MODES A_SENSOR Signal Conversions Satsync SOC EOC Select Sensor_Val ASENSOR_RG Output ER_Val VERDIAG_RG Output VERDIAG_EN ER_Discharge VERDIAG VERDIAG Signal Conversions Figure 47. ADC Logic Sequence Analog Sensor Self Test On-board analog sensor self-test is often used to verify the functionalities and the connection between the sensor and the MCU. To facilitate the test without activation of the Arming outputs due to a fault possibility, the 33789 monitors the Analog Sensor Self Test control signal ASST from the MCU. An internal Analog Sensor Self Test Disable signal ASST_DIS is generated when the ASST pin is read logic high. The ASST_DIS signal is used to block the setting of Sensor_Val, thus inhibit triggering of the HPF and updating of the ASENSOR_RG, as the result, it suspends safing. The ASST input is filtered to prevent either inadvertent disabling of the safing during periodic self-test, or inadvertent arming, due to the slow response of the sensor output after the self-test signal deasserted. The filter is implemented with the following features: • ASST_DIS is cleared upon an internal reset. •ASST_DIS is set only after the ASST input is set for 3 consecutive Satsync falling edges. •Once set, ASST_DIS will be cleared only after the ASST input is cleared for 6 consecutive Satsync falling edges. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 53 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI SENSOR MESSAGE, OPERATION COMMAND AND SPI The 33789 communicates with the MCU via the SPI bus. SI and SO are in parallel, to transmit serial data as a bidirectional communication interface when the chip select CS is active (pulled low), and each bit of both signals is synchronized by the SPI clock SCK. SI data is clocked into the 33789 at the rising edge of SCK, and SO data is clocked out at the falling edge of SCK. Following a SI data request from the MCU, the 33789 transmits a SO response in single stage pipeline fashion. The request/response pattern can be seen in Figure 48. CS SCK SI Request 1 Request 2 Request 3 Response 0 Response 1 Response 2 SO Figure 48. SPI Data Frame Latency MESSAGE FORMATS OF SPI DATA There are two types of messages communicated on the 33789 SPI bus: a sensor request/response message and a non-sensor request/ response message. After an internal reset, the response on SO to the first SPI command is a non-sensor data error response (with RE=1, see Table 9). There is a single bit (SEN, bit 13) in the request frame which defines the message type. Sensor Message Format The MCU uses the sensor request/response to retrieve sensor data from: •The 33789 satellite interface block •On-board digital sensors with SPI interface These types of messages, as well as the analog sensor data, are also monitored by the Safing Logic block of the 33789. Table 9. SPI Sensor Data, - Message Format MSB 15 SI SQ1 x LSB 14 13 SQ0 SEN x 1 12 11 10 9 8 7 6 5 4 3 2 1 SQ2 0 0 0 0 0 0 0 0 LC3 LC2 LC1 x 0 0 0 0 0 0 0 0 a a a MSB SO 0 LC0 Sensor Data Request Digital Sensor Data for Logical Channel ‘aaaa’b a LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SQ2 SQ1 SQ0 P ST1 ST0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 Unused 0 1 Sensor Data from Satellite and On-board Sensors 1 0 Self-test Data 1 1 Sensor Data Response Status Decode: ES1 ES0 0 0 Unused Sensor Data On-board Sensor Self-test Exception Status Exception Status Decode: 0 0 OE ND CNC HE ME DE Slave (Receiver/on-board sensor) Error Status 33789 54 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 9. SPI Sensor Data, - Message Format (continued) MSB LSB 0 1 x x x x x x x 1 0 x x x x x x x 1 1 x x x x x x x x Reserved Used for Non-sensor Data Responses x Reserved Table 10. SPI Sensor Data, - Message Bit Definition SENSOR DATA REQUEST SI BIT DEFINITION Name Bit Position SQ2:SQ0 15, 14, 12 Definition Sequence identifier - used for synchronizing samples SEN 13 Sensor bit - Defines the request as a sensor data request or a non-sensor data request (1 = sensor data, 0 = non-sensor data) LC3:LC0 3:0 Logical channel select SENSOR DATA RESPONSE SO BIT DEFINITION Name Bit Position Definition SQ2:SQ0 15:13 P 12 ST1:ST0 11:10 ES1:ES0 9:8 OE 5 Overcurrent Error - Overcurrent of the low-side driver (short to battery) ND 4 No data (channel specific) - Sensor data not available CNC 3 Conditions Not Correct for operation (channel specific) as defined elsewhere - Request cannot be fulfilled because the channel is off, or in the wrong mode, etc. HE 2 Hardware Error in slave (channel/channel pair specific) - caused by hardware errors defined elsewhere, such as overtemperature overcurrent of the high-side driver (short to GND), reference out of range, etc. ME 1 Manchester error (channel specific) - incorrect number of bits, timing violation, etc. in Manchester bit-stream DE 0 Data error (channel specific) - Parity or CRC error in Manchester data D9:D0 9:0 Sequence identifier - used for synchronizing sensor samples Parity - Ensures odd parity for bits 15:0 of SO Status - Identifies the contents in D9:D0 of SO (sensor data, self-test data, error, etc.) Exception Status - Identifies the contents of exception data (Receiver/On-board Sensor Error Status, or Satellite Error) Sensor Data - For ST1:ST0 = 01 The Logic Channel Field (LC3:LC0) is used for the address of each of all 12 possible satellite sensors and one analog sensor. Each sensor address along with its channel and time slot on the bus, is assigned in Table 11. Table 11. Logic Channel Assignment Logic Channel (LC3: LC0) Physic Channel Time Slot Data Register 0000 PSI5_1 1 PSI5_1 RG_A 0001 PSI5_1 2 PSI5_1 RG_B 0010 PSI5_1 3 PSI5_1 RG_C 0011 PSI5_1 - N/A 0100 PSI5_2 1 PSI5_2 RG_A 0101 PSI5_2 2 PSI5_2 RG_B 0110 PSI5_2 3 PSI5_2 RG_C 0111 PSI5_2 - N/A 1000 PSI5_3 1 PSI5_3 RG_A 1001 PSI5_3 2 PSI5_3 RG_B 1010 PSI5_3 3 PSI5_3 RG_C 1011 PSI5_3 - N/A 1100 PSI5_4 1 PSI5_4 RG_A 1101 PSI5_4 2 PSI5_4 RG_B 1110 PSI5_4 3 PSI5_4 RG_C 1111 A_SENSOR N/A ASENSOR_RG 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 55 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI After the data from a given logic channel is read via the SPI interface, subsequent requests for the data from the same logic channel will result in an ERROR response with the No Data bit set (ND = ’1’). The conditions for setting and clearing of status bits in the Sensor Data Request messages are defined in Table 12. Table 12. SPI Sensor Data Request, - Error and Status Bit Setting Bit Description Setting Condition Clearing Condition Channel Behavior Overcurrent Error Satellite channel low-side overcurrent (short to V+ condition) and no hardware error (HE) detected Internal reset or LINE_ENABLED command with xLE = 0 (OFF) for the affected channel Channel is deactivated ND No Data Channel is ON, no Manchester error, data error or overcurrent error is detected and a valid satellite frame has not been received Cleared after a valid satellite data frame is received None CNC Conditions Not Correct Request for undefined channel or request for a channel not turned ON Internal reset, or upon requesting a valid channel after it has been turned ON None Hardware Error Any of the following: 1. Satellite channel high-side overcurrent (short to GND condition) 2. Satellite average IQ is out of range 3. Channel overtemperature conditions Internal reset, or LINE_ENABLE command with xLE = 0 (OFF) for the affected channel Channel is deactivated ME Manchester Error Improper Manchester data - incorrect number of data bits, incorrect data edge timing, with no overcurrent or hardware errors detected Internal reset, or cleared when read None DE Data Error Satellite data parity error, with no overcurrent error or hardware error detected Internal reset, or cleared when read None OE HE SPI LINE_ENABLE (xLE=0) CH Short to GND CH IQ Out of Range S SET Q HE CH Overtemp R S CH Short to V+ R S CH ON R Invalid Bit Count Invalid Bit Timing S R S Satellite Parity Error Correct Start Bits Received R CLR SET CLR SET CLR SET CLR SET CLR Q Q OE Q Q ND Q Q ME Q Q DE Q Figure 49. SPI Sensor Data Response, - Error Bit Logic Non-sensor Message Format Non-sensor messages are used for all of configurations, diagnostics, controls, etc. data traffic. Their message formats and bit definitions are listed in Table 13 and Table 14. 33789 56 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 13. SPI Non-sensor Data, - Message Format MSB SI LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OP1 OP0 SEN A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 x x x x x x x x x x x x x 0 1 0 Write Address 1 0 0 Read Address 1 1 0 Operand Decode: x x x x Write Data x Reserved Write x x x x x x x x Read x x x x x x x x Test MSB LSB 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 OP1 OP0 P ST1 ST0 ES1 ES0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 P 1 1 1 0 0 0 0 0 0 SE RE 0 0 1 P 1 1 1 0 Slave Status 1 0 P 1 1 1 0 Read Data 1 1 P 1 1 1 0 SO Slave Data Request x x x x x Slave Data Response Error Response Write Response Read Response x x x Test Response Table 14. SPI Non-sensor Data, Message Bit Definition SLAVE COMMAND SI BIT DEFINITION Name Bit Position Definition OP1:OP0 15:14 SEN 13 A4:A0 12:8 Address - For read or write operation D7:D0 7:0 Data - For write operation Opcode - Defines operation (Read, Write) Sensor bit - Defines the request as a sensor data request or non-sensor data request (1 = sensor data, 0 = non-sensor data) SLAVE RESPONSE SO BIT DEFINITION Name Bit Position OP1:OP0 Definition 14:13 p 12 Parity - Ensures odd parity for bits 15:0 of SO ST1:ST0 11:10 Status - Always ‘11’ for non-sensor response ES1:ES0 9:8 Exception Status - Always ‘10’ for non-sensor response D7:D0 7:0 Read Data/ Error Data/ Status SE 2 SPI Error - set to ‘1’ for request (SI) frame violations (incorrect number of SCK pulses, etc.) RE 1 Request Error - set to ‘1’ for illegal, or unknown requests Opcode - Identifies the contents of Read or Write data in D9:D0 - copied from SI if the request is granted OPERATIONAL-MODE SPI COMMANDS PSI5 Interface SPI commands SENSOR_DATA The SENSOR_DATA command is used to sample sensor data from the PSI5 interface and the analog sensor input. This is the only command that uses the sensor data request/response format. The details of this command are defined in Table 9, Table 10, Table 11 and Table 12. LINE_MODE (0x4F, 0x8F) The LINE_MODE command is used to configure the PSI5 receiver channels individually, for either Synchronous TDM Mode or SatsyncSteered. The command is latched until a subsequent SPI update or internal reset. The response indicates the current state of the line mode for each channel. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 57 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 15. SPI Command, - LINE_MODE LINE_MODE (0x4F, 0x8F) Write Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 0 1 1 1 1 x x x x LM4 LM3 LM2 LM1 SO 0 0 1 P 1 1 1 0 0 0 0 0 LM4 LM3 LM2 LM1 SI 1 0 0 0 1 1 1 1 x x x x x x x x SO 0 1 0 P 1 1 1 0 0 0 0 0 LM4 LM3 LM2 LM1 Default LM Line Mode 0 Channel PSI5_x protocol = Synchronous TDM Mode 1 Channel PSI5_x protocol = Satsync-Steered Mode LINE_ENABLE (0x43, 0x83) The LINE_ENABLE command is used to activate or deactivate the PSI5 channels individually. The command is latched until a subsequent SPI update or internal reset. Some incident conditions, such as a thermal or overcurrent shutdown could deactivate the channel as well. The response indicates the current state of the line activation and the overtemperature status for each channel. Table 16. SPI Command, - LINE_ENABLE LINE_ENABLE (0x43, 0x83) Write Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 0 0 0 1 1 x x x x 4LE 3LE 2LE 1LE SO 0 0 1 P 1 1 1 0 OT4 OT3 OT2 OT1 4LE 3LE 2LE 1LE SI 1 0 0 0 0 0 1 1 x x x x x x x x SO 0 1 0 P 1 1 1 0 OT4 OT3 OT2 OT1 4LE 3LE 2LE 1LE OTx Default Overtemperature Shutdown Indicator 0 No overtemperature shutdown on channel PSI5_x 1 Overtemperature shutdown on channel PSI5_x xLE Default Line Enable 0 Channel PSI5_x OFF 1 Channel PSI5_x ON SYNC_ENABLE (0x44, 0x84) The SYNC_ENABLE command is used to individually enable or disable the Sync pulse generation for the PSI5 channels while in Synchronous TDM Mode. It can be used to support bidirectional communication between the 33789 and the satellites. The state of the xSE bits is checked at the rising edge of the Satsync signal for each Satsync period. In Satsync-steered mode, the SYNC_ENABLE command is latched until subsequent SPI update or reset, but it has no effect on the Sync pulse output, because the communication back to the satellite via the Sync pulse modulation is disabled. The internal reset sets xSE = 1 for default. The response indicates the current state of the Sync pulse enable register for each channel. 33789 58 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 17. SPI Command, - SYNC_ENABLE SYNC_ENABLE (0x44, 0x84) Write Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 0 0 1 0 0 x x x x 4SE 3SE 2SE 1SE SO 0 0 1 P 1 1 1 0 0 0 0 0 4SE 3SE 2SE 1SE SI 1 0 0 0 0 1 0 0 x x x x x x x x SO 0 1 0 P 1 1 1 0 0 0 0 0 4SE 3SE 2SE 1SE xSE Default Sync Pulse Enable 0 Channel PSI5_x sync pulse disabled 1 Channel PSI5_x sync pulse enabled LIN Interface Control SPI Commands LIN_CONFIG (0x50, 0x90) The LIN_CONFIG command is used to control the LIN physical interface configuration. It supports two functions: 1) LIN signal wave-shaping: There are three different slew rates that can be selected along with the LIN speed selection for the best EMC performance. •>20 kBaud: Wave-shaping disabled. For test and production configuration use only •20 kBaud: For LIN compliant 20 kBaud communications •10.4 kBaud: For 10.4 kBaud LIN communications. It also can be used for ISO-9141communication. 2) Output Manchester Code at the RXD Pin: This Manchester code output feature allows one of four PSI5 current/voltage converters to output the voltage modulated Manchester signal through the RXD pin. The logic level changes of the output voltage represent the detection threshold triggering status of the selected PSI5_x channel current drawn. This feature provides a convenient access for using test and development tools to acquire satellite sensor data. The LIN_CONFIG command is latched until a subsequent SPI update or internal reset. The response indicates the current state of the LIN_CONFIG bits. Table 18. SPI Command, - LIN_CONFIG LIN_CONFIG (0x50, 0x90) Write Read 15 14 13 12 11 SI 10 9 8 7 6 5 4 3 2 1 0 0 1 SO x 0 0 1 0 0 0 0 x x REN RXO1 RXO0 FSEL LSR1 LSR0 1 P 1 1 1 0 x x REN RXO1 RXO0 0 LSR1 LSR0 SI 1 SO 0 0 1 0 0 0 0 x x x x x x x x x 1 0 P 1 1 1 0 x x REN RXO1 RXO0 0 LSR1 LSR0 LIN Slew Rate Select LSR1 LSR0 Default Function 0 0 20 kBaud communications 0 1 10.4 kBaud communications 1 0 > 20 kBaud communications (no pulse shaping) 1 1 > 20 kBaud communications (no pulse shaping) Boost/Buck Frequency Selection FSEL Default Function 0 Low speed switching (140 kHz) 1 High speed switching (245 kHz) 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 59 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 18. SPI Command, - LIN_CONFIG (continued) RX Output Select (for REN = 1) RXO1 RXO0 Default Function 0 0 Satellite Channel 1 0 1 Satellite Channel 2 1 0 Satellite Channel 3 1 1 Satellite Channel 4 RXD Output Enable REN Default Function 0 Normal function (RX outputs LIN signal) 1 Satellite monitor (RX outputs satellite Manchester signal) Power Supply Control SPI Commands PS_CONTROL (0x51, 0x91) The PS_CONTROL command is used for the system power management, including controls of boost supply, buck supply, sync supply, energy reserve, and VCC, as shown in Table 19. The command is latched until a subsequent SPI update or internal reset occurs. Some incident conditions, such as a thermal or overcurrent shutdown, could also deactivate the function. The response indicates the current state of system power management. The charge / discharge fault (CDF) bit is cleared by an internal reset, or by a SPI command attempting to deactivate both switches, by setting ERC[1:0] to '00'. Unlike other registers that are only set to their default state by an internal reset, the ERC bits are set to their default state by a Sleep Reset. V BST VBST Boost Enable Charge SPI Command V PRE _HIGH = 0 Internal Reset Discharge SPI Command V PRE _HIGH = 0 SW CHARGE CBST ERSW V ER Re xt SWDISCHARGE CER Figure 50. Energy Reserve Charge and Discharge Logic 33789 60 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 19. SPI Command, - PS_CONTROL PS_CONTROL (0x51, 0x91) Write Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 0 0 0 1 x x SC BOE x BUE ERC1 ERC0 SO 0 0 1 P 1 1 1 0 BST CDF SC BOE 0 BUE ERC1 ERC0 SI 1 0 0 1 0 0 0 0 x x x x x x x x SO x 1 0 P 1 1 1 0 x x REN RXO1 RXO0 x LSR1 LSR0 Boost Status BST Default Function 0 Boost voltage is less than threshold (~80% of target) 1 Boost voltage is greater than threshold (~80% of target) CER Charge/Discharge Switch Failure Status CDF Default Function 0 No overcurrent/temp fault on charge or discharge switches 1 Overcurrent/temp fault on charge or discharge switches Sync Supply Control SC Default Function 0 Deactivate sync supply 1 Activate sync supply Boost Enable BOE Default Function 0 Deactivate boost 1 Activate boost Buck Enable BUE Default Function 0 Deactivate buck request 1 Activate buck ERC1 ERC0 Discharge Switch Charge switch 0 0 OFF OFF 0 1 OFF ON 1 0 ON OFF 1 1 OFF OFF Energy Reserve Control Default ESR_DIAG (0x42, 0x82) The ESR_DIAG command is used to initiate the energy reserve capacitor ESR test and read the VERDIAG voltage for the test. Writing the enable bit (EN = '1') in the command will open the charge switch and close the discharge switch at the next Satsync falling edge, to allow the measurement of the ESR voltage. The enable state will remain set for repeating ESR test until a subsequent SPI ESR_DIAG command with EN = '0'. The ESR_DIAG command will respond to a read request with the most recent VERDIAG voltage from the A/D converter. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 61 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 20. SPI Command, - ESR_DIAG ESR_DIAG (0x42, 0x82) Write Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 0 0 0 1 0 x x x x x x x EN SO 0 1 0 P 1 1 1 0 x x x x x x x EN SI 1 0 0 0 0 0 1 0 x x x x x x x x SO 0 1 0 P 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 Boost Status EN Default Function 0 Disable ESR test (VERDIAG_EN = 0) 1 Enable ESR test (VERDIAG_EN = 1) D7:D0 Function Data VERDIAG voltage (ADC[9:2]) 1.95 mV/count Analog Interface SPI Commands AI_CONTROL (0x52, 0x92) The AI_CONTROL command selects an analog voltage source to be routed to the analog diagnostics output AOUT pin. The lower 5 bits of the command are used for the selection to form the multiplexed analog measurement. The AI_CONTROL command is latched until a subsequent SPI update, or a DIAG_CLR SPI command, or an internal reset occurs. The response indicates the current state of the analog interface control. Table 21. SPI Command - AI_CONTROL AI_CONTROL (0X52, 0X92) Write Read 15 14 13 12 11 10 9 8 SI 0 1 0 1 0 0 1 0 X X X AIC4 AIC3 AIC2 AIC1 AIC0 SO 0 0 1 P 1 1 1 0 0 0 0 AIC4 AIC3 AIC2 AIC1 AIC0 SI 1 0 0 1 0 0 1 0 X X X X X X X X SO 0 1 0 P 1 1 1 0 0 0 0 AIC4 AIC3 AIC2 AIC1 AIC0 Analog Interface Request Bits AIC4 AIC3 AIC2 ACIC1 AIC0 HEX 0 0 0 0 0 $00 RSENSE 1 0 0 0 0 1 $01 VERDIAG x5 0 0 0 1 0 $02 VPWR 5.6 8.5 Function Multiplier 0 0 0 1 1 $03 VBST 0 0 1 0 0 $04 VER 8.5 0 0 1 0 1 $05 VBUCK 2.8 0 0 1 1 0 $06 VSYNC 5 2 0 0 1 1 1 $07 IN1 0 1 0 0 0 $08 IN2 2 0 1 0 0 1 $09 IN3 2 0 1 0 1 0 $0A IN4 2 2 0 1 0 1 1 $0B IN5 0 1 1 0 0 $0C IN6 2 0 1 1 0 1 $0D IN7 2 33789 62 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Analog Interface Request Bits Default 0 1 1 1 0 $0E IN8 2 0 1 1 1 1 $0F IN9 2 1 0 0 0 0 $10 Unused (High-Z-output) 1 0 0 0 1 $11 OUT1-D 5.6 1 0 0 1 0 $12 OUT1-S 5.6 1 0 0 1 1 $13 OUT2-D 5.6 5.6 1 0 1 0 0 $14 OUT2-S 1 0 1 0 1 $15 Unused (High-Z-output) 1 0 1 1 0 $16 Unused (High-Z-output) 1 0 1 1 1 $17 Unused (High-Z-output) 1 1 0 0 0 $18 Unused (High-Z-output) 1 1 0 0 1 $19 Unused (High-Z-output) 1 1 0 1 0 $1A Unused (High-Z-output) 1 1 0 1 1 $1B Unused (High-Z-output) 1 1 1 0 0 $1C Unused (High-Z-output) 1 1 1 0 1 $1D Unused (High-Z-output) 1 1 1 1 0 $1E Unused (High-Z-output) 1 1 1 1 1 $1F Unused (High-Z-output) DC Sensor Interface SPI Commands DCS_CONTROL (0x53, 0x93) The DCS_CONTROL command is used to control two internal analog multiplexers for the DC sensor input interface activation, which include: •Sensor Channel Selection (SS): Determines which DC sensor input shall be connected to the internal regulated bias voltage supply for the analog diagnostic output AOUT. •Bias Voltage Selection (VS): Determines which one of four predefined voltages shall be used for the bias supply applied on the selected DC sensor output stage. The DCS_CONTROL command is latched until a subsequent SPI update, or a DIAG_CLR SPI command, or an internal reset occurs. Some incident conditions, such as thermal or overcurrent shutdown could deactivate the selections. The response of the command indicates the current state of the DC sensor interface control. Table 22. SPI Command - DCS_CONTROL DCS_CONTROL (0X53, 0X93) Write Read Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 0 0 1 1 SS3 SS2 SS1 SS0 VS1 VS0 x x SO 0 0 1 P 1 1 1 0 SS3 SS2 SS1 SS0 VS1 VS0 0 0 SI 1 0 0 1 0 0 1 1 X X X X X X X X SO 0 1 0 P 1 1 1 0 SS3 SS2 SS1 SS0 VS1 VS0 0 0 Input Sensor Select SS3 SS2 SS1 SS0 0 0 0 0 Voltage Supply not connected to any INx 0 0 0 1 Voltage Supply connected to IN1 0 0 1 0 Voltage Supply connected to IN2 0 0 1 1 Voltage Supply connected to IN3 0 1 0 0 Voltage Supply connected to IN4 0 1 0 1 Voltage Supply connected to IN5 0 1 1 0 Voltage Supply connected to IN6 0 1 1 1 Voltage Supply connected to IN7 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 63 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Default Input Sensor Select SS3 SS2 SS1 SS0 1 0 0 0 Voltage Supply connected to IN8 1 0 0 1 Voltage Supply connected to IN9 1 0 1 0 Voltage Supply not connected to any INx (reserved) 1 0 1 1 Voltage Supply not connected to any INx (reserved) 1 1 0 0 Voltage Supply not connected to any INx (reserved) 1 1 0 1 Voltage Supply not connected to any INx (reserved) 1 1 1 0 Voltage Supply not connected to any INx (reserved) 1 1 1 1 Voltage Supply not connected to any INx (reserved) VS1 VS0 0 0 Supply Voltage = 1.5 V 0 1 Supply Voltage = 2.5 V 1 0 Supply Voltage = 5.0 V 1 1 Supply Voltage = 6.5 V Supply Voltage Select Safing Logic SPI Commands SAFE_CONTROL (0x58, 0x98) The SAFE_CONTROL command is used for the following safing logic features: •Safing State Machine (SSM) operation mode control •Arming output test mode control, - the Arming outputs (via ARM and DISARM pins) can only be tested while SSM is in Diag mode •Request of the number of valid data messages received from sensors •Error status of the safing logic The Sequence Error (SE) bit is cleared upon the Satsync rising edge. Once an offset of the digital A_SENSOR data is detected at the HPF, which corresponds to an offset falls outside of 25% of the expected output, an internal offset error signal will be created and the Offset Error (OE) bit will be set. The HPF will continue process the A_SENSOR data received from the ACD, but ASENSOR_RG will not be updated with the OE bit set. The OE bit is cleared upon the SPI read only if the offset error condition is no longer present, which means the A_SENSOR input has returned to the valid range. Table 23. SPI Command - SAFE_CONTROL SAFE_CONTROL (0X58, 0X98) Write Read Default Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 1 0 0 0 X X X X MR1 MR0 TEN LEV SO 0 0 1 P 1 1 1 0 VD3 VD2 VD1 VD0 MD1 MD0 OE SE SI 1 0 0 1 1 0 0 0 X X X X X X X X SO 0 1 0 P 1 1 1 0 VD3 VD2 VD1 VD0 MD1 MD0 OE SE Mode Request MR1 MR0 0 0 No mode change requested 0 1 Request change to Safing Mode 1 0 Request change to Scrap Mode 1 1 No mode change requested TEN Arming Output Test Enable 0 ARM/DISARM output Test mode disabled 1 ARM/DISARM output Test mode enabled 33789 64 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Default Arming Output Test Level Select LEV 0 Set ARM=0, DISARM = 0 if TEN = 1 and in Diag mode 1 Set ARMN=1, DISARM = 1 if TEN = 1 and in Diag mode Valid Data Count VD3:VD0 xxxx MD1 Default Default Default Number of digital sensor messages received with valid sensor data Mode Status MD0 0 0 Startup Mode or Diag mode 0 1 Safing mode 1 0 Scrap mode 1 1 Arming mode OE A_SENSOR Data Offset Error 0 Offset error not detected on analog safing sensor input 1 Offset error detected on analog safing sensor input SE Sequence Error 0 Sequence error not detected 1 Sequence error detected SCRAP_SEED (0x59, 0x99) The SCRAP_SEED command is a read-only command used to request an 8-bit seed value for the safing state machine to enter into Arming mode. Upon reception of this command, the 33789 freezes the free-running seed counter, calculates a key value, and populates the frozen value as the response. A subsequent command that submits the key value (SCRAP_KEY) will allow the entry into Arming mode. Table 24. SPI Command, - SCRAP_SEED SCRAP_SEED (0x59, 0x99) Write * Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SI 0 1 0 1 1 0 0 1 x x x x x x x x SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 SI 1 0 0 1 1 0 0 1 x x x x x x x x SO 0 1 0 P 1 1 1 0 S7 S6 S5 S4 S3 S2 S1 S0 S7:S0 SEED 0 Function 8-bit seed value for Scrap Mode entry * The Write response will always be ERROR with the RE bit set to ‘1’ SCRAP_KEY (0x5A, 0x9A) The SCRAP_KEY command is a write-only command used to request an 8-bit key value for the Safing state machine to enter into Scrap mode. Upon reception of this command, the 33789 checks the submitted key value against the internally calculated key value, if they are equal, enters Arming mode. Periodic SCRAP_KEY commands are required for the Safing state machine to remain in Arming mode. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 65 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 25. SPI Command, - SCRAP_KEY SCRAP_KEY (0x5A, 0x9A) Write Read * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 1 0 1 0 K7 K6 K5 K4 K3 K2 K1 K0 SO 0 0 1 P 1 1 1 0 0 0 0 0 0 0 0 0 SI 1 0 0 1 1 0 1 0 x x x x x x x x SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 K7:K0 Function KEY 8-bit key value for Scrap Mode entry * The READ response will always be ERROR with the RE bit set to ‘1’ T_UNLOCK (0x4D, 0x8D) The T_UNLOCK command is a write-only command used to submit an unlock code to the Safing state machine to enable updating of the safing thresholds. The response from the 33789 is a fixed write response with all of data bits set to '0'. This command is only valid while the Safing state machine is in Start-up mode, and attempting T_UNLOCK commands while in other modes will result in an ERROR response with the RE bit set. Table 26. SPI Command, - T_UNLOCK T_UNLOCK (0x4D, 0x8D) Write Read * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 0 1 1 0 1 U7 U6 U5 U4 U3 U2 U1 U0 SO 0 0 1 P 1 1 1 0 0 0 0 0 0 0 0 0 SO ** 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 SI 1 0 0 0 1 1 0 1 x x x x x x x x SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 U7:U0 Function UNLOCK 8-bit key value for safing threshold update * The Read response will always be ERROR with the RE bit set to ‘1’ ** The response to a Write while not in Start-up Mode results in ERROR with RE = 1 SAFE_THx (0x45 ~ 0x4C, 0x85 ~ 0x8C) The SAFE_THx command is a read/write command used for reading and writing the 8 safing threshold values. Writing of the safing thresholds can be enabled only if the following conditions are all met: •The previously received message was a T_UNLOCK command •The Unlock code in the T_UNLOCK command is correct per definition •The Safing state machine is in Start-up mode Reading of the safing thresholds is enabled in any state, and requires no prior unlock message. A total of eight safing thresholds can be read or written using the eight commands as shown in Table 27. Table 27. SPI Command, - SAFE_THx SAFE_THx (0x45~0x4C, 0x85~0x8C) Write 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 0 A3 A2 A1 A0 DE T6 T5 T4 T3 T2 T1 T0 SO 0 0 1 P 1 1 1 0 DE T6 T5 T4 T3 T2 T1 T0 SO ** 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 33789 66 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 27. SPI Command, - SAFE_THx Read * SI 1 0 0 0 A3 A2 A1 A0 x x x x x x x x SO 0 1 0 P 1 1 1 0 DE T6 T5 T4 T3 T2 T1 T0 Comman d A3 A2 A1 A0 0x45,0x85 0 1 0 1 Safing Threshold 0 Command 0x46,0x86 0 1 1 0 Safing Threshold 1 Command 0x47,0x87 0 1 1 1 Safing Threshold 2 Command 0x48,0x88 1 0 0 0 Safing Threshold 3 Command 0x49,0x89 1 0 0 1 Safing Threshold 4 Command 0x4A,0x8 A 1 0 1 0 Safing Threshold 5 Command 0x4B,0x8 B 1 0 1 1 Safing Threshold 6 Command 0x4C,0x8 C 1 1 0 0 Safing Threshold 7 Command Function DE Default Dwell Extension 0 Dwell Extension = 255 ms 1 Dwell Extension = 2 s T6:T0 Safing Threshold THRESHOLD 7-bit Safing Threshold data * Response when [T_UNLOCK register value] = [DE, T6:T0]^0xAD ** Response when any of the following conditions exist (ERROR with RE = 1) 1 Previous SPI command was not T_UNLOCK write 2 [T_UNLOCK register value] <> [DE, T6:T0]^0xAD 3 Not in Start-up Mode Watchdog Control SPI Commands WDOG_FEED (0x4E, 0x8E) The WDOG_FEED command is a write-only command used to service the watchdog. Only watchdog 'high' or watchdog 'low' is accepted, any other values are ignored by the logic. The 33789 responds to the command is a fixed write response with all data bits set to '0'. Any attempted read access to WDOG_FEED will result in an ERROR response with the RE bit set to '1'. Table 28. SPI Command, - WDOG_FEED WDOG_FEED (0x4E, 0x8E) Write Read * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 0 1 1 1 0 D7 D6 D5 D4 D3 D2 D1 D0 SO 0 0 1 P 1 1 1 0 0 0 0 0 0 0 0 0 SI 1 0 0 0 1 1 1 0 x x x x x x x x SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 * The READ response will always be ERROR with the RE bit set to ‘1’ D7:D0 Function 0x55 Watchdog feed value LOW 0xAA Watchdog feed value HIGH Other No effect 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 67 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI WDOG_TEST (0x55, 0x95) The WDOG_TEST command is a write-only command used to put the watchdog state machine into the “wait for refresh failure” state. This can be used to test the watchdog error. The 33789 responds to the command is a fixed write response with all data bits set to '0'. Any attempted read access to WDOG_TEST will result in an ERROR response with the RE bit set to '1'. Table 29. SPI Command, - WDOG_TEST WDOG_TEST (0x55, 0x95) Write Read * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 0 1 0 1 x x x x x x x x SO 0 0 1 P 1 1 1 0 0 0 0 0 0 0 0 0 SI 1 0 0 1 0 1 0 0 x x x x x x x x SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 * The READ response will always be ERROR with the RE bit set to ‘1’ Other SPI Commands DIAG_CLR (0x54, 0x94) The DIAG_CLR command is a write-only command used to force all diagnostic controls to their default state. It affects two latched commands: AI_CONTROL and DCS_CONTROL. The response to the command is a fixed write response with all data bits set to '0'. Any attempted read access to DIAG_CLR will result in an ERROR response with the RE bit set to '1'. Table 30. SPI Command, - DIAG_CLR DIAG_CLR (0x54, 0x94) Write Read * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SI 0 1 0 1 0 1 0 0 x x x x x x x 0 x SO 0 0 1 P 1 1 1 0 0 0 0 0 0 0 0 0 SI 1 0 0 1 0 1 0 0 x x x x x x x x SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 * The READ response will always be ERROR with the RE bit set to ‘1’ STATUS (0x56, 0x96) The STATUS command is a read-only command used to retrieve the C33789 status for diagnostic purposes. The response to the command is a read response containing the current 33789 status. Attempted write access to STATUS will result in an ERROR response with the RE bit set to '1'. There are two status bits latched in the 33789 after they are set to their 'active' states. Once the bits are read via a STATUS command, they are set to their 'inactive' states. Only an internal reset and the STATUS read command can set these bits to their 'inactive' states, and immediately after either of them occur, the states are updated to reflect their true status. This is designed to ensure intermittent error conditions can be detected by the system. The following table defines these bits and their 'active' and 'inactive' states: Table 31. Two Latched Status Bit Name Function Active State Inactive State BOT Boost Supply Overtemperature 1 0 IGN IGNSTAT state 0 1 The WDR bit is set whenever the 33789 detects an incorrect watchdog refresh, and can be cleared by a WSM Reset or by a correct watchdog feed. 33789 68 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 32. SPI Command - STATUS STATUS(0x56, 0x96) Write * Read 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 0 1 1 0 X X X X X X X X SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 SI 1 0 0 1 0 1 1 0 X X X X X X X X SO 0 1 0 P 1 1 1 0 SOT DCOT BOT IGN WU WS1 WS0 WDR SOT Default Sync Supply Overtemperature Error 0 Sync supply overtemperature error not detected 1 Sync supply overtemperature error detected DCOT Default DC Sensor Regulator Overtemperature Error 0 DC sensor regulator overtemperature error not detected 1 DC sensor regulator overtemperature error detected BOT Default Boost Supply Overtemperature Error 0 Boost supply overtemperature error not detected 1 Boost supply overtemperature error detected IGN Default IGNSTAT State 0 VPWR < IGNSTAT threshold VBST_UV 1 VPWR IGNSTAT threshold VBST_UV WU Default Wake Pin State 0 WAKE Pin = 0 1 WAKE Pin = 1 Watchdog State WS1 Default WS0 Function 0 0 Watchdog State = “INITIAL” 0 1 Watchdog State = “DRIVE” and ARM_LOCKOUT = 0 1 0 Watchdog State = “DRIVE” and ARM_LOCKOUT = 1 1 1 Watchdog State = “WDOG_TEST” or “WDOG_OVERRIDE” WDR Default 0 1 Watchdog Error Status Previous reset was not caused by watchdog error Previous reset was caused by watchdog error * The Write response will always be ERROR with RE bit set to “1” OUT1_CTL (0x5B, 0x9B) and OUT2_CTL (0x5C, 0x9C) The OUTx_CTL commands are used to activate/deactivate the general purpose drivers. OUT1_CTL is for driver1 (OUT1_D, OUT1_S), and OUT2_CTL is for driver 2 (OUT2_D, OUT2_S). They are also used to configure the PWM duty cycle. Setting the duty cycle to 111111b will turn the driver ON without PWM, i.e. 100% duty cycle. Setting the duty cycle to 000000b will deactivate the driver, i.e. 0% duty cycle, thus it is considered as an “OFF” command. The OUTx_CTL commands also configure the drivers as a Highside Driver or Low-side Driver. The response from the command indicates the echo of the driver designation, comparator diagnostics information, and shows if a thermal shutdown occurred. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 69 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 33. SPI Command, - OUT1_CTL OUT1_CTL (0x5B, 0x9B) Write Read * Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 1 0 1 1 DC5 DC4 DC3 DC2 DC1 DC0 HS x SO 0 0 1 P 1 1 1 0 TS 0 ON23 ON13 HS 0 SI 1 0 0 1 1 0 1 1 x x SO 0 1 0 P 1 1 1 0 TS 0 DC5:D C0 DC% DC5:D C0 DC% DC5:D C0 DC% 0 000000 OFF 22 010110 34.9 43 101011 68.3 1 000001 1.6 23 010111 36.5 44 101100 69.8 2 000010 3.2 24 011000 38.1 45 101101 71.4 3 000011 4.8 25 011001 39.7 46 101110 73.0 4 000100 6.3 26 011010 41.3 47 101111 74.6 5 000101 7.9 27 011011 42.9 48 110000 76.2 6 000110 9.5 28 011100 44.4 49 110001 77.8 7 000111 11.1 29 011101 46.0 50 110010 79.4 8 001000 12.7 30 011110 47.6 51 110011 81.0 9 001001 14.3 31 011111 49.2 52 110100 82.5 10 001010 15.9 32 100000 50.8 53 110101 84.1 11 001011 17.5 33 100001 52.4 54 110110 85.7 12 001100 19.0 34 100010 54.0 55 110111 87.3 13 001101 20.6 35 100011 55.6 56 111000 88.9 14 001110 22.2 36 100100 57.1 57 111001 90.5 15 001111 23.8 37 100101 58.7 58 111010 92.1 16 010000 25.4 38 100110 60.3 59 111011 93.7 17 010001 27.0 39 100111 61.9 60 111100 95.2 18 010010 28.6 40 101000 63.5 61 111101 96.8 19 010011 30.2 41 101001 65.1 62 111110 98.4 20 010100 31.7 42 101010 66.7 63 111111 ON 21 010101 33.3 OFF23 OFF13 x HS Default Default Default Default Default Default x OFF23 OFF13 x x x x ON23 ON13 HS 0 Driver Configuration Select 0 LS Driver 1 HS Driver ON13 Driver ON 1/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold ON23 Driver ON 2/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold OFF13 Driver OFF 1/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold OFF23 Driver OFF 2/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold TS Thermal Shutdown Indicator 0 No shutdown has occurred 1 Thermal shutdown has occurred* * Status is cleared after OFF command is sent 33789 70 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Table 34. SPI Command, - OUT2_CTL OUT2_CTL (0x5C, 0x9C) Write Read * Default 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 0 1 0 1 1 1 0 0 DC5 DC4 DC3 DC2 DC1 DC0 HS x SO 0 0 1 P 1 1 1 0 TS 0 ON23 ON13 HS 0 SI 1 0 0 1 1 1 0 0 x x SO 0 1 0 P 1 1 1 0 TS 0 DC5:D C0 DC% DC5:D C0 DC% DC5:D C0 DC% 0 000000 OFF 22 010110 34.9 43 101011 68.3 1 000001 1.6 23 010111 36.5 44 101100 69.8 2 000010 3.2 24 011000 38.1 45 101101 71.4 3 000011 4.8 25 011001 39.7 46 101110 73.0 4 000100 6.3 26 011010 41.3 47 101111 74.6 5 000101 7.9 27 011011 42.9 48 110000 76.2 6 000110 9.5 28 011100 44.4 49 110001 77.8 7 000111 11.1 29 011101 46.0 50 110010 79.4 8 001000 12.7 30 011110 47.6 51 110011 81.0 9 001001 14.3 31 011111 49.2 52 110100 82.5 10 001010 15.9 32 100000 50.8 53 110101 84.1 11 001011 17.5 33 100001 52.4 54 110110 85.7 12 001100 19.0 34 100010 54.0 55 110111 87.3 13 001101 20.6 35 100011 55.6 56 111000 88.9 14 001110 22.2 36 100100 57.1 57 111001 90.5 15 001111 23.8 37 100101 58.7 58 111010 92.1 16 010000 25.4 38 100110 60.3 59 111011 93.7 17 010001 27.0 39 100111 61.9 60 111100 95.2 18 010010 28.6 40 101000 63.5 61 111101 96.8 19 010011 30.2 41 101001 65.1 62 111110 98.4 20 010100 31.7 42 101010 66.7 63 111111 ON 21 010101 33.3 OFF23 OFF13 x HS Default Default Default Default Default Default x OFF23 OFF13 x x x x ON23 ON13 HS 0 Driver Configuration Select 0 LS Driver 1 HS Driver ON13 Driver ON 1/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold ON23 Driver ON 2/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold OFF13 Driver OFF 1/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold OFF23 Driver OFF 2/3 VPWR Comparator Result 0 Diagnosis below threshold 1 Diagnosis above threshold TS Thermal shutdown indicator 0 No shutdown has occurred 1 Thermal shutdown has occurred* * Status is cleared after OFF command is sent NOP (0x57, 0x97) The NOP command is used to retrieve the response from a previous command without altering anything within the 33789. The response for the command is a fixed write response with all data bits set to '0'. Any attempted read access to NOP will result in an ERROR response with the RE bit set to '1'. Table 35. SPI Command, - NOP NOP (0x57, 0x97) Write Read * 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 SI 0 1 0 1 0 1 1 1 x x x x x x x 0 x SO 0 0 1 P 1 1 1 0 0 0 0 0 0 0 0 0 SI 1 0 0 1 0 1 1 1 x x x x x x x x SO 0 0 0 P 1 1 1 0 0 0 0 0 0 0 1 0 * The READ response will always be ERROR with the RE bit set to ‘1’ 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 71 FUNCTIONAL DEVICE OPERATION SENSOR MESSAGE, OPERATION COMMAND AND SPI Operational Mode SPI Command Table All of the 33789 operational mode SPI commands are summarized in Table 36. Table 36. Operational Mode SPI Command Table Operational Mode SPI Commands ADD R 00 01 02 Command Function R/W ESR_DIAG 03 04 LINE_ENABLE SYNC_ENABLE 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 SAFE_TH_0 SAFE_TH_1 SAFE_TH_2 SAFE_TH_3 SAFE_TH_4 SAFE_TH_5 SAFE_TH_6 SAFE_TH_7 T_UNLOCK WDOG_FEED LINE_MODE LIN_CONFIG Enable ESR Test / Read VERDIAC Satellite Channel Enable Satellite Channel Sync Pulse Enable Safing Threshold 0 Value Safing Threshold 1 Value Safing Threshold 2 Value Safing Threshold 3 Value Safing Threshold 4 Value Safing Threshold 5 Value Safing Threshold 6 Value Safing Threshold 7 Value Safing Threshold Unlock Watchdog Pet Command Satellite Synchronization Select LIN Configuration 11 PS_CONTROL 12 13 14 15 16 AI_CONTROL DCS_CONTROL DIAG_CLR WDOG_TEST STATUS 17 18 NOP SAFE_CTL 19 SCRAP_SEED 1A 1B SCRAP_KEY OUT1_CTL 1C OUT2_CTL Write Data 4 3 7 6 5 R/W 15:08 40 41 42 2 1 0 x x x x x x x R/W R/W 43 44 x x x x x x x x 4LE 4SE 3LE 3SE 2LE 2SE R/W R/W R/W R/W R/W R/W R/W R/W W W R/W R/W 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 T7 T7 T7 T7 T7 T7 T7 T7 U7 D7 x x T6 T6 T6 T6 T6 T6 T6 T6 U6 D6 x x T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 U5 U4 U3 D5 D4 D3 x x LM4 REN RX01 RXO 0 SC BOE x T2 T2 T2 T2 T2 T2 T2 T2 U2 D2 LM3 x Energy Reserve Activation Control Analog Interface Control DC Sensor Control Diagnostic Test Clear Watchdog Test 33789 Status R/W 51 x x BUE R/W R/W W W R 52 53 54 55 56 x SS3 x x x x SS2 x x x x SS1 x x x AIC4 SS0 x x x AIC3 VS1 x x x No-Op ARM/DISARM Output and Mode Control Scrapping Function Seed Request Scrapping Function Key Submit General Purpose Driver1 Output Control General Purpose Driver2 Output Control W R/W 57 58 x X x X x X x X R 59 x x x W R/W 5A 5B K7 DC5 K6 DC4 R/W 5C DC5 DC4 1D 1E 1F Read Data 4 3 7 6 5 EN 15:08 80 81 82 D7 D6 D5 D4 1LE 1SE 83 84 OT4 0 OT3 0 OT2 0 OT1 0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 U1 U0 D1 D0 LM2 LM1 LSR1 LSR0 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 T7 T7 T7 T7 T7 T7 T7 T7 0 0 0 x T6 T6 T6 T6 T6 T6 T6 T6 0 0 0 x ERC 0 AIC0 x x x x 91 BST CDF AIC2 VS0 x x x ERC 1 AIC1 x x x x 92 93 94 95 96 0 SS3 0 0 SOT x MR1 x MR0 x TEN x LEV 97 98 x x x x x K5 DC3 K4 DC2 K3 DC1 K2 DC0 K1 HS DC3 DC2 DC1 DC0 HS 5D 5E 5F 2 1 0 D3 D2 D1 D0 4LE 4SE 3LE 3SE 2LE 2SE 1LE 1SE T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 T5 T4 T3 0 0 0 0 0 0 0 0 lLM4 REN RX01 RXO 0 SC BOE 0 T2 T2 T2 T2 T2 T2 T2 T2 0 0 LM3 x T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 T1 T0 1 0 1 0 LM2 LM1 LSR1 LSR0 BUE 0 SS1 0 0 BOT AIC4 SS0 0 0 IGN AIC3 VS1 0 0 WU AIC2 VS0 0 0 WS1 0 VD3 0 SS2 0 0 DCO T 0 VD2 ERC ERC 1 0 AIC1 AIC0 0 0 1 0 1 0 WS0 WDR 0 VD1 0 VD0 0 MD1 0 MD0 1 OE 0 SE 99 S7 S6 S5 S4 S3 S2 S1 S0 K0 x 9A 9B 0 TS 0 0 1 HS 0 0 x 9C TS 0 0 ON1 3 ON1 3 HS 0 0 0 0 OFF2 OFF1 ON2 3 3 3 OFF2 OFF1 ON2 3 3 3 9D 9E 9F TEST-MODE SPI COMMANDS The 33789 enters Test mode when the PPT pin is driven high, i.e. 5.0 V, and the test-mode entry command is received. Table 37. SPI Command, - Test Mode Entry TESTMODE (ADDR=0xD5, DATA=0x52) TEST 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SI 1 1 0 1 0 1 0 1 0 1 0 1 0 0 1 0 SO 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 FAILURE MODE REQUIREMENTS SPI Error SPI Error is defined as a condition where the SPI frame format is incorrect. When a SPI error is detected, the 33789 will respond with an error response message on SO with the 'SPI Error' (SE) bit set. When a SPI error is detected, the 33789 will immediately set SO to a high-impedance state. SPI errors could be caused by: •An incorrect number of SPI SCK cycles (>16, or <16 but >0), while CS is active •Too short of an inter-frame time 33789 72 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SAFING SPI Request Error A SPI Request Error is defined as a condition, where the content of a SPI request message is incorrect. When a SPI Request Error is detected, the 33789 will respond with an error response message on SO with the 'Request Error' (RE) bit set. SPI request errors could be caused by: •An undefined command (e.g. incorrect address in bits [12:8]) •An illegal operation for a defined command (e.g. attempting to write when receiving a read-only command) •An attempted command request while in the incorrect state for the command (e.g. T_UNLOCK command while not in Start-up mode) SAFING SAFING CONCEPT The safing concept involves the utilization of logic independence of the MCU to monitor both on-board and remote satellite sensors, to determine if a sufficient inertial activity is present to warrant deployment Arming of the system. While in the Safing state, on the rising edge of the SATSYNC input, the MCU will request samples from all digital sensing sources, in a predetermined sequence with SPI commands. If sensor data in response is valid, the safing logic will compare it to the appropriate safing threshold. The threshold was arranged based on the expected sequence of sampling. The safing thresholds of the 33789 have been assigned to pairs of sequence numbers as shown in Table 38. Table 38. Sequence to Safing Threshold Mapping Sequence Identifier 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 Safing Threshold Threshold 0 Threshold 1 Threshold 2 Threshold 3 Threshold 4 Threshold 5 Threshold 6 Threshold 7 If three consecutive samples from the same sensor exceed the threshold, an internal safing signal is set. This safing signal activation will assert the Arming outputs (ARM and DISARM) for the duration of the signal, plus a Dwell Extension period after it is cleared. The Dwell Extension period is defined either 255 ms or 2.0 seconds depending on the safing condition. To prevent a loss of synchronization between the sampling order and the desired threshold (e.g. a sensor fails to respond), an internal Sequence Counter is designated to maintain the increments each time a sensor’s data response is received, whether it includes valid data or not. This Sequence Counter is reset at each rising edge of Satsync to re-synchronize with the next sampling period. If a sequence ID in the SPI request/response (SQ2:SQ0) does not match the corresponding value in the Sequence Counter, the 33789 will immediately set a Sequence Error bit and disable safing on digital sensors for the rest of the sample period, until the next Satsync rising edge. Another counter, Valid Data Counter, which is also reset at each rising edge of Satsync, is used to determine how many SPI data frames containing valid sensor data have been received in each sampling period. The Valid Data Counter is readable via the SPI for the MCU. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 73 FUNCTIONAL DEVICE OPERATION SAFING SAFING STATE MACHINE The Safing State Machine (SSM) is used to control the safing function and provide diagnostics. The control logic of the 33789 Safing State Machine can be described in Figure 51. This logic provides a high level of robustness to the system architecture by restricting the primary safing function while diagnostics are performed. It facilitates key-on and run-time diagnostic tests. It also provides a means of activating safing for the scrap function, which would be useful to safely activate the Arming outputs for disposal of pyrotechnic devices at the end of vehicle life. The 33789 Safing State Machine supports five mutually exclusive modes of operation: Start-up Mode The Start-up mode is entered upon the release of SSM Reset. While in Start-up mode, sampling sensor data and activating the ARM/DISARM outputs are inhibited. Updating the safing thresholds is permitted only while in Start-up mode. When the watchdog service begins (upon the first successful watchdog feed), the SSM enters the Diagnostic mode. Diagnostic Mode When the Diagnostic mode is entered, testing of the ARM and DISARM outputs are enabled, which allows the MCU to activate the signals both high or both low for testing the interface. It is not possible to set both of the outputs in their active states (ARM=1 and DISARM=0) in this mode. The SSM remains in this mode until a SAFE_CTL SPI command is received for either a Safing mode transition or a Scrap mode transition. Safing Mode Upon reception of the SAFE_CTL command with the CTL field set to 'Safing' while in Diagnostic mode, the SSM enters Safing mode. Safing mode is the primary run-time mode for normal operation. The safing logic can perform all of the safing functions, including monitoring sensor data and setting the ARM/DISARM signals for Arming output while in this state. The only means of exiting Safing mode is the assertion of the SSM Reset signal. Scrap Mode If the MCU sends the 33789 a SAFE_CTL command with the CTL field set to 'Scrap', while the SSM is in Diagnostic mode, it will force the SSM enter into Scrap mode. Once entered into Scrap mode, the SSM stops monitoring the sensor interface, and the safing compare logic is disabled. From Scrap mode, the SSM can be moved into Arming mode only if the MCU initiates the transition. The only way to move it back from Scrap mode to Start-up mode is through an SSM Reset. Arming Mode While in Arming Mode, the safing outputs are asserted (ARM = 1 and DISARM = 0) to enable firing of squibs. In order to protect from an inadvertent enter into Arming mode, and to prevent undesired activation of the safing signal, a handshake is used to control entering into and exiting out of Arming mode. 33789 74 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SAFING SSM Reset Start-up Mode SAFE_CTL = Safing WSM = DRIVE (ARM, DISARM determined by Safing) WSM = DRIVE OR [WSM = WDOG OVERRIDE and SPI WDOG Feed] (ARM, DISARM can be tested: ARM = 0 and DISARM = 0, or ARM = 1 and DISARM = 1) Diag Mode SAFE_CTL = Scrap WSM = DRIVE First Scrap KEY Safing Mode (ARM = 0, DISARM = 1) Scrap Mode Invalid Key OR Key timeout OR Incorrect ACL Valid Key: KEY value correct AND KEY received before scrap timeout is expired Valid key AND Correct ACL Incorrect ACL Valid Key AND Correct ACL Arming Mode (ARM = 1, DISARM = 0) Figure 51. Safing State Diagram The handshake sequence for activating the Arming outputs is illustrated in Figures 52. The strategy is: The 33789 uses a free-running 8-bit counter to generate a seed value; The MCU read the seed value with the SCRAP_SEED command; The MCU uses the seed value to generate an 8-bit key; The MCU submits the key value with the SCRAP_KEY command; The 33789 freezes the seed value read by the MCU and computes its own key; Compares two key values at the 33789; The 33789 receives the ACL signal at the SCRAP pin from the MCU; If two key values match each other, AND the ACL signal is valid, Transition into Arming mode To remain in Arming mode, the MCU must periodically refresh the 33789 with SCRAP_KEY command containing correct key value, and the 33789 must continuously receive a valid ACL signal at the SCRAP pin from either the MCU or another external device, depending on the application. This must occur before the scrap timeout timer expires (in about 600 µs). If the periodic scrap key is incorrect, or not been received before timeout, or there is no valid ACL signal at the SCRAP pin, the SSM reverts back to the Scrap mode, and the Arming outputs are deactivated. The scrap key is derived from the seed value using a simple logic inversion on the even-numbered bit (0, 2, 4, 6), - equivalent to a bitwise XOR of the seed value with 0x55, logically. 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 75 FUNCTIONAL DEVICE OPERATION SAFING MCU 33789 MCU Reset Enter Diag mode Start watchdog service to enter Diag mode Enter Scrap mode Send SAFE_CTL command with CTL = SCRAP Request seed value from the 33789 using SCRAP_SEED Command Calculate key using the seed received from the 33789, Submit key using SCRAP_KEY Command Freeze seed counter, respond with seed, calculate key using the seed Receive the first key from the MCU, compare it to the internally generated key, start scrap timer Receive key from the MCU and compare it to the internally generated key. If they are equivalent, and scrap timer has not expired and one valid ACL signal is received, enter Arming mode (assert safing signals and resets scrap timer) Submit key using SCRAP_KEY Command Continue SCRAP? Yes Submit key using SCRAP_KEY Command If key is received before scrap timer expires, both key and ACL signal are correct, reset scrap timer and continue remain in Arming mode; if not, enter Scrap mode and deactivate safing signals Figure 52. Arming Mode Handshake SPI MONITOR AND DECODER The SPI Monitor block extracts valid sensor data from the SPI sensor data messages read by the MCU to be able to determine the safing status. All of the safing related sensor data received by the safing block, including the satellite sensor data from the PSI5 interface, analog sensor data from A_SENSOR input, and other digital sensor data from local ECU sensors, are monitored for correctness of data and sequence by the SPI monitor decoder, and will be further used in the safing logic processing. The SPI monitor is capable of receiving sensor data through the SPI interface from up to 4 sources with 4 specifically assigned chip select signals: •CS: Dedicated to the PSI5 satellite channels •CS_A: Intended for an on-board high-g X, or X/Y accelerometer •CS_B: Intended for an on-board high-g Y, or expansion of satellite receiver •CS_C: Intended for an expansion of satellite receiver While the Safing State Machine is in Safing mode, the SPI Monitor listens to all of the SPI SO responses from satellite receivers and on-board sensors corresponding to sensor data request from the MCU, and uses predefined sensor message format and data validation criteria to check the messages. Functions of the SPI Monitor results in generation of three important internal signals within the safing block: Sensor Message Detection: - generate SENS_MSG When the SENS_MSG signal is activated, it indicates a valid sensor message is received and the Sequence Counter is not frozen (when frozen, the counter value equal to '1110'). The SPI Monitor needs to qualify the SPI message frame first by “Frame Check”: 1. SPI data is captured when the chip select is low; 2. The first 16 bits of SO data are captured regardless of the total number of SCK edges detected; 3. A valid frame is detected when the chip select goes high and at least 16 SCK edges have been detected; 4. Frames fewer than 16 SCK edges are ignored; 33789 76 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SAFING 5. If more than one chip select is active at any time during an SPI frame, the SPI frame shall not be validated. All of the necessary conditions to generate SENS_MSG can be found in Figure 53. SPI SO Sensor Data Response from Satellite Receiver or on-board Sensor MSB 15 SQ2 14 SQ1 13 SQ0 12 P 11 ST1 10 ST0 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 LSB 3 D3 2 D2 1 D1 0 D0 Parity Check SO[15:0] (OK = ‘1’) Frame Check SPI CSx SCK SENS_MSG: STx:ESx = ‘1110’ AND SPI parity correct AND Valid SPI message AND SSM = Safing Mode AND SEQ_CTR = ‘1110’ (OK = ‘1’) Safing Mode Sequence Counter = ‘1110’ D SET CLR Q Q Satsync Figure 53. SPI Decode Logic for SENS_MSG Signal Sequence Error Detection: - Generate SEQ_ERROR When a valid sensor message is detected (SENS_MSG = 1), the SPI Monitor compares the SQ2:SQ0 field (sequence number) of the SPI response message with the expected sequence number determined by the Sequence Counter. If there is a mismatch, the SEQ_ERROR signal is asserted, as shown in Figure 54. Activation of SEQ_ERROR will set the Sequence Error bit of the SPI SAFE_CTL command register (SE = 1), and disable the safing comparison for the affected sensor and all subsequent sensors for the rest of the current sampling period, until the next Satsync rising edge. While in Safing mode, the MCU must ensure that the sampling sequence is maintained for every sampling period, regardless of the state of sensors, to prevent a sequence error from disabling safing on the remaining channels in the sequence. Therefore, if there is a sensor disabled, the MCU must continue requesting data from the sensor to maintain the sampling sequence. However, it may load a “dummy” request to fill the SQ2:SQ0 field of the response message. SPI SO Sensor Data Response from Satellite Receiver or on-board Sensor MSB 15 SQ2 14 SQ1 13 SQ0 12 P 11 ST1 10 ST0 9 D9 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 LSB 2 D2 1 D1 0 D0 3-bit Compare: Output = 1, if equal Output = 0, if not equal = SEQ_ CTR[2:0] SEQ_ERROR SENS_MSG Figure 54. Sequence Error Detection Logic Sensor Data Validation: - generate DAT_VALID The DAT_VAL signal is activated whenever a SPI sensor data response message containing valid sensor data is received while in Safing mode. All of following conditions must be met to validate the sensor data: 1. ST1:ST0 field of the SO response must be '01', - to confirm this is a sensor data; 2. The SENS_MSG signal must be active, - to confirm it has a qualified message frame; 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 77 FUNCTIONAL DEVICE OPERATION SAFING 3. The data must be in the valid value range: • Data (D9:D0) within -480DEC ~ +480DEC inclusive if the sequence counter value >2 •Data (D9:D0) within -512DEC ~ +511DEC inclusive if the sequence counter value <3 4. The Sequence Error (SE) bit is clear. The SPI decode logic to validate sensor data can be illustrated in Figure 55. SPI SO Sensor Data Response from Satellite Receiver or on-board Sensor MSB 15 SQ2 14 SQ1 13 SQ0 12 P 11 ST1 10 ST0 9 D9 8 D8 7 D7 6 D6 5 D5 SENS_MSG SEQ_ERROR |SO[9:0]| < 481DEC 4 D4 3 D3 LSB 2 D2 1 D1 0 D0 DAT_VALID: [ST1:ST0] = ‘01’ AND SENS_MSG = ‘1’ AND SO data within the range |SEQ_ CTR| > 2 Figure 55. SPI Decode Logic for DAT_VAL Signal SAFING CONTROL COUNTERS There are two 4-bit Safing control counters in the Safing logic block. Data Valid Counter Satsync DAT_VALID (4-bit) Count Sequence Counter (4-bit) Reset SENS_MSG (4-bit) Reset Count (4-bit) To SPI Decoder and SPI Interface (MCU read SAFE_CTL) To SPI Monitorr and Safing Compare Logic Figure 56. Safing Control Counters Sequence Counter The Sequence Counter increments each time a valid sensor SPI message is received, regardless of whether it contains valid data, an error message, or self-test data. It is incrementally based on the SENS_MSG signal from the SPI Monitor block, and it resets on each Satsync rising edge. Due to the control of SENS_MSG, the Sequence Counter will never advance beyond '1110'. In order to correlate correctly with the received SPI messages, the Sequence Counter is reset to a value of '1111', so the first sample received causes it to increment to '0000'. This counter is not read nor write accessible via the SPI interface. The counter contents are used by the SPI Monitor logic to detect sequence errors, and by the Safing Compare Logic, to correlate sensor samples to the appropriate safing threshold for comparison. Data Valid Counter The Data Valid Counter increments each time a sensor SPI message is received that contains valid sensor data (ST1:ST0 = '01'). It is incrementally based on the DAT_VALID signal from the SPI Monitor block, and resets on each Satsync rising edge. Due to the control of SENS_MSG, the Data Valid Counter will freeze once the Sequence Counter reaches a value of '1110'. The Data Valid Counter is reset to a value of '0000' on each Satsync rising edge to accurately reflect the number of samples received. The count value can be read by the MCU using the SPI SAFE_CTL command to determine whether all digital sensor samples have been received by safing logic. 33789 78 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SAFING SAFING THRESHOLD LOGIC The Safing Threshold logic ensures the safing comparison threshold value can be reliably written and read by the MCU. The 33789 is capable of storing eight 8-bit safing thresholds. The MSB of threshold data is used to indicate the Dwell Extension pulse width (either 255 ms or 2.0 s). The thresholds are correlated to the sampling sequence number pair, as shown in Figure 57. Safing Threshold Sequence Identifier Threshold 0 Threshold 1 0000 0001 First sample requested (normally on-board X) Second sample requested (normally on-board Y) 0010 Third sample requested 0011 Forth sample requested etc. Threshold 6 Threshold 7 D654321 1100 1101 1110 Fifteenth sample requested Lower 3 bits are used to synchronize SPI request/response Threshold Value Dwell Extension bit (0 - 255 ms, 1.0 - 2.0 s) Figure 57. Safing Threshold Storage Upon the Safing state machine reset, all of the threshold values are rest to default values. Applications may choose to use these default values or reprogram them. The default safing thresholds are listed in Table 39: Table 39. Default Safing Thresholds Sequence # (Sampling Order) Sequence ID 0 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 1000 9 1001 10 1010 11 1011 12 1100 13 1101 14 1110 Desired 10-bit Threshold Value (dec) Desired 10-bit Threshold Value (hex) Dwell Extension 27 1B 255 ms 42 2A 2.0 s 16 10 255 ms 16 10 16 Targeted Sensor Type On-board 50 g X Targeted Encoded 8-bit Sensor Threshold Threshold (hex) 2.8 g 0D 30°/s 95 Satellite 240 g 10 g 08 255 ms Satellite 240 g 10 g 08 10 255 ms Satellite pressure 7.8%o 08 16 10 255 ms Satellite 240 g 10 g 08 8 8 255 ms Satellite 480 g 10 g 04 8 8 255 ms Satellite 480 g 10 g 04 On-board 50 g Y Digital ARS Analog ARS 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 79 FUNCTIONAL DEVICE OPERATION SAFING SPI Read / Write Access to Safing Thresholds The MCU has read and write access to the safing thresholds via the SPI interface, using eight SPI SAFE_THx commands. The application specific safing thresholds are allowed to be written to the safing logic only when the 33789 in Start-up mode, to ensure the Arming outputs are disabled during the threshold updates and to prevent inadvertent modification of the thresholds during Safing or Scrap mode. As additional protection against an undesired safing threshold update, writing an “unlock key” into the T_UNLOCK register prior to writing thresholds value through the SAFE_THx command is required. The T_UNLOCK command must immediately precede the SAFE_THx command to correctly update the threshold values. The unlock key value is calculated by bit-wise XORing the threshold value with the value '0xAD'. To successfully update the safing threshold registers, all of the following conditions must be met: •The 33789 is in Start-up mode •The previous SPI command must be a T_UNLOCK write command •The SAFE_THx command data field must be equal to the unlock code from the T_UNLOCK command XORed with 0xAD: •SAFE_THx(data) = [T_UNLOCK(data)] ^ 0xAD Start SPI_CMD (n-1) = ‘T_UNLOCK’? N Y SPI_CMD (n) = ‘SAFE_THx’? N Y KEY = SPI_DAT(n)^0xAD KEY = SPI_DAT (n-1)? N Y THRESHx SPI_DAT(n) END Figure 58. Safing Threshold Write Flowchart Safing Threshold Encoding Since the safing comparison involves the 8-bit threshold and a 9-bit magnitude, the desired threshold value must be divided by two (shift right by one bit) before being stored in the 33789. An additional MS '0 ' bit is then appended to the threshold value used for comparison. 33789 80 Analog Integrated Circuit Device Data Freescale Semiconductor FUNCTIONAL DEVICE OPERATION SAFING Threshold Encoding Example Threshold Decoding Example Unlock Encoding Example 27DEC Convert to Hex 8DHEX 1BHEX Convert to Binary Convert to Binary 0001 1011 0000 1101 Apply MS Dwell Extension bit 1000 1101 1000 1101 8DHEX Divide by 2 Bit wise XOR with 0xAD Convert to Binary 1000 1101 1000 1101 1010 1101 0010 0000 Strip off Dwell Extension bit 0000 1101 Multiply by 2 20HEX 0 0001 1010 8DHEX Value stored in Threshold Register 9-bit threshold used for compensation to the 9-bit sensor data Unlock Key used for writing threshold Figure 59. Safing Threshold and Unlock Key Encoding SAFING COMPARISON LOGIC Safing Comparison Enable The sensor data comparison is conducted under conditions of: • The SPI message frames are received • The sensor data is valid • There is no Sequence Error Figure 60. Safing Comparison Enable Logic Safing Magnitude Comparison All sensor data fed into the Safing Comparison logic is 9-bit, zero-adjusted, positive data, therefore the comparison involves a simple digital magnitude comparison between two 9-bit data. The sensor data in the SPI response message frame uses a 10-bit sensor data format. It must be converted into 9-bit magnitude data for the comparison with the safing threshold. 9-bit Sensor Data D8 D7 D6 D5 D4 D3 D2 D1 D0 9-bit Magnitude Compare 9-bit Threshold Data ‘0’ T6 T5 T4 T3 T2 T1 T0 ‘0’ 7-bit threshold stored in the 33789 Figure 61. Magnitude Comparison 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 81 FUNCTIONAL DEVICE OPERATION SAFING Sample Counters The sensor logic block consists of 16 2-bit Sample Counters to facilitate multi-sample evaluation of sensor data for safing. Each counter corresponds to a specific Sequence ID in the 33789, and is incremented each time when the received sample exceeds its associated safing threshold. If there are three consecutive samples from a same sensor exceed the threshold (Sample Counter = '11’b), the Arming outputs are asserted (ARM = 1, DISARM = 0). Once the counters reach their maximum value, they are not incremented further. The sample counters are reset upon Safing State Machine Reset, or whenever the corresponding data falls bellow its threshold. DWELL EXTENSION While in Safing mode, whenever the Arming signals is activated, Dwell Extension is used to extend the assertion time. The Dwell Extension is disabled while in Diagnostic mode, - the Arming outputs could be activated for test. While in Safing mode, If any of the 16 Sample Counters reach to their maximum value('11'b), the Arming outputs are asserted. They will be continuously asserted as long as any of the Sample Counters contain '11'b. and additionally, plus the established Dwell Extension time, after all Sample Counters contain values less than '11'b. The Dwell Extension time is determined by the MSB (bit 7) of the safing threshold in which safing was met (i.e. the data exceeded the threshold for three consecutive samples). The Dwell Extension time can be either 255 ms or 2.0 s, based on this bit assigned with the safing threshold setting. If safing is met on more than one Sequence ID with threshold(s) containing both 255 ms and 2.0 s Dwell Extension time choices, the longer (2.0 s) Dwell Extension is used for the safing outputs, which means the longer Dwell Extension time will override the shorter one. An example of Sample Counter, Dwell Extension time and Arming output is shown in Figure 62. Safing Threshold Sensor Magnitude Sample Counter 0 1 2 0 1 2 3 0 ARM DISARM Dwell Extension Sample Times Figure 62. Example of Safing Dwell Extension 33789 82 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE MECHANICAL DIMENSIONS PACKAGING PACKAGE MECHANICAL DIMENSIONS Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.freescale.com and perform a keyword search for the drawing’s document number. Table 40. Packaging Information Package Suffix 64-Pin LQFP-EP AFE Package Outline Drawing Number 98ASA10763D 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 83 PACKAGING PACKAGE MECHANICAL DIMENSIONS 33789 84 Analog Integrated Circuit Device Data Freescale Semiconductor PACKAGING PACKAGE MECHANICAL DIMENSIONS 33789 Analog Integrated Circuit Device Data Freescale Semiconductor 85 PACKAGING REVISION HISTORY REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 1.0 2/2011 • Initial Release 2.0 12/2011 • • • Revised ESD Capability. Took Human Body Model - JESD22/A114(3) from 6.0 kV to 2.0 kV Redefined INx Active Pull-down Current. Changed Max. from -50 to -30 µA Added First Dominant bit Delay 3.0 4/2012 • Updated datasheet to include SafeAssure branding and technology identification. 9/2014 • • • • • • • • • • • • • • Removed MCZ33789AE from the ordering information Added MCZ33789BAE to the ordering information Updated IERSW_LEAK parameter in Table 5 Deleted IVDD parameter in Table 5 Updated VCC_UV parameter in Table 5 Updated ISAT_TH_OFS parameter Table 5 Updated ISAT_TH_HYST parameter Table 5 Corrected the parameter label for fBST/BUCK in Table 5 Added Note 16 Added FSEL bit in LIN_CONFIG register in Table 17 Added new table to explain FSEL bit function in Table 17 Corrected Figure 37 Corrected Table 18 Updated format and back page. 4.0 33789 86 Analog Integrated Circuit Device Data Freescale Semiconductor How to Reach Us: Information in this document is provided solely to enable system and software implementers to use Freescale products. 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Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/SalesTermsandConditions. Freescale, the Freescale logo, and SafeAssure are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. SMARTMOS is a trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © 2014 Freescale Semiconductor, Inc. Document Number: MC33789 Rev. 4.0 9/2014