AN4437 Application note L9678 user configurable airbag Introduction This document explains the features and benefits of the L9678 device, target for entry level airbag system, with flexible configuration for power supply and management. The configuration of the device depends on the specific application. Guidelines for different operating modes of the device are provided. Meaning features are the flexible configuration, availability of different voltage regulators, two PSI-5 sensor interfaces, four DC sensors interface, two GPOs, high or low level diagnostic test, arming managed following both internal or external safing engine, deployment profile selectable, 32 bit SPI communication. Note: March 2015 The following information is given as a hint for the implementation of the device only and shall not be regarded as a description or warranty of a certain functionality, condition or quality of the device. DocID025845 Rev 2 1/201 www.st.com Contents AN4437 Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 Power off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.1 2.2 2.3 2.4 3 4 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.1 From sleep to active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.2.2 From active back to sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.3.1 From active to passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.3.2 From active back to sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Passive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.4.1 COVRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.4.2 From passive back to active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.3 From passive back to sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.4.4 From passive back to power off mode . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power up and power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Power down sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Operative state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 2/201 From power off to sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Initialization - Watchdog function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.1.1 WATCHDOG INITIAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.1.2 WD1 INITIAL - WD1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.1.3 WD1 INITIAL - WD1 OVERRIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4.1.4 WD1 INITIAL - WD1 RUN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.1.5 WD1 RUN - WD1 TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 SAFING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.4 SCRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 DocID025845 Rev 2 AN4437 Contents 4.5 5 ARMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.1 Internal voltage regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.2 ERBOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5.3 ER CHARGE - ER SWITCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.4 VDD5 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 VDD3V3 linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 5.6 VSUP Linear regulator (available for L9678S version) . . . . . . . . . . . . . . . 45 5.7 VSF linear regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.8 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7 SAFING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8 7.1 SPI sensor data decoding - Configuration . . . . . . . . . . . . . . . . . . . . . . . . 65 7.2 SPI sensor data decoding - MASK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3 SPI sensor data decoding - Example arming without on board sensor . . 78 7.4 Additional communication line (ACL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Deployment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.1 9 Deployment requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 8.1.1 ARMING state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 8.1.2 DIAGNOSTIC state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 8.1.3 SAFING state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8.1.4 DEPLOYMENT driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 8.1.5 Deployment current monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 8.2 Deployment driver protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 8.3 Deployment driver example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 9.1 Low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 9.1.1 High voltage leak test, oxide isolation IC-car chassis . . . . . . . . . . . . . 102 9.1.2 VRCM test validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 9.1.3 Leakage test - High side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 9.1.4 Leakage test - low side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 DocID025845 Rev 2 3/201 5 Contents AN4437 9.2 10 9.1.5 Leakage test - low side IPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 9.1.6 Short between loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 9.1.7 Squib resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9.1.8 High squib resistance diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 9.1.9 High side FET diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 9.1.10 Low side FET diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 9.1.11 High side driver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 9.1.12 LOSS of Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 9.1.13 Safing FET diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 9.1.14 Deployment time diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 High level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 9.2.1 VRCM check - High side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 9.2.2 VRCM check - Low side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9.2.3 Leakage check - High side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 9.2.4 Leakage check - Low side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 9.2.5 Short between loops . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 9.2.6 Squib resistance range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 9.2.7 Squib resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 9.2.8 High side FET diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.2.9 Low side FET diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Remote sensor interface - L9678-S only . . . . . . . . . . . . . . . . . . . . . . . 169 10.1 Fault protection, short to GND, current limit . . . . . . . . . . . . . . . . . . . . . . 173 10.2 Fault protection, short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 10.3 Cross link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 10.4 Leakage to battery / open condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.5 Leakage to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 10.6 Thermal shut-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10.7 Manchester decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 10.8 Trip current auto adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 11 DC sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 12 GPO drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 13 ISO9141 transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 4/201 DocID025845 Rev 2 AN4437 14 Contents System voltage diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 14.1 ADC algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 15 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 16 Footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Appendix A Energy reserve capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 DocID025845 Rev 2 5/201 5 List of tables AN4437 List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. 6/201 VER measurement of the value ratio ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Blocks disabled in each IC state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Global SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Deployment driver example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 VRESDIAG and SFx measurement of the value ratio ADC . . . . . . . . . . . . . . . . . . . . . . . 104 Squib x resistance measurement of the value ratio ADC . . . . . . . . . . . . . . . . . . . . . . . . . 122 VSF and SS measurement of the value ratio ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Resistance measurement of the value ratio ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 RSUx measurement to obtain the voltage value. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 GPODx and GPOSx measurement of the value ratio ADC . . . . . . . . . . . . . . . . . . . . . . . 188 Voltage measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 DocID025845 Rev 2 AN4437 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. Figure 48. Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Device states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Wake-up input signal behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 WAKEUP filter time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 COVRACT external components usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Example of power up sequence - VBAT then WAKEUP . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Example of power up sequence - WAKEUP then VBAT . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Microcontroller drives the power shutdown. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power shutdown due to low or lost battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Device functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Watchdog functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 WD1 INITIAL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WD1 INITIAL - WD1 RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 WD1 INITIAL vs. WD1 OVERRIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 WD1 INITIAL vs. WD1 RUN vs. WD1 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 WATCHDOG service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 WD1 RESET - WD1 TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 ERBOOST functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 ERBOOST protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 ER CAP functionality. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ER SWITCH functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 VDD5 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 VDD3V3 functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 VSUP functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 VSF enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Regulators diagnostic errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 RESET organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 SPI signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Internal ARIMNG signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 ARMING organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 MOSI, MISO, SPI_CS, SAF_CS0, SAF_CS1, SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Sensor's axis and vehicle's axis correlation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 ARMING enable pulse stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 SPI sensor frame organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 MOSI, MISO, SPI_CS,SAF_CS0, SAF_CS1, SCLK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 ACL signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Device functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 High side and low side squib enable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 High side and low side squib enable in ARMING state. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 High side and low side squib enable in DIAG state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 High side and low side squib enable with ARMING signal . . . . . . . . . . . . . . . . . . . . . . . . . 87 Driver's DEPLOYMENT signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 DEPLOYMENT enable/disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Current measurement during deploy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Diagnostic - blocks overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 High voltage leak test, oxide isolation IC-car chassis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Diagnostic - VRCM test validation (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Diagnostic - VRCM test validation (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 DocID025845 Rev 2 7/201 8 List of figures Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. 8/201 AN4437 Diagnostic - leakage test - high side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Diagnostic - leakage test - low side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Diagnostic - leakage test - low side IPD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Diagnostic - short between loops, HSi, HSx, ix (case 1). . . . . . . . . . . . . . . . . . . . . . . . . 114 Diagnostic - short between loops, HSi, LSx, ix (case 2) . . . . . . . . . . . . . . . . . . . . . . . . . 115 Diagnostic - short between loops, LSi, HSx, ix (case 3) . . . . . . . . . . . . . . . . . . . . . . . . . 116 Diagnostic - short between loops, LSi, LSx, ix (case 4) . . . . . . . . . . . . . . . . . . . . . . . . . 117 Diagnostic - HS short to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Diagnostic - LS short to Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Diagnostic - Squib resistance measurement (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Diagnostic - Squib resistance measurement (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Diagnostic - High squib resistance diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Diagnostic - High side FET diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Diagnostic - High side FET diagnostic, SR short to GND . . . . . . . . . . . . . . . . . . . . . . . . . 131 Diagnostic - Low side FET diagnostic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Diagnostic - Low side FET diagnostic, SF short to Battery. . . . . . . . . . . . . . . . . . . . . . . . 134 Diagnostic - Low side FET diagnostic, SR short to Battery . . . . . . . . . . . . . . . . . . . . . . . 135 Diagnostic - High side driver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Diagnostic - Safing FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Cases of status of the VSF (on or off) and on the commands from the microcontroller . . 141 Deployment timer diagnostic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Deployment timer - no programmation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Deployment timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 High level loop diagnostic flow 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 High level loop diagnostic flow 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Diagnostic - Safing FET flow. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Diagnostic - VRCM check - High side. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Diagnostic - VRCM check - High side waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Diagnostic - VRCM check - Low side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Diagnostic - Leakage check - High side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Diagnostic - Leakage check - High side waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Diagnostic - Leakage check - High side waveform, long time . . . . . . . . . . . . . . . . . . . . . 155 Diagnostic - Leakage check - Low side . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Diagnostic - Squib resistance range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 Diagnostic - Squib resistance measurement (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Diagnostic - Squib resistance measurement (2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Diagnostic - High side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Diagnostic - Low side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Manchester bit encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 In rush current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Remote sensor current auto adjust. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 GPO low side configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 GPO high side configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 ISO9141 transceiver block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 FIFO filling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 Footprint L9678-L9680 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Footprint L9678-L9679 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 Blocks active in Autarchy mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Energy reserve capacitor depletion - timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 DocID025845 Rev 2 AN4437 1 Description Description The L9678 IC is a system chip solution targeted for emerging market applications. Base system designs can be completed with the L9678, SPC560Px microcontroller and an onboard acceleration sensor or PSI5 sensor. 1.1 Main features Main features are: Energy reserve voltage power supply – High frequency boost regulator, 1.875 MHz – Output voltage user selectable, 23 V or 33 V ±5% User configurable linear power supplies – 5.0 V and 7.2 V ±4% output voltages – External pass transistor Fully integrated 3.3 V ±4% linear regulator Battery voltage monitor and shutdown control with wake-up control System voltage diagnostics with integrated ADC Crossover switch – Crossover performance, max 3 Ω, 250 mA max. Squib deployment drivers – 4 channel HSD/LSD – 25 V maximum deployment voltage – 1.2 A @ 2 ms and 1.75 A @ 0.5/0.7 ms deployment profiles – Integrated safing FET linear regulator, 20 V nominal – Current monitoring – Rmeasure, STB, STG and leakage diagnostics – High and low side driver FET tests – Safing FET test User customizable safing logic Two channel PSI-5 remote sensor interface with SPI selectable switched/regulated output voltage (asynchronous mode) Four channel hall-effect, resistive or switch sensor interface ISO9141 transceiver Dual channel configurable high-side/low-side LED driver Watchdog timer Two integrated oscillators: 7.5/16 MHz COVRACT function to connect externally of IC VIN to reserve capacitor Temperature sensor 32 bit SPI communications Minimum operating voltage = 6 V Operating temperature, -40 °C to 95 °C Packaging - 64 pin DocID025845 Rev 2 9/201 200 Description 1.2 AN4437 Application overview Different configurations for the device are possible. The device configurations are selected via SPI. Two different ways for the diagnostics, high level and low level, can be chosen. In low level diagnostic an external logic takes care of all the required set-up necessary for the requested measurement. In high level diagnostic, the set-up for the measurement request is managed by the device itself. The choice of high level or low level diagnostic is done via SPI. The IC status during its running can be partitioned in 4 phases POWER OFF / SLEEP MODE / ACTIVE MODE / PASSIVE MODE. This document explains in which way the device can be used. 10/201 DocID025845 Rev 2 AN4437 Description Figure 1. Functional block diagram 9EDW + Q) X) 66 $ X) ) Q) Q) P)WRP) (5%676: (5%2267 9(5 9%DW0RQ X&B)/(1 (5&KDUJH (5 %RRVW %67*1' 9,1 Q) N %9'' %&3 9'' 6DILQJ UHJXODWRU (56ZLWFK 9'' OLQHDU UHJXODWRU 96) *1'68%[ Q) *32' ) 9''9 ) :$.(83 9,JQ 9''4 &9'' 9''9 OLQHDUUHJ *326 *32' *32 GULYHUV VXSSO\ 9,179 UHJ IRU DQDORJ EORFN V *326 'LJLWDO 2XWSXWV 95(6',$* Q) &9''UHJ IRU GLJLWDOEORFN V *1'' 66 *1'$ N %9683 %&3 66 9683 OLQHDU UHJXODWRU 'LJLWDO EORFN 9683 6) 6) ) 6DWHOOLWH'ULYHU 'HFRGHU 2SWLRQDO /6 6) Q) 6) (QDEOH &RQWURO )(1+ +9DQDORJ08; DQG $WR'FRQYHUWHU ELWV )(1/ 65 65 'HFRGHU 568 65 /6 568 Q) 65 '&+DOOVHQVRULQWHUIDFH Q) 6* (QDEOH &RQWURO 6TXLEGULYHUV DQG 'LDJQRVWLF '&6 6DILQJ /RJLF '&6 6* $&/ $50 '&6 Q) '&6 6\VWHPFRQWURO FRQILJXUDWLRQ ,62 WUDQVFHLYHU *1'68% &295$&7 :'7',670 63,B026, 5(6(7 63,B6&. 63,B0,62 6$)B&6 6$)B&6 63,B&6 ,627; ,625; *1',62 ,62. 9EDW &DSDFLWRURQ(5%2267FDQEHVHOHFWHGVPDOOHULQFDVH(5%2267LVVHWWRUHPDLQ21DOVRLQ$XWDUFK\PRGH(567$7(7KLVVHOHFWLRQLVFKRVHQVHWWLQJ E>@ .HHSB(5%RRVWB21LQ6<6B&)*,1,75HFRPPHQGHGYDOXHLV))PLQORZ(65RWKHUZLVHLWVYDOXHLVKLJKHU))ORZ(65 DocID025845 Rev 2 *$3*36 11/201 200 Power up 2 AN4437 Power up Power off / sleep mode / active mode / passive mode To pass from one mode to the others, see the flow here below: Figure 2. Device states )URP DQ\VWDWH 325 32:(5 2)) VWDWH :$.(83! :8BPRQ :DNH8S)LOW $1' 63,B6<6B&7/63,B2)) 32:(52))02'( $OOVXSSOLHVGLVDEOHG :$.(83 :8BPRQ :$.(83 021,725 VWDWH :$.(83! :8BRQ >:$.(83:8BRII$1':DNH8S)LOW @ :DNH8S)LOW $1' 9%$7PRQ9%*22' 25 9,19,1*22' $:$.( 6WDWH :DNH8S)LOW 25 9%$7PRQ9%%$' 25 9,19,1%$' :DNH8S)LOW $1' 9%$7PRQ!9%*22' $1' 9,1!9,1*22' 6/((302'( $OO6XSSOLHV'LVDEOHG 99,17DQG&9''UHJ HQDEOHGLQ$:$.(VWDWH 67$5783 VWDWH :DNH8S)LOW $1' 9%$7PRQ!9%*22' $1' 9,1!9,1*22' 7ZDNHXS!PV :DNH8S)LOW $1' 63,B6/((3 581 VWDWH 9%$7PRQ! 9%*22' EODQNLQJWLPHPV $&7,9(02'( $OO6XSSOLHV(QDEOHG (56ZLWFK'LVDEOHG 9,19,1*22' 32:(502'( 6+87'2:1 VWDWH (5 VWDWH :DNH8S)LOW $1' 63,B6/((3 7ZDNHXS7LPHU&OHDUHGLI6WDWH :$.(83021,725RU$:$.( DQG:DNH8S)LOW 12/201 DocID025845 Rev 2 3$66,9(02'( 'LVDEOH(5%RRVW (QDEOH(56ZLWFK RWKHUVXSSOLHVHQDEOHG *$3*36 AN4437 Power up Status of power control is readable via SPI: $04 SYS_STATE POWER_CTL_STATE, bit [2:0] 2.1 000 = AWAKE 001 = START UP 010 = RUN 011 = ER 100 = POWER SHUT-DOWN 101, 110, 111 unused Power off This state represents the case of low power supply and POR. No voltage regulators are enabled. 2.1.1 From power off to sleep mode Condition to enter into the next phase (sleep mode): WAKEUP>WU_mon WU_mon (1.5V max) Power supplies are not necessary at their correct value. 2.2 Sleep mode Supposing the external power supplies are increasing and WAKEUP pin connected to external power supply, WAKEUP pin raises too. As WAKEUP pin is over the second threshold WU_on (4V÷5V), the two internal 3.3V voltage regulators run: 3V3INT is not accessible as it is internal only; CVDD is available on pin 9 WakeUpFlt=1 means that WAKEUP pin is high at least 1 ms. 2.2.1 From sleep to active mode Condition to enter into the next phase (Active mode): (WakeUpFlt=1) & (VBATmon>VBGOOD) & (VIN>VINGOOD) That means: the IC waits until WAKEPU is steadily high (at least 1ms) and the external power supplies have reached their correct values, VBGOOD for VBATmon pin and VINGOOD for VIN pin. VBGOOD / VBBAD and VINGOOD/VINBAD are fixed via SPI (so through the microcontroller), writing SYS_CTL register at any time and the default value: b12=0, VINGOOD = [5V:5.5V], VINBAD = [4.5V:5V] b11, b10=00, VBGOOD = [5.5V:6V], VBBAD = [5V:5.5V] DocID025845 Rev 2 13/201 200 Power up AN4437 $02 SYS_CTL Config. in INIT, DIAG, SAFING, SCRAP, ARMING state VIN_TH_SEL, bit 12 VBATMON_TH_SEL, bit 11, 10 2.2.2 0 1 = 5.5V, VINGOOD = [5V:5.5V], VINBAD = [4.5V:5V] = 7.5V, VINGOOD = [7V:7.5V], VINBAD = [6.5V:7V] 00 01 10 11 = 6V, VBGOOD = [5.5V:6V], VBBAD = [5V:5.5V] = 6.8V, VBGOOD = [6.3V:6.8V], VBBAD = [5.5V:6.3V] = 8V, VBGOOD = [7.5V:8V], VBBAD = [7V:7.5V] = 8.8V, VBGOOD = [8.3V:8.8V], VBBAD = [7.8V:8.3V] From active back to sleep mode Condition to turn back into the previous phase (POWER-OFF MODE): WAKEUP<WU_mon WU_mon (1.5V max) That means that WAKEUP turns low. 2.3 Active mode Active mode corresponds to the normal IC operation. Until POR is not released, ERBOOST follows VBATT; the two internal voltage regulators, VINT3V3 and CVDD are running. As POR is released (see Section 5.8: RESET), ERBOOST starts running, followed by VDD5 and then by VDD3V3 (VDD3V3 is supplied by VDD5). Once VDD5 and VDD3V3 are at their correct value, the microcontroller is supplied. IC RESET pin is released and the microcontroller starts running too. Microcontroller first checks In this phase the microcontroller shall service the watchdog routine, (see Section 4.1: Initialization - Watchdog function. The microcontroller has to verify the correct connection of the external reserve capacitor on VER pin, enabling ER charge block $02 SYS_CTL ER_CUR_EN, bit 7 Config. in INIT, DIAG, SAFING, SCRAP, ARMING state 0 = ER current source OFF requested 1 = ER current source ON requested and verify that VER voltage increases linearly (constant current). VER voltage is readable through ADC. Registers involved in this operation are the four DIAGCTRL_x $3x DIAGCTRL_x → x = A, B, C, D Case x = A 14/201 DocID025845 Rev 2 AN4437 Power up $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] new data available from the conversion 0 = cleared on read 1 = conversion finished ADCREQ_A, bit [6:0] request (MOSI) $26 = VER ADCREQ_A, bit [16:10] readout (through MISO), $26 = VER ADCRES_A, bit [9:0] 10bit ADC result correspondent to the ADCREQ_A, bit [9:0] Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio of the ADC. In case of VER, it is 15:1. Table 1. VER measurement of the value ratio ADC Divider ratio Measurements 15:1 VER 10:1 7:1 4:1 1:1 √ In case of problem, the microcontroller has to switch off the ER charge. Note: ER charge is limited at 20mA, so any load connected to VER (VRESDIAG for example) subtracts current to the external reserve capacitor charge. As shown in Figure 3, a 1 ms filter time is implemented on the WAKEUP input signal. After that 9 ms has been elapsed with no WAKEUP de-assertions, WAKEUP active condition is latched. Figure 3. Wake-up input signal behaviour $&7,9(02'( 6/((302'( 3$66,9(02'( :8BRQ :8BRII :$.(83 W PV PV PV :DNH8S)LOW PV PV W *$3*36 DocID025845 Rev 2 15/201 200 Power up 2.3.1 AN4437 From active to passive mode Conditions to enter into the next phase (PASSIVE MODE): 1 - (WakeUpFlt=0) & SPI_SLEEP cmd 2 - VIN<VBGOOD VBGOOD (5.5 V÷6 V) The first case represents the normal IC shut-down, required by the microcontroller. The microcontroller puts the WAKEUP pin low for at least 1ms and sends the dedicated SPI command: $03 SPI_SLEEP SLEEP_MODE, [15:0] Config. in INIT, DIAG, SAFING, SCRAP, ARMING state $3C95 The second case represents the event of low battery, because, for example, battery connection has been lost. 2.3.2 From active back to sleep mode Condition to enter into the previous phases (SLEEP MODE): (WakeUpFlt=0) OR (VBATmon < VBBAD) OR (VIN<VINBAD) That means that WAKEUP is not steadily high for at least 1ms in the first 9ms, or the external power supplies are turned at low value: VBATmon<VBBAD or VIN<VINBAD (4.5 V÷5 V) being VBBAD = 5 V÷5.5 V and VINBAD = 4.5 V÷5 V. 2.4 Passive mode In Passive mode (ER state) ERBOOST can be disabled or not; it depends on KEEP_ERBST_ON bit, SYS_CFG register: KEEP_ERBST_ON=0 → ERBOOST disabled in ER state KEEP_ERBST_ON=1 → ERBOOST not disabled in ER state In PASSIVE MODE "ER charge" is disabled to decouple ERBOOST from VER. There are two cases: 1. The first case is a driven switch off through an SPI_ SLEEP command and WAKEUP is low. The driven switch off can be received by the IC also during a low VIN voltage (second case). In this condition the system survival is guaranteed by the energy stored in the external reserve capacitor. 2. The second case is related to a low VIN voltage value. ER switch is automatically turned on to connect VIN to VER. The energy requirement, which may include the firing too, is taken from the external reserve capacitor, until the capacitor is depleted and POR happens. In this condition, current from the external reserve capacitor is limited by "ER switch" at 300 mA min, regardless VER value (22 V or 33 V). The external reserve capacitor has to be chosen taking into account the highest energy requirement. 16/201 DocID025845 Rev 2 AN4437 Power up Note: If the capacitor on VER pin is not fully charged and VIN goes low, the external reserve capacitor could not be able to supply the system with the energy required. 2.4.1 COVRACT When the IC moves in PASSIVE MODE, COVRACT signal is asserted. Figure 4. WAKEUP filter time In Figure 4 are reported signals when the IC moves in PASSIVE MODE because of battery lost: ch1 = RESET, ch2 = COVRACT, ch3 = VIN, ch4=VER. In the next Figure 5 two possible usages of COVRACT function are shown in case of supplementary deployment ASICs and/or satellite receivers to be supplied during Autarchy mode (battery loss). Being ER SWITCH current limited (300-500 mA), in the above mentioned cases a supplementary cross over switch may be needed and the simplified external circuitry to be used is shown below. DocID025845 Rev 2 17/201 200 Power up AN4437 Figure 5. COVRACT external components usage 9%$7 aP) 237,21$ 9,1 6833/< 9(5 / &295$&7 6XSSOHPHQWDO 'HSOR\PHQW$6,&¶V DQG RU6DWHOOLWH 5HFHLYHUV 237,21% 9%$7 aP) 9,1 9(5 / &295$&7 6833/< 6XSSOHPHQWDO 'HSOR\PHQW$6,&¶V DQG RU6DWHOOLWH 5HFHLYHUV *$3*36 The difference between options A and B is just the current that flows through the diode (active or passive) placed between battery line (VBAT) and VIN pin. If the current consumption of additional ASICs is too high to permit the L9678 to work at low battery level, the option A is mandatory, otherwise option B is OK too. 18/201 DocID025845 Rev 2 AN4437 2.4.2 Power up From passive back to active mode Condition to turn into the previous phases (ACTIVE MODE): If the IC is in PASSIVE MODE due to low battery, as VBATmon turns at correct value (before POR event) the IC turns back into ACTIVE MODE VBATmon >VBGOOD If the IC has been passed in PASSIVE MODE due to a SPI request, to turn back in ACTIVE MODE it is necessary: (WakeUpFilt=1) & (VBATmon >VBGOOD) & (VIN> VINGOOD) 2.4.3 From passive back to sleep mode Condition to turn into the previous phases (SLEEP MODE): If the IC is in PASSIVE MODE - power shutdown state, to turn back in SLEEP MODE it is necessary (WakeUpFilt=1) & [(VBATmon <VBGOOD) OR (VIN< VINGOOD)] 2.4.4 From passive back to power off mode Condition to turn into POWER OFF MODE: If the IC is in PASSIVE MODE - power shutdown state, to turn back in POWER OFF MODE it is necessary a second SPI command WakeUpFlt=0) & SPI_POWER OFF cmd $02 SYS_CTL Config. in INIT, DIAG, SAFING, SCRAP, ARMING state SPI_OFF, bit 4 0 = no effect 1 = transition to POWER OFF If this second SPI request is not received by the IC, that is in PASSIVE MODE due to a SPI SLEEP mode request (with correct value of power supply), the IC remains in PASSIVE MODE. In the table here below disabled blocks in each IC state are shown: Table 2. Blocks disabled in each IC state SLEEP MODE ACTIVE MODE POWER WAKEUP AWAKE STARTUP OFF Wakeup Detector Disabled Intern reg. Disabled RUN PASSIVE MODE POWERMODE SHUTDOWN ER Disabled DocID025845 Rev 2 19/201 200 Power up AN4437 Table 2. Blocks disabled in each IC state (continued) SLEEP MODE ACTIVE MODE POWER WAKEUP AWAKE STARTUP OFF 20/201 ERBOOST Reg. Disabled Disabled Disabled VSUP reg. (only L9678-S) Disabled Disabled Disabled ER CAP current charge Disabled Disabled Disabled ER switch Disabled Disabled Disabled VDD5 reg. Disabled Disabled Disabled VDD3V3 reg. Disabled Disabled Disabled Deployment drivers Disabled Disabled Disabled VSF safing FET reg. Disabled Disabled Disabled Remote Sensor Interf. Disabled Disabled Disabled Watchdog Disabled Disabled Disabled Diagnostic Disabled Disabled Disabled DC sensor interf. Disabled Disabled Disabled GPO drivers Disabled Disabled Disabled Safing logic Disabled Disabled Disabled ISO 9141 Disabled Disabled Disabled Disabled DocID025845 Rev 2 RUN Disabled PASSIVE MODE POWERMODE SHUTDOWN ER Disabled Disabled Disabled Disabled AN4437 Power up and power down 3 Power up and power down 3.1 Power up sequence The aim of the procedure is to reach WakeUpFilt=1, VBATmon>VBGOOD, VIN>VINGOOD. Different cases are possible as: WAKEUP rises after that VBAT is GOOD, Figure 6; WAKEUP rises while VBAT is rising, Figure 7. Figure 6. Example of power up sequence - VBAT then WAKEUP 9,1FXUUHQW 9%$7 9%$7PRQ 9%*22' :8BRQ :$.(83 :8BPRQ 9,17&9'' 325 %676: (5%2267 9'' 9''9 9''9 WKUHVKROG 5(6(7 5(6(7 +ROG 7LPH 63,(5 FKDUJHRQ 9(5 *$3*36 DocID025845 Rev 2 21/201 200 Power up and power down AN4437 Figure 7. Example of power up sequence - WAKEUP then VBAT 9,1FXUUHQW 9%$7 9%$77PRQ 9%*22' :8BRQ :$.(83 :8BPRQ 9,17&9'' 325 %676: (5%2267 9'' 9''9 WKUHVKROG 9''9 5(6(7 5(6(7 +ROG 7LPH 63,(5 FKDUJHRQ 9(5 *$3*36 At the end of the power up sequence the device is in ACTIVE MODE. 22/201 DocID025845 Rev 2 AN4437 3.2 Power up and power down Power down sequence Different possibilities are available. Normal power shut down driven by microcontroller: first WAKEUP is driven low and then an appropriate command is sent (SLEEP MODE), Figure 8: It could happen that the IC receives the first command, indicated as SLEEP MODE in the figure, but not the second. Being VIN at its correct value, the IC remains in that state. Microcontroller should recognize the bad situation and manage it. Figure 8. Microcontroller drives the power shutdown 9%$7 9%$77PRQ 9%*22' 9%%$' :$.(83 63, :8BRQ :8BRII 6/((3 02'( 6+87 '2:1 9,17&9'' WKUHVKRO 9,17&9'' %676: (5%2267 9(5 9'' 9''9 WKUHVKROG 9''9 5(6(7 325 7KLVSHULRGRIWLPHFDQEHKHOGIRUDORQJ WLPHEHFDXVHEDWWHU\LVJRRG7KHV\VWHP ZDLWVXQWLODGHGLFDWHGIUDPHKDVVZLWFKRII *$3*36 DocID025845 Rev 2 23/201 200 Power up and power down AN4437 Another shut down is related to low battery. Shut down is related to low energy available, until POR happens, see Figure 9. In this case "ER switch" is automatically closed. VIN is thus connected to VER whose voltage is close to ERBOOST. As consequence, the external reserve capacitor depletes, VER and VIN voltages are consequently reduced. CVDD/VINT and VDD5/VDD3V3 switch off depends on their load. The higher is the current they have to furnish, the shorter is the time they are on. Figure 9. Power shutdown due to low or lost battery 9%$7 :$.(83 9,1 9,1*22' 9,17&9'' WKUHVKROG 9,17&9'' %676: (5%2267 9(5 ,QWKLVSHULRGRIWLPH(5VZLWFKLV21 9'' 9''9 WKUHVKROG 9''9 5(6(7 325 *$3*36 24/201 DocID025845 Rev 2 AN4437 4 Operative state Operative state As the device has been turned on, all voltage regulators run. Being VDD5, VDD3V3 present, the microcontroller is supplied, but still in RESET. As VDD5 and VDD3V3 are at their correct value and no fails are present (see Section 5.8: RESET), RESET pin is released and the microcontroller starts working. The following states are distinguishable (see Figure 10): Initialization / diagnostic / safing / scrap / arming Figure 10. Device functionality 33-2ESET #ONFIGURATIONENABLEDFOR 7ATCHDOGTIMINGTHRESHOLDS !2-INOUTSELECT 235OUTPUTTYPE'M37 $IAGSAMPLESELECT 63&VOLTAGESELECT )NIT 3TATE 7$25. 7$/6%22)$% #ONFIGURATIONENABLEDFOR 3AFINGRECORDSANDCONTROL $EPLOYMASK (3,3'0/ $IAG 3TATE 30)3!&).'?34!4% 4ESTINGENABLEDFOR !2-X63& $EPLOYTIME (3,3(33&%4 30)3#2!0?34!4% !2-63&DETERMINED BYSAFINGENGINE 3AFING 3TATE 3CRAP 3TATE !2-X 63& !#,'//$ !#,"!$ !RMING 3TATE !2-X 63& '!0'03 IC states are readable through SPI: $04 SYS_STATE OPER_CTL_STATE, bit [10:8] 000 = INIT 001 = DIAG 010 = SAFING 011 = SCRAP 100 = ARMING 101, 110, 111 unused DocID025845 Rev 2 25/201 200 Operative state 4.1 AN4437 Initialization - Watchdog function The first state of the IC is when the microcontroller starts is the INITIALIZATION state. The state in which the IC is, is readable via SPI: $04 SYS_STATE OPER_CTL_STATE bit [10:8] 000 = IC in INIT state In this phase the following configurations are managed: Set-up of watchdog parameters, before the watchdog is asserted Safing engine parameters General system configuration VSF voltage Figure 11. Watchdog functionality :60UHVHWIURPDQ\VWDWH :'B/2&.287 :'B:'5 :'B(55B&17 :'B(55B7+B:( PV$1' :'B7295 :'770!9:'B29(55,'($1' 63,:'B7(67 :'B/2&.287 PV :'B:'5 :',1,7,$/ PV$1' :'B7295 :'B/2&.287 :'B(55B&17 :'5(6(7 :'B(5525 :'B/2&.287 :'B(55B&17 :'29(55,'( :'BUHIUHVK2. :'B:'5 :'B(55B7+B:( ,I :'B(55B&17:'B5(75<B7+ :'B/2&.287 :'581 :'B(5525 63,:'B7(67 :'BUHIUHVK2. :'7(67 *$3*36 Watchdog status is readable via SPI: 26/201 DocID025845 Rev 2 AN4437 Operative state $2C WD_STATE WD1_STATE bit [10:8] 4.1.1 000 = INIT 001 = RUN 010 = TEST 011 = RESET 100 = OVERRIDE WATCHDOG INITIAL As WSM is released (see Section 5.8: RESET), watchdog is in its initial state, WD1 INITIAL. In WD1 INITIAL state all arming signals are disabled to prevent deployment. As entered in WD1 INITIAL, the counter of a first 500 ms time window is started. In this phase, through WDTCR register, it is also defined the time window to service WD1. As the IC passes in DIAGNOSTIC state, WD1 parameters can't be modified any more. WD_RETRY_CONF register $28 has also to be programmed during this phase in order to set the WD1_RETRY_TH bit: the meaning of such a threshold is explained in Section 4.1.2: WD1 INITIAL - WD1 RESET. $2A WDTCR WD1_MODE, bit 14 WDTMIN bit [13:7] WDTDELTA bit [6:0] Config. in INIT only state 0 = fast WD1, 8 μs timer resol. (2 ms max value) 1 = slow WD1, 64 μs timer resol. (16.3 ms max value) WD1 min time window. In according to WD1_MODE, $32 = 400 μs in fast mode. Update by WSM_RESET or dedicated SPI write WD1 delta value (WDTMAX=WDTMIN+MDTDELTA), in according to WD1_MODE, $19 = 200 μs in fast mode Update by WSM_RESET or dedicated SPI write $28 WD_RETRY_CONF Config. in INIT only state WD1_RETRY_TH bit [2:0] WD1 ERR_CNT threshold before setting definitively WD1_LOCKOUT bit. Once the ASIC leaves the WD1INITIAL state, the register $28 cannot be anymore written (internal signal WD1_ERR_TH_WE is no more asserted and register is locked for writing access). The watchdog block can remain indefinitely in INITIAL state, without any watchdog service, in case WD1_TOVR is set via SPI. In this case, RESET toggling (1ms RESET active each 500ms) is disabled allowing some very initial operations (i.e. microcontroller FW flash) DocID025845 Rev 2 27/201 200 Operative state AN4437 Figure 12. WD1 INITIAL PV$1' :'B7295 :',1,7,$/ *$3*36 $01 SYS_CFG Config. in INIT only state WD1_TOVR, bit 0 Note: 0 = timeout is active 1 = timeout is disabled Disabling initial RESET toggling does not depend on the state of WDT/TM pin: SPI command is effective even if WDT/TM is grounded. To pass to another WD1 state, from WD1 INITIAL, there are the following possibilities: 4.1.2 WD1 INITIAL - WD1 RESET Figure 13. WD1 INITIAL - WD1 RESET :60UHVHWIURPDQ\VWDWH :'B/2&.287 :'B:'5 :'B(55B&17 :'B(55B7+B:( PV :'B:'5 :',1,7,$/ PV$1' :'B7295 :'B/2&.287 :'B(55B&17 :'5(6(7 *$3*36 If neither WD1_TOVR is set in the first 500 ms nor WDOG service occurs, WD1_LOCKOUT bit is set and an error counter, WD1_ERR_CNT, is incremented. Then WATCHDOG block moves in reset, WD1 RESET. WD1_ERR_CNT is readable via SPI: 28/201 DocID025845 Rev 2 AN4437 Operative state $2C WD_STATE WD1_ERR_CNT bit [3:0] Range 0:7 When WD1_LOCKOUT is set, all arming signals are disabled and deployment is inhibited. WD1_LOCKOUT is readable on SPI: $00 FLTSR WD1_LO, bit 7 4.1.3 0 = WD1_LOCKOUT is inactive 1 = WD1_LOCKOUT is active WD1 INITIAL - WD1 OVERRIDE Figure 14. WD1 INITIAL vs. WD1 OVERRIDE :'770!9:'B29(55,'($1' 63,:'B7(67 :'B/2&.287 :',1,7,$/ :'29(55,'( *$3*36 The watchdog transition from WD1_INITIAL state to WD1_OVERRIDE state corresponds to the transition from INIT to DIAGNOSTIC mode of the IC, see Figure 10. In order to enter this state, the pin WDT/TM must be biased to the voltage VWD_OVERRIDE and a proper SPI frame must be sent, accessing to the register $35 WD_TEST Config. in INIT, DIAG, SAFING state Bit [15:8] $3C to enter in WD_TEST VWD_OVERRIDE = 10 V ÷ 14 V DocID025845 Rev 2 29/201 200 Operative state 4.1.4 AN4437 WD1 INITIAL - WD1 RUN When the watchdog routine is correctly serviced, the watchdog block enters in RUN MODE (Figure 15). Figure 15. WD1 INITIAL vs. WD1 RUN vs. WD1 RESET :',1,7,$/ :'BUHIUHVK2. :'B:'5 :'B(55B7+B:( ,I :'B(55B&17:'B5(75<B7+ :'B/2&.287 :'5(6(7 :'B(5525 :'B/2&.287 :'B(55B&17 :'581 *$3*36 In the transition WD1_INITIAL state to WD1_RUN, WD1_ERR_CNT holds its value. If WD1_ERR_CNT has reached its threshold, WD1_RETRY_TH, WD1_LOCKOUT bit remains set; lockout is automatically removed otherwise. The number of allowed error cycle before permanently asserting the lockout is defined via SPI into the WD1_RETRY_TH. $28 WD_RETRY_CONF Config. in INIT WD1_RETRY_TH bit [2:0] WD1 ERR_CNT threshold before setting definitively WD1_LOCKOUT bit. The watchdog transition from WD1_INITIAL state to WD1_RUN state corresponds to the transition from INIT to DIAGNOSTIC mode of the IC, see Figure 10. Watchdog service is defined into register WD1T: $2B WD1T WD1CTL, bit[1:0] Config. in INIT, DIAG, SAFING, SCRAP, ARMING state 00 OR 11 NOP 01 = code A 10 = code B Correct watchdog service is controlled through a programmable time resolution counter, WD1_TIMER, whose parameters are defined in WDTCR register $2A in INIT state, (see Section 4.1.1: WATCHDOG INITIAL). 30/201 $2B WD1T Config. in INIT, DIAG, SAFING, SCRAP, ARMING state WD1_TIMER, bit[15:8] 8 bit wd counter DocID025845 Rev 2 AN4437 Operative state The counter WD1_TIMER, is reset every time a valid WD1CTL (watchdog service) is received. If WD1CTL are serviced too early or too late with respect to the time window, the watchdog error counter, WD1_ERR_CNT, is incremented. WD1_LOCKOUT is set and watchdog status passes in WD1 RESET state, (see Section 4.1.2: WD1 INITIAL - WD1 RESET) for the management. RESET pin is asserted with twdrst time: 0.9ms < twdrst <1.1ms Watchdog error, WD1 WDR, is readable via SPI: $00 FLTSR WD1 WDR, bit5 0: WD1_WDR signal = 0, WD1 correctly serviced 1: WD1_WDR signal = 1 being WD1 not correctly serviced In the follow Figure 16 is sketched the WD1 service. :'&7/ % :'&7/ % :'&7/ $ :'&7/ % :'&7/ $ :'&7/ $ Figure 16. WATCHDOG service :'&7/ $ :'7'(/7$ :'70,1 :' FRXQWHU $Q\:' UHIUHVKLQWKLV SHULRG GHWHUPLQH :'(5525 :'VHUYLFHGLQ WKHFRUUHFWWLPZ ZLQGRZUHIUHVKRI :'FRXQWHU $Q\:'UHIUHVKLQ WKLVSHULRG GHWHUPLQH:' UHIUHVK :'VHUYLFHGLQ WKHFRUUHFWWLPZ ZLQGRZUHIUHVKRI :'FRXQWHU $Q\:' UHIUHVKLQWKLV SHULRG GHWHUPLQH :'(5525 *$3*36 If more than one WD1 with the same key value is received (for example A instead of B, see Figure 16), the WD1 counter is not refreshed until the correct key value is received in the defined time window (WDTMIN, WDTDELTA) and no error signals are asserted. If more than one WD1 with the same key value (….A A A instead of …A and than B) is received no error signals are asserted even if the WD1 refresh command arrived before the counter has reached WDTMIN programmed value. DocID025845 Rev 2 31/201 200 Operative state 4.1.5 AN4437 WD1 RUN - WD1 TEST From WD1 RUN, through a SPI command, WD1 passes in WD1 TEST: $35 WD_TEST Config. in INIT, DIAG, SAFING state bit [15:8] $3C to enter in WD_TEST This state generates a WD1_ERROR, without asserting WD1_LOCKOUT=1. Figure 17. WD1 RESET - WD1 TEST :'581 63,:'B7(67 :'BUHIUHVK2. :'7(67 *$3*36 This is used to test the WD refresh. Typically it is implemented once per power up, even if there are no restrictions to accede to this mode in other moments. In this state, deployments are not enabled. Servicing WD1, watchdog turns back into WD1 RUN. 4.2 Diagnostic Once WD1 is in WD1 RUN state or WD1 OVERRIDE state, the IC passes in DIAGNOSTIC state, see Figure 10. The state in which the IC is, is readable via SPI: $04 SYS_STATE OPER_CTL_STATE bit [10:8] 001 = IC in DIAG state In DIAGNOSTIC state, the remaining IC configuration is allowed: Safing records; Deployment masks. 32/201 DocID025845 Rev 2 AN4437 Operative state In DIAGNOSTIC state, several tests of the device are allowed: HS LS switch tests of the squib drivers (ignored out of this phase); HS safing FET (ignored out of this phase); Arming output to check for non stuck-at conditions on the pin and for configured firing time. Note: ARM output and VSF test are mutually exclusive. Diagnostic foresees two different modes, high level and low level diagnostic. In high level diagnostic, set-up of each requested test is managed by the IC itself. In low level diagnostic, set-up of each requested test is managed by the external logic (microcontroller). The selection between high and low level diagnostic is done writing the appropriate value of DIAG_LEVEL (bit 15) $38 LPDIAGREQ register: $38 LPDIAGREQ DIAG_LEVEL, bit 15 Config. in DIAG, SAFING, SCRAP, ARMING state 0 = low level mode 1 = high level mode Once in DIAGNOSTIC state there is the possibility to pass in SAFING state or in SCRAP state, through dedicated commands. 4.3 SAFING To pass in SAFING from DIAG state it is necessary a dedicated SPI frame: $31 SAFING_STATE bit [15:0] Config. in DIAG state only $ACAC to enter in SAFING state The state in which the IC is, is readable via SPI: $04 SYS_STATE OPER_CTL_STATE bit [10:8] 010 = IC in SAFING state Logic performs safing function through safing engine management. Once in SAFING state, the IC returns to INITIALIZATION state only through a SSM_RESET. DocID025845 Rev 2 33/201 200 Operative state 4.4 AN4437 SCRAP To pass in SCRAP from DIAG state it is necessary a dedicated SPI frame: $30 SCRAP_STATE Config. in DIAG state only bit [15:0] $3535 to enter in SCRAP state The state in which the IC is, is readable via SPI: $04 SYS_STATE OPER_CTL_STATE bit [10:8] 011 = IC in SCRAP state Once in SCRAP state, the IC returns to INITIALIZATION state only through a SSM_RESET. In SCRAP state the microcontroller drives the transition to ARMING state and monitors Remote Sensor SPI interface (L9678-S). Safing logic is disabled. 4.5 ARMING This phase is the last enabling for the deployment. Special care has to be taken to control the entry into and exit from ARMING state. The mechanism is managed through ACL (Additional Communication Line). In ARMING state the arming output is asserted. Exit from this state occurs when a timeout happens without a correct ACL signal or SSM_RESET is asserted. 34/201 DocID025845 Rev 2 AN4437 5 Voltage regulators Voltage regulators 2 internal linear voltage regulators: 3V3INT for internal analog blocks CVDD for internal digital blocks. It requires an external filter capacitor (100 nF) on pin CVDD. 1 switching regulator, ERBOOST 23 V or 3 3V programmable via SPI 1 linear regulator VDD5 5 V 1 linear regulator VDD3V3 3.3 V 1 optional linear regulator VSUP 7 V (L9678-S) 1 linear regulator VSF 20 V, 25 V programmable via SPI 5.1 Internal voltage regulators In SLEEP MODE, the two internal regulators, 3V3INT and CVDD, are switched on, so that the device is ready for the full activation. The other voltage regulators are enabled in ACTIVE MODE. Requirement: VIN>VINGOOD1max = 5.5 V 5.2 ERBOOST Features Boost enable via SPI (default active) Boost works at 1.875 MHz, 2.13 MHz, 2 MHz, selectable via SPI. ERBOOST is 23 V as default value and it is configurable, via SPI, at 33 V. SPI configuration: $02 SYS_CTL ER_BST_V, bit 9 ER_BST_EN, bit 6 $2D CLK_CONF ERBST_SEL, bit [1,0] Config. in INIT, DIAG, SAFING, SCRAP, ARMING state 0 = 23V selected (22.6v÷25V) 1 = 33V selected (31.65V÷35V) 0 = ER_BOOST OFF 1 = ER_BOOST ON - default Config. in INIT state only 00 = 1.88Mhz 01 = 2.13Mhz 10 = 11 = 2Mhz DocID025845 Rev 2 35/201 200 Voltage regulators AN4437 Activation Requirement: VINGOOD1max = 5.5 V ≤ VIN ≤ 18 V IC in ACTIVE mode ERBOOST pin follows battery until POR is released. As POR is released, BOOST runs being as default active, and ERBOOST voltage increases up to 23 V (default) or 33 V, if selected, (see Section 3.1: Power up sequence). Normal function ERBOOST supplies VSF safing regulator, the GPO drivers and the internal current generator "ER charge" 30 mA typ. ER charge then charges the external reserve capacitor on VER pin. Figure 18. ERBOOST functionality 32:(52))B02'( 256/((3B02'( (5%2267 SRZHUPRGHFRQWURO (5%672)) 'HIDXOW6<6B&7/(5B%67B(1 DW325 $FWLYHBPRGH $1' 9%$7021!9%*22' $1' 9,1!9,1*22' $1' 6<6B&7/(5 B%67 B(1 $1' *1'%2267BORVV $1' (5%67 B27 $1' (5%67B',6$%/( 63,B6<6B&7/(5B%67B(1 $1' (5%67 B27 >$FWLYHBPRGH 25 (5%6767%< 9%$70219%%$' $1' (5BVWDWH 25 6<6B&)*.((3B(5%67B21 @ 25 9,19,1%$' 63,B)/7655($' 25 $1' 6<6&7/(5B%67B(1 (5%67 B27 25 *1'%2267BORVV 25 (5%67B',6$%/( (5%6721 (5%6727 (5%67 B27 '!0'03 Diagnostic Diagnostic read out via SPI: ERBOOST status (ON or OFF) OVER/UNDERVOLTAGE $05 POWER STATE ER_BST_NOK, bit 12 ER_BST_ON, bit8 1 = V_ERBOOST<ERBOOST_OK 0 = V_ERBOOST>ERBOOST_OK 1 = ERBOOST ON 0 = ERBOOST OFF or (OVERTEMPERATURE or STANDBY) ERBOOST_OK = 18 V ÷ 22 V if ERBOOST = 23 V ERBOOST_OK = 26 V ÷ 30 V if ERBOOST = 33 V 36/201 DocID025845 Rev 2 AN4437 Voltage regulators Protection Short to battery determines an over-temperature event (readable via SPI) that switches off the regulator. Overtemperature $00 FLTSR ER_BST_OT, bit 17 0 = NO FAULT 1 = FAULT The over-temperature event is latched in the register until it is read through the SPI. To switch on again ERBOOST, it is necessary to enable again ERBOOST via SPI: $02 SYS_CTL Config. in INIT, DIAG, SAFING, SCRAP, ARMING state ER_BST_EN, bit 6 0 = ER_BOOST OFF 1 = ER_BOOST ON Ground loss determines the regulator's switch off. As soon as ground connection is restored, the regulator restarts automatically, without the ‘SWITCH ON’ SPI command. After an under/over voltage detection, as soon as voltage turns to its correct value, the regulator restarts automatically, without the ‘SWITCH ON’ SPI command. Threshold to deactivate ERBOOST: ERBST_DISABLETH = VIN-ERBOOST 1.6 V < ERBST_DISABLETH < 2.5 V Threshold to activate the ER Boost CLAMP: CLAMP_ENTH = (ERBSTSW - ERBOOST) 1.6 V < CLAMP_ENTH < 2.5 V Figure 19. ERBOOST protection 9,1 &/$03B(17+ (5%67 'ULYHU &RQWURO (5%67B',6$%/( 7+ HQDEOH (5%2267 (5%676: &RPS &/$03 %67*1' *$3*36 DocID025845 Rev 2 37/201 200 Voltage regulators AN4437 Deactivation ERBOOST can be disabled via SPI: $02 SYS_CTL ER_BST_EN, bit 6 Config. in INIT, DIAG, SAFING, SCRAP, ARMING state 0 = ER_BOOST OFF 1 = ER_BOOST ON In case of low or lost battery, the IC passes in PASSIVE MODE / ER state, the regulator can be switched off or not, depending on KEEP_ERBST_ON bit, SYS_CFG register: 5.3 $01 SYS_CFG Config. in INIT KEEP_ERBST_ON bit 12 0 = ERBOOST disabled in ER state 1 = ERBOOST not disabled in ER state ER CHARGE - ER SWITCH ER CHARGE Features IER_charge 20 mA ÷ 40 mA RDS(on) max = 20 Ω Activation Requirement: VINGOOD1max = 5.5 V ≤ VIN ≤ 35 V ERBOOST ≤ 8 V IC in ACTIVE mode SPI command: $02 SYS_CTL ER_CUR_EN, bit 7 38/201 Config. in INIT, DIAG, SAFING, SCRAP, ARMING state 0 = ER current source OFF requested 1 = ER current source ON requested DocID025845 Rev 2 AN4437 Voltage regulators Normal function ER CHARGE charges the external reserve capacitor connected to VER pin. Figure 20. ER CAP functionality 660B5HVHW (5&$3FKDUJHFRQWURO 'HIDXOW6<6B&7/(5B&85B(1 DW 660B5(6(7 (5BFKDUJHB21 $FWLYHBPRGH $1' 6<6B&7/(5B&85B(1 $FWLYHBPRGH 25 6<6B&7/(5B&85B(1 (5BFKDUJHB21 '!0'03 Note: ER CHARGE is able to deliver 20 mA (worse case) to charge the external capacitor. Any connections to VER pin determines an additive contribution in terms of current consumption. Due to the max current limitation of ER CHARGE block, each additive load on the pin lowers the current inside the external reserve capacitor increasing the time needed to fully charge it. For example, connecting VRESDIAG to VER, during diagnostic or at the DCS switch on, the current required by VRESDIAG is higher than 20mA (the capacitor provides the extra current). Diagnostic ER charge status is readable on SPI: $05 POWER STATE ER_CHRG_ON, bit 7 0 = ER charge ON 1 = ER charge OFF Deactivation Out of ACTIVE mode ER charge is switched off to decouple ERBOOST pin from VER DocID025845 Rev 2 39/201 200 Voltage regulators AN4437 ER SWITCH Features RDS(on) = 0.5 Ω ÷ 3 Ω current limitation at his activation (300 mA min / 500 mA max) Activation Requirement: VINGOOD1max = 5.5 V ≤ VIN ≤ 35 V IC in PASSIVE mode. Normal function When ER switch is on, VIN is supplied through ER switch by the external reserve capacitor. The energy stored in the external reserve capacitor guarantees the energy supply for the device until POR occurs, including the deployment (if required) in case of battery low or lost too. ER switch implements a current limitation (300mA:500mA) to avoid in-rush current as ER switch is enabled or in case of a short to ground. Figure 21. ER SWITCH functionality 77LPHRXW (56ZLWFK 325 ³'HSOR\PHQWLQSURJUHVV´ (5BVZLWFKB67%< 6WDUW7PV (5BVZLWFKB2)) ³'HSOR\PHQWLQSURJUHVV´ 3DVVLYHBPRGH 25 (5B6:B29 3DVVLYHBPRGH $1' (5B6:B29 (5B6:,7&+B76' $1' ³GHSOR\PHQWQRWLQ SURJUHVV´ (5B6:,7&+B76' (5B6:,7&+B76' (5BVZLWFKB2))B27 (5BVZLWFKB21 (5B6:,7&+B76' $1' ³GHSOR\PHQWQRWLQSURJUHVV´ (5B6:B29 LI9,19(59 *$3*36 40/201 DocID025845 Rev 2 AN4437 Voltage regulators Protection Dedicated thermal sensor, active when no deploy is running and monitored through ER_SW_TSD comparator. In thermal shutdown, with no deployment running, ER_SWITCH is turned OFF so the energy taken from the external reserve capacitor is not available. In this condition the regulators are not any more supplied and POR occurs. Comparator thresholds are: 150°C < TJSD_ERSW < 190°C 5°C < THYS_TSDERSW <15°C ER switch status is readable on SPI: $05 POWER STATE ER_SW_ON, bit 4 0 = ER SWITCH OFF 1 = ER SWITCH ON To avoid continuously on and off cycling, there is a timeout T1, 1ms typ. ER switch is protected against reverse biasing to avoid back-feeding of battery to the external reserve capacitor. Deactivation It is deactivated when the device exits from PASSIVE mode. 5.4 VDD5 linear regulator Features 5 V linear regulator, slope controlled, derived directly from battery line through an external PNP (hFE min 50). VDD5 output voltage: 4.85 V ÷ 5.15 V VDD5 load current 0.5 mA ÷ 200 mA VDD5 stability requires an external small capacitor 3 μF ÷ 31 μF. Current limitation is guaranteed controlling the output current on BVDD5 pin. Activation Requirement: VINGOOD1max = 5.5 V ≤ VIN ≤ 35 V It starts in ACTIVE mode and continues to work in PASSIVE mode too, being supplied through ER switch by the external reserve capacitor. As the regulator starts running, the under-voltage that occurs before the regulator has reached its correct value, it is not considered a fault (under-voltage fault) in the first 3ms after the regulator is switched on. DocID025845 Rev 2 41/201 200 Voltage regulators AN4437 Normal function VDD5 is used to supply eventual 5 V compatible devices on board. VDDQ pin defines the voltage level on I/O pin: if VDDQ is connected to VDD5 it means that digital I/O pins 5V are compliant. if VDDQ is connected to VDD3V3 it means that digital I/O pins 3.3V are compliant. Figure 22. VDD5 functionality 9'' SRZHUPRGHFRQWURO 32:(52))B02'( 256/((3B02'( 9''B2)) &OHDU9''B29 7WLPHRXW $&7,9(B02'(25 3$66,9(B02'( 9''BUDPSXS 9''B896' $1'7WLPHRXW 25 9''B29 6WDUW7PV 9''B896'PDVNLQJ 9'' 6+87'2:1 6WDUW7PV /DWFK9''B29 9''B89/ $1' 7WLPHRXW 9''B21 9''B89/ 25 9''B29 25 9''9B29 '!0'03 VDD5UVSD = VDD5UVL = 1.8 V ÷ 2.2 V 42/201 DocID025845 Rev 2 AN4437 Voltage regulators Diagnostic: OVERVOLTAGE UNDERVOLTAGE UNDERVOLTAGE LOW LEVEL VDD5 state active VDD5_ACT VDD5_OV = 5.2V ÷ 5.5V, latched VDD5_UV = 4.5V ÷ 4.8V VDD5_UVL = 1.8V ÷ 2.2V Diagnostic read out through SPI: $05 POWER STATE VDD5_UV, bit 11 0 = VDD5>VDD5_UV 1 = VDD5>VDD5_UV VDD5_OV, bit 10 0 = VDD5<VDD5_OV 1 = VDD5>VDD5_OV VDD5_ACT, bit 3 0 = VDD5 in OFF or SHUTDOWN state 1 = VDD5 in RAMPUP or ON VDD5_ACT bit is used by the microcontroller to monitor the VDD5 status, ON or OFF. Protection Current limitation is guaranteed by means of controlling output current on BVDD5 pin (4 mA to 10 mA). Deactivation Deactivation is determined by all the conditions that bring back the IC in SLEEP mode. In case of VDD5_UV, or VDD5_OV or VDD3V3_OV the regulator is switched off. 5.5 VDD3V3 linear regulator Features 3.3 V full integrated linear regulator slope controlled derived from VDD5. VDD3V3: 3.2 V ÷ 3.4 V VDD3V3 load current 0.5 mA ÷ 125 mA VDD3V3 load current limitation: 150 mA min VDD3V3 stability requires an external small capacitor 3 μF ÷ 31 μF. Activation Requirement: VDD5min = 4.85 V ≤ VDD5. It starts in ACTIVE mode and continues to work in PASSIVE mode too, being supplied by VDD5 and VDD5 is supplied, via ER switch, by the external reserve capacitor. DocID025845 Rev 2 43/201 200 Voltage regulators AN4437 Normal function VDD3V3 is used to supply 3.3 V devices, as for example, the microcontroller if it has been chosen one whose I/O pins are 3.3 V compatible. VDDQ pin defines the voltage level on I/O pin: if VDDQ is connected to VDD5 it means that digital I/O pins 5 V are compliant. if VDDQ is connected to VDD3V3 it means that digital I/O pins 3.3 V are compliant. Figure 23. VDD3V3 functionality 6/((3B02'( 25 32:(52))B02'( 9''9 2)) 9''9 SRZHUPRGHFRQWURO 7WLPHRXW ,Q9''B21VWDWH 9''9 6+87'2:1 6WDUW7PV 1RWLQ9''B21VWDWH 9''9B21 '!0'03 Diagnostic OVERVOLTAGE UNDERVOLTAGE VDD3V3 active state VDD3V3OV = 3.43V ÷ 3.6V VDD3V3UV = 3.0V ÷ 3.17V Diagnostic read out through SPI: $05 POWER STATE 44/201 VDD3V3_UV, bit 14 0 = VDD3V3>VDD3V3_UV 1 = VDD3V3>VDD3V3_UV VDD3V3_OV, bit 13 0 = VDD3V3<VDD3V3_OV 1 = VDD3V3>VDD3V3_OV VDD3V3_ACT, bit 1 0 = VDD3V3 in OFF or SHUTDOWN state 1 = VDD3V3 is ON DocID025845 Rev 2 AN4437 Voltage regulators VDD3V3_ACT bit is used by the microcontroller to monitor the VDD3V3 status, ON or OFF. Protection Current limitation of VDD3V3 is IO_LIM = 150 mA max. Note: If the VDDQ pin (digital outputs supply) is connected to the VDD3V3 and any of the digital I/O pins are connected to 5V logic, there is no internal blocking diode to prevent 3.3V supply back feeding. Deactivation Deactivation is determined by all the conditions that bring back the IC in SLEEP mode. It is switched off in case VDD5 is NOT IN on STATE. 5.6 VSUP Linear regulator (available for L9678S version) Features 6.8 V linear regulator slope controlled, derived directly from battery line through an external PNP (hFE min 50) VSUP output voltage: 6.5 V ÷ 7.1 V VSUP load current 0.5 mA ÷ 200 mA VSUP stability requires an external small capacitor 3 μF ÷ 30 μF. Current limitation is guaranteed controlling the output current on BVSUP pin. As the regulator starts running, the under-voltage that occurs before the regulator has reached its correct value, it is not considered a fault (under-voltage fault) in the first 3ms after the regulator is switched on. Activation Requirement: VINGOOD2max = 6.8 V ≤ VIN ≤ 35 V IC in ACTIVE or PASSIVE mode; in PASSIVE mode VSUP is supplied through ER switch by the external reserve capacitor. SPI command: $02 SYS_CTL VSPU_EN, bit 5 Config. in INIT, DIAG, SAFING, SCRAP, ARMING state 0 = VSUP commanded OFF 1 = VSUP commanded ON Normal function VSUP is used to supply 6.8 V devices as, for example, the PSI-5 sensor. In case of L9678 version, VSUP pin can be connected to GND. DocID025845 Rev 2 45/201 200 Voltage regulators AN4437 Figure 24. VSUP functionality 9683 SRZHUPRGHFRQWURO 32:(52))B02'( 256/((3B02'( 'HIDXOW6<6B&7/9683B(1 DW325 9683 2)) $&7,9(B02'(25 3$66,9(B02'( $1' 6<6B&7/9683B(1 9683 UDPSXS 7WLPHRXW 6<6B&7/9683B(1 9683B89 $1'7WLPHRXW 6WDUW7PV 9683B89PDVNLQJ 9683 6+87'2:1 6WDUW7 PV 9683B89 $1' 7WLPHRXW 9683B89 9683B21 '!0'03 Diagnostic $05 POWER STATE VSUP_NOK, bit 9 0: VSUP is in its correct range VTHLVSUP<VSUP<VTHHVSUP 1: VSUP is out of its correct range (VSUP<VTHLVSUP) OR (VSUP> VTHHVSUP) VSUP_ACT, bit 2 0 = VSUP in OFF or SHUTDOWN state 1 = VSUP in RAMPUP or ON VTHHVSUP = 8 V max VTHLVSUP = 6.5 V min VSUP_ACT bit is used by the microcontroller to monitor the VSUP status, ON or OFF. Protection Current limitation is guaranteed by means of controlling output current on BVSUP pin (4 mA to 10 mA). Deactivation Through SPI disable command. In case of VSUP under-voltage condition that lasts for at least Tvsupuvfilt (27 μs ÷ 33 μs) after 5 ms, VSUP is switched off. 46/201 DocID025845 Rev 2 AN4437 5.7 Voltage regulators VSF linear regulator Features full integrated linear regulator derived from ERBOOST VSF is 20 V as default value and it is configurable at 25 V via SPI $01 SYS_CFG Config. in INIT state VSF_V, bit 2 0 = 20 V selected (18 V ÷ 20 V) 1 = 25 V selected (23 V ÷ 27 V) VSF stability requires an external small capacitor 2.9 μF ÷ 14 μF. Turn on time = 100 μs Activation Requirement: VINGOOD1max = 5.5 V ≤ VIN ≤ 35 V VSF + 2 V ≤ ERBOOST IC in ACTIVE or PASSIVE mode Activation of this regulator is so conditioned: Figure 25. VSF enable !2-?%. 3!&%3%, !2-).4 !2-).4 &%.( &%., 3!&).'34!4% $)!'34!4% 63&?%. $34%3463& !2-).'34!4% '!0'03 SAFESEL configures (via SPI) the safing logic, internal or external: $01 SYS_CFG SAFESEL, bit 3 Config. in INIT state 0 = internal safing engine 1 = external safing engine - default If the IC is in DIAGNOSTIC state, VSF_EN is linked to the request to activate VSF: DocID025845 Rev 2 47/201 200 Voltage regulators AN4437 $36 SYSDIAGREQ Config. in DIAG state DSTEST, bit [3÷0] 0110 = VSF regulator active Normal function VSF is used to supply an external N channel safing FET. Diagnostic $05 POWER STATE VSF_ACT, bit 0 0: VSF_EN = 0 1: VSF_EN = 1 Protection Output load current limitation IO_LIM = 7 mA ÷ 13 mA Output voltage drop-out = (ERBOOST-VSF) = 2 V max Deactivation See picture above: any condition that does not satisfy the condition reported. 5.8 RESET RESET is active low. Figure 26. Regulators diagnostic errors 9%*5 5HIHUHQFH 9,179 5HIHUHQFHIRU &RQWUROOLQJDOOVXSSOLHV 9%*0 0RQLWRU 9%*B5($'< 9,179 0RQLWRU 9'' 9''9 9'' *1'68%[ 9'' 0RQLWRU 9''9 0RQLWRU 9'' 0RQLWRU *1'$ *1'$ 0RQLWRU *1'' *1'' 0RQLWRU 9,17B29 9,17B89 9''B29 9''B89 9''9B29 9''9B89 9''B29 9''B89 95(*B(55 9''9B(55 9''B(55 *1'$B(55 *1'B(55 48/201 *1''B(55 '!0'03 DocID025845 Rev 2 AN4437 Voltage regulators List of the internal reset signals: VBG_READY problem on band gap VREG_ERR problem on internal voltage regulators VDD3V3_ERR problem on VDD3V3 voltage regulator VDD5_ERR problem on VDD5 voltage regulator GNDA_ERR GNDD_ERR GND_ERR GNDA shift greater than 300mV respect to GND SUB GNDD shift greater than 300mV respect to GND SUB GNDA_ERR or GNDD_ERR These signals are grouped into 3 internal bit: Figure 27. RESET organization *1'B(55 &/.)5(55 325 9%*B5($'< 95(*B(55 9''B(55 :60B5HVHW 6<6B&)*',6B9''B(55 9''9B(55 PV VWUHWFK 660B5HVHW :'5(6(7VWDWH 5(6(7SLQ '!0'03 POR (POR bit) takes into account problems on the internal voltage regulators (3V3INT and CVDD), on GND connections, and problems in the clock frequency. WSM_Reset (WSMRST bit) takes into account the same problem of POR and problems on the external voltage regulators, VDD5 or VDD3V3. Problems on VDD5 can be ignored depending on DIS_VDD5_ERR bit configuration: $01 SYS_CFG DIS_VDD5_ERR, bit 14 Config. in INIT state 0 = VDD5 OV/UV generates reset 1 = VDD5 OV/UV doesn’t generate reset DocID025845 Rev 2 49/201 200 Voltage regulators AN4437 SSM_Reset (SSMRST bit) takes into account the same problem of WSM_Reset and problems on the watchdog service. $00 FLTSR WSMRST, bit 3 0 = WSM RESET has not occurred 1 = WSM RESET has occurred SSMRST, bit 2 0 = SSM RESET has not occurred 1 = SSM RESET has occurred POR, bit 0 0 = POR RESET has not occurred 1 = POR RESET has occurred RESET pin (not SSM_Reset) summarizes all the above mentioned cases. 50/201 DocID025845 Rev 2 SPI AN4437 6 For configuration, control and read out status of the IC. Table 3. Global SPI register map GID RID / WID 0 Description Operating State(1) DocID025845 Rev 2 Name 0 0 0 0 0 0 0 $00 R FLTSR 0 0 0 0 0 0 0 1 $01 R/W SYS_CFG Power supply configuration (regulators' output voltage selection, enable internal safing engine) X 0 0 0 0 0 0 1 0 $02 R/W SYS_CTL Register to control the power management (enable for tests in diag state, enable for power mode control bit) X X X X X 0 0 0 0 0 0 1 1 $03 W SPI_SLEEP Sleep Mode command X X X X X 0 0 0 0 0 1 0 0 $04 R SYS_STATE Read register to report in which state the power control state machine is and also in which Operating state we are. 0 0 0 0 0 1 0 1 $05 R POWER_STATE 0 0 0 0 0 1 1 0 $06 R/W DCR_0 X X X X 0 0 0 0 0 1 1 1 $07 R/W DCR_1 X X X X 0 0 0 0 1 0 0 0 $08 R/W DCR_2 X X X X 0 0 0 0 1 0 0 1 $09 R/W DCR_3 X X X X 0 0 0 0 1 0 1 0 $0A 0 0 0 0 1 0 1 1 $0B 0 0 0 0 1 1 0 0 $0C 0 0 0 0 1 1 0 1 $0D 0 0 0 0 1 1 1 0 $0E 0 0 0 0 1 1 1 1 $0F 0 0 0 1 0 0 0 0 $10 0 0 0 1 0 0 0 1 $11 Init Diag Ssafing Scrap Arming Global fault status register Power state register (feedback on regulators' status and voltage thresholds) Deployment configuration register SPI 51/201 Hex R/W Hex R/W Name Description SPI 52/201 Table 3. Global SPI register map (continued) Operating State(1) DocID025845 Rev 2 GID RID / WID 0 0 0 1 0 0 1 0 $12 R/W DEPCOM 0 0 0 1 0 0 1 1 $13 R DSR_0 0 0 0 1 0 1 0 0 $14 R DSR_1 0 0 0 1 0 1 0 1 $15 R DSR_2 0 0 0 1 0 1 1 0 $16 R DSR_3 0 0 0 1 0 1 1 1 $17 0 0 0 1 1 0 0 0 $18 0 0 0 1 1 0 0 1 $19 0 0 0 1 1 0 1 0 $1A 0 0 0 1 1 0 1 1 $1B 0 0 0 1 1 1 0 0 $1C 0 0 0 1 1 1 0 1 $1D 0 0 0 1 1 1 1 0 $1E 0 0 0 1 1 1 1 1 $1F R DCMTS01 0 0 1 0 0 0 0 0 $20 R DCMTS23 0 0 1 0 0 0 0 1 $21 0 0 1 0 0 0 1 0 $22 0 0 1 0 0 0 1 1 $23 0 0 1 0 0 1 0 0 $24 0 0 1 0 0 1 0 1 $25 R/W SPIDEPEN 0 0 1 0 0 1 1 0 $26 R LP_GNDLOSS 0 0 1 0 0 1 1 1 $27 R VERSION_ID 0 0 1 0 1 0 0 0 $28 R/W WD_RETRY_CONF Watchdog Retry Configuration X 0 0 1 0 1 0 0 1 $29 0 0 1 0 1 0 1 0 $2A R/W WDTCR Watchdog timer configuration X 0 0 1 0 1 0 1 1 $2B R/W WD1T Watchdog key transmission & Test mode X Init Diag Ssafing Scrap Deployment command register Arming X X X X Deployment status register Deployment current monitor register Lock/Unlock command Loss of ground fault for squib loops Device version X X X AN4437 X GID RID / WID Hex R/W R Name Description WD_STATE Watchdog state CLK_CONF Clock Configuration Operating State(1) Init Diag Ssafing Scrap DocID025845 Rev 2 0 0 1 0 1 1 0 0 $2C 0 0 1 0 1 1 0 1 $2D R/W 0 0 1 0 1 1 1 0 $2E 0 0 1 0 1 1 1 1 $2F 0 0 1 1 0 0 0 0 $30 W SCRAP_STATE Scrap State command X 0 0 1 1 0 0 0 1 $31 W SAFING_STATE Safing State command X 0 0 1 1 0 0 1 0 $32 0 0 1 1 0 0 1 1 $33 0 0 1 1 0 1 0 0 $34 0 0 1 1 0 1 0 1 $35 W WD_TEST 0 0 1 1 0 1 1 0 $36 R/W SYSDIAGREQ Diagnostic command for system safing 0 0 1 1 0 1 1 1 $37 R LPDIAGSTAT Diagnostic results register for deployment loops 0 0 1 1 1 0 0 0 $38 R/W LPDIAGREQ Diagnostic configuration command for deployment loops 0 0 1 1 1 0 0 1 $39 R/W SWCTRL 0 0 1 1 1 0 1 0 $3A R/W 0 0 1 1 1 0 1 1 Watchdog first and second level test Arming AN4437 Table 3. Global SPI register map (continued) X X X X X X X X X DC sensor diagnostic configuration X X X X DIAGCTRL_A In WID is AtoD converter control register A. In RID is AtoD result A request. X X X X $3B R/W DIAGCTRL_B In WID is AtoD converter control register B. In RID is AtoD result B request. X X X X 0 0 1 1 1 1 0 0 $3C R/W DIAGCTRL_C In WID is AtoD converter control register C. In RID is AtoD result C request. X X X X 0 0 1 1 1 1 0 1 $3D R/W DIAGCTRL_D In WID is AtoD converter control register D. In RID is AtoD result D request. X X X X 0 0 1 1 1 1 1 0 $3E 0 0 1 1 1 1 1 1 $3F 0 1 0 0 0 0 0 0 $40 0 1 0 0 0 0 0 1 $41 SPI 53/201 X X GID RID / WID Hex R/W Name 0 1 0 0 0 0 1 0 $42 R/W GPOCR 0 1 0 0 0 0 1 1 $43 R/W 0 1 0 0 0 1 0 0 $44 0 1 0 0 0 1 0 1 $45 0 1 0 0 0 1 1 0 0 Description Operating State(1) Init Diag Ssafing Scrap Arming DocID025845 Rev 2 X X GPOCTRL0 General Purpose Output control register X X X X X R/W GPOCTRL1 General Purpose Output control register X X X X X $46 R GPOFLTSR General Purpose Output fault status register 1 0 0 0 1 1 1 $47 R ISOFLTSR ISO9141 fault status register 0 1 0 0 1 0 0 0 $48 0 1 0 0 1 0 0 1 $49 0 1 0 0 1 0 1 0 $4A R/W RSCR1 0 1 0 0 1 0 1 1 $4B R/W RSCR2 0 1 0 0 1 1 0 0 $4C 0 1 0 0 1 1 0 1 $4D 0 1 0 0 1 1 1 0 $4E R/W X X X 0 1 0 0 1 1 1 1 $4F 0 1 0 1 0 0 0 0 $50 R RSDR1 0 1 0 1 0 0 0 1 $51 R RSDR2 0 1 0 1 0 0 1 0 $52 0 1 0 1 0 0 1 1 $53 0 1 0 1 0 1 0 0 $54 0 1 0 1 0 1 0 1 $55 0 1 0 1 0 1 1 0 $56 0 1 0 1 0 1 1 1 $57 0 1 0 1 1 0 0 0 $58 0 1 0 1 1 0 0 1 $59 0 1 0 1 1 0 1 0 $5A 0 1 0 1 1 0 1 1 $5B RSCTRL PSI5 configuration register X X Remote sensor control register X Remote sensor data and fault flag registers SPI 54/201 General Purpose Output configuration AN4437 Table 3. Global SPI register map (continued) GID RID / WID Hex R/W Name Description Operating State(1) Init Diag Ssafing Scrap DocID025845 Rev 2 1 0 1 1 1 0 0 $5C 0 1 0 1 1 1 0 1 $5D 0 1 0 1 1 1 1 0 $5E 0 1 0 1 1 1 1 1 $5F 0 1 1 0 0 0 0 0 $60 0 1 1 0 0 0 0 1 $61 0 1 1 0 0 0 1 0 $62 0 1 1 0 0 0 1 1 $63 0 1 1 0 0 1 0 0 $64 0 1 1 0 0 1 0 1 $65 0 1 1 0 0 1 1 0 $66 0 1 1 0 0 1 1 1 $67 0 1 1 0 1 0 0 0 $68 0 1 1 0 1 0 0 1 $69 0 1 1 0 1 0 1 0 $6A 0 1 1 0 1 0 1 1 $6B 0 1 1 0 1 1 0 0 $6C 0 1 1 0 1 1 0 1 $6D 0 1 1 0 1 1 1 0 $6E R/W LOOP_MATRIX_ARM1 Assignment of ARM 1 pin to which LOOPS X 0 1 1 0 1 1 1 1 $6F LOOP_MATRIX_ARM2 Assignment of ARM 2 pin to which LOOPS X 0 1 1 1 0 0 0 0 $70 0 1 1 1 0 0 0 1 $71 0 1 1 1 0 0 1 0 $72 0 1 1 1 0 0 1 1 $73 R AEPSTS_ARM1 0 1 1 1 0 1 0 0 $74 R AEPSTS_ARM2 R/W SAF_ALGO_CONF R ARM_STATE R/W Safing Algorithm configuration register X Status of internal arming signals FENH, FENL, ARMx Arming pulse stretch timer value SPI 55/201 0 Arming AN4437 Table 3. Global SPI register map (continued) Hex R/W Name Description Operating State(1) DocID025845 Rev 2 GID RID / WID 0 1 1 1 0 1 0 1 $75 0 1 1 1 0 1 1 0 $76 0 1 1 1 0 1 1 1 $77 0 1 1 1 1 0 0 0 $78 0 1 1 1 1 0 0 1 $79 0 1 1 1 1 0 1 0 $7A 0 1 1 1 1 0 1 1 $7B 0 1 1 1 1 1 0 0 $7C 0 1 1 1 1 1 0 1 $7D 0 1 1 1 1 1 1 0 $7E 0 1 1 1 1 1 1 1 $7F R/W SAF_ENABLE 1 0 0 0 0 0 0 0 $80 R/W SAF_REQ_MASK_1 X 1 0 0 0 0 0 0 1 $81 R/W SAF_REQ_MASK_2 X 1 0 0 0 0 0 1 0 $82 R/W SAF_REQ_MASK_3 X 1 0 0 0 0 0 1 1 $83 R/W SAF_REQ_MASK_4 X 1 0 0 0 0 1 0 0 $84 1 0 0 0 0 1 0 1 $85 1 0 0 0 0 1 1 0 $86 1 0 0 0 0 1 1 1 $87 1 0 0 0 1 0 0 0 $88 1 0 0 0 1 0 0 1 $89 Safing record enable SPI 56/201 Table 3. Global SPI register map (continued) Init Diag Ssafing Scrap X X X Arming X Safing record request mask AN4437 Hex R/W Name Description Operating State(1) DocID025845 Rev 2 RID / WID 1 0 0 0 1 0 1 0 $8A 1 0 0 0 1 0 1 1 $8B 1 0 0 0 1 1 0 0 $8C 1 0 0 0 1 1 0 1 $8D 1 0 0 0 1 1 1 0 $8E 1 0 0 0 1 1 1 1 $8F 1 0 0 1 0 0 0 0 $90 1 0 0 1 0 0 0 1 $91 1 0 0 1 0 0 1 0 $92 1 0 0 1 0 0 1 1 $93 R/W SAF_REQ_TARGET_1 X 1 0 0 1 0 1 0 0 $94 R/W SAF_REQ_TARGET_2 X 1 0 0 1 0 1 0 1 $95 R/W SAF_REQ_TARGET_3 X 1 0 0 1 0 1 1 0 $96 R/W SAF_REQ_TARGET_4 X 1 0 0 1 0 1 1 1 $97 1 0 0 1 1 0 0 0 $98 1 0 0 1 1 0 0 1 $99 1 0 0 1 1 0 1 0 $9A 1 0 0 1 1 0 1 1 $9B 1 0 0 1 1 1 0 0 $9C 1 0 0 1 1 1 0 1 $9D 1 0 0 1 1 1 1 0 $9E 1 0 0 1 1 1 1 1 $9F 1 0 1 0 0 0 0 0 $A0 1 0 1 0 0 0 0 1 $A1 1 0 1 0 0 0 1 0 $A2 Init Diag Ssafing Scrap Arming Safing record request mask Safing record request target SPI 57/201 GID AN4437 Table 3. Global SPI register map (continued) Hex R/W Name Description SPI 58/201 Table 3. Global SPI register map (continued) Operating State(1) DocID025845 Rev 2 GID RID / WID 1 0 1 0 0 0 1 1 $A3 1 0 1 0 0 1 0 0 $A4 1 0 1 0 0 1 0 1 $A5 1 0 1 0 0 1 1 0 $A6 R/W SAF_RESP_MASK_1 X 1 0 1 0 0 1 1 1 $A7 R/W SAF_RESP_MASK_2 X 1 0 1 0 1 0 0 0 $A8 R/W SAF_RESP_MASK_3 X 1 0 1 0 1 0 0 1 $A9 R/W SAF_RESP_MASK_4 X 1 0 1 0 1 0 1 0 $AA 1 0 1 0 1 0 1 1 $AB 1 0 1 0 1 1 0 0 $AC 1 0 1 0 1 1 0 1 $AD 1 0 1 0 1 1 1 0 $AE 1 0 1 0 1 1 1 1 $AF 1 0 1 1 0 0 0 0 $B0 1 0 1 1 0 0 0 1 $B1 1 0 1 1 0 0 1 0 $B2 1 0 1 1 0 0 1 1 $B3 1 0 1 1 0 1 0 0 $B4 1 0 1 1 0 1 0 1 $B5 1 0 1 1 0 1 1 0 $B6 1 0 1 1 0 1 1 1 $B7 1 0 1 1 1 0 0 0 $B8 1 0 1 1 1 0 0 1 $B9 R/W SAF_RESP_TARGET_1 1 0 1 1 1 0 1 0 $BA R/W SAF_RESP_TARGET_2 1 0 1 1 1 0 1 1 $BB R/W SAF_RESP_TARGET_3 1 0 1 1 1 1 0 0 $BC R/W SAF_RESP_TARGET_4 Init Diag Ssafing Scrap Arming Safing record request target Safing record response mask X X X X AN4437 Safing record response target GID RID / WID Hex R/W Name Description Operating State(1) Init Diag Ssafing Scrap DocID025845 Rev 2 1 0 1 1 1 1 0 1 $BD 1 0 1 1 1 1 1 0 $BE 1 0 1 1 1 1 1 1 $BF 1 1 0 0 0 0 0 0 $C0 1 1 0 0 0 0 0 1 $C1 1 1 0 0 0 0 1 0 $C2 1 1 0 0 0 0 1 1 $C3 1 1 0 0 0 1 0 0 $C4 1 1 0 0 0 1 0 1 $C5 1 1 0 0 0 1 1 0 $C6 1 1 0 0 0 1 1 1 $C7 1 1 0 0 1 0 0 0 $C8 1 1 0 0 1 0 0 1 $C9 1 1 0 0 1 0 1 0 $CA 1 1 0 0 1 0 1 1 $CB 1 1 0 0 1 1 0 0 $CC R/W SAF_DATA_MASK_1 X 1 1 0 0 1 1 0 1 $CD R/W SAF_DATA_MASK_2 X 1 1 0 0 1 1 1 0 $CE R/W SAF_DATA_MASK_3 1 1 0 0 1 1 1 1 $CF R/W SAF_DATA_MASK_4 1 1 0 1 0 0 0 0 $D0 1 1 0 1 0 0 0 1 $D1 Arming AN4437 Table 3. Global SPI register map (continued) Safing record response target Safing record data mask X X SPI 59/201 GID RID / WID Hex R/W Name Description SPI 60/201 Table 3. Global SPI register map (continued) Operating State(1) Init Diag Ssafing Scrap DocID025845 Rev 2 1 1 0 1 0 0 1 0 $D2 1 1 0 1 0 0 1 1 $D3 1 1 0 1 0 1 0 0 $D4 1 1 0 1 0 1 0 1 $D5 1 1 0 1 0 1 1 0 $D6 1 1 0 1 0 1 1 1 $D7 1 1 0 1 1 0 0 0 $D8 1 1 0 1 1 0 0 1 $D9 1 1 0 1 1 0 1 0 $DA 1 1 0 1 1 0 1 1 $DB 1 1 0 1 1 1 0 0 $DC 1 1 0 1 1 1 0 1 $DD 1 1 0 1 1 1 1 0 $DE 1 1 0 1 1 1 1 1 $DF R/W SAF_THRESHOLD_1 X 1 1 1 0 0 0 0 0 $E0 R/W SAF_THRESHOLD_2 X 1 1 1 0 0 0 0 1 $E1 R/W SAF_THRESHOLD_3 X 1 1 1 0 0 0 1 0 $E2 R/W SAF_THRESHOLD_4 X 1 1 1 0 0 0 1 1 $E3 1 1 1 0 0 1 0 0 $E4 1 1 1 0 0 1 0 1 $E5 1 1 1 0 0 1 1 0 $E6 1 1 1 0 0 1 1 1 $E7 1 1 1 0 1 0 0 0 $E8 1 1 1 0 1 0 0 1 $E9 1 1 1 0 1 0 1 0 $EA Arming Safing record data mask Safing record threshold AN4437 GID RID / WID Hex R/W Name Description Operating State(1) Init Diag Ssafing Scrap DocID025845 Rev 2 1 1 1 0 1 0 1 1 $EB 1 1 1 0 1 1 0 0 $EC 1 1 1 0 1 1 0 1 $ED 1 1 1 0 1 1 1 0 $EE 1 1 1 0 1 1 1 1 $EF R/W SAF_CONTROL_1 X 1 1 1 1 0 0 0 0 $F0 R/W SAF_CONTROL_2 X 1 1 1 1 0 0 0 1 $F1 R/W SAF_CONTROL_3 X 1 1 1 1 0 0 1 0 $F2 R/W SAF_CONTROL_4 X 1 1 1 1 0 0 1 1 $F3 1 1 1 1 0 1 0 0 $F4 1 1 1 1 0 1 0 1 $F5 1 1 1 1 0 1 1 0 $F6 1 1 1 1 0 1 1 1 $F7 1 1 1 1 1 0 0 0 $F8 1 1 1 1 1 0 0 1 $F9 1 1 1 1 1 0 1 0 $FA 1 1 1 1 1 0 1 1 $FB 1 1 1 1 1 1 0 0 $FC 1 1 1 1 1 1 0 1 $FD 1 1 1 1 1 1 1 0 $FE 1 1 1 1 1 1 1 1 $FF Arming AN4437 Table 3. Global SPI register map (continued) Safing record threshold Safing record control R SAF_CC Safing record compare complete 1. A check mark indicates in which operating state a WRITE-command is valid. SPI 61/201 SPI AN4437 SPI_MOSI: for input register. MSB is the first bit received, LSB the last SPI_MISO: for output register. MSB is the first bit transmitted, LSB the last SPI_SCK: clock, slave input data latched on SPI_SCK rising edge and slave output data shifted on falling edge SPI_CS: chip select CS = H → SPI pins in tri-state CS = L → SPI communication enabled There are other two chip selects, SAF_CS0 and SAF_CS1. They are used for a specific communication between sensor interface and IC, see Section 4.3: SAFING. Figure 28. SPI signals 63,B&6 63,B6&/. 06%287 /6%287 '$7$ '21¶7 &$5( 63,B0,62 63,B026, '$7$ 06%,1 /6%,1 '!0'03 SPI is 32 bit, so organized: SPI_MOSI SPI_MISO 31 GID 30 29 28 15 14 13 12 27 26 25 RID[6:0] GSW[10:0] 11 10 9 SPI_MOSI SPI_MISO 24 23 22 21 8 7 6 WRITE[15:0] READ[15:0] 5 20 19 WID[6:0] RPAR 4 16 WPAR READ[19:16] 3 GID global ID, shared between RID and WID WID / RID register definition Write and Read WPAR / RPAR odd parity bit Write and Read, calculated on all the 32 bit GSW Global Status Word WRITE Data input (15:0) READ Data output (19:0) 18 17 2 1 0 MSB is the first bit transmitted from the master to the IC slave and LSB (MOSI signal) is the last. The same happens on MISO signal. 62/201 DocID025845 Rev 2 AN4437 SPI MISO BIT 31 30 29 28 27 26 25 24 23 22 21 MISO SPIFLT DEPOK RSFLT WDTDIS_S ERSTATE POWERFLT FLT CONVRDY2 CONVRDY1 ERR_WID ERR_RID Global Status Word bit organization: GSW BIT 10 9 8 7 6 5 4 3 2 1 0 Due to an SPI_MOSI, the correspondent SPI_MISO is available in the same slot of time of the SPI_MOSI (in frame). FAULT cases on SPI GSW SPIFLT, bit 31 (bit 10 of GSW) 0 = no fault 1 = fault SPI_FLT indicates: 1. number of SPI_SCK different from 32; 2. WPAR bit error in MOSI Any incorrect access to a register (write/read) is forbidden, but SPIFLT bit is not set. ERR_WID / ERR_RID If an SPI write command, with correct WID, is received but the IC is in a status where the writing operation into the addressed register is forbidden (see INIT, DIAG, SAFING, SCRAP, ARMING states), the command itself is discharged and ERR_WID in the next GSW is set. ERR_WID is not set when a read only register is addressed through WID. The command is ignored. GSW ERR_WID, bit 22 (bit 1 of GSW) 0 = no error 1 = error If an SPI command is referred, through a RID address, to an unused register, ERR_RID is set in the current GSW and the command is discharged. GSW ERR_RID, bit 21 (bit 1 of GSW) 0 = no error 1 = error DocID025845 Rev 2 63/201 200 SAFING 7 AN4437 SAFING Safing logic is based on On board sensors and/or remote sensors (PSI 5) ARM signal: two internal ARMiINT (i=1,2) or two external FENH, FENL Figure 29. Internal ARIMNG signals 6&/.B* 026,B* 0,62B* &6B* 6$)B&6 6$)B&6 63,'HFRGH 7KUHVKROG &RPSDUH 3XOVH 6WUHWFK 6$),1*67$7( ',$*67$7( $50,17 '67(67$50 '67(6738/6( &+['(3 $50,17 $50,1*67$7( *$3*36 ARM pin can be (in according to SAFESEL, bit3 $01 SYS_CFG) the output of the arming signal generated by the integrated safing engine or it can be the combination of FENH/FENL signals that come from external logic: Figure 30. ARMING organization :'B581 :'B/2&.287 660B5(6(7 $50B(1 :'B29(55,'( $50,17 6DILQJ (QJLQH $50,17 $50 )(1/ )(1+ 6$),1*67$7( 6$)(6(/ 64/201 *$3*36 DocID025845 Rev 2 AN4437 7.1 SAFING SPI sensor data decoding - Configuration IC is able to process data coming from both PSI5 remote sensors or on board sensor. Data processed can be used in order to engage the ARMING internal procedure. Following pins are involved in this process: SPI_CS (active low) is the standard chip select of SPI; SAF_CS0, SAF_CS1 (active low) to select up to two on board sensors; MOSI is the input data for the IC and MISO is the output data of the IC when CS is low. MISO is internally read back. Data will be sent out the IC or not basing on SPI_CS. When SAF_CS0 or SAF_CS1 is asserted, IC can sniff data on MISO pin (MOSI remains an input pin). So the IC knows what microcontroller requires and what sensor answers. Figure 31. MOSI, MISO, SPI_CS, SAF_CS0, SAF_CS1, SCLK 63,B&6 026, 0,&52&21752//(5 0,62 / 5(4B0$6.5(4B7$5*(7 5(63B0$6.5(63B7$5*(7 '$7$ B0$6. 0,62 EORFN 6&/. 6(1625 6$)B&6 6(1625 6$)B&6 Note: *$3*36 The external logic guarantees that SAF_CS0, SAF_CS1 and SPI_CS are not asserted simultaneously; if it happens, the frame is discharged. Safing configuration register is done through SAF_CONTROL_x registers x=1÷4. $EF → SAF_CONTROL_x → x=1 $F0 → SAF_CONTROL_x → x=2 $F1 → SAF_CONTROL_x → x=3 $F2 → SAF_CONTROL_x → x=4 All safing records are reset by SSM reset. Case x=1 DocID025845 Rev 2 65/201 200 SAFING AN4437 ARMING considering positive or negative acceleration It defines if arm is with positive or negative acceleration or both. $EF SAF_CONTROL_1 Config only in DIAG state ARMSEL1, bit [15,14] 00, 11 = ARMP or ARMN 01 = ARMP 10 = ARMN SPI field selection SPI field selects (for the safing record x) which 16-bit field in the SPI messages will be used in the response on MISO. In case of message having less than 32 bit, this bit doesn't care. This bit will be relevant in the SAF_RESP_MASK definition, where it is defined which bit, sent from sensor to microcontroller, contain the data, the first 16 or the second 16 bit. $EF SAF_CONTROL _1 SPIFLDSEL1, bit 13 Config. only in DIAG state 0 = first 16 bit of SPI_MISO frame 1 = second 16 bit of SPI_MISO frame LIMIT SELECTION It defines the out-of-range threshold, considering PSI 5 sensor at 8 bit or 10 bit. This bit is taken into account if LIM_ENx is set. $EF SAF_CONTROL _1 LIM_EN1, bit 12 Config. only in DIAG state 0 = 8 bit data range |data|>120d, data not recognized valid 1 = 10 bit data range |data|>480d, data not recognized valid LIMIT ENABLE To enable or not the out of range control. $EF SAF_CONTROL _1 LIM_EN1, bit 11 Config. only in DIAG state 0 = data range limit disabled 1 = data range limit enabled COMB This command allows, performing mathematic elaboration as sum or difference between accelerations read from different sensors, to elaborate the direction of the acceleration detected from x-y axis to have an on-axis response. The direction depends on the sensor orientation inside the system. $EF SAF_CONTROL_1 COMBx, bit [10] 66/201 Config. only in DIAG state 0 = combine function disabled 1 = combine function enabled DocID025845 Rev 2 AN4437 SAFING When the “combine function” is enabled, the elaboration, being x=1, 3, is: Safing record pairs x, x+1 (1, 2 / 3, 4) Safing record (x) = data(x) + data (x+1) Safing record (x+1) = data(x) - data (x+1) Since this elaboration is performed using two safing records, the elaboration itself is performed only after that the two safing records have been captured (CC_x=1). In case of an on-board dual axis sensor which is offset 45 degrees from center, the IC allows vector addition/subtraction to refer the sensor data to the vehicle axis. Here below it is shown how to refer to the data caught by the sensors, referred to their axis orientation, to the axis LONG and LAT of the vehicle, through simple sum or difference of sensor data, with the aim of managing the ARMING process. Figure 32. Sensor's axis and vehicle's axis correlation /21* ; /21* [ /$7 Q $ < /$7 < *$3*36 /21* ; FRVQ < FRVQ n /$7 ; FRVQ < FRVQ LI Q n < /$7 ; < /21* ; ; < ; < *$3*36 Thresholds are referred to LONG and LAT reference system; Data caught from sensor are referred to X and Y axis. These axis are rotated with respect to LONG and LAT axis, see Figure 32. DocID025845 Rev 2 67/201 200 SAFING AN4437 The thresholds (TH_LONG and TH_LAT thresholds) must consider the sensor direction with respect to the vehicle axis, so the trigonometric parameters (θ) are known and included in the thresholds: 7+ B /21* ; < 7+ 7+ B /$7 ; < 7+ *$3*36 DWELL Once an arming condition is detected, it remains valid for DWELL time (pulse stretch time) waiting for an eventual firing command. DWELL time is blocked by SSM reset. In case different values are configured for the four safing records, the value considered is the longest one. Figure 33. ARMING enable pulse stretch $UPLQJ6DILQJ/RJLF 3URFHVVHGUHVXOW $UPLQJ(QDEOH 3XOVH6WUHWFK 3XOVH6WUHWFK7LPH /HVV7KDQ3XOVH 6WUHWFK7LPH 3XOVH6WUHWFK 7LPH '!0'03 $EF SAF_CONTROL _1 DWELLx (x=1), bit [9,8] Note: Config. only in DIAG state 00 = 2048ms 01 = 256ms 10 = 32ms 11 = 0ms In SAFING configuration it is defined the time DWELL, that is the period of time in which the ARMING signal, once asserted, is valid waiting for a deployment command. In DEPLOYMENT configuration it is defined the time DEPLOY EXPIRE TIME, that is the period of time in which the deployment command, once received, is valid waiting for the ARMING signal asserted. 68/201 DocID025845 Rev 2 AN4437 SAFING ARM There are two internal arming signals (ARM1INT, ARM2INT). The safing record can be assigned to one or both of them (ARM1INT ARM2INT). This allows grouping the sensors that recognize a high acceleration based on their direction, representing then the crash event. ARM1INT - ARM2INT are linked to the deployment loop following LOOP_MATRIX_ARMx set-up, $6E and $6F registers: $6E LOOP_MATRIX_AMR1 $6F LOOP_MATRIX_AMR2 ARMx_Li, i=3..0, b[3:0] Config. only in DIAG state 0 = ARMx not associated with loop i 1 = ARMx associated with loop i In this way it is possible to establish which deployment loop will take place based on the direction of the crash event. A safing record can be mapped at the same time both on ARM1INT and ARM2INT x=1 $EF SAF_CONTROL _1 Config. only in DIAG state ARM2x, bit 5 0 = safing record x not assigned to ARM2INT 1 = safing record x assigned to ARM2INT ARM1x, bit 4 0 = safing record x not assigned to ARM1INT 1 = safing record x assigned to ARM1INT CS To associate a safing record with one of the 3 chip select, SPI_CS, SAF_CS0, SAF_CS1 $EF SAF_CONTROL _1 CSx, bit [3÷1] Config. only in DIAG state 001 = SAF_CS0 associated to safing record x 010 = SAF_CS1 associated to safing record x 101 = SPI_CS associated to safing record x Others = no CS associated to safing record x DocID025845 Rev 2 69/201 200 SAFING AN4437 IN FRAME As said, the answer (on MISO) can be in frame with the request (MOSI) or out of frame. The IC has to be aligned to the option chosen Figure 34. SPI sensor frame organization -/3) 2EQUESTN -)3/ 3TATUS 5NUSED 2ESPONSEN -/3) 2EQUESTN 2EQUESTN -)3/ 2EQUESTN 2ESPONSEN $EF SAF_CONTROL _1 *$3*36 Config. only in DIAG state IF1, bit 0 0 = response out of frame (record x) 1 = response in frame (record x) SPI is 32bit: 31 SPI_MOSI REQUEST SPI_MISO REQUEST 29 28 GID 27 26 25 24 23 22 21 RID[6:0] 14 13 12 11 20 19 18 17 WID[6:0] GSW[10:0] 15 SPI_MOSI REQUEST SPI_MISO REQUEST 30 10 9 WPAR RPAR 8 7 6 5 4 16 READ[19:16] 3 2 1 0 WRITE[15:0] READ[15:0] Compatible on board sensors are able to communicate over 16, 32 or even more bit frames. Useful information for the microcontroller requests is supposed to be always located on the first 16MSBs (GID, RID, WID, WPAR), while the useful information for sensor response can be located both on first 16 or second 16bit block of response from sensor. If the frame is shorter than 16 bit, the frame is discharged; In case of frame length between 16 and 32 bit, 16 MSB are latched while the latter bits are ignored. In case of 32 bit frame or longer, 32 MSB are latched, while the latter bits are ignored by the IC; in this case first or second 16 bit block is considered, depending on the configuration of the bit SPIFLDSEL1. In order to extract useful information from the data sniffed over the SPI bus, IC provides definition for configurations of proper request masks and response masks, which can be programmed by the microcontroller, see Section 7.2. 70/201 DocID025845 Rev 2 AN4437 SAFING Sensor data are processed as described below. The IC provides four 16 bit registers for safing records. ENABLE Each safing record has to be activated, through 7F SAF_ENABLE These bit determine when a safing record is active or inactive. $7F SAF_ENABLE EN_SAF4, bit 3 EN_SAF3, bit 2 EN_SAF2, bit 1 EN_SAF1, bit 0 Config. in DIAG, SAFING, SCRAP, ARMING state 0 = disable 1 = enable THRESHOLD Each safing record has to be compared with a threshold, configured only in DIAGNOSTIC state, one threshold for each safing record: $DF → SAF_THRESHOLD_x → x=1 $E0 → SAF_THRESHOLD_x → x=2 $E1 → SAF_THRESHOLD_x → x=3 $E2 → SAF_THRESHOLD_x → x=4 x=1, $DF SAF_THRESHOLD_1 Config. only in DIAG state SAF_THRESHOLD_1, bit [15÷0] The threshold is always programmed in absolute value, even if the safing record is a simple sensor data or data combination, sum or difference. The safing record is compared with the SAF_TH. Inside the IC there are two dedicated counters (POS_COUNT, NEG_COUNT) to count, with the weight ADD_VAL and SUB_VAL, how many times the safing record overcomes the threshold SAF_TH. These counters (POS_COUNT, NEG_COUNT) have their limits, ARMN_TH, ARMP_TH. These parameters are defined in the SAF_ALGO_CONF register. Counters' values are updated on each sensor sample received. $66 SAF_ALGO_CONF Config. only in DIAG state ADD_VAL, bit [2÷0] incremental step size SUB_VAL, bit [5÷3] decremental step size ARMN_TH, bit [13÷10] ARMP_TH, bit [9÷6] Threshold negative counter Threshold positive counter DocID025845 Rev 2 71/201 200 SAFING AN4437 If safing record > +|SAF_TH| → it is incremented the positive counter, POS_COUNT of ADD_VAL; otherwise the counter is decremented of SUB_VAL If safing record < -|SAF_TH| → it is incremented a negative counter, NEG_COUNT of ADD_VAL; otherwise the counter is decremented of SUB_VAL. Values of NEG_COUNT and POS_COUNT counters are compared with two thresholds, ARMN_TH and ARMP_TH respectively to define ARMN and ARMP signals If POS_COUNT ≥ ARMP_TH → ARMP set If NEG_COUNT ≥ ARMN_TH → ARMN set Based on ARMSEL bit (register $EF-$F2) and on ARMP/ARMN result, the internal arming flags will be asserted or not. Once the sample cycle time is elapsed, the sensor data received (CC_x=1) flags that the arming processing has been successfully run. In case of no data received (CC_x=0) it is possible to configure how the IC behaves. A possibility is to consider the "no data" received event in a similar way than a data below threshold (arming counters decremented) or by taking a more severe alternative (arming counters reset). $66 SAF_ALGO_CONF NO_DATA, bit 15 Config. only in DIAG state 0 = event count reset if CC=0 when SPI has read the SAF_CCx bit (no acceleration data received) 1 = event count decremented by SUB_VAL when SPI has read the SAF_CCx bit (no acceleration data received) COMPARE COMPLETE Data sample cycle is managed by the microcontroller reading CC_x bit; typical timing for sampling cycle is 500 μs (sensor sampling period 475 μs ÷ 525 μs). Once the IC receives data from sensors, post processing for arming purpose starts and any other valid data received from sensors are ignored until the microcontroller reads the CC_x bit. Should the microcontroller read the CC_x bit and no valid data have been received yet, IC reacts according to the $66 SAF_ALGO_CONF register, NO DATA bit $FF SAF_CC CC_4, bit 3 CC_3, bit 2 CC_2, bit 1 CC_1, bit 0 72/201 0 = compare not completed 1 = compare completed DocID025845 Rev 2 AN4437 7.2 SAFING SPI sensor data decoding - MASK Sensors regularly exchange data with the main microcontroller through multiple SPI messages. Since not all communications between sensors and microcontroller contain data, it is important for the decoder to properly sort the communications and extract only the targeted data. The solution is specific masking definition, per safing record: REQUEST MASK, TARGET REQUEST (MOSI line) RESPONSE MASK, TARGET RESPONSE (MISO line) DATA MASK SAFING THRESHOLD REQUEST MASK (on MOSI line) The registers to be configured are the four SAF_REQ_MASK _x. The explanation is the same for all the four registers, so only the first is considered: $80 SAF_REQ_MASK_x → x=1 $81 SAF_REQ_MASK_x → x=2 $82 SAF_REQ_MASK_x → x=3 $83 SAF_REQ_MASK_x → x=4 Case x=1 $80 SAF_REQ_MASK_1 Config. only in DIAG state SAF_REQ_MASK_1, bit [15÷0] Here is defined the position, inside the frame, of the bit to be considered in the data received. This is done by setting bit in SAF_REQ_MASK_x located in the position to be considered. Extraction of data is done by putting in AND (bit per bit) the SAF_REQ_MASK with the data received. TARGET REQUEST (on MOSI line) The registers to be configured are the four SAF_REQ_TARGET_x. The explanation is the same for all the four registers, so only the first is considered: $93 SAF_REQ_TARGET_x → x=1 $94 SAF_REQ_TARGET_x → x=2 $95 SAF_REQ_TARGET_x → x=3 $96 SAF_REQ_TARGET_x → x=4 Case x=1 $93 SAF_REQ_TARGET_1 Config. only in DIAG state SAF_REQ_TARGET_1, bit [15÷0] Considering the bit selected through REQUEST MASK, the value they have to assume is indicated in the REQUEST TARGET. DocID025845 Rev 2 73/201 200 SAFING AN4437 So in REQUEST MASK it is defined which bit positions to look at; in REQUEST TARGET it is defined the expected value the bit in the positions defined through REQUEST MASK have to assume. This procedure is the definition of the filter of all the data exchanged: which bit consider and which value they have to assume. RESPONSE MASK (on MISO line) The registers to be configured are the four SAF_RESP_MASK_x. The explanation is the same for all the four registers, so only the first is considered: $A6 SAF_RESP_MASK_x → x=1 $A7 SAF_RESP_MASK_x → x=2 $A8 SAF_RESP_MASK_x → x=3 $A9 SAF_RESP_MASK_x → x=4 Case x=1 $A6 SAF_RESP_MASK_1 Config. only in DIAG state SAF_RESP_MASK_1, bit [15÷0] Here is defined the position, inside the frame received from the sensor (MISO), of those bit to be considered. This is done setting the bit, in SAF_RESP_MASK_x, located in the position of the bit to be considered. RESPONSE TARGET (on MISO line) The registers to be configured are the four SAF_RESP_TARGET_x. The explanation is the same for all the four registers, so only the first is considered: $B9 SAF_RESP_TARGET_x → x=1 $BA SAF_RESP_TARGET_x → x=2 $BB SAF_RESP_TARGET_x → x=3 $BC SAF_RESP_TARGET_x → x=4 Case x=1 $B9 SAF_RESP_TARGET_1 Config. only in DIAG state SAF_RESP_TARGET_1, bit [15÷0] Considering all the data that can pass on MISO line, the only one that has to be considered is the data that in the position defined in RESP MASK has the value defined in the RESP TARGET. So in RESP MASK it is defined which bit look at; in REQUEST TARGET it is defined the expected value these bit, coming from the sensors (MISO line), should have. This procedure is the definition of the filter of all the data exchanged: which bit consider and which value they should have, sensor side. 74/201 DocID025845 Rev 2 AN4437 SAFING DATA MASK (on MISO line) definition, only in DIAGNOSTIC state The registers to be configured are the four SAF_DATA_MASK_x. The explanation is the same for all the four registers, so only the first is considered: $CC SAF_DATA_MASK_x → x=1 $CD SAF_DATA_MASK_x → x=2 $CE SAF_DATA_MASK_x → x=3 $CF SAF_DATA_MASK_x → x=4 Case x=1 $CC SAF_DATA_MASK_1 Config. only in DIAG state SAF_DATA_MASK _1, bit [15÷0] Here is defined the position, inside the frame received from the sensor (MISO), of those bit to be considered. This is done by setting the bit, in SAF_DATA_MASK_x, located in the position of the bit to be considered. Example Figure 35. MOSI, MISO, SPI_CS,SAF_CS0, SAF_CS1, SCLK &6 026, 0,&52&21752//(5 0,62 5(4B0$6.5(4B7$5*(7 5(63B0$6.5(63B7$5*(7 '$7$ B0$6. 6&/. / 6$)B&6 6(1625 6$)B&6 6(1625 DocID025845 Rev 2 *$3*36 75/201 200 SAFING AN4437 Example to explain safing MASK definition 1. Data sensors are so organized: Bit 15 14 13 12 11 10 SO 0 CH1 CH0 P ST1 ST0 9 8 7 6 5 4 3 2 1 0 3 2 1 0 1 0 1 0 Sensor data bit [14,13]= channel selection, x or y bit [9÷0]=data sensor bit 12=patity bit bit [11,10]=type of data in sensor data field (acceleration, self-test, error) If the microcontroller request is (MOSI): 2. Bit 15 14 13 12 11 10 SI 0 0 1 X 1 0 3. 9 8 7 6 5 4 X bit [14,13]= 01 this codification can be for example the sensor for x acceleration bit 12=don't care bit [11,10]=01 this codification can indicate for example that in the data field are reported acceleration data bit [9÷4]= don't care. These are the data the sensor sends. Microcontroller reads them, but doesn't write them bit [3÷0]=address of the sensor, for example 1010 that is sensor n.3 Based on this information, the MASK will be: SAF_REQ_MASK - microcontroller requires something SAF_REQ_MASKx[15:0] Bit 15 14 13 12 11 10 1 1 1 0 1 1 9 8 7 6 0 5 4 3 2 1 0 1 1 1 1 bit [15:13], b[11:10], b[3:0] set bit 12, bit [9:4] correspond to the position of bit not to be considered; they are left at 0. 76/201 DocID025845 Rev 2 AN4437 SAFING 4. SAF_REQ_target - microcontroller says what it expects SAF_REQ_TARGETx[15:0] Bit 15 14 13 12 11 10 9 0 0 1 X 1 0 X 8 7 6 5 4 3 2 1 0 1 0 1 0 bit 15 is expected @0 bit [14:13] is expected to be 01 being x axis data bit 12 is the parity bit, so a priori is not defined bit [11:10] is expected to be 10 because it is supposed that the data received from sensor will be the acceleration bit [9:4] are the data, so their value is not known a priori. bit [3:0] is expected to be 1010 being selected the sensor number 3 5. SI[15:0] AND SAF_REQ_MASKx[15:0] = SAF_REQ_TARGETx[15:0] The SAF_RESP_MASK allows choosing one message among those in the SPI bus. In this case, the IC sniffs the frame on MISO line. It considers the position of bit at 1 in the frame. SAF_RESP_MASKx[15:0] Bit 6. 15 14 13 12 11 10 9 1 1 1 0 1 1 0 8 7 6 5 4 3 2 1 0 bit 15 is expected at 0, so bit 15 is in a relevant position and bit 15 in the SAF_RESP_MASK is set. bit [14:13] expected 01 so bit 14 and bit 13 are set bit 12 don't care so bit 12 is left at 0 bit [11:10] expected 10 so bit 11, bit 10 are set bit [9:0] are the data, not useful to identify which message has to be chosen, so they are left 0 The SAF_RESP_TARGET indicates which values are expected for the bit selected in the SAF_RESP_MASK: SAF_RESP_TARGETx[15:0] Bit 15 14 13 12 11 10 0 0 1 X 1 0 9 8 7 6 5 4 3 2 1 0 X bit 15=0 bit [14:13]=01 bit 12 don't care → x bit [11:10]=10 bit [9:0] this field corresponds to the data that are not known a priori → x DocID025845 Rev 2 77/201 200 SAFING AN4437 The SAF_DATA_MASK indicates where the data bits are localized, in the frame received from the sensor and identified through SF_RESP_MASK, SAF_RESP_TARGET In this example data are supposed to be localized in position 9:0, so the correspondent bit [9:0] =1 SO[15:0] AND SAF_RESP_MASKx[15:0] = SAF_RESP_TARGETx[15:0] SAF_DATA_MASKx[15:0] Bit 7.3 15 14 13 12 11 10 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0 1 SPI sensor data decoding - Example arming without on board sensor Here below there is an example to show how to configure the MASK registers in case of an ECU where on board sensors are not present and the arming is driven by the data received through RSU interface. It is supposed a 10 bit PSI5 data transmission (L9678-S case). In particular, the example shows how to assign safing record 1 to the data from RSU0; safing record 1 is assigned to both ARM1int and ARM2int signals. 1. Enable safing record #1 2. $7F SAF_ENABLE Config. in DIAG, SAFING, SCRAP, ARMING state EN_SAF1 (bit 0) =1 0 = safing record 1 disabled 1 = safing record 1 enabled ← chose Configure SAF_REQ_MASK for safing record 1 $80 SAF_REQ_MASK_1 SAF_REQ_MASK1 bit[15:0] Config. only in DIAG state 0111 1111 0000 0000 = $7F00 SAF_REQ_MASK is applied on messages recorded from MOSI pin; peripheral device identification is through GID, RID, WID that are located always in the first 16 bit: bit 31 = GID, not important in this exercise bit [30:24] = RID [6:0] is the address of the data to be read. bit [23:17] = WID [6:0] is the address of the data to be written, not relevant bit 16 = WPAR not relevant SAF_REQ_MASK defines, in the first 16 bit, which of them have to be considered, here all the RIDs, moved to the range [15:0] instead of [31:0]. They are set. 3. Configure SAF_REQ_TARGET for safing record 1 $93 SAF_REQ_TARGET_1 SAF_REQ_TARGET1 bit[15:0] 78/201 Config. only in DIAG state 0101 0000 0000 0000 = $5000 DocID025845 Rev 2 AN4437 SAFING Here is defined the expected value of the bit extracted through the request MASK. When bit[14:8] = RID[6:0] = 101, $50, of MOSI frame sent to the IC, a reading access to the sensor register RSDR0. All remaining bit, bit[7:0] in the register $93, are don't care in this exercise. 4. Configure SAF_RESP_MASK for safing record 1 $A6 SAF_RESP_MASK_1 SAF_RESP_MASK1 bit[15:0] Config. only in DIAG state 1111 1100 0000 0000 = $FC00 SAF_RESP_MASK is applied on messages sniffed from MISO pin; Useful information from sensor is in the second 16 bit block, READ[15:0] Here is defined which bit of the sensor RSU0 ($50 RSDR0 register) have to be considered. Useful information is FLT bit, ON/OFF bit and LCID[3:0] bit. All remaining bits are don't care in this exercise. 5. Configure SAF_RESP_ TARGET for safing record 1 $B9 SAF_RESP_TARGET_1 SAF_RESP_TARGET1 bit[15:0] Config. only in DIAG state 0100 0000 0000 0000 = $4000 Here is defined the expected value of the bit extracted through the response MASK in the data received: IC is addressed to read RSU0 ($50 RSDR0 register). In this step the following bit have to be considered (see RESP_MASK): bit 15 = FLT, expected to be 0 bit 14 = on/off expected to be 1, that means the channel is ON bit [13:10] = LCID[3:0] expected to be 0000, RSU0 All remaining bits are don't care in this exercise. 6. Configure SAF_DATA_MASK for safing record 1 $CC SAF_DATA_MASK_1 SAF_DATA_MASK1 bit[15:0] Config. only in DIAG state 0000 0011 1111 1111 = $03FF Here is defined which bit of the sensor RSU0 ($50 RSDR0 register) have to be read as data from sensor. Note: In case of 8 bit data transmission the data from sensor would be available on DATA[7:0] so mask would be $00FF All remaining bits are don't care in this exercise. DocID025845 Rev 2 79/201 200 SAFING AN4437 7. Configure SAF_CONTROL for safing record 1 $EF SAF_CONTROL_1 Config. only in DIAG state SPIFLDSEL1 bit 13 = 1sensor data are transmitted on second 16 bit block of MISO word ARM21 bit 5 = 1 safing record 1 is assigned to both ARM1int and ARM2int signals. ARM11 bit 4 = 1 safing record 1 is assigned to both ARM1int and ARM2int signals CS1[3:1] IF1 bit[3:1] = 101 SPI_CS is selected for safing record 1 bit 0 = 1 SPI MISO answer is in frame All remaining bits are left at their default value 8. Enter in SAFING STATE $31 SAFING_STATE Config. only in DIAG state bit[15:0] = 1010110010101100 = $ACAC This is needed to bring IC in SAFING state from DIAG state: safing records are enabled only in SAFING STATE. 9. Check IC STATE $04 SYS_STATE OPER_CTL_STATE bit [10:8] expected to be 010 ie. IC in SAFING STATE This SPI reading command allows to check in which state the IC is (SAFING expected). 10. Read PSI5 Sensor data $50 RSDR0 FLT, bit 15 on/off, bit 14 LCID[3:0], bit [13:10] this bit is expected to be 0 this bit is expected to be 1 channel ON expected to be 0000, PSI5 channel 0 DATA, bit [9:0] 80/201 DocID025845 Rev 2 AN4437 SAFING 11. Check SAF CC bit $FF SAF_CC CC_1 bit 0 0 = compare not completed for record 1 1 = compare completed for record 1 Safing record can only be evaluated on the first matching input packet. Any further data packet matches are ignored (i.e. once CC is set, record can't be processed until next sensor sampling period) 7.4 Additional communication line (ACL) The ACL pin is the Additional Communication Line input with the purpose of safely activate the arming output for disposal of restraints devices at the end of vehicle life. A valid ACL allows the IC to pass from Scrap state to Arming state. To remain in Arming state the IC must receive the correct ACL signal; this must occur before the scrap timeout timer expires: TdisEOL= (2*TALC(min)) ÷ (2*TACL(max)) TACL = 187ms ÷ 213ms A specific waveform needs to be present on this input in order to instruct the IC to arm all deployment loops and implement the scrapping feature. For those systems not having a proper ACL stimulus available, L9678 allows the ACL input pin to be successfully triggered also with one of the MCU output digital ports. The disposal signal may come from either the vehicle's service connector, or the systems main microcontroller, depending on the customer's requirements. The arming function monitors the disposal PWM input (ACL pin) for a command to arm all loops for vehicle end-of-life airbag disposal. Figure 36. ACL signal &\FOHWLPH 2QWLPH '!0'03 To remain in Arming state, at least three cycles of the ACL signal must be qualified. To qualify the ACL signal, the period and duty cycle are checked. Two consecutive cycles of invalid disposal signal are enough to disqualify the ACL signal. DocID025845 Rev 2 81/201 200 Deployment 8 AN4437 Deployment Features: 4 independent loops composed by 4 independent high side and 4 independent low side all 4 squibs can deploy at the same time or according to a given sequence deployment granted in case of short to ground of the low side SRx. firing voltage capability across SSxy and SFi is maximum 25 V max resistance of high side and low side is 10 Ω. each loop can sustain 50 deployment max, waiting at least 10s between each of them 2 supply pins, SS01, SS23 directly connected to the High Side for each channel; 2 dedicated power ground SG01, SG23 each of them able to sustain the current of two channels simultaneously SGxy is connected to GNDSUB through a diode so that the device is able to fire in case of SGxy lost. 8.1 Deployment requirement Deployment features are deploy current, deploy time and deployment expiration time. The deployment expiration time is the duration time in which the deploy command remains valid, once it is received, waiting for the arming signal. These parameters are defined in DCR register, one per each channel. Here are explained the commands to configure the IC deployment. Deployment configuration is done through the four registers DCR_x, x=0-3, DIAG, SAFING, SCRAP, ARMING state. $06 DCRx → x=0 channel 0 $07 DCRx → x=1, channel 1 $08 DCRx → x=2, channel 2 $09 DCRx → x=3, channel 3 All deployment configuration registers are reset by SSM reset. Case x=0 82/201 DocID025845 Rev 2 AN4437 Deployment Deploy current, Deploy time and Deploy expiration time definition $06 DCR0 Config. in DIAG, SAFING, SCRAP, ARMING state Dep_current, bit [5:4] Deploy_timer, bit [7:6] Dep_expire_time, bit [3:2] Note: 00 - 11= not used 01 = 1.75A min 10 = 1.2A min 00 = no deploy 01 = 0.5ms 10 = 0.7ms 11 = 2ms 00 = 500ms 01 = 250ms 10 = 125ms 11 = 0ms DWELL time is defined in SAFING configuration. DWELL time is the period of time in which the ARMING signal once asserted, is valid waiting for a deployment command. DEPLOY EXPIRE TIME is defined in DEPLOYMENT configuration. DEPLOY EXPIRE TIME is the period of time in which the deployment command, once received, is valid waiting for the ARMING signal asserted. Note: The combination 1.75 A, 2 ms is not allowed. If the above mentioned case should happen, the IC changes the set-up into 1.2 A / 500 μs and flags the bit CHxDD, in DSRx register (deployment status register), one per each channel: $13 DSRx register, x=0, channel 0 $14 DSRx register, x=1, channel 1 $15 DSRx register, x=2, channel 2 $16 DSRx register, x=3, channel 3 $13 DSR0 register CH0DD, bit [13] Note: 0 = correct current / time combination 1 = incorrect current / time combination. In order to perform deployment, all the deploy configurations registers ($06 DCR_0, $07 DCR_1, $08 DCR_2, $09 DCR_3) have to be accessed, also if the default values have just to be confirmed; otherwise IC inhibits deployment. DRCxERR bit in DSRx register reports this information. $13 DSR0 register DRCxERR, bit [12] 0 = Deploy configuration change accepted and stored in memory 1 = Deploy configuration change rejected because deploy is in progress (or DEP_EXPIRE_TIME changed when in DEP_ENABLED state) For each channel, the deploy requires that high side and low side are enabled first and then switched on. DocID025845 Rev 2 83/201 200 Deployment AN4437 The pictures below show the states of the IC and the signal paths which enable the high side and low side. Figure 37. Device functionality 33-2ESET #ONFIGURATIONENABLEDFOR 7ATCHDOGTIMINGTHRESHOLDS !2-INOUTSELECT 235OUTPUTTYPE'M37 $IAGSAMPLESELECT 63&VOLTAGESELECT )NIT 3TATE 4ESTINGENABLEDFOR !2-X63& $EPLOYTIME (3,3(33&%4 7$25. 7$/6%22)$% #ONFIGURATIONENABLEDFOR 3AFINGRECORDSANDCONTROL $EPLOYMASK (3,3'0/ $IAG 3TATE 30)3!&).'?34!4% 30)3#2!0?34!4% !2-63&DETERMINED BYSAFINGENGINE 3AFING 3TATE !2-X 63& 3CRAP 3TATE !#,'//$ !#,"!$ !RMING 3TATE !2-X 63& '!0'03 Figure 38. High side and low side squib enable $50,1*67$7( $QDORJ ',$*67$7( 'HSOR\PHQW /3',$*5(4/($.B&+6(/[ '67(67+6)(7B7(67 %ORFN 6$)(6(/ )(1+ (1$%/(B+6[ $50,17 $50B/[ $50,17 $50B/[ )(1/ 6$),1*67$7( $50B(1 (1$%/(B/6[ ',$*67$7( /3',$*5(4/($.B&+6(/[ '67(67/6)(7B7(67 '!0'03 84/201 DocID025845 Rev 2 AN4437 Deployment In the next pages the conditions required to deploy are considered. 8.1.1 ARMING state This state corresponds to the disposal of the vehicle (see figures 37 and 39 for correspondent signals). In this state the high side and low side are enabled. Figure 39. High side and low side squib enable in ARMING state $50,1*67$7( $QDORJ ',$*67$7( 'HSOR\PHQW /3',$*5(4/($.B&+6(/[ '67(67+6)(7B7(67 %ORFN 6$)(6(/ )(1+ (1$%/(B+6[ $50,17 $50B/[ $50,17 $50B/[ )(1/ 6$),1*67$7( $50B(1 (1$%/(B/6[ ',$*67$7( /3',$*5(4/($.B&+6(/[ '67(67/6)(7B7(67 *$3*36 DocID025845 Rev 2 85/201 200 Deployment 8.1.2 AN4437 DIAGNOSTIC state In DIAGNOSTIC state (see Figure 37) it is possible to perform the high side FET test and low side FET test. These tests require a sequence of steps, as listed here below. Correspondent signals are summarized in Figure 40. 1. Chose the channel: $38 LPDIAGREQ LEAK_CHSEL, bit [3:0] Config. in DIAG, SAFING, SCRAP, ARMING state 0000= CHANNEL 0 0001= CHANNEL 1 0010= CHANNEL 2 0011= CHANNEL 3 2a. Chose the test, high side FET: $36 SYSDIAGREQ DSTEST [3:0]0 Config. in DIAG state 0111 = high side FET test active 2b. Chose the test, low side FET: $36 SYSDIAGREQ DSTEST [3:0]0 Config. in DIAG state 1000 = low side FET test active Figure 40. High side and low side squib enable in DIAG state $50,1*67$7( $QDORJ ',$*67$7( 'HSOR\PHQW /3',$*5(4/($.B&+6(/[ '67(67+6)(7B7(67 %ORFN 6$)(6(/ )(1+ (1$%/(B+6[ $50,17 $50B/[ $50,17 $50B/[ )(1/ 6$),1*67$7( $50B(1 (1$%/(B/6[ ',$*67$7( /3',$*5(4/($.B&+6(/[ '67(67/6)(7B7(67 *$3*36 86/201 DocID025845 Rev 2 AN4437 8.1.3 Deployment SAFING state Figure 41. High side and low side squib enable with ARMING signal $50,1*67$7( $QDORJ ',$*67$7( 'HSOR\PHQW /3',$*5(4/($.B&+6(/[ '67(67+6)(7B7(67 %ORFN 6$)(6(/ )(1+ (1$%/(B+6[ $50,17 $50B/[ $50,17 $50B/[ )(1/ 6$),1*67$7( $50B(1 (1$%/(B/6[ ',$*67$7( /3',$*5(4/($.B&+6(/[ '67(67/6)(7B7(67 *$3*36 If WD_LOCKOUT is not set (that is ARM_EN=1 in the Figure 41), high side and low side enable depends on the safing engine machine, internal or external, in according to SAFESEL bit. $01 SYS_CFG SAFSEL, bit 3 Config. in INIT state 0 = internal safing engine 1 = external safing engine - default In case of external safing engine (SAFESEL=1), the signals to be considered are FENH, active high, and FENL, active low. Note: If the external safing engine is used, FENH and FENL drive directly the output. So, if their status changes during a deployment, passing from their active state to their inactive state, the deployment is immediately interrupted. If the internal safing engine is chosen, FENH and FENL are ignored. Note: The internal arming signals (ARM1INT, ARM2INT) drive, at the same time, the high side and the low side; The external arming signals (FENH, FENL) drive the high side and the low side separately. Note: If the internal safing engine is used, it is recommended keeping FENH and FENL in their inactive status, FENH=L, FENL=H to prevent that in case of safing internal engine fault, the arming signal is set. In case of internal safing engine (SAFESEL=0), the signals to be considered are ARM1INT, ARM2INT, ARM1_Lx, ARM2_LX. DocID025845 Rev 2 87/201 200 Deployment AN4437 ARM1_Lx, ARM2_Lx signals are used to link the ARM signals, to the deployment loop. Case x=1 $6E LOOP_MATRIX_ARM1 Config. in DIAG state ARM1_L3, bit 3 0 = ARM1 not associated to loop 3 1 = ARM1 associated to loop 3 ARM1_L2, bit 2 0 = ARM1 not associated to loop 2 1 = ARM1 associated to loop 2 ARM1_L1, bit 1 0 = ARM1 not associated to loop 1 1 = ARM1 associated to loop 1 ARM1_L0, bit 0 0 = ARM1 not associated to loop 0 1 = ARM1 associated to loop 0 The same for the other ARM2, mapped on register $6F LOOP_MATRIX_ARMx, x=2 8.1.4 DEPLOYMENT driver Figure 42. Driver's DEPLOYMENT signals $50,1*67$7( ([SLUDWLRQ 7LPHU 6$),1*67$7( '(3B(1$%/('67$7( 6 63,B'(35(4[ 5 6605(6(7 '(3B',6$%/('67$7( 8S&WU (;3B7KUHVK (1 &/5 &+['(3 &+[67$7 6 5 '(3B7KUHVK 8S&WU (1$%/(B+6[ (1$%/(B/6[ 6 ',$*67$7 ( '67(6738/6( 5 (1 &/5 /6B29(5B&85[ *1'B/266[ 'HSOR\ 7LPHU 6605(6(7 6 6 5 5 &+['6 +6B21[ '67(67+6)(7B7(67 /3',$*5(4/($.B&+6(/[ /6B21[ '67(67/6)(7B7(67 $1$/2* 'HSOR\PHQW%/2&. '!0'03 88/201 DocID025845 Rev 2 AN4437 Deployment List of the requirements to deploy 1. high side and low side are enabled, see previous point (ENABLE_HS & ENABLE_LS =1) 2. no problem on SSM reset that means internal voltage references are at their correct value (POR=0), VDD5 & VDD3V3 voltage regulators at their correct value too (WSM_reset=0) and WD asserted or overridden (SSM_reset=0). 3. IC in ARMING or SAFING state 4. SPI DEPREQx, x=0, 1, 2, 3 $12 DEPCOM Config. in SAFING and ARMING state CHxDEPREQ, bit x 5. 0 = no change to deploy. control ch x 1 = clear and start the expiration timer in ARMING, SAFING and DEP_ENABLED state DEP_ENABLE_STATE SPI, unlock command: $25 SPIDEPEN Config. in SAFING and ARMING state DEPEN_WR, bit [15:0] $0FF0 = LOCK enter deploy disable state $F00F = UNLOCK enter deploy enable state As the SSM_Reset is released, to perform the deployment the DEPEN_WR = UNLOCK (F00F) is required for the channel that has to deploy. After a deploy, the next deployment requires a toggle DEPEN_WR = UNLOCK(F00F) LOCK(0FF0)-UNLOCK (F00F) for the channel that has to deploy. The same is necessary in case of a multiple deployment request, after each deployment event. Figure 43 summarizes these requirements: Figure 43. DEPLOYMENT enable/disable 660B5HVHW '(3B',6$%/(' 63,B63,'(3(1'(3(1B:5 63,B63,'(3(1'(3(1B:5 81/2&. /2&. '(3B(1$%/(' '!0'03 Once the 5 above points are satisfied, the Expiration time counter starts. DocID025845 Rev 2 89/201 200 Deployment AN4437 This counter takes into account the feature of the IC to accept a deploy command even if the arming is not yet serviced. If the arm command occurs inside the expiration time, the deployment takes place otherwise the deployment command is discharged. Dep_exp_time is defined in DRCx (x=0-3) registers, together with the Deploy_timer and Dep_current, $06 DCRx → x=0 channel 0 $07 DCRx → x=2, channel 1 $08 DCRx → x=3, channel 2 $09 DCRx → x=4, channel 3 Case x=0: $06 DCR0 Dep_current, bit [5:4] Deploy_timer, bit [7:6] Dep_expire_time, bit [3:2] Config. in DIAG, SAFING, SCRAP, ARMING state 00 - 11= not used 01 = 1.75A min 10 = 1.2A min 00 = no deploy 01 = 0.5ms 10 = 0.7ms 11 = 2ms 00 = 500ms 01 = 250ms 10 = 125ms 11 = 0ms Once the deployment is started, any DEP_EN = $0FF0 (that means deploy disable), is ignored. If the same command arrives before the deployment has been started, the deployment is really disabled and the deploy command ignored. Once the deployment is started, it can be interrupted by over-current in the low side GND loss SSM reset End of deployment time Status of the deployment is reported to the microcontroller through SPI read out in deployment status register: $13 DSRx register, x=0, channel 0 $14 DSRx register, x=1, channel 1 $15 DSRx register, x=2, channel 2 $16 DSRx register, x=3, channel 3 Case x=0, the same for the others: 90/201 DocID025845 Rev 2 AN4437 Deployment $13 DSR0 CH0STAT, bit [14] 0 = deployment not in progress 1 = deployment in progress CH0DS, bit [15] 0 = deployment not successful 1 = deployment successful If the deployment command lasts for the programmed deploy time, the flag CHxDS (deploy success) is set. MISO BIT 31 30 29 28 27 26 25 24 23 22 21 MISO SPIFLT DEPOK RSFLT WDTDIS_S ERSTATE POWERFLT FLT CONVRDY2 CONVRDY1 ERR_WID ERR_RID The event is also reported in GSW, DEPOK bit that is the "OR" of the deployment success of all the four channels. GSW BIT 10 9 8 7 6 5 4 3 2 1 0 GSW DEPOK, bit 30 (bit 9 of GSW) 0 = all DSR_x / CHxDS bits are = 0 (no deployment success on all channel) 1 = at least a deployment successful on the channels. In case the deploy success=1, this doesn't mean that the current is really passed through the squib for the programmed time. This bit means only that no inhibition of deployment has been received (in external safing engine FENH/FENL could have disabled the high side or the low side). In order to know if the current is really passed through the squib the Deploy Current_Mon registers have to be read. DocID025845 Rev 2 91/201 200 Deployment 8.1.5 AN4437 Deployment current monitor Each High Side (SFx) has a current comparator to indicate when the current flowing through is greater than the deployment current threshold (ITHDEPL=90%IDEPLx) and for each channel there is a timer (Current_Mon_Timer) that measures, with 16us resolution, how long the current is at high level. This parameter is considered useful for the microcontroller to identify if the deployment has been effective or not. During a deploy event, if the current falls momentarily below the threshold, the timer stops (timer pause), and continues to count as the current turns high. The time value obtained is stored into two registers, $1F DCMTS01 and $20 DCMTS23. Current_Mon_Timer is refreshed upon read or a new DEPCOM command on the channel is received for the channel. For this reason, the microcontroller reads the data after the deployment event and before a new deployment command. The current measurement stops at the end of the deployment time. $1F DCMTSxy (x=0, y=1) $20 DCMTSxy (x=2, y=3) Current_mon_timer_y bit [15:8] Current_mon_timer_x bit [7:0] Figure 44. Current measurement during deploy ,64+[ 1RUPDO RSHUDWLRQ 7LPHUSDXVH 7LPHUFRQWLQXHVIURPW ,7+'(3/ W W W W W W &XUUHQW 0RQ7LPHU W 92/201 &XUUHQW B0R QB7LPHU LQFUHDVHV 7LPHUSDXVH DocID025845 Rev 2 W &XUUHQW B0RQ B7LPHU FRQWLQXHVIURPWYDOXH *$3*36 AN4437 Deployment In case of a short to ground of the Low Side during the deployment, the current is limited by the High Side avoiding the device's damage. The same protection is available if an open load condition occurs, followed by a short to ground of the Low Side. If a deployment is required, but arming (internal safing logic or FENH/FENL signal) is not satisfied, deploy command is terminated following the expiration time criteria. If the arming condition is satisfied, but the deploy command is not received, the arming is disabled at the end of DWELL time. The remaining pulse stretcher time values are reported in the two registers AEPSTS_ARMi, i = 1,2. 8.2 $73 AEPSTS_ARM1 Timer count [9:0] $74 AEPSTS_ARM2 Timer count [9:0] Deployment driver protection In order to avoid to damage the IC due to eventual free wheeling, two protections are implemented. 1. after a deployment, once the High Side is switched off, the low side is kept on for tDEL_SD_LS (50 μs min.) in order to allow fly-back. 2. once low side is switched off, a protection against the overvoltage through a clamp structure is implemented. On the Low Side there is a current limitation and overcurrent protection circuit that attends limiting the current at ILIM_SR (2.2 A ÷ 4 A) IOC_SR (2.2 A ÷ 4 A) avoiding, in case of pin short to battery, the channel's damage. If the malfunction lasts over tFLT_ILIM_LS (100 μs typ) the whole channel (High and Low Side) is switched off until a new deployment command, via SPI_DEPEN occurs. The squib driver can stand the short to ground of the pins during the deployment, because the high side current is limited by the high side itself. It can manage also the case of SR short to ground after an open circuit, because it is able to detect the open circuit condition and then limiting the current overshoot as the open circuit disappears. In case of squib's intermittence during deployment phase, current limitation is ensured by the Low Side current limitation, ILIM_SR. If the condition lasts longer than tLIMOS (20 μs max) the High Side is switched off for tOFF_OS_HS (4 μs ÷ 12 μs) and then on again. This allows distinguish Open Load and Low Side short to battery cases and then proper manage them. DocID025845 Rev 2 93/201 200 Deployment driver example Table 4. Deployment driver example Register (1) (2) 15 14 13 12 11 10 DocID025845 Rev 2 $01 SYS_CFG I W X $04 SYS_STATE - R $2A WDTCR I W 2C WD_STATE - R 2B WDIT - W $04 SYS_STATE - R $7F SAF_ENABLE (I) W X X X X $80 SAF_REQ_MASK_1 D W 0 1 1 $93 SAF_REQ_TARGET_1 D W 0 1 $A6 SAF_RESP_MASK_1 D W 1 $B9 SAF_RESP_TARGET_1 D W $CC SAF_DATA_MASK_1 D W X X 0 X 0 X 1 X 1 9 8 0 1 0 0 0 0 0 0 1 0 0 0 7 0 0 6 0 0 5 0 0 4 X 1 3 0 1 2 1 0 Description 0 X 1 10: 01=short time 9: RSU switch 8, 7: 8 sample DC-squib-temp measure 6, 5: 4 sample 3: internal saf eng 2: VSF=20V 0:timeout disable 0 1 0 10, 9, 8 000=INIT 2, 1, 0: 010=RUN 0 0 1 14: WDTMODE = FAST 13÷7: WDTMIN = 400us 6÷0: WDT DELTA = 200us Deployment 94/201 8.3 10÷8: WD1_STATE=INITIAL Service watchdog A/B/A…. 0 1 0 10, 9, 8: 001=DIAG 2, 1, 0: 010=RUN 0 0 0 1 3÷0: SAF1 enabled, other disabled 0 0 0 0 0 14÷8: chose RID [6:0] bit 0 0 0 0 0 0 14÷8: RID [6:0] bit selection (50=RSU1) 0 0 0 0 0 0 0 15÷10: chose RSU status bit 0 0 0 0 0 0 0 0 15÷10: expected bit status of RSU 1 1 1 1 1 1 1 1 9÷0: 10 data RSO data bit selection 0 0 1 X X X X X X X X 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 AN4437 Register (2) 15 14 13 12 11 10 0 0 1 X 0 0 9 0 8 0 7 X 6 X 5 1 4 1 3 1 2 0 DocID025845 Rev 2 1 0 Description 1 14, 15: 00=arming on ARMP or ARMN 13: 1=last 16 bit in RESP_MASK/DATA_MASK 11: DATA RANGE LIMIT 0=disable 10: COMB 0=disabled 1 9, 8: DWELL 00 = 2048ms 5: 1=SAF_RECORD_1 assigned to ARM2INT 4: 1=SAF_RECORD_1 assigned to ARM1INT 3÷1: 101=SPI_CS 0: 1=SPI MISO answer in frame $EF SAF_CONTROL_1 D W $DF SAF_THRESHOL_1 D W Set threshold D W 0 X 0 0 1 1 0 0 1 1 0 1 1 0 0 1 $6E LOOP_MATRIX_ARM1 D W X X X X X X X X X X X X 1 0 1 0 3, 1: ARM1 assigned to L1 and L3 $6F LOOP_MATRIX_ARM2 D W X X X X X X X X X X X X 0 1 0 1 2, 4: ARM2 assigned to L0 and L2 X 9: ERBOOST=23V 7: ER_CHARGE ON X 6: ER_BOOST ON 5: VSUP ON 4: SPI_OFF not required $02 SYS_CTL - W X X X X X X 0 X 1 1 1 0 X X 95/201 Deployment $66 SAF_ALGO_CONF 15: counter reset 13÷10: 0011=NEGATIVE EVENT COUNT=3 9÷6: 0011=POSITIVE EVENT COUNT=3 5÷3: 011=-3 2÷0: 001=1 AN4437 Table 4. Deployment driver example (continued) (1) Register $05 POWER STATE - (2) R 15 14 13 12 11 10 0 0 0 0 0 0 9 0 8 1 7 1 6 X 5 X 4 0 3 1 2 1 1 1 Description 1 15: 0=VIN>VINGOOD expected 14: 0=CDD3V3>VDD3V3_UV expected 13: 0= CDD3V3<VDD3V3_OV expected 12: 0=ER_BOOST>ER_BOOST_OK expected 11: 0= VDD5>VDD5_UV expected 10: 0=VDD5<VDD5_OV expected 9: 0=VTHLSUP<VSUP<VTHHSUP expected 8: 1=ERBOOST ON expected 7: 1=ER_CHARGE ON expected 4: 0=ER_SWITCH OFF expected 3: 1=VDD5 ramp up or ON expected 2: 1= VSUP ramp up or ON expected 1: 1=VSUP ON expected 0: 1= VSF_EN=1 expected DocID025845 Rev 2 0 (3) 19 18 17 16 1 0 0 0 19: 1=WAKEUP>WU_on expected 18: 0=VBATMON>VBBAD expected 17: 0=VBATMON>VBGOOD expected 16: 0=VIN>VINBAD expected D W X X X X X 0 X X X X X X 0 0 1 0 10: blanktime=5ms 3÷0: 0010=PSI5async, 10bit, 125khz $4E RSCTRL (I) W X X X X X X X X X X X X 0 X 1 X 3: 0=CH1EN OFF 1: 1= CH0EN ON X 7, 6: 01=0.5ms deploy time 5, 4: 01=1.75A deploy current X 3, 2: 00=500ms deploy expiration time (I) W X X X X X X X X 0 1 0 1 0 0 AN4437 $4A RSCR1 $06 DCR_0 Deployment 96/201 Table 4. Deployment driver example (continued) (1) Register $07 DCR_1 $08 DCR_2 (I) (I) (2) W W 15 14 13 12 11 10 X X X X X X X X X 0 1 0 1 0 0 DocID025845 Rev 2 X 7, 6: 01=0.5ms deploy time 5, 4: 01=1.75A deploy current X 3, 2: 00=500ms deploy expiration time X 7, 6: 10=0.7ms deploy time 5, 4: 10=1.2A deploy current X 3, 2: 00=500ms deploy expiration time $15 DSR_2 - R 0 13: 0=CH2DD correct time/current expected $16 DSR_3 - R 0 13: 0=CH3DD correct time/current expected $31 SAFING_STATE D W $04 SYS_STATE (4) - R $6A ARM_STATE - R 0 1 0 1 0 1 1 1 1 0 0 15÷0: ACAC from DIAG to SAFING state 0 1 0 10, 9, 8: 010=SAFING expected 2, 1, 0: 010=RUN expected 1 3: 1=ARMINT_2 ok expected 2: 1=ARMINT_1 ok expected 97/201 15: FLT=0 expected 14: ON/OFF=1 expected 13÷10: LCID 0000 expected 9÷0: DATA Deployment 0 0 X 13: 0=CH1DD correct time/current expected 0 0 0 0 1 0 0 7, 6: 10=0.7ms deploy time 5, 4: 10=1.2A deploy current X 3, 2: 00=500ms deploy expiration time R 0 1 0 Description - 0 0 1 0 $14 DSR_1 1 1 0 1 13: 0=CH0DD correct time/current expected R X 1 2 0 - X X 3 R 1 X X 4 - 0 X X 5 $13 DSR_0 1 X X 6 W 0 X X 7 (I) 1 X X 8 $09 DCR_3 $50 RSDR0 (5) X X 9 AN4437 Table 4. Deployment driver example (continued) (1) Register $FF SAF_CC (5) $25 SPIDEPEN (2) - R S, A W 15 14 13 12 11 10 1 1 1 1 0 0 9 0 8 0 7 0 6 0 5 0 4 0 3 2 1 0 Description 1 1 1 1 3: 1=CC_4 expected 2: 1=CC_3 expected 1: 1=CC_2 expected 0: 1=CC_1 expected 1 1 1 1 $F00F=UNLOCK S, A W 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 3: 1=CH3DEPLOY 2: 1= CH2DEPLOY 1: 1= CH1DEPLOY 0: 1= CH0DEPLOY $25 SPIDEPEN - R 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 $0FF0=LOCK $13 DSR_0 - R 1 15: 1=CH0DS deployment successful $14 DSR_1 - R 1 15: 1=CH1DS deployment successful $15 DSR_2 - R 1 15: 1=CH2DS deployment successful $16 DSR_3 - R 1 15: 1=CH3DS deployment successful $12 DEPCOM Deployment 98/201 Table 4. Deployment driver example (continued) (1) DocID025845 Rev 2 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I) = no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 3. Further bit over the 16 standard. 4. Once a deployment successful, restart from point *5 if no parameters have to be changed. 5. repeat the sequence read $50 read $FF up to the data received is greater than threshold or lower than the -threshold defined in $DF for a number of time equal to that defined in $66. AN4437 AN4437 9 Diagnostic Diagnostic For all channels the following diagnostics are implemented: High voltage leak test, for SFx, SRx oxide isolation Leakage to battery/ground for SFx SRx with/ without squib Loop to loop short diagnostic Squib resistance measurement -leakage cancellation High squib resistance, 500 ÷ 2000 SSxy, SFx, VER voltage monitor High & Low FET diagnostics High side driver diagnostic Loss of ground High Side Safing FET diagnostic Deployment timer diagnostic These diagnostics data are elaborated by a 10 bit ADC converter. Diagnostic can be done in two ways: high level or low level. In high level diagnostic, the set-up for each requested measurement is managed by the device itself. In low level diagnostic, the set-up for each requested measurement is managed by an external logic, step by step. The choice of high level or low level diagnostic is done via SPI: $38 LPDIAGREQ DIAG_LEVEL, bit 16 Config. in DIAG, SAFING, SCRAP, ARMING state 0 = low level 1 = high level In the next figure the relevant blocks used for the diagnostic are reported. In particular there are a Voltage Regulator Current Monitor (VRCM) and three current generators that withstand diagnostic operations, ISRC (40 mA), ISNK (limit 70 mA), pulldown (1mA). DocID025845 Rev 2 99/201 200 Diagnostic AN4437 Figure 45. Diagnostic - blocks overview 'ULYHQWKURXJK /($.B&+6(/>@ /3',$*5(4UHJLVWHU 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU 95(6',$* ,65& P$ 66[\ 6$7%8&. %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ Y VXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0 YROWDJHUHJXODWRUFXUUHQWPRQLWRU 'ULYHQWKURXJK 5(6B0($6B&+6(/>@ /3',$*5(4UHJLVWHU *$3*36 100/201 DocID025845 Rev 2 AN4437 9.1 Diagnostic Low level 1. 2. 3. ER charge has to be previously turned ON before running the diagnostic; verify that the IC is in DIAG state, reading register $04; decide, writing the appropriate bit in reg. $38, which diagnostic mode is used; (1) (2) 1 2 $02 SYS_CTL $04 SYS_STATE 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - W X X X R 0 0 1 3 $38 LPDIAGREQ (I) W 0 4 $37 LPDIAGSTAT (3) 19 18 17 16 $3xDIAGCTRL_x X=A, B, C, D 4 (3) 19 18 17 16 1 0 X 1 1 0 0 X X X X 12:, VIN_TH_SEL depends on application; 11,10: VBATMON_TH_SEL depend on application; 9: ER_BST_V 0=23V, 1=33V 7: ER_CUR_EN 0=OFF, 1=ON 6: ER_BST_EN 0=OFF, 1=ON, 5: VSUP_EN 0=OFF, 1=ON 4: SPI_OFF 0=no effect, 1=POWER OFF required R 0 W 10, 9, 8 001=DIAG 2, 1, 0: 010=RUN 14:0 define the test, see next chapters 15: 0=LOW LEVEL diag setup 14:0 define the test, see next chapters 15: 0=LOW LEVEL diag X X X X X X X X 16:10 ADC address 6:0 ADC address 9:0 ADC result 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. In low level mode, the IC performs the measurement, following external requests. Each test set-up is driven, step by step, by the microcontroller and the timing for the measurement is fixed by the microcontroller too. DocID025845 Rev 2 101/201 200 Diagnostic 9.1.1 AN4437 High voltage leak test, oxide isolation IC-car chassis Figure 46. High voltage leak test, oxide isolation IC-car chassis 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU 95(6',$* ,65& P$ 6$7%8&. 66[\ 7KHYROWDJHRQ6)[DQG65[SLQVUDLVHDKLJKYDOXH 95(6',$*WKURXJK,65&FXUUHQWJHQHUDWRU 7KLVKLJKYROWDJHEUHDNVWKHHYHQWXDOR[LGHSUHVHQWRQWKH FKDVVLVRIWKHFDULI6)[RU65[DUHVKRUWFLUFXLWHGWRLW %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 This test is mandatory and verifies that no leakages are present on SFx or SRx pins when high voltage is applied. ISRC current generator is ON and addressed on SFx. If there is no leakage, SFx raises up to VRESDIAG and, being the impedance between SFx and SRx very low (squib connected), SRx follows SFx. Confirmation of this is done through an ADC measurement request of SFx voltage value. Supply= VRESDIAG SET-UP, see Figure 46. 102/201 DocID025845 Rev 2 AN4437 Diagnostic (1) (2) 15 14 13 12 11 10 9 3 $38 LPDIAGREQ (I) W 0 X 1 0 1 0 0 8 7 6 5 4 3 2 1 0 0 RES_MEAS_C LEAK_CHSEL 15: 0=DIAG LOW LEVEL HSEL 0100:1111 13:1= pull-down curr. OFF 0000 = ch0 all ch 0001 = ch1 12,11: 01=ISRC=40mA RES_MEAS_CHSEL, 0010 = ch2 OFF for the others 0011 = ch3 10: 0= ISINK all OFF 9,8:00 VRCM not connected 7:4 RES_MEAS_CHSEL 3:0 0100-1111 not selected 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I) = no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. SFx voltages and VRESGIAG are readable by the microcontroller through the ADC converter in the registers $3X DIAGCTRL_X → X=A, B, C, D Case X=A: (1) (2) $3A DIAGCTRL_A (3) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - W X X X X X X X X X ADCREQ_A $46 = SF0 $47 = SF1 $48 = SF2 $49 = SF3 $42 = VRESDIAG 19 18 17 16 0 0 ADCREQ_A 1 - R ADCREQ_A $46 = SF0 $47 = SF1 $48 = SF2 $49 = SF3 $42 = VRESDIAG ADCREQ_A 10bit ADC result 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I) = no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio of the ADC. In case of SFx and VRESDIAG, it is 15:1. DocID025845 Rev 2 103/201 200 Diagnostic AN4437 Table 5. VRESDIAG and SFx measurement of the value ratio ADC Divider Ratio Measurements 15:1 VRESDIAG √ SFx √ 10:1 7:1 4:1 1:1 As a conversion example, let's consider the case where the VRESDIAG conversion has been requested and the readout of the ADC register is done. VRESDIAG = 22.6 V measured ADC = (100110100)2 = (616)10 In order to obtain the result in Volt, being the ADC characteristic linear, [ [$'&ĺ  9 9 *$3*36 Considering the divider ratio (DR) stated above, the result is x * DR = 1.5 * 15 = 22.6 V Test result: In case of leakage on High (SFx) or Low Side (SRx), SFx voltage is not able to reach VRESDIAG and the microcontroller can detect the leakage problem, both on the high side or on the low side, with no possibility, at this stage, to distinguish which of them is involved in the problem. 9.1.2 VRCM test validation Before using VRCM block, that is used in many IC diagnostic, it is necessary a test for its validation. The test is done through short to battery and short to ground flag verification. Measurement set-up is composed by 2 steps: VRESDIAG supplied 104/201 DocID025845 Rev 2 AN4437 Diagnostic 1st step Figure 47. Diagnostic - VRCM test validation (1) 9(5SLQ IURP(QHUJ\5HVHUYH +6)(7GLDJQRVWLFKHFN95&0IXQFWLRQDOLW\ 95(6',$* 6DILQJ WUDQVLVWRU )LUVWZHXVH,65&FXUUHQWJHQHUDWRUWRFKHFN95&0EORFN ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65[ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 47. 3 $38 LPDIAGREQ (1) (2) (I) W 15 14 13 12 11 10 9 0 X 1 0 0 8 7 6 5 4 3 2 1 0 1 VRCM RES_MEAS LEAK_CHSE 15: 0=DIAG LOW LEVEL L _CHSEL 13: 1=pulldown curr OFF 01 0000 = ch0 0000 = ch0 all ch 0001 = ch1 0001 = ch1 12,11: 01=ISRC=40mA 0010 = ch2 0010 = ch2 (RES_MEAS_CHSEL), 0011 = ch3 0011 = ch3 OFF for the others 10: 0= ISINK all OFF 9,8:01 VRCM connected to SFx (LEAK_CHSEL ch) 7:4 RES_MEAS_CHSEL 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R=READ / W = WRITE RES_MEAS_CHSEL, bit[7:4] and LEAK_CHSEL, bit[3:0] must refer to the same channel. DocID025845 Rev 2 105/201 200 Diagnostic AN4437 Test result: Being ISRC and VRCM connected to SFx, if VRCM works correctly, short to battery, readable in LPDIAGSTAT register, is asserted for the channel selected: (1) 4 $37 LPDIAGSTAT (3) 19 18 17 16 0 X (2) 15 14 13 12 11 10 9 R R 0 8 7 6 5 4 3 2 1 0 RES_MEAS_C X HSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 X 1 1 LEAK_CHSEL 19: 0= LOW LEVEL 5: 1=STB expected 0000 = ch0 4: 1=test on SFx 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R=READ / W = WRITE 3. further bit over the 16 standard If the first step of VRCM test is passed, proceed with the second step. 2nd step Figure 48. Diagnostic - VRCM test validation (2) 9(5SLQ IURP(QHUJ\5HVHUYH /6)(7GLDJQRVWLF FKHFN95&0IXQFWLRQDOLW\ 95(6',$* 6DILQJ WUDQVLVWRU 6HFRQGZHXVH ,6,1.FXUUHQW JHQHUDWRUWRFKHFN95&0EORFN ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 106/201 DocID025845 Rev 2 *$3*36 AN4437 Diagnostic For set up, refer to Figure 48. (1) (2) 15 14 13 12 11 10 9 3 $38 LPDIAGREQ (I) W 0 X 1 0 0 8 7 6 5 4 1 VRCM RES_MEAS_ CHSEL 10 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 3 2 1 0 LEAK_CHSEL 15: 0=DIAG LOW LEVEL 13: 1=pulldown curr OFF all ch 0000 = ch0 12,11: 00/11=ISRC OFF 0001 = ch1 all channel 0010 = ch2 10: 1= ISINK ON 0011 = ch3 (RES_MEAS_CHSEL) 9,8:10 VRCM connected to SRx (LEAK_CHSEL) 7:4 RES_MEAS_CHSEL 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE RES_MEAS_CHSEL, bit[7:4] and LEAK_CHSEL, bit[3:0] must refer to the same channel. Test result: Being ISNK and VRCM connected to SRx, if VRCM works correctly, short to ground, readable in LPDIAGSTAT register, is asserted for the channel selected: (1) 4 $37 LPDIAGSTAT (3) 19 18 17 16 0 X (2) R R 0 15 14 13 12 11 10 9 8 7 RES_MEAS_ CHSEL 0000 = ch0 X 0001 = ch1 0010 = ch2 0011 = ch3 6 1 5 X 4 3 2 1 0 0 LEAK_CHSEL 19: 0= LOW LEVEL 6: 1=STG expected 0000 = ch0 4: 0=test on SRx 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 3. further bit over the 16 standard If the second step of VRCM test is passed too, VRCM test is validated. DocID025845 Rev 2 107/201 200 Diagnostic 9.1.3 AN4437 Leakage test - High side Figure 49. Diagnostic - leakage test - high side 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU +6/HDNDJHWHVW 95(6',$* ,SXOOGRZQ 2))RQORRSXQGHUPHDVXUH 21RQWKHRWKHUV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[6)[SLQYROWDJHWR Y UHDGFXUUHQWWKURXJK6)[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW (0,ORZSDVV ILOWHU +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65[ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 49. ISRC and ISINK are kept off and VRCM is connected to SFx, chosen through LEAK_CHSEL. (1) (2) 15 14 13 12 11 10 9 3 $38 LPDIAGREQ (I) W 0 X 0 0 0 0 0 8 7 6 5 4 3 2 1 0 1 RES_MEAS_ LEAK_CHSEL 15: 0=DIAG LOW LEVEL CHSEL 13: 0=pulldown curr OFF for VRCM ch; ON the 0000 = ch0 0100:1111 others 0001 = ch1 12,11: 00/11=ISRCOFF on 0010 = ch2 all channel 0011 = ch3 10: 0= ISINK all OFF 9,8:01 VRCM to SFx (LEAK_CHSEL) 7:4 0100-1111 no selection 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 108/201 DocID025845 Rev 2 AN4437 Diagnostic Test result: If there is no leakage on the high side, SFx voltage is equal to VREF=2.5V and no current is detected by VRCM itself. SFx voltage is readable addressing the ADC read out on it. The registers involved in this operation are the four DIAGCTRL_x $3X DIAGCTRL_X → X = A, B, C, D Case X = A: (1) (2) $3A DIAGCTRL_A 8 7 6 5 4 3 2 1 0 - W X X X X X X X X X ADCREQ_A $46 = SF0 $47 = SF1 $48 = SF2 $49 = SF3 19 18 17 16 1 0 0 ADCREQ_A (3) 15 14 13 12 11 10 9 - R ADCREQ_A $46 = SF0 $47 = SF1 $48 = SF2 $49 = SF3 ADCREQ_A 10bit ADC result 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 3. further bit over the 16 standard Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio of the ADC. In case of SFx and VRESDIAG, it is 15:1 (see Table 5). In case of a leakage (to ground or to battery), VRCM will sink or source a current to maintain SFx at VREF. As a consequence, STG or STB is set: (1) (2) 4 $37 LPDIAGSTAT R (3) R 19 18 17 16 0 X 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RES_MEAS_ X 1 1 1 LEAK_CHSEL CHSEL 0000 = ch0 0100-1111 0001 = ch1 0010 = ch2 0011 = ch3 19: 0 = LOW LEVEL 6: 1=STG if leak vs GND 5: 1= STB if leak vs BATT 4: 1 = test on SFx 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 3. further bit over the 16 standard Note: Pull-down current (1mA) is active on all the channels except the one under analysis. So, the STG requires further investigation to understand if it comes from a real short to ground of the channel itself or it comes from a short between the channel itself and another one. DocID025845 Rev 2 109/201 200 Diagnostic 9.1.4 AN4437 Leakage test - low side Figure 50. Diagnostic - leakage test - low side 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU /6/HDNDJHWHVW 95(6',$* ,SXOOGRZQ 2))RQORRSXQGHUPHDVXUH 21RQWKHRWKHUV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[65[SLQYROWDJHWR Y UHDGFXUUHQWWKURXJK65[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 50. ISRC and ISINK are kept off and VRCM is connected to SRx, chosen through LEAK_CHSEL. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 0 X 0 0 0 0 1 0 RES_MEAS_CHSEL LEAK_CHSEL 15: 0=DIAG LOW LEVEL 13: 0=pulldown curr OFF for 0100:1111 0000 = ch0 VRCM ch; ON the others 0001 = ch1 12,11: 00/11=ISRCOFF on 0010 = ch2 all channel 0011 = ch3 10: 0= ISINK all OFF 9,8:10 VRCM to SRx 7:4 0100-1111 no selection 3:0 channel selection 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 110/201 DocID025845 Rev 2 AN4437 Diagnostic Test result: If there is no leakage on the high side, SRx voltage is equal to VREF=2.5V and no current is detected by VRCM itself. Only if the squib is connected, SFx and SRx pin are at the same voltage, so SRx voltage is readable indirectly through SFx voltage, as done in case of high side leakage test. SFx voltage is readable addressing the ADC read out on it. The registers involved in this operation are the four DIAGCTRL_x. $3X DIAGCTRL_X → X=A, B, C, D Case X = A: (1) (2) $3A DIAGCTRL_A 8 7 6 5 4 3 2 1 0 - W X X X X X X X X X ADCREQ_A $46 = SF0 $47 = SF1 $48 = SF2 $49 = SF3 19 18 17 16 1 0 0 ADCREQ_A (3) 15 14 13 12 11 10 9 - R ADCREQ_A $46 = SF0 $47 = SF1 $48 = SF2 $49 = SF3 ADCREQ_A 10bit ADC result 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 3. further bit over the 16 standard. Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio of the ADC. In case of SFx and VRESDIAG, it is 15:1 (see Table 5). If the squib between SFx and SRx pin is not connected, SRx voltage read out is not possible, as it is not mapped into ADC request command. DocID025845 Rev 2 111/201 200 Diagnostic AN4437 In case of a leakage (to ground or to battery), VRCM will sink or source a current to maintain SFx at VREF. As a consequence, STG or STB is set: (1) 4 $37 LPDIAGSTAT (3) 19 18 17 16 0 X (2) 15 14 13 12 11 10 9 R 8 RES_MEAS_ CHSEL 0100-1111 R 0 7 6 X 1 5 4 1 3 2 1 0 0 LEAK_CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 19: 0= LOW LEVEL 6: 1=STG if leak vs GND 5: 1= STB if leak vs BATT 4: 0=test on SFx 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE 3. Further bit over the 16 standard. Note: Pull-down current (1mA) is active on all the channels except the one under analysis. So, the case of STG detection, further investigation is necessary to understand if it comes from a real short to ground of the channel or it comes from a short of the channel with another one. 9.1.5 Leakage test - low side IPD Figure 51. Diagnostic - leakage test - low side IPD 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU /6/HDNDJHWHVW 95(6',$* ,65& ,SXOOGRZQ 21RQORRSXQGHUPHDVXUH 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW FRPSDUHFXUUHQWZLWKDWKUHVKROG67* P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 112/201 DocID025845 Rev 2 *$3*36 AN4437 Diagnostic For set up, refer to Figure 51. After having verified that no HS/LS leakage is present, it is possible to verify if IPD is correctly working. VRCM is connected to SRx, chosen through LEAK_CHSEL. IPD is switched on for that channel. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 0 X 0 0 0 0 1 1 RES_MEAS_ LEAK_CHSEL 15: 0=DIAG LOW LEVEL CHSEL 13: 0=pulldown curr OFF for 0000 = ch0 VRCM ch; ON the others 0100:1111 0001 = ch1 12,11: 00/11=ISRC OFF on all 0010 = ch2 channel 0011 = ch3 10: 0= ISINK all OFF 9,8:11 VRCM to SRx 7:4 0100-1111 no selection 3:0 channel selection 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE Test result: If IPD is working, SRx voltage is equal to VOUT_VRCM and VRCM shows STG. If, in this condition, STG is not set, it means that there is something not correctly working in IPD. (1) 4 $37 LPDIAGSTAT (3) 19 18 17 16 0 X (2) 15 14 13 12 11 10 9 8 R R 0 RES_MEAS_CHSEL 0100-1111 7 6 5 4 3 2 1 0 X 1 1 0 LEAK_CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 19: 0= LOW LEVEL 6: 1=STG if OK 5: 0 STB 4: 1=test on SRx 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE 3. Further bit over the 16 standard. DocID025845 Rev 2 113/201 200 Diagnostic 9.1.6 AN4437 Short between loops Supposing the external squib is connected, a short to ground flag of SRx or SFx can be read as: Short of the pin with SR or SF of another channel, both SR and SF Real short of the pin SRx or SFx to GND Below, four possible cases are presented. Case 1 Figure 52. Diagnostic - short between loops, HSi, HSx, ix (case 1) 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU 6KRUWEHWZHHQORRS 6)LDQG6)[ZLWKL[ 6TXLERQ6)[FRQQHFWHG 95(6',$* ,65& P$ 66 %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6) 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW (0,ORZSDVV ILOWHU +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65 , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6* 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 95(6',$* ,65& P$ 66 66 %\SDVV Q) 6)[ &DVHL 6)VKRUWZLWKDQRWKHUKLJKVLGH6)[[DQGVTXLE RQFKDQQHO[FRQQHFWHG ,SXOOGRZQ 2))RQORRSXQGHUPHDVXUH21RQWKHRWKHUV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[6)[SLQYROWDJHWRY UHDGFXUUHQWWKURXJK6)[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG 5/HDN Q) [1 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ 5HVXOW 67*RQ6) ,SXOOGRZQ 65[ , P$ Q) 6* 6* ,6,1. *1'$ ,OLPLW P$ *$3*36 114/201 DocID025845 Rev 2 AN4437 Diagnostic SFi and SFx, ix, squib on channel x connected. If the squib on SFx is not connected, there is no path between SFi (0 in the example) and ground through SFx, squib, SRx and pull down current generator, so the short of a high side SFi with another high side SFx is not detectable. Case 2 Figure 53. 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DocID025845 Rev 2 115/201 200 Diagnostic AN4437 Case 3 Figure 54. Diagnostic - short between loops, LSi, HSx, ix (case 3) 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU 6KRUWEHWZHHQORRS 65LDQG6)[ZLWKL[ 6TXLERQ6)[FRQQHFWHG 95(6',$* ,65& P$ 66 %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6) 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW (0,ORZSDVV ILOWHU +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65 , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6* 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 95(6',$* ,65& P$ 66 66 %\SDVV Q) 6)[ &DVHL 65VKRUWZLWKDKLJKVLGH6)[[DQGVTXLERQ FKDQQHO[FRQQHFWHG ,SXOOGRZQ 2))RQORRSXQGHUPHDVXUH21RQWKHRWKHUV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[65 SLQYROWDJHWRY UHDGFXUUHQWWKURXJK65[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG 5/HDN Q) [1 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ 5HVXOW 67*RQ65 ,SXOOGRZQ 65[ , P$ Q) 6* 6* ,6,1. *1'$ ,OLPLW P$ *$3*36 SRi and SFx, ix, squib on channel x connected If the squib on SFx, is not connected, there is no path between SRi (0 in the example) and ground through SFx, squib, SRx and pull down current generator, so the short of a low side SRi with another high side SFx is not detectable. 116/201 DocID025845 Rev 2 AN4437 Diagnostic Case 4 Figure 55. Diagnostic - short between loops, LSi, LSx, ix (case 4) 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU 6KRUWEHWZHHQORRS 65LDQG65[ZLWKL[ 95(6',$* ,65& P$ 66 %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6) 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW (0,ORZSDVV ILOWHU +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65 , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6* 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 95(6',$* ,65& P$ 66 66 %\SDVV Q) 6)[ &DVHL 65VKRUWZLWKDQRWKHUORZVLGH65[[,SXOOGRZQ 2))RQORRSXQGHUPHDVXUH21RQWKHRWKHUV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[65 SLQYROWDJHWRY UHDGFXUUHQWWKURXJK65[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG 5/HDN Q) [1 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ 5HVXOW 67*RQ65 ,SXOOGRZQ 65[ , P$ Q) 6* 6* ,6,1. *1'$ ,OLPLW P$ *$3*36 SRi and SRx, ix, squib on channel x not necessary. If a STG has been detected, to identify its origin, it is necessary to understand if it is a real short to ground of the channel or a short between loops. With respect to the case of STG investigation, in this test the pull down current generators are switched off for all channels. If the STG is still present, it means a real STG of the channel under test, otherwise the STG is a short between loops. DocID025845 Rev 2 117/201 200 Diagnostic AN4437 Figure 56. Diagnostic - HS short to Ground 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU 6KRUWEHWZHHQORRS 6)LUHDOO\67* 95(6',$* ,65& P$ 66 %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6) 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW (0,ORZSDVV ILOWHU +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65 , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6* 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 95(6',$* ,65& P$ 66 66 %\SDVV Q) 6)[ &DVHL 6)67* 5/HDN Q) [1 ,SXOOGRZQ 2))DOOFKDQQHOV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[6)[SLQYROWDJHWRY UHDGFXUUHQWWKURXJK6)[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ 5HVXOW 67*RQ6) ,SXOOGRZQ 65[ , P$ Q) 6* 6* ,6,1. *1'$ ,OLPLW P$ *$3*36 Real SFi STG in case of STG flag still set and SR pull-down current switched off for all channels. 118/201 DocID025845 Rev 2 AN4437 Diagnostic Figure 57. Diagnostic - LS short to Ground 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU 6KRUWEHWZHHQORRS 65LUHDOO\67* 95(6',$* ,65& P$ 66 %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6) 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65 , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6* 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 95(6',$* ,65& P$ 66 66 %\SDVV Q) 6)[ &DVHL 6567* 5/HDN Q) [1 ,SXOOGRZQ 2))DOOFKDQQHOV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[65[SLQYROWDJHWRY UHDGFXUUHQWWKURXJK65[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ 5HVXOW 67*RQ65 ,SXOOGRZQ 65[ , P$ Q) 6* 6* ,6,1. *1'$ ,OLPLW P$ *$3*36 Real SRi STG in case of STG flag still set and SR pull-down current switched off for all channels. In order to understand which pairs loops are involved in the short, each pair has to be checked. Correspondent set up is done by setting $38 LPDIAG properly: DocID025845 Rev 2 119/201 200 Diagnostic AN4437 (1) (2) 15 14 13 12 11 10 9 3 $38 LPDIAGREQ (I) W 0 0 1 0 0 8 7 6 5 4 3 2 1 0 0 0/1 1/0 RES_MEA LEAK_CHSEL 15: 0=DIAG LOW LEVEL S_CHSEL 0000 = ch0 14: 0=ISRC=40mA 0100:1111 0001 = ch1 13: 1=pulldown curr OFF for all channels 0010 = ch2 12,11: 00/11=ISRCOFF on 0011 = ch3 all channel 10: 0= ISINK all OFF 9,8:01= VRCM to SFx 10 VRCM to SRx 7:4 0100-1111 no selection 3:0 channel selection 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 120/201 DocID025845 Rev 2 AN4437 9.1.7 Diagnostic Squib resistance measurement IC allows measuring the squib resistance value in the range of 1 Ω ÷10 Ω with overall 8% precision. This is a two-step process: 1st step Figure 58. Diagnostic - Squib resistance measurement (1) IURP(QHUJ\5HVHUYH 9(5SLQ VWHSVTXLEUHVLVWDQFHPHDVXUH 95(6',$* 6DILQJ WUDQVLVWRU ,65& P$ ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 58. Through this set-up, the ISRC is connected to the SFx. The squib is correctly connected between SFx and SRx. SRx is internally connected to ISINK that is able to sink the current. DocID025845 Rev 2 121/201 200 Diagnostic AN4437 (1) (2) 15 14 13 12 11 10 9 3 $38 LPDIAGREQ (I) W 0 X 1 0 1 1 0 8 7 6 5 4 3 2 1 0 0 RES_MEAS LEAK_CHSEL 15: 0=DIAG LOW LEVEL _CHSEL 0100:1111 13:1= pull down curr OFF all 0000 = ch0 ch 0001 = ch1 12,11: 01=ISRC=40mA (RES_MEAS_CH), OFF in 0010 = ch2 the others 0011 = ch3 10: 1= ISINK (RES_MEAS_CH) ON, OFF the others 9,8:00 VRCM not connected 7:4 RES_MEAS_CHSEL 3:0 0100-1111 not selected 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. The first step of the measurement is the read out of the voltage between SFx and SRx that is named resistance into ADC addressing. This parameter is readable by the microcontroller, via 10bit ADC, through a dedicated request. The registers to be read are still the four DIAGCTRL_x. Again the explanation of the first register (x=A) is true also for the other three registers: $3X DIAGCTRL_X → X=A, B, C, D Case X=A: (1) $3A DIAGCTRL_A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - W X X X X X X X X X ADCREQ_A $06 = squib x resistance - R ADCREQ_A $06 = squib x resistance 19 18 17 16 1 0 0 ADCREQ_A (3) (2) ADCREQ_A 10bit ADC result 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Once read the ADC measurement, to obtain the value it is necessary to consider the divider ratio of the ADC. In case of resistance x, it is 1:1. Table 6. Squib x resistance measurement of the value ratio ADC Measurements Divider Ratio 15:1 Squib x resistance 122/201 10:1 7:1 4:1 1:1 √ DocID025845 Rev 2 AN4437 Diagnostic 2nd step Figure 59. Diagnostic - Squib resistance measurement (2) 9(5SLQ IURP(QHUJ\5HVHUYH VWHSVTXLEUHVLVWDQFHPHDVXUH 95(6',$* 6DILQJ WUDQVLVWRU ,65& P$LQ%<3$66 ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65[ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 59. The set-up is the ISRC connected to the SRx. The squib is correctly connected between SFx and SRx. SRx is internally connected to ISINK that is able to sink the current. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 0 X 1 1 0 1 0 0 RES_MEAS_ LEAK_CHSEL 15: 0=DIAG LOW LEVEL CHSEL 0100:1111 13:1= pull down curr OFF all ch 0000 = ch0 12,11: 10=ISRC=40mA by 0001 = ch1 pass (RES_MEAS_CH), 0010 = ch2 OFF in the others 0011 = ch3 10: 1= ISINK (RES_MEAS_CH) ON, OFF the others 9,8:00 VRCM not connected 7:4 RES_MEAS_CHSEL 3:0 0100-1111 not selected 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE. DocID025845 Rev 2 123/201 200 Diagnostic AN4437 The second step of the measurement is the read out of the voltage between SFx and SRx, named resistance into ADC addressing. This measurement takes into account the leakage that may be present on SFx SRx pins. As the previous measurement, also this is readable by the microcontroller, via 10bit ADC, through the same dedicated request. The registers to be read are still the four DIAGCTRL_x. Again the explanation of the first register (x=A) is true also for the other three registers: $3X DIAGCTRL_X → X=A, B, C, D Case X=A: (1) (2) $3A DIAGCTRL_A - 15 14 13 12 11 10 9 W X X X X X X 8 7 6 5 4 3 2 1 0 X X X ADCREQ_A $06 = squib x resistance 1 0 ADCREQ_A 19 18 17 16 (3) 0 - R ADCREQ_A ADCREQ_A 10bit ADC result $06 = squib x resistance 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Once read the ADC measurement, to obtain the value it is necessary to consider the divider ratio of the ADC. In case of resistance x, it is 1:1. Measurements Divider Ratio 15:1 10:1 7:1 4:1 Squib x resistance 1:1 √ In LPDIAGSTAT is possible to verify on which channel the resistance measurement has been performed: (1) 4 $37 LPDIAGSTAT (3) 19 18 17 16 (2) R R 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 RES_MEAS_CH X X X X LEAK_CHSEL 19: 0= LOW LEVEL SEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE. 3. Further bit over the 16 standard. 124/201 1 DocID025845 Rev 2 AN4437 Diagnostic Having the microcontroller these two measurements (that are two voltage drops across SF and SR), the squib resistance is so calculated: ¨ 9RXW 6)[ í 65[ í 6)[ í 65[ *$3*36 ¨ 9RXW 5VTXLE * ,65& *$3*36 G = 5.25 ±2% differential amplifier gain ISRC = 40 mA ±5% Let's consider an example where ADC1ST CONVERSION = (0100111000)2 = (312)10 ADC2ND CONVERSION = (0010000001)2 = (129)10 ΔADC = 312-129 = 183 In order to obtain the result in Volt, being the ADC characteristic linear, 9 [ ¨ $'& ĺ[ 9 *$3*36 In order to obtain resistance value, considering typical factors 5VTXLE [ 9 * ,65& P$ ȍ *$3*36 Note: Immediately after the ADC read-out, ISRC is automatically switched OFF to reduce the power consumption. DocID025845 Rev 2 125/201 200 Diagnostic 9.1.8 AN4437 High squib resistance diagnostic The aim of the test is to understand if the squib resistor is below 200 Ω, between 500 Ω and 2000 Ω or beyond 5000 Ω In case of a very high squib resistance, there is the possibility to set a lower ISRC current, through ISRC_CURR_SEL bit, bit 14, $LPDIAGREQ. In this way, ADC maintains a good dynamic. The following description, referred to ISRC = 40 mA, is true also in case of ISRC = 8 mA. Figure 60. Diagnostic - High squib resistance diagnostic 9(5SLQ IURP(QHUJ\5HVHUYH +LJKVTXLEUHVLVWDQFHYDOXHGHWHFWLRQ 6DILQJ WUDQVLVWRU 95(6',$* ,65& :LWK95&0EORFNZHGHWHFW 6TXLEUHVLVWDQFHLQORZUDQJHȍ·ȍ 6TXLEUHVLVWDQFHLQ+LJKUDQJH.ȍ·.ȍ P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWR ȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 60. The set-up is the ISINK connected to the SRx. The squib is correctly connected between SFx and SRx. SRx is internally connected to ISINK that is able to sink the current. 126/201 DocID025845 Rev 2 AN4437 Diagnostic (1) (2) 15 14 13 12 11 10 9 3 $38 LPDIAGREQ (I) W 0 X 1 0/1 0/1 1 0 8 7 6 5 4 1 RES_MEAS_ CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 3 2 1 0 LEAK_CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 15: 0=DIAG LOW LEVEL 13:1= pull down curr OFF all ch 12,11: 00 or 11 ISRC OFF all channels 10: 1= ISINK (RES_MEAS_CH) ON, OFF the others 9,8:01 VRCM SFx LEAK_CHSEL) 7:4 RES_MEAS_CHSEL 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Note: ISINK and VRCM have to be addressed to the same channel, that means RES_MEAS_CHSEL, bit[7:4] and LEAK_CHSEL, bit[3:0]are equal. If there is a wrong selection in the two fields RES_MEAS_CHSEL / LEAK_CHSEL, there is no notice of the mistake. Test result: Through this set-up, the VRCM is connected to SFx and ISINK to SRx. Current flowing through SFx is measured and compared with ISRlow, ISRhigh thresholds to identify in which range the resistor measured is. HSR HIGH = RSqhigh = 2 kΩ ÷ 5 kΩ HSR LOW = RSqlow = 200 Ω ÷ 500 Ω In case of low resistance value, VRCM sees a path from SRx and GND so STG (very low impedance towards ground) could be detected. Read out of these bit has to be done before the next diagnostic request, because these bits are not latched. DocID025845 Rev 2 127/201 200 Diagnostic AN4437 (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 15 14 13 12 11 10 9 R R 0 8 7 0/1 0/1 RES_MEAS_ X CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 6 5 0/1 X 4 3 2 1 0/1 LEAK_CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. 128/201 DocID025845 Rev 2 0 19: 0= LOW LEVEL 13: 0 = resis < HSR HIGH 1 = resis > HSR HIGH 12: 0 = resis < HSR LOW 1 = resis > HSR LOW 6: STG 1=yes/0=no 4:VRCM connected to: 0= SR 1=SF AN4437 9.1.9 Diagnostic High side FET diagnostic The test is possible only in the diagnostic phase (see Section 4.2). These are two tests performed separately for the high side and the low side, with dedicated commands. Note: Before running this test, VRCM has to be previously validated (see Section 9.1.2: VRCM test validation) and leakage tests have to be already performed with no fails found (see Section 9.1.3: Leakage test - High side and Section 9.1.4: Leakage test - low side). Only if these mentioned tests have been successfully done, the HIGH SIDE (and LOW SIDE) FET tests can be performed. Figure 61. Diagnostic - High side FET diagnostic 9(5SLQ IURP(QHUJ\ 5HVHUYH 7R6<1&%2267 +6)(7GLDJQRVWLF FKHFN)(7 6DILQJ WUDQVLVWRU 5 ,65& P$ 95&0FRQQHFWHGWR6)[ ([WHUQDOGLRGHSOXVUHVLVWDQFHELDVWKH66[\SLQYROWDJH DQGOLPLWWKHPD[LPXPFXUUHQWOHYHOGXULQJWHVW 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 61. ISRC and ISINK are kept off and VRCM is connected to SFx, chosen through LEAK_CHSEL. DocID025845 Rev 2 129/201 200 Diagnostic AN4437 (1) (2) 15 14 13 12 11 10 9 3 $38 LPDIAGREQ (I) W 0 X 1 0 0 0 0 8 7 6 5 4 3 2 1 0 1 RES_MEAS_ LEAK_CHSEL 15: 0=DIAG LOW LEVEL CHSEL 0000 = ch0 13: 1=pulldown curr 0100:1111 0001 = ch1 OFF for all ch. 0010 = ch2 12,11: 00/11=ISRCOFF 0011 = ch3 on all channel 10: 0= ISINK all OFF 9,8: 01 VRCM to SFx (LEAK_CHSEL) 7:4 0100-1111 no selection 3:0 LEAK_CHSEL 3 $36 SYSDIAGREQ D W X X X X X X X X 0 1 1 1 0111: DSTEST=HSFET active 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Test result: High side FET test turns ON the HS power: if it turns ON correctly, SFx is connected to SSxy which is at VER voltage through the resistor R in parallel to the safing FET. During the test, the device monitors the current flowing through VRCM. If the high side FET works properly, this current exceeds the thresholds IHSFET (high side) and the channel is immediately turned off, IHSFET = 1.8mA ± 10% In case the current doesn't exceed the limit mentioned, after a fixed time, TFETTIMEOUT, the test is terminated and the output is turned off. TFETTIMEOUT = 200 μs During TFETTIMEOUT period, FET activation is flagged through a bit, FETON, readable via SPI: In any condition, current in SFx doesn't exceed ISVRCM and during the FET test the energy provided to the squib is limited at EFETtest. ISVRCM: ILIM_SRC = -20mA ÷ -10mA; ILIM_SNK = 10mA ÷ 20mA EFETtest < 170μJ 130/201 DocID025845 Rev 2 AN4437 Diagnostic (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 0 X R 15 14 13 12 11 10 9 0/1 R 0 8 7 6 5 4 3 2 1 0 RES_MEAS_C 0 0/1 0/1 1 LEAK_CHSEL HSEL 0000 = ch0 0100-1111 0001 = ch1 0010 = ch2 0011 = ch3 19: 0= LOW LEVEL 15: 0=FET OFF during diag 1= 0=FET ON during diag 6: 0=STG 5: 1=STB 4: 1=test on SFx 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Possible results for high side: STB=1 & STG=0 ok STB=0 or STG=1 missing SSxy connection during FET test or high side not switched ON or short to GND during FET test STG & STB, after FET test, are latched. They are cleared through a new LPDIAGREQ or a new SYSDIAGREQ. Note: If VRCM is not previously connected to the SFx and the test is run, a dangerous condition could happen. In case of SRx shorted to GND, when the HS is turned ON, even if the current flowing through the squib is greater than IHSFET, the HS is not immediately turned off and the current flows through the squib until TFETTIMEOUT expires: this could determine an undesired deployment. Figure 62. Diagnostic - High side FET diagnostic, SR short to GND P)WR P) 9(5 6DILQJ WUDQVLVWRU 95(6',$* 66[\ KLJKVLGH Q) 6)[ Q)WR X) 5VTXLE 65[ Q)WR X) 6*[ *1'$ *$3*36 DocID025845 Rev 2 131/201 200 Diagnostic 9.1.10 AN4437 Low side FET diagnostic Figure 63. Diagnostic - Low side FET diagnostic 9(5SLQ IURP(QHUJ\ 5HVHUYH /6)(7GLDJQRVWLF FKHFN)(7 95(6',$* 6DILQJ WUDQVLVWRU 95&0FRQQHFWHGWR65[ 5 ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65[ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 63. ISRC and ISINK are kept off and VRCM is connected to SRx, chosen through LEAK_CHSEL. (1) (2) 3 $38 LPDIAGREQ 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 (I) W 0 X 1 0 0 0 1 0 RES_MEA LEAK_CHSE 15: 0=DIAG LOW LEVEL S_CHSEL L 13: 1=pulldown curr OFF for all ch. 0100:1111 0000 = ch0 12,11: 00/11=ISRCOFF on all channel 0001 = ch1 10: 0= ISINK all OFF 0010 = ch2 9,8: 10 VRCM to SRx 0011 = ch3 (LEAK_CHSEL) 7:4 0100-1111 no selection 3:0 LEAK_CHSEL 3 $36 SYSDIAGREQ D W X X X X X X X X 1 0 0 0 1000: DSTEST=LSFET active 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 132/201 DocID025845 Rev 2 AN4437 Diagnostic Test result: Low side FET test turns ON the low side. If the low side turns ON correctly, SRx is connected to SGxy. During the test, the device monitors the current flowing through VRCM. If the FET works properly, this current exceeds the thresholds ILSFET and the channel is immediately turned off, ILSFET = 450μA ± 10% In case the current doesn't exceed the limit mentioned, after a fixed time, TFETTIMEOUT, the test is terminated and the output is turned off. TFETTIMEOUT = 200 μs During TFETTIMEOUT period, FET activation is flagged through a bit, FETON, readable via SPI. In any condition, current in SRx doesn't exceed ISVRCM and during the FET test the energy provided to the squib is limited at EFETtest. ISVRCM: ILIM_SRC = -20mA ÷ -10mA; ILIM_SNK = 10mA ÷ 20mA EFETtest < 170uJ (1) 4 $37 LPDIAGSTAT (3) 19 18 17 16 0 X (2) R 15 14 13 12 11 10 9 0/1 R 0 8 7 6 5 4 3 2 1 0 RES_MEAS_ 0 0/1 0/1 1 LEAK_CHSEL CHSEL 0000 = ch0 0100-1111 0001 = ch1 0010 = ch2 0011 = ch3 19: 0= LOW LEVEL 15: 0=FET OFF during diag 1= 0=FET ON during diag 6: 1=STG 5: 0=STB 4: 0=test on SRx 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Possible results for low side: STB=0 and STG=1 ok STB=1 or STG=0 short to battery in LS or low side not switched ON. Note: Ground loss (SGxy) is not detected through FET test, because there is a diode between SGxy and the substrate. STG & STB, after FET test, are latched. They are cleared through a new LPDIAGREQ or a new SYSDIAGREQ. Note: If VRCM is not previously connected to the SRx and the test is run, a dangerous condition could happen. In case of SFx shorted to SSxy, when the LS is turned ON, even if the current flowing through the squib is greater than ILSFET, the LS is not immediately turned off and the current DocID025845 Rev 2 133/201 200 Diagnostic AN4437 flows through the squib until TFETTIMEOUT expires: this could determine an undesired deployment. Figure 64. Diagnostic - Low side FET diagnostic, SF short to Battery P)WR P) 9(5 6DILQJ WUDQVLVWRU 95(6',$* 66[\ Q) 6)[ Q)WR X) 5VTXLE 65[ ORZVLGH Q)WR X) 6*[ *1'$ *$3*36 Note: If VRCM is not previously connected to the SRx and the test is run, a dangerous condition could happen. In case of SRx shorted to SSxy, when the LS is turned ON, even if the current flowing through the squib is greater than ILSFET, the LS is not immediately turned off and the current flows through the squib until TFETTIMEOUT expires: such a high current could damage the LS power. 134/201 DocID025845 Rev 2 AN4437 Diagnostic Figure 65. Diagnostic - Low side FET diagnostic, SR short to Battery P)WR P) 9(5 6DILQJ WUDQVLVWRU 95(6',$* 66[\ Q) 6)[ Q)WR X) 5VTXLE 65[ ORZVLGH Q)WR X) 6*[ *1'$ *$3*36 DocID025845 Rev 2 135/201 200 Diagnostic 9.1.11 AN4437 High side driver diagnostic The aim of the test is to check the functionality of the high side FET and the external squib connection. Current flowing through the high side is internally limited at IHSdiag, lower than the normal deployment current. Figure 66. Diagnostic - High side driver diagnostic 9(5SLQ IURP(QHUJ\ 5HVHUYH +LJK6LGHGULYHUGLDJQRVWLF 95(6',$* 6DILQJ WUDQVLVWRU ,6,1.FRQQHFWHGWR65[ 5 ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ ,+6',$* P$ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU For set up, refer to Figure 66. 136/201 DocID025845 Rev 2 *$3*36 AN4437 Diagnostic ISRC is kept off; ISINK is 70mA limited and VRCM is disconnected. Through this test, the HS regulates a current IHSdiag. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 0 X 1 0 0 1 0 0 RES_MEAS LEAK_CHS 15: 0=DIAG LOW LEVEL EL _CHSEL 13: 1=pulldown curr OFF for all ch. 0000 = ch0 0100:1111 12,11: 00/11=ISRCOFF on all 0001 = ch1 channel 0010 = ch2 10: 1= ISINK 0011 = ch3 (RES_MEAS_CHSEL) ON, OFF the others. 9,8: 00 VRCM not connected 7:4 RES_MEAS_CHSEL 3:0 0100-1111 no selection 3 $36 SYSDIAGREQ D W X X X X X X X X 1 0 1 0 1010: DSTEST=HS driver FET test active 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Test result: As the current flowing through the high side exceeds 90% of IHSdiag value, the driver is considered well-functioning and HS_DRV_OK bit in LPDIAGSTAT is set: (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 0 X 15 14 13 12 11 10 9 R R 0 1 8 7 6 5 RES_MEAS_ CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 4 3 2 1 0 1 LEAK_CHSEL 19: 0= LOW LEVEL 0100-1111 14: 0= HS squib driver full path test not completed successfully 1= HS squib driver full path test completed successfully STB 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. DocID025845 Rev 2 137/201 200 Diagnostic 9.1.12 AN4437 LOSS of Ground This test is based on the voltage of ground pin, SGxy, during the squib resistor measurement or the high side driver diagnostic, refers to those sketches. Any voltage shift of SGxy pin over VSGopen is considered loss of ground, readable in LP_GNDLOSS register. VSGopen = 400-600-800 mV (1) (2) 4 $26 LP_GNDLOSS (3) 19 18 17 16 0 X 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 0 0 0 0 CH3 CH2 CH1 CH0 0 = no loss of ground 1 = loss of ground R i: chi i=3:0 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. GNDLOSSx is set considering tSGopen filter time and it is cleared upon read tSGopen = 46 μs - 50 μs - 54 μs Note: 138/201 Only two GND pins are available, SG01, SG23; IC is able to detect GND loss on CHx or CHy basing on the channel selected either for Section 9.1.7: Squib resistance measurement or Section 9.1.11: High side driver diagnostic. DocID025845 Rev 2 AN4437 Diagnostic 9.1.13 Safing FET diagnostic The aim of the test is to verify the VSF and SSxy voltage level. VSF is turned ON via SPI. Set up (1) (2) 15 14 13 12 11 10 9 8 3 $36 SYSDIAGREQ D W X X X X X X X X 7 6 5 4 3 2 1 0 0 1 1 0 0110: DSTEST= VSF regulator active 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Test result: VSF and SSxy voltage are readable by the microcontroller through the ADC converter in the registers: $3X DIAGCTRL_X → X=A, B, C, D Case X = A: (1) (2) $3A DIAGCTRL_A (3) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 - W X X X X X X X X X ADCREQ_A $36 = SS0 $37 = SS1 $38 = SS2 $399 = SS3 $2A = VSF 19 18 17 16 0 - 0 ADCREQ_A 1 R ADCREQ_A $36 = SS0 $37 = SS1 $38 = SS2 $399 = SS3 $2A = VSF ADCREQ_A 10bit ADC result 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. DocID025845 Rev 2 139/201 200 Diagnostic AN4437 Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio of the ADC. In case of SS and VSF, it is 15:1. Table 7. VSF and SS measurement of the value ratio ADC Divider Ratio Measurements 15:1 VSF √ SSx √ 10:1 7:1 4:1 1:1 In the schematics here below a possible solution to perform the test is represented: such a solution allows performing SAFING FET test only if the external reserve capacitor CER has been charged. Figure 67. Diagnostic - Safing FET 96) 9(5 Q ȍ 67'1) 6* ȍ ȍ ȍ 081': 3 6* 66 6* 66 ȍ B&0' (QDEOH '(3/2< 9'(3/2< ȍ ȍ ȍ Q Q ȍ ȍ ȍ 3B&0' (QDEOH ',$*1267,& %&3 ȍ *$3*36 The solution is based on the reading of the voltage on SSxy pins through ADC; it also requires an external component network and two commands from the microcontroller, 140/201 DocID025845 Rev 2 AN4437 Diagnostic μP_cmd1 and μP_com2. Depending on the status of the VSF (ON or OFF) and on the commands from the microcontroller, the cases described below can occur. Figure 68. Cases of status of the VSF (on or off) and on the commands from the microcontroller 96) 3BFPG 3BFPG 66[\ SLQYROWDJHUDQJH 9'(3/2<± 9GLRGH QRUPDORSHUDWLQJ 21 ; ; 96) 9FHVDW 9GLRGH 9JV 9GLRGH Y ; 9GLRGH 9(5 9FHVDW[9FHVDW Y Y 9(59GLRGH Y )(7UHJDQG'LDJQRVWLFHQDEOHG )(7UHJDQG'LDJQRVWLFGLVDEOHG )(7UHJGLVDEOHG'LDJQRVWLFHQDEOHG Y *$3*36 In the first case of the table reported above, external FET is working in voltage regulator mode (VSF ON, μp_cmd1, μp_cmd2 set) and voltage on SSxy pin is: 966 [\ 96)í 9&( 6$7 í9 ',2'(í9*6 í9 ',2'( *$3*36 The expected value read on ADC, depending on all the parameter variation, is in the range of 10V÷22V. In the second case the low side command of the diagnostic is enabled and voltage on SSxy pin is: 966 [\ 9(5í 9&( 6$7 9&( 6$7 í9 ',2'( *$3*36 The expected value read on ADC, depending on all the parameter variation, is in the range of 4V÷7V. In the last case everything is disabled so the voltage on SSxy is expected to be close to VER.: 966 [\ § 9(5í9 ',2'( *$3*36 In case of an ADC reading out of the expected range, it has to be considered as a faulty condition. Note: Once μp_cmd2 is active, capacitors on SSxy pins are discharged through 4.7k which requires about 1ms to reach steady state so a proper time should be elapsed before running ADC conversion. Besides, in order to guarantee more safety, it is possible to read the voltage on VDEPLOY net through a voltage divider which is sensed by ADC of the microcontroller. In order to guarantee redundancy on safing FET enabling, two independent conditions must be verified. The assertion of the two conditions must come from two separate activation logics. In the solution here presented, the first condition (VSF switch ON) comes from the IC in arming state while the second one (up_cmd1 asserted) comes from the microcontroller. DocID025845 Rev 2 141/201 200 Diagnostic AN4437 In case the ARMING algorithm is run by the microcontroller, the circuit which turns ON the safing FET can be removed (both MUN5332DW1 and S1G diode): VSF can be connected directly to the FET gate and μp_cmd1 can be used to drive FENH and FENL. 9.1.14 Deployment time diagnostic The aim of the test is to pass to the microcontroller the deploy time information that the IC has stored with the previous SPI commands (see DEPLOYMENT REQUIREMENT chapter 8.1). Set up, only in DIAG state (1) (2) 15 14 13 12 11 10 9 3 $36 SYSDIAGREQ D W X X X X X X X X 8 7 6 5 4 3 2 1 0 1 0 0 1 1001: DSTEST= output timing on ARM pin 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Note: Once $36 SYSDIAGREQ register is set for output timing on ARM pin check, even if the test has been performed, it is not possible any modification in the deployment channel configuration, $06 DCR0, $07 DCR1, $08 DCR2, $09 DCR3. This feature prevent any modification in the deployment time and deployment current after the test has been performed and, as a consequence, is no longer visible by the microcontroller. To modify again the deployment channel configuration ($06 DCR0, $07 DCR1, $08 DCR2, $09 DCR3) it is first necessary to change the DSTEST request, and secondly to modify the deployment channel configuration itself as previously done. Test result: Once the test is ongoing, a signal 0V ->5/3.3V (depending on VDDQ) is output on ARM pin, which reports in sequence, from channel 0 to channel 3, the deployment time programmed, with a 8ms delay between each channel: starting from ch0, ARM signal is high for the deploy time of ch0; then remains low until the next pulse corresponding to the channel 1 occurs (8 ms delay between each pulse to start); the same happens with the next channels 2, 3. The microcontroller can test the latest deployment time programmed in DRCx (see Section 8.1: Deployment requirement) measuring the duration of high ARM pulse. If the test is performed on a channel with no deployment time previously configured, the high ARM pulse lasts 8 μs. If the combination time/current deployment programmed for a channel is wrong, then, as explained in the DRCx (see Section 8.1: Deployment requirement) the combination time/current deployment turns back to the default value. In case the deployment time is then monitored through ARM signal, the default one is output. 142/201 DocID025845 Rev 2 AN4437 Diagnostic Figure 69. Deployment timer diagnostic sequence )URPDQ\VWDWH ',$*VWDWH63,B6<65(4'67(67 38/6( 38/6(B7(67[ 37B705 PV 37B705 38/6(B7(67[ 38/6(B7(67 37B:$,7 660B5(6(7 38/6(B7(67[ 37 37B705 PV 37B705 38/6(B7(67[ 38/6(B7(67 37B2)) 37 37B705 PV 38/6(B7(67[ 37B705 PV 37B705 38/6(B7(67[ 38/6(B7(67 37 37 37B705 PV 37B705 38/6(B7(67[ 38/6(B7(67 *$3*36 Figure 70. Deployment timer - no programmation DocID025845 Rev 2 143/201 200 Diagnostic AN4437 Figure 71. Deployment timer 144/201 DocID025845 Rev 2 AN4437 Diagnostic 9.2 High level Figure 72. High level loop diagnostic flow 1 /2:/(9(/GLDJQRVWLF VHOHFWE/3',$*5(4LV ORZ25LQYDOLGKLJKOHYHO GLDJQRVWLFVHOHFW25,&LQ '(3B(1$%/(VWDWH 7,3 (QDEOH95&0 'LVDEOH,65&DQG,6,1. 'LVDEOHDOOSXOOGRZQFXUUHQW /HDNDJHWHVWWLPHHODSVHG 6%/IODJLVDVVHUWHGLI67*LV QRPRUHSUHVHQW /($.$*( B7(67B /HDNDJHWHVWWLPH XVXV /HDNDJHLVGHWHFWHGGXHWRWKH IDWWKDW)(7VZRUNSURSHUO\ 25 IHWWHVWWLPHHODSVHG 7,3 )(7B7(67 ',$*B2)) )(7WHVWWLPHRXW XV /HDNDJHWHVWWLPHHODSVHG $1'6%/LVVHOHFWHG$1' OHDNDJHLVSUHVHQW 7,3 (QDEOH95&0 'LVDEOH,65&DQG,6,1. (QDEOH+6RU/6)(7LIDOVR '67(67 RU /HDNDJHWHVWWLPHHODSVHG $1')(7WHVWLVVHOHFWHG $1'12OHDNDJHLVSUHVHQW 1HZKLJKOHYHOGLDJQRVWLF UHTXHVWELWRI /3',$*5(*LVKLJK /HDNDJHWHVWWLPHHODSVHG$1'/($.$*( WHVWLVVHOHFWHG256%/DQGQROHDNDJHLV SUHVHQW25)(7WHVWDQGOHDNDJHLVSUHVHQW /DWFK67%67*IODJV )3 LI)(7WHVWLVVHOHFWHG /($.$*( B7(67B /HDNDJHWHVWWLPH XVXV :$,72)) 2IIWLPH XV 7,3 :DLWHQRXJKWLPHWREH VXUHWKDWDOOFXUUHQWVDQG YROWDJHVVXSSOLHVVWDUWLQ 2))VWDWH 95&0WHVWWLPHHODSVHG$1'95&0B&+(&. WHVWLVVHOHFWHG25950&IDLOV /DWFK67%67*IODJV )3 LI/($.$*(RU)(7WHVWVDUHVHOHFWHG 7,3 (QDEOH95&0 'LVDEOH,65&DQG,6,1. 95&0WHVWWLPHHODSVHG$1' /($.$*(RU6%/RU)(7WHVWLV VHOHFWHG$1'95&012IDLOV 2IIWLPHHODSVHG$1'QHZ GLDJQRVWLFUHTXHVWLV 95&0B&+(&.25/($.$*( 256%/25)(7WHVWV 95&0B&+(&. 95&0FKHFNWLPH XVXV 7,3 (QDEOH95&0 (QDEOH,65&DQG,6,1. DocID025845 Rev 2 *$3*36 145/201 200 Diagnostic AN4437 Figure 73. High level loop diagnostic flow 2 /2:/(9(/GLDJQRVWLF VHOHFWE/3',$*5(4LV ORZ25LQYDOLGKLJKOHYHO GLDJQRVWLFVHOHFW25,&LQ '(3B(1$%/(VWDWH (QGRIFRQYHUVLRQ 6WRUHUHVXOWLQ$'&5(6% 7,3 ',$*B2)) 648,%5(60($6 &219 5HVLVWDQFHUDQJHWHVWWLPHHODSVHG /DWFK+65B+,+65B/2IODJV 7,3 (QDEOH95&0 'LVDEOH,6,1. 1HZKLJKOHYHOGLDJQRVWLF UHTXHVWELWRI /3',$*5(*LVKLJK 648,%5(65$1*( 7(67 5HVLVWDQFH5DQJHWHVWVHWWOLQJ WLPH XVXV :$,72)) 2IIWLPHHODSVHG$1'QHZ GLDJQRVWLFUHTXHVWLV648,% 5(6,67$1&(5$1*(WHVW 2IIWLPH XV (QGRIVHWWOLQJWLPH 7,3 :DLWHQRXJKWLPHWREH VXUHWKDWDOOFXUUHQWVDQG YROWDJHVVXSSOLHVVWDUWLQ 2))VWDWH 648,%5(60($6&219 (QGRIVHWWOLQJWLPH 2IIWLPHHODSVHG$1'QHZ GLDJQRVWLFUHTXHVWLV648,% 5(6,67$1&(PHDVXUHWHVW (QGRIFRQYHUVLRQ 6WRUHUHVXOWLQ$'&5(6$ 648,%5(60($6 6(77/( 648,%5(60($6 6(77/( 5HVLVWDQFHWHVWVHWWOLQJWLPH XVXV 7,3 (QDEOH,65&RQ6)[ (QDEOH,6,1. 5HVLVWDQFHWHVWVHWWOLQJWLPH XVXV 7,3 (QDEOH,6,1. (QDEOH,65& %<3$66,65&RQ65[ *$3*36 Device performs the measurement, as requested by the microcontroller, through LPDIAGREQ register. Based on the requests from the microcontroller, diagnostics run according to the setups described for the low level mode but each test set up is driven step by step by the IC itself. IC timing schedule is selected through HI_LEV_DIAG_TIME bit in INIT: 146/201 DocID025845 Rev 2 AN4437 Diagnostic (1) (2) $01 SYS_CFG I W 15 14 13 12 11 10 9 X 8 7 6 5 4 3 2 1 0 0 10: HI_LEV_DIAG_TIME 0=short time 1=long time 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL SQP LOOP_DIAG_ 15: 1=DIAG HIGH LEVEL CHSEL _DIAG_SEL 4 SQP 0=SRx 1= SFx 0000 = ch0 000=No diag sel 0001 = ch1 001=VRCM 0010 = ch2 Check 0011 = ch3 010=Leakage Check 011=Short Btw Loops Check 100 = Unused 101=Squib resist range Check 110=Squib resist measure 111=FET test 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. In case of high level diagnostic selection, the IC automatically schedules the preparatory tasks to be eventually run in order to perform the required diagnostic.The following flow chart shows the time sequence implemented: DocID025845 Rev 2 147/201 200 Diagnostic AN4437 Figure 74. Diagnostic - Safing FET flow ,'/( 67$575(4 95&0&+(&. )3 < 95&07(67 UHTXHVWHG" 1 95&07(67 2." 1 < /($.7(67 < /($.7(67 UHTXHVWHG" 1 /($.7(67 2." 1 < )(77(67 *$3*36 FP bit in LPDIAGSTAT register is available only in case of high level diagnostic selected; it is stuck at 0 otherwise. Once a test which requires preliminary measurement phases is selected (ie leakage test, FET test), this bit is set if the diagnostic procedure has been stopped because of a fault recorded in such a preliminary steps. 148/201 DocID025845 Rev 2 AN4437 9.2.1 Diagnostic VRCM check - High side Figure 75. Diagnostic - VRCM check - High side 9(5SLQ IURP(QHUJ\5HVHUYH +6)(7GLDJQRVWLFFKHFN95&0IXQFWLRQDOLW\ 95(6',$* 6DILQJ WUDQVLVWRU )LUVWZHXVH,65&FXUUHQWJHQHUDWRUWRFKHFN95&0EORFN ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW (0,ORZSDVV ILOWHU +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65[ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6TXLEUHVLVWRU/2: 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0 YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 75. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVE 1 LOOP_DIAG_ 15: 1=DIAG HIGH LEVEL CHSEL L_DIAG_SEL 4: SQP 0=SRx 1= SFx 0000 = ch0 001=VRCM Check 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. DocID025845 Rev 2 149/201 200 Diagnostic AN4437 Figure 76. Diagnostic - VRCM check - High side waveform Test result: (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 1 0 0 15 14 13 12 11 10 9 R 0 R 0 8 7 6 5 4 3 2 1 0 HIGH_LEVEL _DIAG_SEL 001=VRCM Check 0 0 1 1 LEAK_CHSEL 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 0=FET off during diagn 7: SBL 0= no short loops 6: STG 0= no short GND 5: STB 1=short to battery 4:SQP=1 SFx 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Note: 150/201 VRCM check, once required, is not run one shot on both HS and LS, but microcontroller selects through SQP bit the high side or the low side. DocID025845 Rev 2 AN4437 9.2.2 Diagnostic VRCM check - Low side Figure 77. Diagnostic - VRCM check - Low side 9(5SLQ IURP(QHUJ\5HVHUYH /6)(7GLDJQRVWLFFKHFN95&0IXQFWLRQDOLW\ 95(6',$* 6DILQJ WUDQVLVWRU 6HFRQGZHXVH ,6,1.FXUUHQW JHQHUDWRUWRFKHFN95&0EORFN ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW ,SXOOGRZQ 65[ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. ,OLPLW P$ *1'$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 77. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL 0 LOOP_DIAG_ 15: 1=DIAG HIGH LEVEL CHSEL _DIAG_SEL 4: SQP 0=SRx 1= SFx 0000 = ch0 001=VRCM Check 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Test result: Being ISRC and VRCM connected to SFx, if VRCM works correctly, short to battery, readable in LPDIAGSTAT register, is asserted for the channel selected: DocID025845 Rev 2 151/201 200 Diagnostic AN4437 (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 1 0 0 15 14 13 12 11 R 0 R 0 10 9 8 7 6 5 4 3 2 1 0 HIGH_LEVEL_DIA 0 1 0 0 LEAK_CHSEL G_SEL 0000 = ch0 001=VRCM Check 0001 = ch1 0010 = ch2 0011 = ch3 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 0=FET off during diagn 7: SBL 0= no short loops 6: STG 1= short GND 5: STB 0=no short to battery 4:SQP=0 SRx 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Note: 152/201 VRCM check, once required, is not run one shot on both HS and LS, but microcontroller selects through SQP bit the high side or the low side. DocID025845 Rev 2 AN4437 9.2.3 Diagnostic Leakage check - High side Figure 78. Diagnostic - Leakage check - High side 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU +6/HDNDJHWHVW 95(6',$* ,65& P$ 66[\ ,SXOOGRZQ2))RQORRSXQGHUPHDVXUH21RQWKHRWKHUV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[6)[SLQYROWDJHWRY UHDGFXUUHQWWKURXJK6)[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 Figure 79. Diagnostic - Leakage check - High side waveform For set up, refer to Figure 78. DocID025845 Rev 2 153/201 200 Diagnostic AN4437 (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL 1 LOOP_DIAG_CH 15: 1=DIAG HIGH LEVEL _DIAG_SEL SEL 4: SQP 0=SRx 1= SFx 010=leakage 0000 = ch0 test 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Test result: (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 1 0 0 15 14 13 12 11 10 R 0 R 0 9 8 7 6 5 4 3 2 1 0 HIGH_LEVEL_ 0 0 0 1 LEAK_CHSEL DIAG_SEL 0000 = ch0 010=LEAKAGE 0001 = ch1 Check 0010 = ch2 0011 = ch3 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 0=FET off during diagn 7: SBL 0= no short loops 6: STG 0= no short GND 5: STB 0= no short to batt. 4:SQP=1 SFx 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Depending on the value of the capacitors mounted on the ECU, the same high level diagnostic can be performed setting HI_LEV_DIAG_TIME bit in order to increase the time of the internal diagnostic finite state machine operation. This bit can be written only in INIT state. Note: 154/201 In case HI_LEV_DIAG_TIME has to be written, microcontroller should do it before the RST activation after the initial 500ms are expired. DocID025845 Rev 2 AN4437 Diagnostic It could be necessary to disable the watchdog time out function through bit WD1_TOVR as described in Section 5.1. $01 SYS_CFG (1) (2) I W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X 1 1 10: HI_LEV_DIAG_TIME 0=short time 1=long time 0: WD1_TOVR 1=timeout disabled 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Figure 80. Diagnostic - Leakage check - High side waveform, long time DocID025845 Rev 2 155/201 200 Diagnostic 9.2.4 AN4437 Leakage check - Low side Figure 81. Diagnostic - Leakage check - Low side 9(5SLQ IURP(QHUJ\5HVHUYH /6/HDNDJHWHVW 95(6',$* 6DILQJ WUDQVLVWRU ,65& P$ 66[\ ,SXOOGRZQ 2))RQORRSXQGHUPHDVXUH21RQWKHRWKHUV 9ROWDJH5HJXODWRU&XUUHQW0RQLWRUFLUFXLW IL[65[SLQYROWDJHWRY UHDGFXUUHQWWKURXJK65[SLQ FRPSDUHFXUUHQWZLWKDWKUHVKROG %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6TXLEUHVLVWRU/2: 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 For set up, refer to Figure 81. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL 0 LOOP_DIAG_CH 15: 1=DIAG HIGH LEVEL SEL _DIAG_SEL 4: SQP 0=SRx 1= SFx 0000 = ch0 010=leakage test 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 156/201 DocID025845 Rev 2 AN4437 Diagnostic Test result: (1) (2) 4 $37 LPDIAGSTAT (3) R 0 19 18 17 16 1 0 0 15 14 13 12 11 10 R 0 9 8 7 6 5 4 3 2 1 0 HIGH_LEVEL_ 0 0 0 0 LEAK_CHSEL DIAG_SEL 0000 = ch0 010=LEAKAGE 0001 = ch1 Check 0010 = ch2 0011 = ch3 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 0=FET off during diagn 7: SBL 0= no short loops 6: STG 0=no short GND 5: STB 0=no short to batt. 4:SQP=0 SRx 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. 9.2.5 Short between loops To be selected if the test is on SFx or SRx via SQP bit: (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL 0/1 LOOP_DIAG_C 15: 1=DIAG HIGH LEVEL HSEL _DIAG_SEL 4: SQP 0=SRx 1= SFx 0000 = ch0 011=short between loop 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. DocID025845 Rev 2 157/201 200 Diagnostic AN4437 Test result: (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 1 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 0=FET off during diagn 7: SBL 0= no short loops 6: STG 0=no short GND 5: STB 0=no short to batt. 4:SQP=0 SRx/1=SFz 3:0 LEAK_CHSEL HIGH_LEVEL 0 0 0 0/ LEAK_CHSEL 1 0000 = ch0 _DIAG_SEL 011=short 0001 = ch1 between loop 0010 = ch2 0011 = ch3 R 0 R 0 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. 9.2.6 Squib resistance range Figure 82. Diagnostic - Squib resistance range 9(5SLQ IURP(QHUJ\5HVHUYH 6DILQJ WUDQVLVWRU +LJKVTXLEUHVLVWDQFHYDOXHGHWHFWLRQ 95(6',$* ,65& :LWK95&0EORFNZHGHWHFW 6TXLEUHVLVWDQFHLQORZUDQJHȍ·ȍ 6TXLEUHVLVWDQFHLQ+LJKUDQJH.ȍ·.ȍ P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU For set up, refer to Figure 82. 158/201 DocID025845 Rev 2 *$3*36 AN4437 Diagnostic (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL 1 LOOP_DIAG_CH 15: 1=DIAG HIGH LEVEL _DIAG_SEL SEL 4: SQP 0=SRx 1= SFx 101=squib 0000 = ch0 res range 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Test result (2 Ω squib): (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 1 0 0 15 14 13 12 11 10 R 0 R 0 0 9 8 7 6 5 4 3 2 1 0 1 HIGH_LEVEL_ 0 1 0 1 LEAK_CHSEL DIAG_SEL 0000 = ch0 101=squib res 0001 = ch1 range 0010 = ch2 0011 = ch3 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 0=FET off during diagn 7: SBL 0= no short loops 6: STG 1= short GND 5: STB 0=no short to batt. 4:SQP=1 SFx 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. STG=1 in case the squib has a very low resistive value SQP=1 means that VRCM is connected to the high side DocID025845 Rev 2 159/201 200 Diagnostic 9.2.7 AN4437 Squib resistance measurement IC allows measuring the squib resistance value in the range of [1-10]Ω with overall 8% precision. Two steps of the measurement described below are managed by the IC, which makes also ADC conversion results available. Figure 83. Diagnostic - Squib resistance measurement (1) 9(5SLQ IURP(QHUJ\5HVHUYH VWHSVTXLEUHVLVWDQFHPHDVXUH ,65& P$ 95(6',$* 6DILQJ WUDQVLVWRU ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 160/201 DocID025845 Rev 2 *$3*36 AN4437 Diagnostic Figure 84. Diagnostic - Squib resistance measurement (2) 9(5SLQ IURP(QHUJ\5HVHUYH VWHSVTXLEUHVLVWDQFHPHDVXUH ,65& P$LQ%<3$66 95(6',$* 6DILQJ WUDQVLVWRU ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍ ȍWR (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6TXLEUHVLVWRU/2: 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU *$3*36 IC triggers at the end of each step above an ADC conversion; once the high level diagnostic has been performed, results of ADC conversions have to be read in the registers $3C, $3D DIAGCTRL_x by selection of SQUIB resistance measurement (bit [6:0]=$06). For set up, refer to Figure 84. (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL X LOOP_DIAG_CH 15: 1=DIAG HIGH LEVEL SEL _DIAG_SEL 0000 = ch0 110=squib res meas 0001 = ch1 0010 = ch2 0011 = ch3 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Test result: The registers to be read are still the four DIAGCTRL_x. Again the explanation of the first register (x=A) is true also for the other three registers: $3X DIAGCTRL_X → X= C, D DocID025845 Rev 2 161/201 200 Diagnostic AN4437 Case X = C: (1) (2) $3C DIAGCTRL_C - W X X X X X 5 4 3 2 1 0 X X X X ADCREQ_A $06 = squib x resistance 19 18 17 16 1 0 0 ADCREQ_A (3) 15 14 13 12 11 10 9 8 7 6 - R ADCREQ_A ADCREQ_A 10bit ADC result $06 = squib x resistance 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Results read in the bit[9:0] will be named in the following as ADC1ST CONVERSION. Case X = D: (1) (2) $3C DIAGCTRL_D - W X X X X X 5 4 3 2 1 0 X X X X ADCREQ_A $06 = squib x resistance 19 18 17 16 1 0 0 ADCREQ_A (3) 15 14 13 12 11 10 9 8 7 6 - R ADCREQ_A ADCREQ_A 10bit ADC result $06 = squib x resistance 19:1=conversion finished 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Results read in the bit[9:0] will be named in the following as ADC2ND CONVERSION. Once read the ADC measurement, to obtain the value it is necessary to consider the divider ratio of the ADC. In case of resistance x, it is 1:1. Table 8. Resistance measurement of the value ratio ADC Divider Ratio Measurements 15:1 RESISTANCE 162/201 10:1 7:1 4:1 1:1 √ DocID025845 Rev 2 AN4437 Diagnostic Being two measurements, the squib resistance is so calculated: ¨ 9RXW 6)[ í 65[ í 6)[ í 65[ 5VTXLE ¨ 9RXW * ,65& *$3*36 G= 5.25 ±2% differential amplifier gain ISRC = 40 mA ±5% Let's consider an example where ADC1ST CONVERSION = (0100111000)2 = (312)10 ADC2ND CONVERSION = (0010000001)2 = (129)10 ΔADC = 312 - 129 = 183 In order to obtain the result in Volt, being the A2D characteristic linear, [ ¨ $'& ĺ[ 9 9 *$3*36 In order to obtain resistance value, considering typical factors 5VTXLE [ 9 * ,65& P$ DocID025845 Rev 2 *$3*36 163/201 200 Diagnostic 9.2.8 AN4437 High side FET diagnostic The test is possible only in the diagnostic phase (see Section 4.2: Diagnostic). These are two tests performed separately for the high side and the low side, with dedicated commands. Before running this test, IC validates VRCM, then performs leakage test and in case of no failures, high side FET tests is performed. Figure 85. Diagnostic - High side FET test 9(5SLQ IURP(QHUJ\ 5HVHUYH 7R6<1&%2267 +6)(7GLDJQRVWLFFKHFN)(7 6DILQJ WUDQVLVWRU 5 ,65& P$ 95&0FRQQHFWHGWR6)[ ([WHUQDOGLRGHSOXVUHVLVWDQFHELDVWKH66[\SLQYROWDJH DQGOLPLWWKHPD[LPXPFXUUHQWOHYHOGXULQJWHVW 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍ ȍWR (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU For set up, refer to Figure 85. 164/201 DocID025845 Rev 2 *$3*36 AN4437 Diagnostic Before selecting FET test, a writing access to the register $36 must be done, as it is shown here below: (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL S LOOP_DIAG_CH 15: 1=DIAG HIGH LEVEL _DIAG_SEL Q SEL 4 SQP 0=SRx 1= SFx 111=FET test P 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 3 $36 SYSDIAGREQ D W X X X X X X X X 0 1 1 1 0111: DSTEST=HSFET active 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. High side FET test turns ON the HS power: if it turns ON correctly, SFx is connected to SSxy which is at VER voltage through the resistor R in parallel to the safing FET. During the test, the device monitors the current flowing through VRCM. If the high side FET works properly, this current exceeds the thresholds IHSFET (high side) and the channel is immediately turned off, IHSFET = 1.8 mA ± 10% In case the current doesn't exceed the limit mentioned, after a fixed time, TFETTIMEOUT, the test is terminated and the output is turned off. TFETTIMEOUT = 200 μs Test result: Possible results for high side, readable in register $37: STB=1 & STG=0 ok STB=0 or STG=1 missing SSxy connection during FET test or high side not switched ON or short to GND during FET test DocID025845 Rev 2 165/201 200 Diagnostic AN4437 (1) (2) 4 $37 LPDIAGSTAT (3) R 1 19 18 17 16 1 0 0 15 14 13 12 11 10 0 R 0 9 8 7 6 5 4 3 2 1 0 1 HIGH_LEVEL_ 0 1 0 1 LEAK_CHSEL DIAG_SEL 0000 = ch0 111 = FET test 0001 = ch1 0010 = ch2 0011 = ch3 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 1=FET off during diagn 7: SBL 0= no short loops 6: STG 0=no short GND 5: STB 1=short to batt. 4:SQP=1 SFx 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. STG & STB, after FET test, are latched. They are cleared through a new LPDIAGREQ or a new SYSDIAGREQ. 9.2.9 Low side FET diagnostic Before running this test, IC validates VRCM, then performs leakage test and in case of no failures, low side FET test is performed. Figure 86. Diagnostic - Low side FET test 9(5SLQ IURP(QHUJ\ 5HVHUYH /6)(7GLDJQRVWLFFKHFN)(7 95(6',$* 6DILQJ WUDQVLVWRU 95&0FRQQHFWHGWR65[ 5 ,65& P$ 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU 166/201 DocID025845 Rev 2 *$3*36 AN4437 Diagnostic For set up, refer to Figure 86. Before selecting FET test, a writing access to the register $36 must be done, as it is shown here below: (1) (2) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 3 $38 LPDIAGREQ (I) W 1 X X X X X X X HIGH_LEVEL S LOOP_DIAG_CH 15: 1=DIAG HIGH LEVEL _DIAG_SEL Q SEL 4 SQP 0=SRx 1= SFx 111FET test P 0000 = ch0 0001 = ch1 0010 = ch2 0011 = ch3 3 $36SYSDIAGREQ D W X X X X X X X X 0 1 1 1 1000: DSTEST=LSFET active 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. Low side FET test turns ON the low side. If the low side turns ON correctly, SRx is connected to SGxy. During the test, the device monitors the current flowing through VRCM. If the FETs work properly, this current exceeds the thresholds ILSFET and the channel is immediately turned off, ILSFET = 450 μA ±10% In case the current doesn't exceed the limit mentioned, after a fixed time, TFETTIMEOUT, the test is terminated and the output is turned off. TFETTIMEOUT = 200 μs DocID025845 Rev 2 167/201 200 Diagnostic AN4437 Test result: Possible results for low side: STB = 0 and STG = 1 ok STB = 1 or STG = 0 short to battery in LS or low side not switched ON. (1) (2) 4 $37 LPDIAGSTAT (3) 19 18 17 16 1 0 0 15 14 13 12 11 10 R 1 R 0 0 9 8 7 6 5 4 3 2 1 0 1 HIGH_LEVEL_ 0 1 0 1 LEAK_CHSEL DIAG_SEL 0000 = ch0 111 = FET test 0001 = ch1 0010 = ch2 0011 = ch3 19: 1= HIGH LEVEL 18: TIP 0= high level diagn not running 16: FP no fault before test 15: 1=FET on during diagn 7: SBL 0= no short loops 6: STG 1=short GND 5: STB 0=no short to batt 4:SQP=1 SFx 3:0 LEAK_CHSEL 1. I=INIT / D=DIAG / S=SAFING / C=SCRAP / A=ARMING / - = ALL STATES (I)=no in INIT / (D)= no in DIAG / (S)= no in SAFING / (C)= no in SCRAP / (A)= no in ARMING. 2. R = READ W = WRITE. 3. Further bit over the 16 standard. Note: Ground loss (SGxy) is not detected through FET test, because there is a diode between SGxy and the substrate. STG & STB, after FET test, are latched. They are cleared through a new LPDIAGREQ or a new SYSDIAGREQ. 168/201 DocID025845 Rev 2 AN4437 10 Remote sensor interface - L9678-S only Remote sensor interface - L9678-S only This feature is available only for L9678-S version. The 2 remote sensor interfaces (RSU0, RSU1) support protocol asynchronous PSI-5 1.3 version, 8 or 10 bit. The two channels are independent from each other and a fault on a channel does not influence the other. Each channel supplies an independently current limited DC voltage to its remote sensor derived from VSUP, and monitors the current to extract encoded data. PSI5 (Peripheral Sensor Interface) is a two-wire protocol, where the active sensor modulates the load current in order to encode data to be transmitted It is a two current protocol, where the sensor applies a high level step superimposed to its normal current consumption. Current level detection threshold is automatically and independently defined for each channel by the IC. The information, Manchester 2 encoded, is brought through current transitions in the middle of a bit time: current rising slope = 0 current falling slope = 1 Figure 87. Manchester bit encoding %LWWLPH 3TARTBITS ,OGICgg &XUUHQW µ¶ ,OGICgg µ¶ µ¶ µ¶ µ¶ -ANCHESTER 03) '!0'03 Features: Transmission speed: 125 k baud or 189 k baud Word data length: 8 & 10 bit 1 bit even parity Registers: RSU configuration is done in DIAG state only: $4A = RSCR1 Register Config only in DIAG state STARTBIT MEAS_DIS, bit 13 0 = used START bit period 1 = not used START bit period DocID025845 Rev 2 169/201 200 Remote sensor interface - L9678-S only AN4437 This bit allows to decide the bit period based on the first two start bit (STARTBIT MEAS_DIS, bit 13 =0) or based on the sensor parameter reported in the bit STSx[3:0] that means 1/125k or 1/189k. $4A = RSCR1 Register Config only in DIAG state BLKTxSEL, x=1, bit 10 0 = 5ms blanking time 1 = 10ms blanking time The same is for $4B register related to RSCR2 Blanking time is active at each channel power-up and masks the inrush current eventually needed to charge capacitors mounted on the line in order to avoid communication error wrong detection. Figure 88. In rush current / ,727 6833/< ,FRQG ,VHQVRU 568 VWDJH & *$3*36 STSx(3:0) bit to select the PSI5 characteristics: data length, transmission speed and parity bit. $4A = RSCR1 Register Config only in DIAG state STSx, x=1, bit [3:0] 0000 = Async. PSI-5, parity 8bit, 125k 0001 = Async. PSI-5, parity 8bit, 189k 0010 = Async. PSI-5, parity 10bit, 125k 0011-1111 = Async. PSI-5, parity 10bit, 189k 170/201 DocID025845 Rev 2 AN4437 Remote sensor interface - L9678-S only Control of RSU is in register $4E: $4E RSCTRL Register Config in DIAG, SAFING, SCRAP, ARMING state CH1EN, bit 3 0 = OFF 1 = ON CH0EN, bit 1 0 = OFF 1 = ON Received data are stored into two stages FIFO readable by microcontroller via SPI (RSDRx). Remote sensor data and fault are reported into two registers, one for each channel ($50 and $51). Content of these registers depends on the status of bit 15. $50 RSDR0 Register FLT, bit 15 0 = no fault 1 = fault present FLT = 0 $50 RSDR0 Register FLT, bit 15 0 = no fault On/off, bit 14 0 = off 1 = on LCID, bit[13:10] 0000 = RSU 0 0100 = RSU 1 DATA, bit[9:0] Data CRC, bit[19:17] Calculated on the entire data received bit[16:0]. Polynomial calculation: g(x) = 1+x+x3, initialized at 111 DocID025845 Rev 2 171/201 200 Remote sensor interface - L9678-S only AN4437 FLT = 1 When a fault condition occurs, RSFLT bit in GSW (bit 8 of GSW that is bit 29 of MISO frame) is set. $50 RSDR0 Register FLT, bit 15 1 = fault present On/off, bit 14 0 = off 1 = on LCID, bit[13:10] 0000 = RSU 0 0100 = RSU 1 STG, bit9 0= no fault 1 = short to ground (in current limit condition) STB, bit8 0= no fault 1 = short to battery CURRENT_HI, bit7 0= no fault 1 = channel current exceeds ILKGG for a determined time OPENDET, bit6 0= no fault 1 = open sensor detected RSTEMP, bit5 0= no fault 1 = over temperature detected INVALID, bit4 0= no fault (Cleared by STG, STB, CURRENT_HI, 1 = frame with data length error or parity or bit time OPENDET, RSTEMP) error. NODATA, bit3 0= no fault (Cleared by STG, STB, CURRENT_HI, 1 = FIFO data empty OPENDET, RSTEMP) Whatever fault occurs, data stored into the 2 stages FIFO are lost and the fault occurred is immediately flagged via SPI. If no fault has occurred, but no more data are received by the sensor, reading access to the register $50 determines a two stages FIFO pop event: once the FIFO is empty, a NODATA fault is flagged via SPI. When a fault condition occurs, (except a NODATA), RSFLT bit in GSW (bit 8 of GSW that is bit 29 of MISO frame) is also set. For the leakage to ground flag described above, the threshold is the following: ILKGG = 36mA ÷ 45mA The above description referred to $50 RSDR0 is valid for $51 RSDR2 too. Data stored into RSDRx register are latched until read via SPI. 172/201 DocID025845 Rev 2 AN4437 10.1 Remote sensor interface - L9678-S only Fault protection, short to GND, current limit Each channel is separately protected against high current. If the output current exceeds ILIMTH for at least TILIMTH STG (bit9) register $50 RSDR1 and/or $51RSDR2 is set; the channel involved in the problem is then switched OFF. ILIMTH = 65mA ÷ 100mA For what concerns the parameter TILIMTH, it depends on the operative state of the IC. At channel power-up, the inrush current due to the capacitive load must be masked so a short to ground condition is masked for a time period depending on the selection programmed via SPI (register $4A, 4B bit 10, BLKTxSEL) TILIMTH = 5ms min if BLKTxSEL=0 TILIMTH = 10ms min if BLKTxSEL=1 Once initial blanking time is elapsed, the IC validates a short to ground condition after a time period TILIMTH = 500 μs ÷ 600 μs Once the channel has been switched off due to an overcurrent condition, in order to reactivate the channel, OFF/ON sequence is necessary. Timer to count TILIMTH has a resolution of 25μs. STG of RSU doesn't interfere with the normal operation of the IC. 10.2 Fault protection, short to battery Each channel is separately protected against short to battery condition, disconnecting the channel from its supply rail. Short to battery condition is detected when RSUx voltage pin rises over VSUP for at least TSTBTH time. STB (bit8) register $50 RSDR1 and/or $51RSDR2 is set. TSTBTH = 12 μs ÷ 16 μs The counter is cleared if the STB condition is not present for at least 1.5 μs STB condition doesn't shut-down the channel involved in the STB condition. STB bit is cleared upon read through SPI. DocID025845 Rev 2 173/201 200 Remote sensor interface - L9678-S only 10.3 AN4437 Cross link This allows the verification of short between RSUx channels. To perform the verification, one channel is turned ON, while the other is kept OFF and the voltage on the OFF channel is read. $4E RSCTRL Register Config in DIAG, SAFING, SCRAP, ARMING state CH1EN, bit 3 0 = OFF 1 = ON CH2EN, bit 1 0 = OFF 1 = ON To read the pin voltage on the other channel: $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] 0 = cleared on read new data available from the conversion 1 = conversion finished - expected ADCREQ_A, bit [6:0] $32 = RSU0 request (MOSI) $33 = RSU1 ADCREQ_A, bit [16:10] $32 = RSU0 readout (through MISO), $33 = RSU1 ADCRES_A, bit [9:0] 10bit ADC result correspondent to the ADCREQ_A, bit [9:0] The same for the other registers, the choice depends on the user: $3B DIAGCTRL, x = B $3C DIAGCTRL, x = C $3D DIAGCTRL, x = D Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio of the ADC. In case of RSUxx, it is 4:1. Table 9. RSUx measurement to obtain the voltage value Divider Ratio Measurements 15:1 RSUx 10:1 7:1 4:1 1:1 √ An external logic has to manage the RSUx voltage read out and to distinguish the value expected with respect to the value read and then declare or not the cross link between loops 174/201 DocID025845 Rev 2 AN4437 10.4 Remote sensor interface - L9678-S only Leakage to battery / open condition Open condition or leakage to battery is detected in the same way: current through RSUx falls down lower than ILKGB for at least TRSUOP_FILT, being ILKGB = 2 mA ÷ 3 mA TRSUOP_FILT: 10 μs ÷ 15 μs When detected this fault OPENDET (bit 6), register $50 RSDR1 and/or $51RSDR2 is set. The channel involved in the problem is not switched OFF. $50 RSDR0 Register FLT, bit 15 1 = fault present OPENDET, bit6 0= no fault 1 = open sensor detected 10.5 Leakage to ground The leakage to ground is detected through high current, greater than ILKGG, for at least TRSUCH_FILT, being ILKGG for = 36 mA ÷ 45 mA TRSUCH_FILT: 10 μs ÷ 15 μs When detected this fault, CURRENT_HI (bit7), register $50 RSDR1 and/or $51RSDR2 is set. The channel involved in the problem is not switched OFF. $50 RSDR0 Register FLT, bit 15 1 = fault present CURRENT_HI, bit7 0= no fault 1 = channel current exceeds ILKGG for a determined time DocID025845 Rev 2 175/201 200 Remote sensor interface - L9678-S only 10.6 AN4437 Thermal shut-down Each channel is equipped with its dedicated over-temperature detection, each one independent from the other. If the over-temperature on a channel is detected, the channel itself is switched off, without influencing the other. In correspondence RSTEMP bit of register $50 RSDR1 and/or $51 RSDR2 is set. $50 RSDR0 Register FLT, bit 15 1 = fault present RSTEMP, bit5 0= no fault 1 = over temperature detected To reactivate the channel after an over-temperature, the sequence OFF-ON of the channel ($4E RSCTRL register, bit 3 and/or1) is required. 10.7 Manchester decoding PSI5 protocol encodes messages by modulating current sunk by the sensor through Manchester 2 codification: IC is able to sense current and decode the messages, in order to provide data via SPI register. Once two valid start bits are detected, IC provides error detection mechanism by monitoring the period and the number of the bit sent in the frame. 10.8 MISO BIT 31 30 29 28 27 26 25 24 23 22 21 MISO SPIFLT DEPOK RSFLT WDTDIS_S ERSTATE POWERFLT FLT CONVRDY2 CONVRDY1 ERR_WID ERR_RID Remote sensor interface errors are reported in the GSW bit8, RSFLT, that corresponds to bit 29 in MISO GSW BIT 10 9 8 7 6 5 4 3 2 1 0 Trip current auto adjust Depending on the number of sensors connected to the line, the quiescent current sunk from each RSU interface may change. IC provides the means to detect such a variation and is able to put an adaptive threshold in order to recognize the current transitions due to the signal modulation. Once the quiescent current value has been detected, the IC recognizes a transition low → high if the current sunk by the sensor is higher than IRSUxTH = IBO+ ITH 176/201 DocID025845 Rev 2 AN4437 Remote sensor interface - L9678-S only Where IBO the base current which can span from 2.5mA up to 41mA covering PSI-5 specification range and ITH is in the range of [(12-9%),(12+9%)]mA Referring to the current sensing auto adjust, there is the possibility to choose the counter frequency, see Figure 89, setting SLOWTRACK bit in register RSCR1 (the same for RSCR2 register) $4A = RSCR1 Register SLOWTRACK, bit 14 Config only in DIAG state 0: 8μs/1μs 1: 16μs/2μs Figure 89. Remote sensor current auto adjust 2X3AT )TRI P )SAT EGM! M! )BASE M! COUNT SS DocID025845 Rev 2 SS *$3*36 177/201 200 DC sensor interface 11 AN4437 DC sensor interface These four interfaces are dedicated to positioning sensors (as, for example presence of the person on the seat, seat belt fasten and so on). They can be Hall Effect sensors, resistive sensors or simply switches. Each channel has an internal pull down (100uA), default active, that is deactivated by switching ON the channel, or by requiring voltage measurement or by setting DCS_PD_CURR bit channel per channel or all the channels together. In DIAG, SAFING; SCRAP or ARMING state, each channel, selected through CHID bit, is controlled and configured via SPI: $39 SWCTRL register CDS_PD_CURR, bit7 SWOEN, bit6 CHID, bit [3:0] Config in DIAG, SAFING; SCRAP or ARMING state 0 = pull down OFF for the channel under voltage or current measurement, ON for all the others 1 = pull down OFF for all the channels 0 = OFF 1 = ON (40mA) 0000 = channel 0 0001 = channel 1 0010 = channel 2 0011 = channel 3 0100-1111 = not used It is possible, through ADC, for each channel, to require the following measurements: Current measurement Voltage measurement, with the channel ON or OFF Resistor measurement Current and resistor measurement require the channel ON (SWOEN=1). As the measure has been performed, the channel is automatically switched off (to prevent power dissipation) or not, following the system configuration: $01 SYS_CFG register Config in INIT state EN_AUTO_SWITCH_OFF, bit15 178/201 0 = auto switch off disable 1= auto switch off disable DocID025845 Rev 2 AN4437 DC sensor interface Current measurement Before running the current measurement, it is previously necessary to switch on the channel by accessing to register $39 as showed above. The result of the measurement is addressed on $3x DIAGCTRLx, x = A...D. Case X = A: $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] new data available from the conversion 0 = cleared on read 1 = conversion finished ADCREQ_A, bit [6:0] request (MOSI) $04 DCSi current ADCREQ_A, bit [16:10] readout (through MISO), $04 DCSi current ADCRES_A, bit [9:0] (MISO) 10bit ADC result Once the current measurement on the channel is completed, the channel is automatically switched off or not based on EN_AUTO_SWITCH_OFF bit configuration. Current measurement is possible both in the range of 2mA÷22mA with a total error ±12% (including all errors which affect ADC measurement) or in the range of 1mA÷2mA: in this case the accuracy of the measurement becomes ±30%. , '&6[ 5 5()B ,'&6[ $'&5() B KL $'&5(6 ',$*&75/Q $'&5(6Q *$3*36 where RREF1_IDCSx = 83.333Ω Example 1 Let's consider an example where 3kΩ resistor is mounted on DCSx: when the channel is ON a voltage of typ 6.25 V is regulated so current flowing is ~2.1 mA $3A DIAGCTRL_A, ADCRES_A, bit [9:0]: ADC = (0001001000)2 = (72)10 In order to obtain the result in A, being the ADC characteristic linear, 9 [ $'&ĺ [ 9 *$3*36 In order to obtain current value, considering typical factors, , '&6[ [ 9 DocID025845 Rev 2 P$ *$3*36 179/201 200 DC sensor interface Note: AN4437 In case of a low value resistor mounted on DCSx channel, the current may be higher than IDCS_LIMIT_L = 24 mA ÷30 mA In this case the IC is no more able to regulate 6.125 V on the channel but the current measurement still works fine. Example 2 Let's consider an example where 65 Ω resistor is mounted on DCSx: when the channel is ON a voltage of ~1.8 V is present with a current flowing ~27 mA (out of regulation) $3A DIAGCTRL_A, ADCRES_A, bit [9:0]: ADC = (1110101001)2 = (937)10 In order to obtain the result in A, being the ADC characteristic linear, 9 [ $'&ĺ [ 9 *$3*36 In order to obtain current value, considering typical factors , '&6[ [ 9 P$ *$3*36 Voltage measurement IC is able to perform voltage measurement in the range of 1.5V÷10V with a total error ±8% (including all errors which affect ADC measurement). For the voltage measurement, it is possible to run such a diagnostic both with channel on and off.: a double step measurement (ch ON and OFF) is recommended in order to reach a good precision by means of offset compensation. In case of channel ON measurement, the channel has to be switched on, then the result of the measurement is addressed on $3x DIAGCTRLx, x=A...D. Case X = A: $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] new data available from the conversion ADCREQ_A, bit [6:0] request (MOSI) $03 DCSi voltage ADCREQ_A, bit [16:10] readout (through MISO), $03 DCSi voltage ADCRES_A, bit [9:0] (MISO) 180/201 0 = cleared on read 1 = conversion finished 10bit ADC result DocID025845 Rev 2 AN4437 DC sensor interface Once this measurement is completed, the channel is not automatically switched off, but if necessary, it can be switched off by the microcontroller. Voltage measurement with the channel OFF is done through DCSx bit, registers $3x DIAGCTRLx, x=A...D: Case x = A $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] new data available from the conversion 0 = cleared on read 1 = conversion finished ADCREQ_A, bit [6:0] request (MOSI) $0B DCS0 voltage pin, channel off $0C DCS1 voltage pin, channel off $0D DCS2 voltage pin, channel off $0E DCS3 voltage pin, channel off ADCREQ_A, bit [16:10] readout (through MISO), $0B DCS0 voltage pin, channel off $0C DCS1 voltage pin, channel off $0D DCS2 voltage pin, channel off $0E DCS3 voltage pin, channel off ADCRES_A, bit [9:0] (MISO) 10bit ADC result In order to calculate the real voltage value from the result coming from an ADC conversion, 7.125 typ scaling factor must be taken into account. Example 3 Let's consider an example where DCSx is at its voltage regulation value 6.25V typ ADCCHON = (0111101011)2 = (491)10 ADCCHOFF = (0010001011)2 = (139)10 ΔADC = ADCCHON – ADCCHOFF = (352)10 In order to obtain the result in V, being the ADC characteristic linear, [ ¨$'& ĺ [ 9 9 *$3*36 Considering typical scaling factor VDCSx = x · 7.125 = 6.12 V Note: The voltage measurement is still available in case the current load is higher than IDCS_LIMIT_L = 24 mA ÷ 30 mA and channel is no more able to regulate 6.25 V typ. DocID025845 Rev 2 181/201 200 DC sensor interface AN4437 Resistor measurement IC is able to perform resistor measurement in the range of 65 Ω ÷ 3000 Ω with a total error defined by the combination of the accuracy obtained on the voltage and current measurements. IC gives possibility to run one shot the resistor measurement by single access to the ADC. In order to perform such measurement, the channel under test has to be previously switched on in the register $39. Note: The one shot resistor measurement can be run only through $3A DIAGCTRL_A access. $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] new data available from the conversion 0 = cleared on read 1 = conversion finished ADCREQ_A, bit [6:0] request (MOSI) $05 DCSx resistance ADCREQ_A, bit [16:10] readout (through MISO), $05 DCSx resistance ADCRES_A, bit [9:0] (MISO) 10bit ADC result Once the one shot measurement is completed, the results are available in the register $3A DIACTRL_A (for the current flowing through the channel) and $3B DIACTRL_B (for the channel voltage). Note: The result which is read on the register $3B corresponds to the voltage with channel ON. It is recommended to subtract from this voltage the offset which can be read with channel OFF. Once current and voltage are available, the resistor can be computed as per the following: , '&6[ 9'&6[ 5'&6[ 55()B,'&6[ $'& 5()BKL $'& 5(6 ',$*&75/Q $'&$ ¤ $'& 5()BKL ³ 5$7,2 9'&6[ ¥ $'&5(6 ',$*&75/Q $'& %&+21 í 9 2))B '&6[´ ¦ µ 5$7,2 9'&6[ 55()B,'&6[ ',$*&75/Q $'& %&+21 í ',$*&75/Q $'&&+2)) ',$*&75/Q $'&$ *$3*36 Let's consider an example where a 3 kΩ resistor is mounted on DCSx DIAGCTRLn(ADCCHOFF) = (001000101)2 = (139)10 DIAGCTRLn(ADC$3BCHON) = (0111101010)2 = (490)10 DIAGCTRLn(ADC$3A) = (0001000111)2 = (71)10 5'&6[ 182/201 í DocID025845 Rev 2 *$3*36 AN4437 DC sensor interface Once the channel resistor measurement is completed, the channel is automatically switched off or not based on EN_AUTO_SWITCH_OFF bit configuration Note: The resistor measurement is still available in case the current load is higher than IDCS_LIMIT_L = 24 mA ÷ -30 mA and channel is no more able to regulate 6.25 V typ. DCSx tolerate external ground shift up to ±1 V. Short between channels: By means of channel pull-down disabling, the IC in combination with the microcontroller can detect a short between channels, enabling one channel $39 SWCTRL register Config in DIAG, SAFING; SCRAP or ARMING state DCS_PUCURR [bit 7] SWOEN, bit6 CHID, bit [3:0] 0 = pull down OFF for the channel under voltage or current measurement, ON for all the others 1 = ON 0000 = channel 0 0001 = channel 1 0010 = channel 2 0011 = channel 3 and measuring the voltage of the others $3X DIAGCTRL_X → X = A, B, C, D Case X = A: $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] new data available from the conversion 0 = cleared on read 1 = conversion finished ADCREQ_A, bit [6:0] request (MOSI) $0B DCS0 voltage pin, channel off $0C DCS1 voltage pin, channel off $0D DCS2 voltage pin, channel off $0E DCS3 voltage pin, channel off ADCREQ_A, bit [16:10] readout (through MISO), $0B DCS0 voltage pin, channel off $0C DCS1 voltage pin, channel off $0D DCS2 voltage pin, channel off $0E DCS3 voltage pin, channel off ADCRES_A, bit [9:0] (MISO) 10bit ADC result Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio that is 7.125 in this measurement. DocID025845 Rev 2 183/201 200 DC sensor interface AN4437 Protections: Each channel is protected against: – Overload – Ground shift (±1V) – Loss ECU battery – Loss ground – Short to ground. 184/201 DocID025845 Rev 2 AN4437 GPO drivers 12 GPO drivers There are two GPO drivers configurable as high side or low side drivers. Their configuration is done via SPI: $42 GPOCR register Config. in DIAG state only GPO1HS, bit1 0 = high side driver configured for ch1 1 = low side driver configured for ch1 GPO0HS, bit0 0 = high side driver configured for ch0 1 = low side driver configured for ch0 Low side GPODx to the external load (that is connected to battery) GPOSx to ground x = 0, 1 Figure 90. GPO low side configuration 9%DWW (5%2267 /2$' *32'[ 63, 3:0FRQWURO ORJLF 21 &XUUHQWVHQVH 2&GHWHFWLRQ +9DQDORJ 08; 2SHQGHWHFWLRQ 21VWDWH Q) 'ULYHUZLWK VOHZUDWH FRQWURO 7KHUPDOZDUQLQJ GHWHFWLRQ &XUUHQWOLPLWDWLRQ *326[ 9LQ ELWV 9UHI 'UDLQ6HOHFWLRQ 9UHI Y *$3*36 DocID025845 Rev 2 185/201 200 GPO drivers AN4437 High side GPODx to battery GPOSx to the external load (that is connected to ground) x = 0, 1 Figure 91. GPO high side configuration 9%DWW (5%2267 *32'[ 63, 3:0FRQWURO ORJLF 8QSRZHUHG RSWLRQ 21 2&GHWHFWLRQ 2SHQGHWHFWLRQ 21VWDWH 'ULYHUZLWK VOHZUDWH FRQWURO &XUUHQWVHQVH 7KHUPDOZDUQLQJ GHWHFWLRQ +9DQDORJ 08; &XUUHQWOLPLWDWLRQ *326[ Q) 6RXUFH6HOHFWLRQ 9LQ ELWV 9UHI /2$' 9UHI Y *$3*36 GPOx are OFF by default. Once they have been configured as high side or low side, they can be independently switched ON through GPOCTRLx register, GPOxPWM bit: $43 GPOCTRL0 register GPOxPWM bit[5:0] $44 GPOCTRL1 register GPO1PWM bit[5:0] 186/201 Config. in DIAG, SAFING, SCRAP, ARMING state PWM duty cycle, 1.6% per count Config. in DIAG, SAFING, SCRAP, ARMING state PWM duty cycle, 1.6% per count DocID025845 Rev 2 AN4437 GPO drivers In case the channels are switched on without their configuration as high or low side, a fault bit (LAMPS_NOT_CONF in GPOFLTSR register) is set: $46 GPOFLT register LAMPS_NOT_CONF bit 15 0= channels configured, activation permitted 1= channels not configured (default), activation not permitted Output can work in a PWM configuration (125 kHz, 0-100% duty-cycle, depending on the GPOxPWM value). Driver is kept OFF in case of 0% duty cycle programmed, full ON in case of 100% duty cycle programmed. When both channels (it doesn't care HS or LS configuration) are used in PWM with the same duty-cycle, they are synchronized to provide parallel configuration capability. Protections: – Each channel can withstand -1V on the pin and +1V as reverse voltage across source and drain. – Each channel is protected against short circuit – Each channel is protected against thermal overload condition All the diagnostics related to GPOx are reported in GPOFLTSR register $46 GPOFLTSR GPO1TEMP, bit9 GPO0TEMP, bit4 0 = no fault 1 = fault GPO1LIM, bit8 GPO0LIM, bit3 0 = no fault 1 = fault GPO1OPN, bit7 GPO0OPN, bit2 0 = no fault 1 = fault All faults (except thermal overload) are latched in the register until it is read. Protection against short circuit is implemented by means of current limitation ILIM, until thermal fault condition is detected. ILIM = 80 mA ÷ 140 mA The limitation flag, GPOxLIM, is also asserted. In case of thermal fault, the correspondent flag, GPO0TEMP, is asserted. Thermal overload fault lasts until the over-temperature condition disappears: a hysteresis is applied for the cool down TJSD = 150°C ÷ 190°C THYS_JSD = 5°C ÷ 15°C The IC is able to detect open load in ON condition, comparing the current flowing into the output pin with a threshold IOpenload = 3mA DocID025845 Rev 2 187/201 200 GPO drivers AN4437 If the current through the pin is lower than the threshold, the open load flag, GPOxOPN, is asserted. For further diagnostics, IC provides the means to read via ADC the voltage on both drain and source pin for each GPOx driver. The registers involved in this operation are the four $3x DIAGCTRL_x → x=A, B, C, D Case x = A $3A DIAGCTRL_A Config. in DIAG, SAFING, SCRAP, ARMING state NEWDATA[19] new data available from the conversion 0 = cleared on read 1 = conversion finished ADCREQ_A, bit [6:0] request (MOSI) $2C = GPO D0 $2D = GPO S0 $2E = GPO D1 $2F = GPO S1 ADCREQ_A, bit [16:10] readout (through MISO), $2C = GPO D0 $2D = GPO S0 $2E = GPO D1 $2F = GPO S1 ADCRES_A, bit [9:0] 10bit ADC result correspondent to the ADCREQ_A, bit [9:0] Once read the ADC measurement, to obtain the voltage value it is necessary to consider the divider ratio of the ADC. Table 10. GPODx and GPOSx measurement of the value ratio ADC Divider Ratio Measurements 15:1 188/201 10:1 GPODx √ GPOSx √ DocID025845 Rev 2 7:1 4:1 1:1 AN4437 13 ISO9141 transceiver ISO9141 transceiver Figure 92. ISO9141 transceiver block diagram 9%$7 9,1 7 ,625; ,62. YGGT 9,+ *DWH &RQWURO ,627; )/765,/,0;&95 7KHUPDO 6KXWGRZQ )LOWHU WG ,OLQ )/765 27;&95 '!0'03 ISOTX is pulled up to VDDQ to guarantee the output is disabled in case of an open load. ISOK is an output pin, connected to BATTERY through an external resistor (510 Ω) ISORX is an output pin referred to VDDQ. Value of this pin depends on the value of ISOK, and then on the value of ISOTX. If ISOK is above ISOK input receiver threshold, VTH_REC, ISORX is high, otherwise it is low. VTH_REC = VIN*0.5 ÷ VIN*0.6 (typ = VIN*0.55) Protections: against short circuit current limitation detection, ILIM 50mA ÷ 100mA thermal shutdown In $47 ISOFLTSR register the diagnostic results are reported: $47 ISOFLTSR register ISOTEMP, bit1 0 = no fault 1 = fault ISOLIM, bit0 0 = no fault 1 = fault In current limit condition, the output stage runs until the thermal shutdown is reached. Thermal shutdown switches OFF the output until the temperature falls down below limit threshold temperature, considering the hysteresis. TJSD = 150°C ÷ 190°C THYS_JSD = 5°C ÷ 15°C DocID025845 Rev 2 189/201 200 System voltage diagnostic 14 AN4437 System voltage diagnostic IC is equipped with a 10 bit ADC running at 16 MHz. Different measurements can be performed and then read via four dedicated commands, $3x_DIAGCTRL_x, x = A ÷ D. All measurements can be addressed in one of these four registers, with the exception of: DCS resistance measurement available in $3A_DIAGCTRL_A Squib resistance measurement available in $3C_DIAGCTRL_C In case of DCS resistance measurement, in $3A_DIAGCTRL_A is reported the current flowing through the pin and in $3B_DIAGCTRL_B is reported the voltage of the pin, as explained in DC SENSOR INTERFACE section, chapter 11. In case of squib resistance measurement, result of ADC conversion is available in registers $3C_DIAGCTRL_C (current) and $3D_DIAGCTRL_D (voltage of the pin), see section SQUIB RESISTANCE MEASUREMENT, chapters 9.1.6, 9.2.7. Structure of DIAGCTRL_A same for the other three registers. $3A, DIAGCTRL_A 19 18 17 16 15 14 13 12 11 10 9 MOSI MISO X NEWDATA_A 0 0 X X X X X X 8 7 X X ADCREQ_A [6:0] 6 5 4 3 2 1 0 ADCREQ_A [6:0] ADC_RES_A [9:0] To get four measurements, the four $3x, DIAGCTRL_x, x = A ÷ D commands have to be sent, regardless their order. If the voltage to be measured requires a certain time to be stable, the requirement has to be done in advance. This is the case of: Squib resistance measurement and diagnostic DCS measurement NEW_DATA_x =1 indicates that the conversion required is finished and the new data is available. NEW_DATA_x is reported in GSW, elaborated in this way: CONVRDY_0 = NEW_DATA_A or NEW_DATA_B 190/201 MISO BIT 31 30 29 28 27 26 25 24 23 22 21 MISO SPIFLT DEPOK RSFLT WDTDIS_S ERSTATE POWERFLT FLT CONVRDY2 CONVRDY1 ERR_WID ERR_RID CONVRDY_1 = NEW_DATA_C or NEW_DATA_D GSW BIT 10 9 8 7 6 5 4 3 2 1 0 DocID025845 Rev 2 AN4437 System voltage diagnostic Once the conversion has been read via SPI, bit NEW_DATA_x is cleared and results of conversion done, ADC_RES_A [9:0], is kept until a new conversion is available. In case a new conversion command is received while a conversion is still running, a 4 stages FIFO queue is available in order to service all conversions commands with the integrated ADC. Figure 93. FIFO filling ),)2,1 W WN 63,UHTXHVW '&$% W WN 63,UHTXHVW & 'N [ [ [ &N 'N [ [ %N &N 'N [ $N %N &N 'N &N $N %N 'N ),)2RXW *$3*36 FIFO management, in a case of 4 conversion commands requested sequentially, is reported in the example above. In case a new conversion is required (ie on DIAGCTRL_C) while a conversion is still running, the new request (Ck+1) overwrites the previous one (Ck) and a new conversion request is located at the end of the queue. Voltage measurements require a proper scaling, as summarized here below: Table 11. Voltage measurements Divider Ratio Measurements 15:1 VER √ ERBOOST √ VSF √ SSxy √ SFx √ 10:1 GPODx √ GPOSx √ VIN √ VBATMON √ WAKEUP √ VSUP 7.125:1 7:1 4:1 1:1 √ DocID025845 Rev 2 191/201 200 System voltage diagnostic AN4437 Table 11. Voltage measurements (continued) Divider Ratio Measurements 15:1 10:1 7.125:1 WDTDIS 4:1 1:1 √ RSUx √ DCSx 14.1 7:1 √ VDD5 √ VDD3V3 √ VINT3V3 √ Band-gap (BGR/BGM) √ TEMP √ ADC algorithm 10 bit data are internally filtered. The number of samples that is filtered depends on set-up of VMEAS bit (default 4 samples) in SYS_CFG register, $01 SYS_CFG register VMEAS, bit[6:5] Config in INIT state only 00 = 4 samples 01 = 16 samples 10 = 8 samples 11 = 2 sample Reference voltage for ADC is 2.5V. Conversion times takes into account several factors: – Number of measurements loaded into the queue – Numbers of sample taken for each measurement – Settling time 192/201 DocID025845 Rev 2 AN4437 15 Temperature sensor Temperature sensor The aim of this sensor is to have a reference for the average junction temperature on the silicon on the surface. The sensor is localized far from the power stages. Temperature is available through ADC conversion, ADRREQ_x = $0A. Once the temperature is available, the formula for the conversion is: 7 & ³ ¤ ³ ¤$'& 5()BKL í ¥ ´ ¥ $'& 5(6 ',$*&75/Q $'&5(6Q´ í ¦ µ ¦ µ # ',$*&75/Q $'&5(4Q DocID025845 Rev 2 $KH[ *$3*36 193/201 200 Footprint 16 AN4437 Footprint L9678 and the other two devices of the same family have a concentric footprint, see next figures: Figure 94. Footprint L9678-L9680 194/201 DocID025845 Rev 2 AN4437 Footprint Figure 95. Footprint L9678-L9679 DocID025845 Rev 2 195/201 200 Energy reserve capacitor Appendix A AN4437 Energy reserve capacitor Energy reserve capacitor stores the necessary energy to operate the Airbag ECU during loss of battery. System operating requirements influence device selection and calculations. The following example makes general operating assumptions and changing the assumptions may effect calculations and results. During loss of battery operation, energy reserve operation can be mechanized as shown. To continue the analysis, system functional operating assumptions must be determined. These assumptions are shown in the drawing below. Operation assumes three states, sensing, deploy and shutdown. During sensing state, all functions operate normally. In deploy state, all functions remain operational and all squib deployment channels are fired. The final state, shutdown, reduces operation to only the microcontroller. Figure 96. Blocks active in Autarchy mode 'HSOR\PHQW &URVVRYHU6ZLWFK 5HVLVWDQFH 56: ,%,$6 /,& 5(65 (QHUJ\5HVHUYH &DSDFLWRU & ,9''9 ,9''9 ,'&6(1625 '&6HQVRU ,568 5HPRWH 6HQVRUV *$3*36 196/201 DocID025845 Rev 2 AN4437 Energy reserve capacitor Figure 97. Energy reserve capacitor depletion - timing diagram (QHUJ\ 5HVHUYH 9 1RUPDORSHUDWLRQ 6HQVLQJ 9(5 'HSOR\ 6KXWGRZQ 9 6\VWHPRSHUDWLRQWUDQVIHUV WRHQHUJ\UHVHUYH 5HVHUYH YROWDJHLPPHGLDWHO\GURSV GXHWRFDSDFLWRU(65DQG FURVVRYHUVZLWFKUHVLVWDQFH 'HSOR\PHQWFXUUHQW LQFUHDVHVFDSDFLWRU(65 YROWDJHGURS 9 9 5HVHUYHYROWDJHUHFRYHUV GXHWRUHGXFHGORVVLQ(65 DQGFURVVRYHUVZLWFK 9 5HVHUYHYROWDJHPXVW EHVXIILFLHQWWRSURYLGH GHSOR\PHQWFXUUHQW 9 9 9(5!9''9'URSRXW '&6HQVRUV(QDEOHG 5HPRWH6HQVRUV(QDEOHG 9''99''96XSSOLHV(QDEOHG 7 6KXWGRZQ &RPSOHWH 7 (QGRI6HQVLQJ 6WDUW'HSOR\PHQW 7 /RVVRI%DWWHU\ 7 'HSOR\PHQW(QGV 6WDUW6KXWGRZQ 7LPH *$3*36 At t = T0 = 0, V0 = VER – ISYS • (RESR + RCO) Where, VER = Energy reserve voltage just prior to loss of battery detection and crossover operation ISYS = System current consumption, L96xx bias, Voltage regulators, RSUs, DC Sensors RESR = Energy capacitor's ESR RCO = Crossover Switch Resistance ¤9 í9 ³ , 6<6 & ¥ ´ ¦ 7 í 7 µ 9 Equation 1 9 9 í *$3*36 , 6<6 7 í 7 9 (5 í , 6<6 5(65 5&2 í & *$3*36 , 6<6 7 & *$3*36 Deployment begins at T1, thus increasing energy reserve current and effects due to ESR Equation 2 V2 = V1 – IDEPLOY • RESR Where IDEPLOY = total deployment current controlled by L96xx Substituting (1) into (2): DocID025845 Rev 2 197/201 200 Energy reserve capacitor AN4437 Equation 3 9 9 (5 í , 6<6 5(65 5&2 í , 6<6 7 & í , '(3/2< 5(65 *$3*36 During deployment phase, reserve voltage behavior is characterized as: , 6<6 , '(3/2< Equation 4 9 9 í & 9 í9 7 í 7 *$3*36 7'(3/2< , 6<6 , '(3/2< & *$3*36 Substituting (3) into (4): 9 9 (5 í , 6<6 5(65 5&2 í , 6<6 7 & í , '(3/2< 5(65 í 7'(3/2< , 6<6 , '(3/2< & *$3*36 Once deployment is complete, the airbag module enters its final state, shutdown. Reserve current is reduced causing reserve voltage to increase due to less loss in capacitor CER and Cross over switch. The change in reserve voltage is calculated as: Equation 5 9 9 , '(3/2< 5(65 , '&6(1625 , 568 5(65 5&2 *$3*36 Equation 6 9 9 (5 í , 6<6 5(65 5&2 í , 6<6 7 , 6<6 7 '(3/2< , '(3/2< 7 '(3/2< & í , '(3/2< 5(65 , '(3/2< 5(65 , '&6(1625 , 568 5(65 5&2 *$3*36 In equation (5) above, the system disables current to all deployment drivers, DC sensor and Remote Sensor Interfaces. During shutdown phase, only Voltage regulator and device (L96xx) bias current is needed from reserve. To complete energy reserve capacitor estimate, the analysis must assume a final reserve voltage requirement. In the study, energy reserve must be higher than VDDx dropout voltage where VDDx is the supply of the microcontroller. By assuming this requirement, the system is designed to operate for the desired reserve time. Equation 7 V5 > VDDxDROPOUT Reserve voltage behavior follows as: Equation 8 198/201 ,6+87'2:1 & 9í9 7í 7 DocID025845 Rev 2 *$3*36 AN4437 Energy reserve capacitor Where ISHUTDOWN = IVDD + IBIAS Re-arranging (8) ISHUTDOWN • (T3 – T2) C • V4 – V5) Substituting (6) and (7): ,6+87'2:1 7 í 7 & 9 (5 í , 6<6 5(65 5&2 í , 6<6 7 , 6<6 7'(3/2< , '(3/2< 7'(3/2< & í , '(3/2< 5(65 , '(3/2< 5(65 , '&6(1625 , 568 5(65 5&2 í 9''[ '523287 *$3*36 Simplify and arrange & , 6+87'2:1 7 í 7 , 6<6 7 , 6<6 7'(3/2< , '(3/2< 7'(3/2< 9 (5 í , 6<6 5(65 5&2 , '&6(1625 , 568 5(65 5&2 í 9''[ '523287 *$3*36 DocID025845 Rev 2 199/201 200 Revision history AN4437 Revision history Table 12. Document revision history 200/201 Date Revision Changes 15-Apr-2014 1 Initial release. 06-Mar-2015 2 Modified in Section 9.1: Low level on page 101 for “$04 SYS_STATE” 010=DIAG in 001=DIAG. DocID025845 Rev 2 AN4437 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID025845 Rev 2 201/201 201