L9680 Automotive advanced airbag IC for mid/high end applications Datasheet - production data System voltage diagnostics with integrated ADC Squib deployment drivers – 12 channel HSD/LSD – 25 V max deployment voltage – Various deployment profiles – Current monitoring – Rmeasure, STB, STG & Leakage diagnostics – High & low side driver FET tests *$3*36 TQFP100 exposed pad down (14x14x1.0mm) High side safing switch regulator and enable control Features AEC-Q100 qualified Boost regulator for energy reserve – 1.882 MHz operation, Iload = 70 mA max – Output voltage user selectable, 23 V/ 33 V ±5% – Capacitor value & ESR diagnostics Boost regulator for PSI-5 SYNC pulse – 1.882 MHz operation, – Output voltage, 12 V/14.75 V, user configurable Four channel remote sensor interface – PSI-5 satellite sensors – Active wheel speed sensors Three channel GPO, HSD or LSD configurable, with PWM 0-100% control Nine channel hall-effect, resistive or switch sensor interface User customizable safing logic Specific disarm signal for passenger airbag Temporal and algorithmic Watchdog timers End of life disposal interface Buck regulator for remote sensor – 1.882 MHz operation – Output voltage, 7.2 V/9 V ±4%, user configurable Temperature sensor Buck regulator for micro controller unit – 1.882 MHz operation – Output voltage user selectable, 3.3 V or 5.0 V ±3% Operating temperature, -40 to 95 °C 32 bit SPI communications Integrated energy reserve crossover switch – 3 Ω - 912 mA max – Switch active output indicator Battery voltage monitor & shutdown control with Wake-up control May 2016 This is information on a product in full production. 5.5 V minimum operating voltage at device battery pin Packaging - 100 pin Table 1. Device summary Order code L9680 L9680TR DocID029257 Rev 1 Package TQFP100 Pacing Tray Tape & Reel 1/277 www.st.com Contents L9680 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 Operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4 Pin out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5 Overview and block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 2/277 5.1 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.2 Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.3 Remote sensor interfaces (4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4 DC sensor interfaces (9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.5 General purpose outputs (3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.6 Arming logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.7 Other features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Start-up and power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.1 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 6.2 Power mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.2.1 POWER OFF mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.2 SLEEP mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.3 ACTIVE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.4 PASSIVE mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.2.5 Power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.2.6 IC operating states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 6.3 ERBOOST switching regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 6.4 Energy reserve capacitor charging and discharging circuits . . . . . . . . . . 40 6.5 ER CAP diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5.1 ER CAP measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.5.2 ER CAP ESR measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.6 ER switch and COVRACT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.7 SYNCBOOST boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 DocID029257 Rev 1 L9680 7 Contents 6.8 SATBUCK regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.9 VCC buck regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 6.10 VCOREMON external core voltage monitor . . . . . . . . . . . . . . . . . . . . . . . 49 6.11 VSF regulator and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.12 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 6.13 Reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 SPI interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.1 SPI protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2 Global SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 7.3 Global SPI tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Global SPI read/write register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.1 Fault status register (FLTSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7.3.2 System configuration register (SYS_CFG) . . . . . . . . . . . . . . . . . . . . . . 70 7.3.3 System control register (SYS_CTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 7.3.4 SPI Sleep command register (SPI_SLEEP) . . . . . . . . . . . . . . . . . . . . . 75 7.3.5 System status register (SYS_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . . 75 7.3.6 Power state register (POWER_STATE) . . . . . . . . . . . . . . . . . . . . . . . . . 77 7.3.7 Deployment configuration registers (DCR_x) . . . . . . . . . . . . . . . . . . . . 80 7.3.8 Deployment command (DEPCOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 7.3.9 Deployment status registers (DSR_x) . . . . . . . . . . . . . . . . . . . . . . . . . . 83 7.3.10 Deployment current monitor registers (DCMTSxy) . . . . . . . . . . . . . . . . 85 7.3.11 Deploy enable register (SPIDEPEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 7.3.12 Deployment ground loss register (LP_GNDLOSS) . . . . . . . . . . . . . . . . 86 7.3.13 Device version register (VERSION_ID) . . . . . . . . . . . . . . . . . . . . . . . . . 87 7.3.14 Watchdog retry configuration register (WD_RETRY_CONF) . . . . . . . . 88 7.3.15 Microcontroller fault test register (MCU_FLT_TEST) . . . . . . . . . . . . . . . 88 7.3.16 Watchdog timer configuration register (WDTCR) . . . . . . . . . . . . . . . . . 89 7.3.17 WD1 timer control register (WD1T) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 7.3.18 WD state register (WDSTATE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 7.3.19 Clock configuration register (CLK_CONF) . . . . . . . . . . . . . . . . . . . . . . . 92 7.3.20 Scrap seed read command register (SCRAP_SEED) . . . . . . . . . . . . . . 93 7.3.21 Scrap key write command register (SCRAP_KEY) . . . . . . . . . . . . . . . . 94 7.3.22 Scrap state entry command register (SCRAP_STATE) . . . . . . . . . . . . . 94 7.3.23 Safing state entry command register (SAFING_STATE) . . . . . . . . . . . . 95 7.3.24 WD2 recover write command register (WD2_RECOVER) . . . . . . . . . . 95 DocID029257 Rev 1 3/277 8 Contents L9680 7.4 4/277 7.3.25 WD2 seed read command register (WD2_SEED) . . . . . . . . . . . . . . . . . 96 7.3.26 WD2 key write command register (WD2_KEY) . . . . . . . . . . . . . . . . . . . 96 7.3.27 WD test command register (WD_TEST) . . . . . . . . . . . . . . . . . . . . . . . . 97 7.3.28 System diagnostic register (SYSDIAGREQ) . . . . . . . . . . . . . . . . . . . . . 98 7.3.29 Diagnostic result register for deployment loops (LPDIAGSTAT) . . . . . . 99 7.3.30 Loops diagnostic configuration command register for low leve diagnostic (LPDIAGREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 7.3.31 Loops diagnostic configuration command register for high level diagnostic (LPDIAGREQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 7.3.32 DC sensor diagnostic configuration command register (SWCTRL) . . . 106 7.3.33 ADC request and data registers (DIAGCTRL_x) . . . . . . . . . . . . . . . . . 108 7.3.34 Configuration register for switching regulators (SW_REGS_CONF) . . 111 7.3.35 Global configuration register for GPO driver function (GPOCR) . . . . . 113 7.3.36 GPOx control register (GPOCTRLx) . . . . . . . . . . . . . . . . . . . . . . . . . . 114 7.3.37 GPO fault status register (GPOFLTSR) . . . . . . . . . . . . . . . . . . . . . . . . 115 7.3.38 Wheel speed sensor test request register (WSS_TEST) . . . . . . . . . . 118 7.3.39 PSI5/WSS configuration register for channel x (RSCRx) . . . . . . . . . . 119 7.3.40 Remote sensor control register (RSCTRL) . . . . . . . . . . . . . . . . . . . . . 123 7.3.41 WSS Threshold configuration register 1 (RS_AUX_CONF1) . . . . . . . 124 7.3.42 WSS Threshold configuration register 2 (RS_AUX_CONF2) . . . . . . . 124 7.3.43 Safing algorithm configuration register (SAF_ALGO_CONF) . . . . . . . 125 7.3.44 Arming signals register (ARM_STATE) . . . . . . . . . . . . . . . . . . . . . . . . 126 7.3.45 ARMx assignment registers to specific Loops (LOOP_MATRIX_ARMx) 127 7.3.46 ARMx enable pulse stretch timer status (AEPSTS_ARMx) . . . . . . . . . 128 7.3.47 Passenger inhibit upper threshold for DC sensor 0 (PADTHRESH_HI) 129 7.3.48 Passenger inhibit lower threshold for DC sensor 0 (PADTHRESH_LO) 129 7.3.49 Assignment of PSINH signal to specific Loop(s) (LOOP_MATRIX_PSINH) 130 7.3.50 Safing records enable register (SAF_ENABLE) . . . . . . . . . . . . . . . . . 130 7.3.51 Safing records request mask registers (SAF_REQ_MASK_x) . . . . . . 131 7.3.52 Safing records request target registers (SAF_REQ_TARGET_x) . . . . 133 7.3.53 Safing records response mask registers (SAF_RESP_MASK_x) . . . . 135 7.3.54 Safing records response mask registers (SAF_RESP_TARGET_x) . . 137 7.3.55 Safing records data mask registers (SAF_DATA_MASK_x) . . . . . . . . 139 7.3.56 Safing record threshold registers (SAF_THRESHOLD_x) . . . . . . . . . 141 7.3.57 Safing control x registers (SAF_CONTROL_x) . . . . . . . . . . . . . . . . . . 143 7.3.58 Safing record compare complete register (SAF_CC) . . . . . . . . . . . . . 146 Remote sensor SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 DocID029257 Rev 1 L9680 Contents 7.5 Remote sensor SPI tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 7.5.1 7.6 8 Remote sensor SPI read/write registers . . . . . . . . . . . . . . . . . . . . . . . . . 149 7.6.1 Remote sensor data/fault registers (RSDRx @FLT = 0) . . . . . . . . . . . 149 7.6.2 Remote sensor data/fault registers w/o fault (RSDRx @ FLT=1) . . . . 152 7.6.3 Remote sensor x current registers y (RSTHRx_y) . . . . . . . . . . . . . . . 156 7.6.4 Arming signals register (ARM_STATE) . . . . . . . . . . . . . . . . . . . . . . . . 157 7.6.5 Safing record compare complete register (SAF_CC) . . . . . . . . . . . . . 158 Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.1 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 8.1.1 Deployment current selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.1.2 Deploy command expiration timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 8.1.3 Deployment control flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 8.1.4 Deployment current monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.1.5 Deployment success . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.2 Energy reserve - deployment voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.3 Deployment ground return . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 8.4 Deployment driver protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.5 9 Remote sensor SPI global status word . . . . . . . . . . . . . . . . . . . . . . . . 148 8.4.1 Delayed low-side deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.4.2 Low-side voltage clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.4.3 Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.4.4 Short to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 8.4.5 Intermittent open squib . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 8.5.1 Low level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 8.5.2 High level diagnostic approach . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 Remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 9.1 9.2 PSI5 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.1.1 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 9.1.2 Sensor data integrity: LCID and CRC . . . . . . . . . . . . . . . . . . . . . . . . . 179 9.1.3 Detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 Active wheel speed sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 9.2.1 Wheel speed data register formats . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 9.2.2 Test mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 DocID029257 Rev 1 5/277 8 Contents L9680 9.3 10 Short to ground, current limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 9.3.2 Short to battery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 9.3.3 Cross link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 9.3.4 Leakage to battery, sensor open . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 9.3.5 Leakage to ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 9.3.6 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 Temporal watchdog (WD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 10.1.1 Watchdog timer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 10.1.2 Watchdog timer operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 10.2 Algorithmic watchdog (WD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 10.3 Watchdog reset assertion timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 10.4 Watchdog timer disable input (WDT/TM) . . . . . . . . . . . . . . . . . . . . . . . . 191 DC sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 11.1 12 9.3.1 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 10.1 11 Remote sensor interface fault protection . . . . . . . . . . . . . . . . . . . . . . . . 184 Passenger inhibit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Safing logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.1 Safing logic overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 12.2 SPI sensor data decoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 12.3 In-frame and out-of-frame responses . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 12.4 Safing state machine operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 12.4.1 12.5 Safing engine output logic (ARMxINT) . . . . . . . . . . . . . . . . . . . . . . . . . . 206 12.5.1 12.6 Simple threshold comparison operation . . . . . . . . . . . . . . . . . . . . . . . 205 Arming pulse stretch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Additional communication line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 13 General purpose output (GPO) drivers . . . . . . . . . . . . . . . . . . . . . . . . 213 14 System voltage diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 14.1 15 6/277 Analog to digital algorithmic converter . . . . . . . . . . . . . . . . . . . . . . . . . . 221 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 DocID029257 Rev 1 L9680 16 Contents Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 16.1 Configuration and control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 16.2 Internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 16.3 Internal regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 16.4 Watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 16.5 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 16.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 16.7 SPI interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 16.8 ERBoost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 16.9 ER CAP current generators and diagnostic . . . . . . . . . . . . . . . . . . . . . . 239 16.10 ER switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 16.11 COVRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.12 SYNCBOOST converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 16.13 SATBUCK converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 16.14 VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 16.15 VSF regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 16.16 Deployment drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 16.17 Deployment driver diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.17.1 Squib resistance measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 16.17.2 Squib leakage test (VRCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 16.17.3 High/low side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 16.17.4 Deployment timer test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.18 Remote sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.18.1 PSI-5 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 16.18.2 WSS interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 16.19 DC sensor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 16.20 Safing engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 16.21 General purpose output drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 16.22 Analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 16.23 Voltage diagnostics (Analog MUX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 16.24 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 17 Quality information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 17.1 OTP memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 DocID029257 Rev 1 7/277 8 Contents L9680 18 Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 19 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 19.1 20 8/277 TQFP100 (14x14x1.4 mm exp. pad down) package information . . . . . . 274 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 DocID029257 Rev 1 L9680 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Operative maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Functions disabling by state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 SPI MOSI and MISO frames layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Global SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Global SPI Global Status Word. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Remote sensor SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 GSW - Remote sensor SPI global status word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Short between loops diagnostics decoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 HS FET TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 LS FET TEST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 Watchdog timer status description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 WD2 states and signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 Example of combine function operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Short to ground fault in LS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Short to battery fault in HS mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Diagnostics control register (DIAGCTRLx) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 Diagnostics divider ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Configuration and control DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 Configuration and control AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 Open ground detection DC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 GND_OPEN_AC - Open ground detection DC specifications . . . . . . . . . . . . . . . . . . . . . 229 Internal analog reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 Internal regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Internal regulators AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230 Temporal watchdog timer AC specifications (WD1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Algorithmic watchdog timer DC specifications (WD2). . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Algorithmic watchdog timer AC specifications (WD2). . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 Oscillators specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 Reset DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Reset AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 Global and remote sensor SPI DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 SPI AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 ERBoost regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 ERBoost regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 ERBOOST Converter external components design info. . . . . . . . . . . . . . . . . . . . . . . . . . 238 ER CAP current generators and diagnostic DC specifications . . . . . . . . . . . . . . . . . . . . . 239 ER CAP current generators and diagnostic AC specifications . . . . . . . . . . . . . . . . . . . . . 240 ER Switch DC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 ER Switch AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 COVRACT DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 COVRACT AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SYNCBOOST converter DC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 SYNCBOOST converter AC specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 SYNCBOOST converter external components design info. . . . . . . . . . . . . . . . . . . . . . . . 243 SATBUCK converter DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 SATBUCK converter AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 DocID029257 Rev 1 9/277 10 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. 10/277 L9680 SATBUCK converter external components design info . . . . . . . . . . . . . . . . . . . . . . . . . . 245 VCC converter DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 VCC converter AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 VCC converter external components design info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 VSF regulator DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 VSF regulator AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Deployment drivers – DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 Deployment drivers – AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 Deployment drivers diagnostics - Squib resistance measurement . . . . . . . . . . . . . . . . . . 253 Squib Leakage Test (VRCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 High/low side FET test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 Deployment timer test - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 PSI-5 satellite transceiver - DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 PSI-5 satellite transceiver - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 WSS sensor - DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 WSS sensor - AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 DC Sensor interface specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Arming Interface – DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 Arming interface – AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 GPO interface DC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 GPO driver interface – AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 Analog to digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Voltage diagnostics (Analog MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 Temperature sensor specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 Errata sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 TQFP100 (14x14x1.4 mm exp. pad down) package mechanical data . . . . . . . . . . . . . . . 275 Document revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 DocID029257 Rev 1 L9680 List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Pin connection diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device function block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power supply block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Power control state flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Wake-up input signal behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Normal power-up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Normal power down sequence through POWERMODE SHUTDOWN state - no ER cap active discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Normal power down sequence through Powermode Shutdown state - ER cap active discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Normal power down sequence through ER state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 IC operating state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 ERBOOST regulator block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ERBOOST regulator state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ER charge state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ER discharge state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ER CAP measurement block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 ER CAP measurement timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 ER ESR measurement block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 ER ESR measurement timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 ER switch state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 SYNCBOOST regulator block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SYNCBOOST regulator state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 SATBUCK regulator state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 VCC regulator state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 VSF control logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Internal voltage monitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Reset control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Deployment driver control blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Deployment driver control logic - Enable signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Deployment driver control logic - Turn-on signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 Deployment driver block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 Global SPI deployment enable state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Current monitor counter behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Deployment loop diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 SRx pull-down enable logic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Deployment timer diagnostic sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 High level loop diagnostic flow1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 High level loop diagnostic flow2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Remote sensor interface logic blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 PSI-5 remote sensor protocol (10-bit, 1-bit parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Manchester bit encoding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 Remote sensor synchronization pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 PSI5 slot timing control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 Manchester decoder state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 Wheel speed sensor protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 WD1 Temporal watchdog state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 Watchdog timer refresh diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 DocID029257 Rev 1 11/277 12 List of figures Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. 12/277 L9680 Algorithmic watchdog timer flow diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 DC sensor interface block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192 Passenger inhibit logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 Top level safing engine flow chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 Safing engine – 32-bit message decoding flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 Safing engine – 16-bit Message decoding flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 Safing engine - Validate data flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 Safing engine - Combine function flow chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 Safing engine threshold comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 Safing engine - Compare complete . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 In-frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Out-of-frame example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Safing engine arming flow diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207 Safing engine diagnostic logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 ARMx input/output control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Pulse stretch timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Scrap SEED-KEY state diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Scrap ACL state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 Disposal PWM signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 GPO driver and diagnostic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 GPO Over temperature logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 ADC MUX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 ADC conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 SPI timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 Deployment drivers diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 TQFP100 (14x14x1.4 mm exp. pad down) package outline. . . . . . . . . . . . . . . . . . . . . . . 274 DocID029257 Rev 1 L9680 1 Description Description The L9680 is an advanced airbag system chip solution targeted for mature airbag market and integrated safety markets. This device is family compatible with the L9678 and L9679 devices. Safety system integration is enabled through higher power supply currents and integrated active wheel speed sensor interface. The active wheel speed interface is shared with the PSI-5 satellite interface to create a generic remote safety sensor interface compliant to both systems. High frequency power supply design allows further cost reduction by using smaller and less expensive external components. All switching regulators operate at 1.882 MHz while buck converters have integrated synchronous rectifiers. Additional attention is given to system integrity and diagnostics. The reserve capacitor is electrically isolated from the boost regulator by a 65 mA nominal fixed current source, controlling in-rush an additional capacitor discharge fixed current source is integrated to diagnose the reserve capacitor value and ESR. The same current sources can be used to discharge the capacitor at shutdown. Thanks to low quiescent current, the device can be directly connected to battery. In this way, the device start-up and shutdown are controlled through the wake-up input function. The power supply and crossover function are controlled automatically through the internal state machine. The user can select both ECU logic voltage (VCC at 3.3 V or 5.0 V) and energy reserve output voltage (at either 23 V or 33 V). Deployment voltage is set to a maximum of 25 V for all profiles and can be controlled through external safing switch circuit using the high side safing switch reference enabled through the system SPI interface or the arming logic. DocID029257 Rev 1 13/277 276 Absolute maximum ratings 2 L9680 Absolute maximum ratings This part may be irreparably damaged if taken outside the specified absolute maximum ratings. Operation above the absolute maximum ratings may also cause a decrease in reliability. The operating junction temperature range is -40 °C to +150 °C. The maximum junction temperature must not be exceeded except when in deployment and within the deploy power stages. Deployment is possible starting with a junction temperature of 150 °C. A power dissipation calculation has to be performed for the final application limiting the available functionality to a subset of it in order to respect to the power dissipation capability. Table 2. Absolute maximum ratings Pin# Pin name 1 CS_RS 2 Min Max Unit Remote SPI interface chip select -0.3 VCC+0.3 6.5 V SCLK_RS Remote SPI interface clock -0.3 VCC+0.3 6.5 V 3 MOSI_RS Remote SPI interface data in -0.3 VCC+0.3 6.5 V 4 MISO_RS Remote SPI interface data out -0.3 VCC+0.3 6.5 V 5 RESET Reset output -0.3 VCC+0.3 6.5 V 6 MISO_G Global SPI interface data out -0.3 VCC+0.3 6.5 V 7 MOSI_G Global SPI interface data in -0.3 VCC+0.3 6.5 V 8 SCLK_G Global SPI interface clock -0.3 VCC+0.3 6.5 V 9 CS_G Global SPI interface chip select -0.3 VCC+0.3 6.5 V 10 WDT/TM Watchdog disable -0.3 20 V 11 SR4 Squib 4 low-side pin -0.3 40 V 12 SF4 Squib 4 high-side pin -1.0 40 V 13 SS45 Squib 4 & 5 deployment supply pin -0.3 40 V 14 SF5 Squib 5 high-side pin -1.0 40 V 15 SR5 Squib 5 low-side pin -0.3 40 V 16 SR0 Squib 0 low-side pin -0.3 40 V 17 SF0 Squib 0 high-side pin -1.0 40 V 18 SS01 Squib 0 & 1 deployment supply pin -0.3 40 V 19 SF1 Squib 1 high-side pin -1.0 40 V 20 SR1 Squib 1 low-side pin -0.3 40 V 21 SR8 Squib 8 low-side pin -0.3 40 V 22 SF8 Squib 8 high-side pin -1.0 40 V 23 SS89 Squib 8 & 9 deployment supply pin -0.3 40 V 24 SF9 Squib 9 high-side pin -1.0 40 V 25 SR9 Squib 9 low-side pin -0.3 40 V 26 DCS8 -2 40 V 14/277 Pin function DC Sensor interface channel 8 DocID029257 Rev 1 L9680 Absolute maximum ratings Table 2. Absolute maximum ratings (continued) Pin# Pin name 27 DCS7 28 Pin function Min Max Unit DC Sensor interface channel 7 -2 40 V DCS6 DC Sensor interface channel 6 -2 40 V 29 DCS5 DC Sensor interface channel 5 -2 40 V 30 DCS4 DC Sensor interface channel 4 -2 40 V 31 DCS3 DC Sensor interface channel 3 -2 40 V 32 DCS2 DC Sensor interface channel 2 -2 40 V 33 DCS1 DC Sensor interface channel 1 -2 40 V 34 DCS0 DC Sensor interface channel 0 -2 40 V 35 RSU0 PSI-5/WSS ch. 0 remote sensor output -1 40 V 36 RSU1 PSI-5/WSS ch. 1 remote sensor output -1 40 V 37 RSU2 PSI-5/WSS ch. 2 remote sensor output -1 40 V 38 RSU3 PSI-5/WSS ch. 3 remote sensor output -1 40 V 39 GPOD0 GPO driver 0 drain output pin -1 40 V 40 GPOS0 GPO driver 0 source output pin -1 40 V 41 GPOS1 GPO driver 1 source output pin -1 40 V 42 GPOD1 GPO driver 1 drain output pin -1 40 V 43 GPOD2 GPO driver 2 drain output pin -1 40 V 44 GPOS2 GPO driver 2 source output pin -1 40 V 45 COVRACT External Crossover Switch Driver -0.3 40 V 46 VCOREMON External Regulator Monitor -0.3 VCC+0.3 6.5 V 47 MCUFAULTB Active Low MCU Fault Monitoring Input -0.3 VCC+0.3 6.5 V 48 SATSYNC Initiate Satellite Sensor Sync Pulse -0.3 VCC+0.3 6.5 V 49 PSINHB Active Low Passenger Airbag Inhibit Control -0.3 VCC+0.3 6.5 V 50 GNDSUB1 Substrate ground / Squib ground -0.3 0.3 V 51 SRB Squib B low-side pin -0.3 40 V 52 SFB Squib B high-side pin -1.0 40 V 53 SSAB Squib A & B deployment supply pin -0.3 40 V 54 SFA Squib A high-side pin -1.0 40 V 55 SRA Squib A low-side pin -0.3 40 V 56 SR3 Squib 3 low-side pin -0.3 40 V 57 SF3 Squib 3 high-side pin -1.0 40 V 58 SS23 Squib 2 & 3 deployment supply pin -0.3 40 V 59 SF2 Squib 2 high-side pin -1.0 40 V 60 SR2 Squib 2 low-side pin -0.3 40 V 61 SR7 Squib 7 low-side pin -0.3 40 V DocID029257 Rev 1 15/277 276 Absolute maximum ratings L9680 Table 2. Absolute maximum ratings (continued) Pin# Pin name 62 SF7 63 SS67 64 Min Max Unit Squib 7 high-side pin -1.0 40 V Squib 6 & 7 deployment supply pin -0.3 40 V SF6 Squib 6 high-side pin -1.0 40 V 65 SR6 Squib 6 low-side pin -0.3 40 V 66 GNDA Analog ground -0.3 0.3 V 67 SAF_CS0 SPI interface safing sensor chip select 0 -0.3 VCC+0.3 6.5 V 68 SAF_CS1 SPI interface safing sensor chip select 1 -0.3 VCC+0.3 6.5 V 69 SAF_CS2 SPI interface safing sensor chip select 2 -0.3 VCC+0.3 6.5 V 70 SAF_CS3 SPI interface safing sensor chip select 3 -0.3 VCC+0.3 6.5 V 71 WD2_LockOut WD2 fault output -0.3 VCC+0.3 6.5 V 72 WS3 Wheel speed output Ch3 -0.3 VCC+0.3 6.5 V 73 WS2 Wheel speed output Ch2 -0.3 VCC+0.3 6.5 V 74 WS1 Wheel speed output Ch1 -0.3 VCC+0.3 6.5 V 75 WS0 Wheel speed output Ch0 -0.3 VCC+0.3 6.5 V 76 VCCSEL VCC select / VCOREMON disable input -0.3 40 V 77 ACL EOL disposal control input -0.3 40 V 78 WAKEUP Wake-up control input -0.3 40 V 79 VBATMON Battery line voltage monitor -18(1) 40 V 80 VSF Safing regulator supply output -0.3 40 V 81 VIN Battery connection -0.3 40 V 82 VER Reserve voltage -0.3 40 V 83 ERBOOST Energy reserve regulator output -0.3 40 V 84 ERBSTSW ER Boost switching output -0.3 40 V 85 BSTGND Boost regulators ground -0.3 0.3 V 86 SYNCBSTSW SYNC Boost switching output -0.3 40 V 87 SYNCBOOST SYNC boost output voltage -0.3 40 V 88 SATBCKSW SAT Buck switching output -0.3 40 V 89 SATGND SAT Buck regulator ground -0.3 0.3 V 90 SATBUCK SAT Buck output voltage -0.3 40 - 91 VCCBCKSW VCC Buck switch output -0.3 40 V 92 VCCGND VCC Buck Ground -0.3 0.3 V 93 CVDD Internal 3.3V regulator output -0.3 4.6 V 94 GNDD Digital ground -0.3 0.3 - 95 VCC VCC Buck voltage -0.3 6.5 V 96 ARM1 Arming output 1 -0.3 VCC+0.3 6.5 V 16/277 Pin function DocID029257 Rev 1 L9680 Absolute maximum ratings Table 2. Absolute maximum ratings (continued) Pin# Pin name 97 ARM2 98 Pin function Min Max Unit Arming output 2 -0.3 VCC+0.3 6.5 V ARM3 Arming output 3 -0.3 VCC+0.3 6.5 V 99 ARM4 Arming output 4 -0.3 VCC+0.3 6.5 V 100 GNDSUB2 Substrate ground / Squib ground -0.3 0.3 V - Exposed pad down Substrate ground / Squib ground -0.3 0.3 V 1. VBATMON negative AMR is -18 V or -20 mA. DocID029257 Rev 1 17/277 276 Operative maximum ratings 3 L9680 Operative maximum ratings Within the operating ratings the part operates as specified and without parameter deviations. Once taken beyond the operative ratings and returned back within, the part will recover with no damage or degradation. Additional supply voltage and temperature conditions are given separately at the beginning of each specification table. Table 3. Operative maximum ratings Pin # Pin name 1 CS_RS 2 Min Max Unit Remote SPI interface chip select -0.1 VCC+0.1 5.5 V SCLK_RS Remote SPI interface clock -0.1 VCC+0.1 5.5 V 3 MOSI_RS Remote SPI interface data in -0.1 VCC+0.1 5.5 V 4 MISO_RS Remote SPI interface data out -0.1 VCC+0.1 5.5 V 5 RESET Reset output -0.1 VCC+0.1 5.5 V 6 MISO_G Global SPI interface data out -0.1 VCC+0.1 5.5 V 7 MOSI_G Global SPI interface data in -0.1 VCC+0.1 5.5 V 8 SCLK_G Global SPI interface clock -0.1 VCC+0.1 5.5 V 9 CS_G Global SPI interface chip select -0.1 VCC+0.1 5.5 V 10 WDT/TM Watchdog disable -0.1 15 V 11 SR4 Squib 4 low-side pin -0.1 SS45 V 12 SF4 Squib 4 high-side pin -1.0 SS45 V 13 SS45 Squib 4 & 5 deployment supply pin -0.1 VER V 14 SF5 Squib 5 high-side pin -1.0 SS45 V 15 SR5 Squib 5 low-side pin -0.1 SS45 V 16 SR0 Squib 0 low-side pin -0.1 SS01 V 17 SF0 Squib 0 high-side pin -1.0 SS01 V 18 SS01 Squib 0 & 1 deployment supply pin -0.1 VER V 19 SF1 Squib 1 high-side pin -1.0 SS01 V 20 SR1 Squib 1 low-side pin -0.1 SS01 V 21 SR8 Squib 8 low-side pin -0.1 SS89 V 22 SF8 Squib 8 high-side pin -1.0 SS89 V 23 SS89 Squib 8 & 9 deployment supply pin -0.1 VER V 24 SF9 Squib 9 high-side pin -1.0 SS89 V 25 SR9 Squib 9 low-side pin -0.1 SS89 V 26 DCS8 DC sensor interface channel 8 -1 18 V 27 DCS7 DC sensor interface channel 7 -1 18 V 18/277 Pin function DocID029257 Rev 1 L9680 Operative maximum ratings Table 3. Operative maximum ratings (continued) Pin # Pin name 28 DCS6 29 Pin function Min Max Unit DC sensor interface channel 6 -1 18 V DCS5 DC sensor interface channel 5 -1 18 V 30 DCS4 DC sensor interface channel 4 -1 18 V 31 DCS3 DC sensor interface channel 3 -1 18 V 32 DCS2 DC sensor interface channel 2 -1 18 V 33 DCS1 DC sensor interface channel 1 -1 18 V 34 DCS0 DC Sensor interface channel 0 -1 18 V 35 RSU0 PSI-5/WSS ch. 0 remote sensor output -1 VRSU_SYNC_MAX V 36 RSU1 PSI-5/WSS ch. 1 remote sensor output -1 VRSU_SYNC_MAX V 37 RSU2 PSI-5/WSS ch. 2 remote sensor output -1 VRSU_SYNC_MAX V 38 RSU3 PSI-5/WSS ch. 3 remote sensor output -1 VRSU_SYNC_MAX V 39 GPOD0 GPO driver 0 drain output pin -0.1 40 V 40 GPOS0 GPO driver 0 source output pin -1 40 V 41 GPOS1 GPO driver 1 source output pin -1 40 V 42 GPOD1 GPO driver 1 drain output pin -0.1 40 V 43 GPOD2 GPO driver 2 drain output pin -0.1 40 V 44 GPOS2 GPO driver 2 source output pin -1 40 V 45 COVRACT External crossover switch driver -0.1 40 V 46 VCOREMON External regulator monitor -0.1 VCC+0.1 5.5 V 47 MCUFAULTB Active low MCU fault monitoring input -0.1 VCC+0.1 5.5 V 48 SATSYNC Initiate satellite sensor sync pulse -0.1 VCC+0.1 5.5 V 49 PSINHB Active low passenger airbag inhibit control -0.1 VCC+0.1 5.5 V 50 GNDSUB1 Substrate ground / Squib ground -0.1 0.1 V 51 SRB Squib B low-side pin -0.1 SSAB V 52 SFB Squib B high-side pin -1.0 SSAB V 53 SSAB Squib A & B deployment supply pin -0.1 VER V 54 SFA Squib A high-side pin -1.0 SSAB V 55 SRA Squib A low-side pin -0.1 SSAB V 56 SR3 Squib 3 low-side pin -0.1 SS23 V 57 SF3 Squib 3 high-side pin -1.0 SS23 V 58 SS23 Squib 2 & 3 deployment supply pin -0.1 VER V 59 SF2 Squib 2 high-side pin -1.0 SS23 V 60 SR2 Squib 2 low-side pin -0.1 SS23 V 61 SR7 Squib 7 low-side pin -0.1 SS67 V DocID029257 Rev 1 19/277 276 Operative maximum ratings L9680 Table 3. Operative maximum ratings (continued) Pin # Pin name 62 SF7 63 SS67 64 Min Max Unit Squib 7 high-side pin -1.0 SS67 V Squib 6 & 7 deployment supply pin -0.1 VER V SF6 Squib 6 high-side pin -1.0 SS67 V 65 SR6 Squib 6 low-side pin -0.1 SS67 V 66 GNDA Analog ground -0.1 0.1 V 67 SAF_CS0 SPI interface safing sensor chip select 0 -0.1 VCC+0.1 <= 5.5 V 68 SAF_CS1 SPI interface safing sensor chip select 1 -0.1 VCC+0.1 <= 5.5 V 69 SAF_CS2 SPI interface safing sensor chip select 2 -0.1 VCC+0.1 <= 5.5 V 70 SAF_CS3 SPI interface safing sensor chip select 3 -0.1 VCC+0.1 <= 5.5 V 71 WD2_LockOut WD2 Fault Output -0.1 VCC+0.1 <= 5.5 V 72 WS3 Wheel Speed Output Ch3 -0.1 VCC+0.1 <= 5.5 V 73 WS2 Wheel Speed Output Ch2 -0.1 VCC+0.1 <= 5.5 V 74 WS1 Wheel Speed Output Ch1 -0.1 VCC+0.1 <= 5.5 V 75 WS0 Wheel Speed Output Ch0 -0.1 VCC+0.1 <= 5.5 V 76 VCCSEL VCC select / VCOREMON disable input -0.1 35 V 77 ACL EOL disposal control input -0.1 35 V 78 WAKEUP Wake-up control input -0.1 VIN V 79 VBATMON Battery line voltage monitor -1 18 V 80 VSF Safing regulator supply output -0.1 27 V 81 VIN Battery connection -0.1 35 V 82 VER Reserve voltage -0.1 35 V 83 ERBOOST Energy reserve regulator output -0.1 35 V 84 ERBSTSW ER Boost switching output -0.1 35 V 85 BSTGND Boost regulators ground -0.1 0.1 V 86 SYNCBSTSW SYNC Boost switching output -0.1 35 V 87 SYNCBOOST SYNC boost output voltage -0.1 35 V 88 SATBCKSW SAT Buck switching output -0.1 35 V 89 SATGND SAT Buck regulator ground -0.1 0.1 V 90 SATBUCK SAT Buck output voltage -0.1 10 - 91 VCCBCKSW VCC Buck switch Output -0.1 10 V 92 VCCGND VCC Buck Ground -0.1 0.1 V 93 CVDD Internal 3.3V regulator output -0.1 3.6 V 94 GNDD Digital ground -0.1 0.1 - 95 VCC VCC Buck Voltage -0.1 5.5 V 20/277 Pin function DocID029257 Rev 1 L9680 Operative maximum ratings Table 3. Operative maximum ratings (continued) Pin # Pin name 96 ARM1 97 Min Max Unit Arming Output 1 -0.1 VCC+0.1 <= 5.5 V ARM2 Arming Output 2 -0.1 VCC+0.1 <= 5.5 V 98 ARM3 Arming Output 3 -0.1 VCC+0.1 <= 5.5 V 99 ARM4 Arming Output 4 -0.1 VCC+0.1 <= 5.5 V 100 GNDSUB2 Substrate ground / Squib ground -0.1 0.1 V Exposed Pad Down Substrate ground / Squib ground -0.1 0.1 V - Pin function DocID029257 Rev 1 21/277 276 Pin out 4 L9680 Pin out The L9680 pin out is shown below. The IC is housed in a 100 pin package (14 x 14 x 1.0mm) with a 7.6 x 7.6 mm exposed pad down. %67*1' (5%676: (5%2267 9&&6(/ 6<1&%676: $&/ 6<1&%2267 :$.(83 6$7%&.6: 9%$7021 6$7*1' 96) 6$7%&. 9(5 9&&%&.6: 9,1 9&&*1' &9'' 9&& $50 *1'' $50 $50 $50 *1'68% Figure 1. Pin connection diagram (top view) &6B56 :6 6&/.B56 :6 026,B56 :6 0,62B56 :6 5(6(7 :'B/RFN2XW 0,62B* 6$)B&6 026,B* 6$)B&6 6&/.B* 6$)B&6 &6B* 6$)B&6 :'770 *1'$ 65 65 6) 6) 66 66 6) 6) 65 65 65 65 6) 6) 66 66 6) 6) 65 65 65 65$ 6) 6)$ 66 66$% 6) 6)% 65 65% '&6 '&6 '&6 '&6 '&6 '&6 '&6 '&6 '&6 568 568 568 568 *32' *326 *326 *32' *32' *326 &295$&7 9&25(021 0&8)$8/7% 6$76<1& 36,1+% *1'68% ([SRVHGSDGGRZQ *$3*36 The exposed pad is electrically shorted to the substrate pins GNDSUB1 and GNDSUB2. These three connection nodes are to be kept shorted on the application. 22/277 DocID029257 Rev 1 L9680 Overview and block diagram 5 Overview and block diagram The L9680 IC is an application specific standard component air bag system chip. Its main functions include, power management, deployment drivers, remote sensor interfaces (PSI-5 satellite sensors or active wheel speed sensors), diagnostics, deployment arming, halleffect sensor interface, general purpose output drivers, watchdog timer, microcontroller failsafe input and control and a dedicated passenger airbag disarm signal. A block diagram for this IC is shown in Figure 2. 6<1&%2267 ; ; (5%676: ; (5%2267 ; ; ; 6<1&%RRVW 5HJXODWRU 9 $50 ; 36,+1% 6$)B&6 ; $50 6$)B&6 ; $50 6$)B&6 ; 6$)B&6 $&/ ; $50 :'770 ; 9&&%&.*1' 9&& ; 5(6(7 9&&6(/ 9&25(021 9&&%&.6: 6$7%8&. ; 9&&%XFN5HJXODWRU 99 6$7%XFN5HJXODWRU 9 6<1&%676: ; %67*1' ; ; ; ; ; ; ; ; *1'68% ([SRVHG3DG ; 9(5 ; 96) 'HSOR\PHQW'ULYHUV *OREDO&RQILJXUDWLRQ &RQWURO 5HPRWH6HQVRU &RQILJXUDWLRQ &RQWURO &RQILJXUDEOH *HQHUDO3XUSRVH 2XWSXW'ULYHUV +665(* :DNHXS 3RZHU0RGLQJ &RQWURO ; ; ; ; ; «« :6 :6 ; ; :6 ; :6 ; '& DocID029257 Rev 1 ; '& ; 0,62B56 ; 6&/.B56 ; 5HPRWH6HQVRU ,QWHUIDFH 026,B56 ; &6B56 *326 ; 0,62B* ; 026,B* ; 6&/.B* ; '&6HQVRU ,QWHUIDFH &6B* ; *326 &295$&7 ; *32' *1'$ ; *326 &9'' ; *32' ; *32' ; *1'' ; ; 66$% ; 6) ; 65 ; (5&$3'LDJQRVWLFV DQG &KDUJH&RQWURO :$.(83 ; 66 ; (QHUJ\5HVHUYH &URVVRYHU&RQWURO 9%$7021 ; ; ; (5%RRVW5HJXODWRU 99 ; 0&8)$8/7% :DWFKGRJ %LDV'LDJQRVWLFV$'& 9,1 :'B/2&.287 $UPLQJ6FUDSSLQJ&38,QWHJULW\0RQLWRU ««« ; ; ««« 6$7*1' ; ; ; ; *1'68% ([SRVHG3DG 6$7%&.6: Figure 2. Device function block diagram ; 6)% ; 65% ; 6$76<1& ; 568 ; 568 ; 568 ; 568 *$3*36 23/277 276 Overview and block diagram 5.1 Power supply 5.2 Integrated 1.882 MHz boost regulator, 33 V ± 5% or 23 V ± 5% nominal output Integrated 1.882 MHz boost regulator,12 V/14.75 V nominal output, user selectable via SPI command Integrated 1.882 MHz synchronous buck regulator, 7.2 V/9 V ± 4% nominal output, user selectable via SPI command Integrated 1.882 MHz synchronous buck regulator, 5 V ± 3% or 3.3 V ± 3% nominal output, user selectable via VCCSEL pin Over and under voltage detection and shutdown for all regulators Under-voltage lockout to guarantee buck regulator outputs disabled and discharged Integrated energy reserve capacitor fixed constant current source (65 mA, nominal) switch for controlled inrush and charge characteristics Integrated energy reserve diagnostics, capacitor value and ESR Integrated energy reserve crossover switch with current limit and battery input voltage monitoring Crossover switch ‘active’ output signal Integrated 25 V/20 V SPI selectable linear regulator for high side safing FET gate supply enabled via SPI or arming logic Reset output Deployment drivers 24/277 L9680 12 high side deployment drivers, 12 low side deployment drivers User programmable deployment options – 1.20 A or 1.75 A minimum – programmable time in 0.1ms increments Capability to deploy a squib with a minimum current of 1.2 / 1.75 A and the low side FET shorted to ground up to 25 V on SSxy Independently-controlled high-side and low-side FETs Squib resistance measurement Firing current monitor feature High and low side FET tests Open & shorts diagnostics, including between loop drivers Independent fire enable logic, SPI and discrete digital input DocID029257 Rev 1 L9680 5.3 Overview and block diagram Remote sensor interfaces (4) 5.4 DC sensor interfaces (9) 5.5 Nine integrated switch interfaces with current sense capability Compatible with Hall-effect, resistive and switch sensors Current limit protected System dedicated path to disable the passenger airbag with input from DC sensor interface General purpose outputs (3) 5.6 Quad channel receiver, user selectable – standard PSI-5 v1.3 compatible with sync pulse or – active wheel speed sensors High side drivers for active wheel speed sensor mode (with driver protection) Current limit with short circuit protection diagnostics PSI-5 satellite sensor mode – Auto-adjusting current trip points for each satellite channel – Even parity, 8 or 10 bit messages, 125k or 189kbps – Satellite message error detection Active wheel speed sensor mode – Standard active dual level sensors, 7ma/14ma – Three level sensors with direction and air gap data, 7ma/14ma/28ma – PWM encoded two level sensor, 2 edges/tooth – PWM encoded two level sensor, 1 edge/tooth – Standard active two and three level sensor data decoding available through SPI Three configurable high-side or low-side drivers ON-OFF mode and PWM 0-100% fine control Diagnostics for short circuit protection and open load detection Current limit and reverse battery protected Arming logic User configurable safing algorithms with 16 safing records Four digital sensor interfaces through SPI Independent user programmable thresholds Independent user programmable latch timers Four discrete and independent arming logic outputs Four discrete and independent internal arming signals End-of-life interface DocID029257 Rev 1 25/277 276 Overview and block diagram 5.7 Other features 26/277 L9680 One dedicated 32-bit SPI bus for global configuration and control One dedicated 32-bit SPI bus for remote sensor configuration and control Microcontroller ‘state of health’ input and control function Integrated watchdog control with 2 independent structures: windowed WD and algorithmic WD Temperature sensor Independent thermal shutdown protection on the ER boost switch, the SYNC boost switch, the energy reserve crossover switch, the energy reserve charge paths, the remote sensor interfaces and the general purpose outputs All diagnostics are digital and are available through SPI communications Configurable logic operation, 5 V or 3.3 V DocID029257 Rev 1 L9680 Start-up and power control 6 Start-up and power control 6.1 Power supply overview The L9680 IC contains a complete power management system able to provide all necessary voltages for a high feature airbag system or integrated safety system. A general block diagram is shown in Figure 3. The power supply block contains the following features: Two 3.3 V internal regulators for operating internal logic (CVDD) and analog circuits (VINT3V3). An external CVDD pin is used to provide filtering capacitance to digital section supply rail. Energy reserve supply (ERBOOST) achieved through an integrated 1.882 MHz switching boost regulator. The energy reserve capacitor is charged using an internal constant current source controllable through SPI. Besides, a second current source is available to discharge the capacitor. The primary function for the second current source is to diagnose the integrity of the energy reserve capacitor, value and ESR. During system shutdown, the device can enable the discharge current source via SPI command to quickly dissipate the remaining energy stored in the energy reserve capacitor. Sync pulse supply (SYNCBOOST) is achieved through an integrated 1.882 MHz switching boost regulator. The SYNCBOOST regulator ensures a minimum voltage is available for operating the satellite sync signal and also provides the input voltage to the remote sensor buck regulator. The sync pulse boost regulator is disabled for battery voltage levels resulting in an output voltage above the set regulation point. The integrated current limited ER switch requires no external components. This switch is controlled through the integrated power control state machine and is enabled either once a loss of battery is detected or a shutdown command is received. Under the same conditions also the discrete digital pin COVRACT is activated allowing the control of an external optional cross-over switch. Two 1.882MHz synchronous buck regulators for remote sensor supply and VCC. The SATBUCK regulator, remote sensor buck supply, is sourced from the SYNCBOOST regulator and can be selected to be either 7.2 V or 9 V nominal. The VCC regulator is sourced from the SATBUCK regulator and is user selectable through the VCCSEL pin to either 5 V or 3.3 V nominal voltage. Battery voltage sense input comparator with hysteresis and wake-up input are the primary control signals for the power supply control state machine. Based on own mission profile and ECU total current consumption, the user must evaluate if the activation of fast slope option of each ERBoost, SyncBoost and SatBuck regulator (bit 8/9/10, $3F SW_REGS_CONF SPI register) is needed to increase the overall efficiency. DocID029257 Rev 1 27/277 276 Start-up and power control L9680 Figure 3. Power supply block diagram Vbat + + ERBSTSW ER CAP VER ERBOOST VSF VSF Regulator ER Boost ER Charge / Discharge and ER CAP Diag ER Switch VBAT _MON Battery monitor VIN IGN WAKEUP Wake up VINT3V3 Regulator VDD Regulator CVDD GNDSUBx SYNCBSTSW SYNC BOOST Logic block Oscillator s GNDD BSTGND SYNCBOOST SATBCKSW SAT BUCK L9680 SATGND SATBCK VCCBCKSW VCC Buck VCCSEL Output Buffer VCCGND VCC RESET GNDSUBx GAPGPS02249 28/277 DocID029257 Rev 1 L9680 6.2 Start-up and power control Power mode control Start-up and power down of the L9680 are controlled by the WAKEUP pin, VBATMON pin, VIN pin, device status and the SPI interface. There are four main power modes: power-off, sleep, active and passive mode. Each power mode is described below and represented in the state flow diagram shown in Figure 4. The descriptions include references to conditions and sometimes nominal values. The absolute values for each condition are listed in the electrical specifications section. Figure 4. Power control state flow diagram )URP DQ\VWDWH 325 32:(5 2)) VWDWH :DNH8S)LOW $1' 63,B6<6B&7/63,B2)) 32:(52))02'( $OOVXSSOLHVGLVDEOHG :$.(83 :8BPRQ :$.(83! :8BPRQ :$.(83 021,725 VWDWH >:$.(83:8BRII$1' :DNH8S)LOW @ :$.(83! :8BRQ :DNH8S)LOW $1' 9,19,1*22' $:$.( 6WDWH 6/((302'( :DNH8S)LOW 25 9,19,1%$' :DNH8S)LOW $1' 9,1!9,1*22' 67$5783 VWDWH :DNH8S)LOW $1' 9,1!9,1*22' 7ZDNHXS!PV :DNH8S)LOW $1'63,B6/((3 581 VWDWH 7!7YLQJRRGBEON $&7,9(02'( 9,19,1*22' 32:(502'( 6+87'2:1 VWDWH :DNH8S)LOW $1'63,B6/((3 (5 VWDWH 9%$7PRQ!9%*22' EODQNLQJWLPHPV :DNH8S)LOW $1'63,B6/((3 7ZDNHXS7LPHU&OHDUHGLI6WDWH :$.(83021,725RU$:$.( DQG:DNH8S)LOW DocID029257 Rev 1 9,1*22' EODQNLQJ VWDWH 3$66,9(02'( *$3*36 29/277 276 Start-up and power control 6.2.1 L9680 POWER OFF mode During the POWER-OFF Mode all supplies are disabled keeping the system in a quiescent state with very low current draw from battery. As soon as WAKEUP>WU_mon the IC will move to SLEEP Mode. 6.2.2 SLEEP mode During the Sleep mode the VINT3V3 and CVDD internal regulators are turned on and the IC is ready for full activation of all the other supplies. As soon as VIN voltage is over a minimum threshold, all the other supplies are turned on and the IC enters the ACTIVE mode. 6.2.3 ACTIVE mode This is the normal operating mode for the system. All power supplies are enabled and the energy reserve boost converter starts to increase the voltage at ERBOOST. Likewise, the SYNCBOOST boost converter continues to charge and regulate to a nominal 12 V (default level at startup). Once the SYNCBOOST has reached a good value, the SATBUCK regulator starts up. In turn, when SATBUCK has ramped up, VCC regulator is enabled. Once the VCC buck regulator is in regulation, RESET is released allowing the system microcontroller and other components to begin their poweron sequence. Among these, also the ER charge current generator can be enabled by the microcontroller via a dedicated SPI command. The active mode can be left when either WAKEUP pin or VIN voltage drop down. For the very first 9ms after having entered the active mode, the WAKEUP pin low would immediately cause the IC to switch back to sleep mode. After that time, WAKEUP pin low must be first confirmed by a μC SPI_SLEEP command prior to cause the system to switch to passive mode. Passive mode is also entered in case of VIN voltage low. 6.2.4 PASSIVE mode In this state, the reserve capacitor charge current and the ERBOOST boost converter are disabled. When in passive mode the device activates both the COVRACT output pin and the integrated ER switch to allow VIN to be connected to the ER capacitor. In this time, VIN is supposed to be increased up to almost VER level and the system operation relies on energy from the ER capacitor. Two scenarios are possible: high or low battery. If VIN < VINGOOD, the device moved from RUN state in ACTIVE mode to the ER state. Here, the ER capacitor is depleted while supplying all the regulators until the POR on internal regulator occurs. The threshold to decide the ER switch activation is based on VIN, because VIN is the supply voltage rail for ERBOOST regulator. If the device has still a good battery level, it entered the POWERMODE SHUTDOWN thanks to a microcontroller command to switch off. In this case, the VER node will be discharged down to approximately VIN level, which then will be supplied out of the battery line. System will continue to run up to a dedicated SPI command to disable the SATBUCK regulator, which will lead the device to enter the POWEROFF state. The wake-up pin is filtered to suppress undesired state changes resulting from transients or glitches. Typical conditions are shown in the chart below and summarized by state. 30/277 DocID029257 Rev 1 L9680 Start-up and power control Figure 5. Wake-up input signal behaviour ACTIVE MODE SLEEP MODE PASSIVE MODE 1 2 3 5 4 6 WU_on WU_off WAKEUP t <1ms 1ms <1ms 10ms 1ms WakeUpFilt t GAPGPS02251 Condition summary: 1. 2. 3. 4. 5. 6. No change of sleep mode state but current consumption may exceed specification for sleep mode. The sleep mode current returns to within specified limits. Power supply exits sleep mode. Switchers start operating if applicable voltages exceed under voltage lockouts. As Twakeup timeout is not elapsed, a low level at WAKEUP instantaneously sends the system back to sleep. Sleep reset is released and the entire system starts operating. An SPI command to enter sleep state would not be executed. No change in system status, an SPI command to turn off switchers would be ignored. No change in system status, but an SPI command to turn off switchers would be accepted and turn the system off. With the below table, all the functionalities of the device are shown with respect of the power states. When one function is flagged, the related circuitry cannot be activated on that state. Table 4. Functions disabling by state Power MODE Functions Power off Sleep Power off Wakeup Awake monitor Active Startup Passive Run Wakeup detector X Internal regulators X X ERBOOST regulator X X X SYNCBOOST regulator X X X ER CAP charge current X X X ER CAP discharge current X X X ER switch X X X X X COVRACT X X X X X Power mode shutdown ER VINGOOD blanking X X DocID029257 Rev 1 X X X X X 31/277 276 Start-up and power control L9680 Table 4. Functions disabling by state (continued) Power MODE Functions Power off Sleep Power off Wakeup Awake monitor Active SATBUCK regulator X X X VCC regulator X X X Deployment Drivers X X X VSF Safing FET regulator X X X Remote Sensor Interfaces X X X Watchdog X X X Diagnostics X X X DC Sensor Interface X X X GPO drivers X X X Safing Logic X X X 32/277 Startup DocID029257 Rev 1 Run Passive Power mode shutdown ER VINGOOD blanking L9680 6.2.5 Start-up and power control Power-up and power-down sequences The behaviour of the IC during normal power-up and power-down is shown in Figure 6 to Figure 9. The following sequences represent just a subset of all possible power-up and power-down scenarios. In Figure 6 a normal IC power-up controlled by the state of the WAKEUP pin is shown. Figure 6. Normal power-up sequence <50μA VIN current <50μA VBGOOD VBAT _MON VBBAD WU_on WU_mon WAKE UP WU_off VINT_UV VINT <1ms POR VIN >1ms VINGOOD VINBAD ERBSTSW and SYNCBSTSW VIN-Vdiode ERBOOST VER 0V VIN-Vdiode SYNCBOOST_OK SYNCBOOST 0V SAT BCKSW SATBUCK_OK SATBUCK 0V VCCBCKSW 0V VCC_UV VCC 0V RESET 0V RESET_Hold_Time SPI command SPI_SYS_CTL(ER_CUR_EN)=01 GAPGPS02252 DocID029257 Rev 1 33/277 276 Start-up and power control L9680 Figure 7. Normal power down sequence through POWERMODE SHUTDOWN state no ER cap active discharge 63,B6/((3 63,FRPPDQG 9%$7 B021 9,1 9%*22' 9EDW9GLRGH 9,1*22' PV :$.( 83 63,B2)) !PV !PV 9,17B89 9,17 325 (5%676: (5%2267 (5GLVFKDUJHE\UHJXODWRUV 9(5 &295$&7 (56:,7&+ (QDEOH 6<1&%676: 6<1&%2267 9,19GLRGH 6$7 %&.6: 6$7%8&. 9&&%&.6: 9&&B89 9&& 5(6(7 *$3*36 34/277 DocID029257 Rev 1 L9680 Start-up and power control Figure 8. Normal power down sequence through Powermode Shutdown state - ER cap active discharge 63,B6/((3 63,FRPPDQG 63,B6<6B&7/ (5B&85B(1 63,B2)) 9%$7 B021 9EDW9GLRGH 9,1 9,1*22' PV :$.( 83 !PV !PV 9,17B89 9,17 325 (5%676: (5%2267 9EDW9GLRGH (5GLVFKDUJHE\UHJXODWRUV 9(5 9(5B9%$7021B97+ 9,19 (5GLVFKDUJHE\P$ &XUUHQWJHQHUDWRU (5B6:,7&+ (QDEOH &295$&7 6<1&%676: 9,19GLRGH 6<1&%2267 6$7 %&.6: 6$7%8&. 9&&%&.6: 9&&B89 9&& 5(6(7 *$3*36 DocID029257 Rev 1 35/277 276 Start-up and power control L9680 Figure 9. Normal power down sequence through ER state 9%*22' 9%%$' 9 9%$7 B021 9EDW9GLRGH 9,1 9,1*22' 9,1%$' :$.( 83 :8BRQ :8BRII 9,17B89 9,17 325 (5%676: (5%2267 (5GLVFKDUJHE\UHJXODWRUV 9(5 &295$&7 (56:,7&+ HQDEOH 6<1&%676: 6<1&%2267 6$7 %&.6: 6$7%8&. 9&&%&.6: 9&&B89 9&& 5(6(7 *$3*36 36/277 DocID029257 Rev 1 L9680 6.2.6 Start-up and power control IC operating states Different states can be identified while operating the device. These states allow safe and predictable initialization, test, operation and final disposal of the part (scrapping). As soon as the RESET signal is de-asserted at the beginning of the ACTIVE mode, the microcontroller powers up. At this stage, L9680 is in the Init state: during this state the device must be initialized by the controller. In particular, the watchdog timer window can be programmed during this state. When the watchdog service begins (upon the first successful watchdog feed), the device switches to Diag state for diagnostics purposes. The remaining configuration of the device is allowed in this state, in particular for safing records and deployment masks. Several tests are also enabled while in this state and all these tests are mutually exclusive to one another. HS and LS switch tests of the squib drivers can only be processed during this Diag state. Also high side safing FET can only be run during this state. When not in Diag state, any commands for squib driver switch tests will be ignored. Other checks are also performed: on the arming outputs to check for non-stuck-at conditions on the pins and on the configured firing time configuration through one of the ARMx pin. The SSM remains in this state until commanded to transition into the Safing state or Scrap state via the dedicated SPI commands. Upon reception of the SAFING_STATE command while in Diag state, the device enters Safing state. This is the primary run-time state for normal operation, and the logic performs the safing function, including monitoring of sensor data and setting of the ARMx signals. The only means of exiting Safing state is by the assertion of the SSM_Reset signal. The Scrap state is entered upon reception of the SCRAP_STATE command while in Diag state. While in Scrap state, the part allows the main microcontroller to initiate a transition to Arming state, and monitoring of the Remote Sensor SPI interface and the safing logic is disabled. From Scrap state, the device can transition to Arming state only, and the only means of moving back to Init state is through an SSM_Reset. In order to protect from inadvertent entry into Arming state, and to prevent undesired activation of the safing signals, a handshake mechanism is used to control entry into, and exit from Arming state. This handshake is described further in Section 11.6. While in Arming state, the arming outputs are asserted. Exit from Arming state occurs when the periodic SCRAP_KEY commands cease (timeout), the key value is incorrect, or when SSM_Reset is asserted. Upon exit, the device re-enters Scrap state, except for the case of SSM_Reset, which results in entry into Init state. The device operating states are shown in Figure 10. DocID029257 Rev 1 37/277 276 Start-up and power control L9680 Figure 10. IC operating state diagram 6605HVHW &RQILJXUDWLRQHQDEOHGIRU : DWFKGRJWLPLQJWKUHVKROGV +6/6*32 $50LQRXWVHOHFW 36,1+ ,QLW 6WDWH 7HVWLQJHQDEOHGIRU $50[96)36,1+ 'HSOR\WLPH +6/6+66)(7 :66 :'B29(55,'(25:'B581 :'B29(55,'(25:'B581 &RQILJXUDWLRQDQDEOHGIRU 6DILQJ5HFRUGVDQGFRQWURO 'HSOR\PDVN +6/6*32 36,:66VHOHFW 'LDJ 6WDWH 63,6&5$3B67$7( 63,6$),1*B67$7( $50[96)GHWHUPLQHG %\VDILQJHQJLQH 6FUDS 6WDWH 6DILQJ 6WDWH $&/%$' 25 A6&5$3.(<VWDWH $50[ 96) $&/*22' $1' 6&5$3.(<VWDWH $UPLQJ 6WDWH $50[ 96) *$3*36 6.3 ERBOOST switching regulator The L9680 IC uses an advanced energy reserve switching regulator operating at 1.882MHz nominal. The higher switching frequency enables the user to select smaller less expensive inductors and moves the operating frequency to permit easier compliance with system emissions. The ERBoost switching regulator uses a classical peak current mode control loop to properly regulate the output voltage and includes an over-voltage protection that immediately switch off the PowerMOS to protect the device. The regulator includes also a soft start circuit which apply a ramp on the over current threshold from the 40% of IOC_ERBST value to the maximum one with 16 steps and within 1024 μs. The soft start is restarted every time the regulator has a transition from the ER_BST_OFF to the ER_BST_ON state. The energy reserve boost regulator charges the external system tank capacitor through an integrated fixed current source significantly reducing in-rush currents typical of large energy reserve capacitors. The boost circuit provides energy for the reserve capacitor with assumed run time load of less than 20 mA and to the VSF regulator. Once system shutdown is initiated or a loss of battery condition is diagnosed, the boost regulator is by default disabled so that system power can be taken from the energy reserve capacitor. Alternatively, the ER Boost could be kept on even during the ER State by setting the SYS_CFG(KEEP_ER_BOOST_ON) bit. The energy reserve boost regulator defaults to 23 V at power-on and can be set to 33 V nominal by the user through an SPI command. The boost converter can also be disabled by the user through an SPI command. Enabling, disabling and setting the boost output voltage 38/277 DocID029257 Rev 1 L9680 Start-up and power control is done through the System Control (SYS_CTL) register. Boost converter diagnostics include over voltage and under voltage and the circuit is fully protected against shorts. Boost fault status is available through the SPI in Fault Status Register (FLTSR). The integrated FET featuring the boost switch is protected against short to battery by means of a thermal shutdown circuit. When thermal fault is detected the FET is switched off and latched in this state until the related fault flag ERBST_OT in the FLTSR register is read. In case of loss of BSTGND ground the FET is not turned on. Loss of ground can be detected also when the FET is off thanks to a pull-up current present on the BSTGND pin. The FET will be automatically reactivated as soon as ground connection is restored. Over-voltage protection from load dump and inductive flyback is provided via an active clamp and an ER_Boost disable circuitry, see Figure 11. Figure 11. ERBOOST regulator block diagram 9,1 (5%67B&/$03 B(17+ (5%67 'ULYHU &RQWURO (5%67B',6$%/( 7+ HUEVW BHQ (5%2267 (5%676: &RPS &/$03 %67*1' *$3*36 Normal run time power for the system is provided directly from the battery input, not from the boost. Boost energy is available to the system through the energy reserve crossover switch once battery is lost or a commanded system shutdown is initiated. DocID029257 Rev 1 39/277 276 Start-up and power control L9680 Figure 12. ERBOOST regulator state diagram 32:(52))B02'( 256/((3B02'( (5%2267 SRZHUPRGHFRQWURO 'HIDXOW6<6B&7/(5B%67B(1 DW325 $FWLYHBPRGH $1' 9%$7021!9%*22' 25 (5BVWDWH $1' 6<6B&)*.((3B(5%67B21 $1' 9,1!9,1*22' $1' 6<6B&7/(5B%67B(1 $1' *1'%2267BORVV $1' (5%67B27 $1' (5%67B',6$%/( 63,B6<6B&7/(5B%67B(1 $1' (5%67B27 (5%672)) (5%6767%< (5%6721 (5%6727 >$FWLYHBPRGH 25 9%$70219%%$' $1' (5BVWDWH 25 63,B)/7655($' 6<6B&)*.((3B(5%67B21 @ $1' 25 (5%67B27 9,19,1%$' (5%67B27 25 6<6&7/(5B%67B(1 25 *1'%2267BORVV 25 (5%67B',6$%/( (5%67B27 *$3*36 6.4 Energy reserve capacitor charging and discharging circuits The energy reserve capacitor connected to VER pin can be charged in an efficient way by means of a current generator. Its capability is 65 mA nominal, so that for example a 10 mF capacitor can be charged in approximately 4 s to 24 V. The current generator is activated or deactivated by SPI command only while in ACTIVE mode. When not in ACTIVE mode, the generator is always switched off in order to decouple ERBOOST node voltage from VER reserve voltage. Figure 13. ER charge state diagram (5&KDUJH SRZHUPRGHFRQWURO 660B5HVHW 63,B6<6B&7/(5B&85B(1>@ $1' (5&+$5*(B27 'HIDXOW6<6B&7/(5B&85B(1>@ DW 660B5(6(7 (5&+$5*( 67%< (5&+$5*( 2)) $FWLYHBPRGH $1' 6<6B&7/(5B&85B(1>@ $1' ³(5&$3(65',$*QRWLQSURJUHVV´ $FWLYHBPRGH 25 6<6B&7/(5B&85B(1>@ (5&+$5*( 21 (5&+$5*(B27 63,B)/7655($' $1' (5&+$5*(B27 (5&+$5*( 27 (5&+$5*(B27 *$3*36 L9680 also offers a safe control to discharge the ER capacitor by means of a fixed current generator. This discharge can be controlled via SPI command while not in SLEEP mode. Furthermore, this discharge circuit is mutually exclusive with the ER charging circuit, to avoid inefficient way of controlling the charge on the VER energy reserve capacitor. 40/277 DocID029257 Rev 1 L9680 Start-up and power control Figure 14. ER discharge state diagram (5'LVFKDUJH SRZHUPRGHFRQWURO 660B5HVHW 'HIDXOW6<6B&7/(5B&85B(1>@ DW 660B5(6(7 6/((3B02'( 25 (5B67$7( 25 63,(5B&85B(1>@ (5',6&+$5*( 2)) 5HVHW7 6/((3B02'( 25 (5B67$7( 25 63,(5B&85B(1>@ 25 32:(5B02'(B6+87'2:1 $1' 9(5B9%$7021B&203 >$FWLYHBPRGH 25 32:(5B02'(B6+87'2:1 $1' 9(5B9%$7021B&203 @ $1' 6<6B&7/(5B&85B(1>@ $1' ³(5&$3(65',$*QRWLQSURJUHVV´ (5',6&+$5*( 21 6WDUW7PV (5',6&+$5*( 67%< (5B'LVFKDUJH2)) 32:(5B02'(B6+87'2:1 32:(5B02'(B6+87'2:1 $1'7WLPHRXW 9(5B9%$7021B&203 ZKHQ9(59%$70219YHUBYEDWPRQBWK *$3*36 6.5 ER CAP diagnostic The L9680 IC contains a full integrated solution to check the connection, value and series resistance of energy reserve capacitor independent from ER Cap leakage current and Boost Voltage level. 6.5.1 ER CAP measurement The IC contains two current generators used to charge and discharge the energy reserve capacitor connected on ER pin. The simplified block diagram is shown in the figure below. Figure 15. ER CAP measurement block diagram (5&DS (5%2267 9(5 (5B&+$5*( (65 & (1 , OHDN &$3PHV (5B',6&+$5*( $'& ELW *1'$ *1'B$'& *$3*36 To obtain an accurate ER CAP measurement, the VER voltage conversion must be required when both current generators are off, namely no current flows through ER cap permits to avoid ESR error contribution. DocID029257 Rev 1 41/277 276 Start-up and power control L9680 The user can decide the charge and discharge time based on the ER CAP used in application, in order to maximize the differential voltage and then improve the accuracy. Anyway, a timeout on ER Discharge current has been implemented to prevent thermal issue, so the discharge time cannot be longer than 350 ms. Figure 16. ER CAP measurement timing diagram (65! 9HQG 9VWDUW 9(5W 9VWRS (65 (5B&+$5*( (5B',6&+$5*( 7 7 *$3*36 The following formulas can be used to retrieve the ER CAP value from the voltage and timing measurements. I 1 + I LEAK I 2 – I LEAK - T 1 + --------------------------T V 1 + V 2 = -------------------------2 C C 2IT C = ---------------------------------------------------------------V start + V end – 2 V stop T1 = discharge time T2 = charge time, same as discharge time T1 = T2 = T V1 = Vstart - Vstop V2 = Vend - Vstop I1 = discharge current I2 = charge current, same as discharge current I1 = I 2 = I ILEAK = leakage current 42/277 DocID029257 Rev 1 L9680 6.5.2 Start-up and power control ER CAP ESR measurement The IC contains the capability to perform a measurement of the equivalent series resistance of energy reserve capacitor. In this case the discharge current is 10 times higher to create a voltage difference proportional to the ER CAP ESR. The voltage measurement and conversion is automatically executed once the user requires the ESR measurement through the LPDIAGREQ register. Figure 17. ER ESR measurement block diagram (5&DS 9(5 (65 , OHDN & /HYHOVKLIWHU 6+ (5B',6&+$5*( *1'$ $'& ELW *1'B$'& *$3*36 Upon an ESR measurement is requested, the IC executes an internal automatic sequence to take three voltage measurements at the ER node, toggling the ER discharge current source on and off as shown in Figure 18. The test lasts for TESR_DIAG. After this time has elapsed, the results can be retrieved by reading the DIAGCTRL_x registers. The three ER voltage measurements are provided at the same time in DIAGCTRLA, DIAGCTRLB and DIAGCTRLC registers. During the execution of the ESR measurement no other activity on ADC is allowed. The user must ensure no other ADC requests are queued to be executed at the same time of ESR measurement. The ESR diagnostic, once initiated, will continue without interruption even if the device enters in ER State because of a battery loss event. DocID029257 Rev 1 43/277 276 Start-up and power control L9680 Figure 18. ER ESR measurement timing diagram &6B*GLDJQRVWLFUHTXHVWIURPPLFURFRQWUROOHU V V (5B',6&+$5*( (1$%/( V V V V 9(5YROWDJH 9D9E9F VWDUWVDPSOLQJ 9D VWRSVDPSOLQJ VWDUWRIFRQY 9E VWRSVDPSOLQJ VWDUWRIFRQY 9F VWRSVDPSOLQJ VWDUWRIFRQY *$3*36 The ER CAP ESR can be calculated according to the following formula: VC – VB - + OFF ER_ESR ESR ERCAP = ---------------------------------------------------------------------------------------G ER_ESR I ER_DISCHARGE_HIGH 6.6 ER switch and COVRACT pin L9680 allows the system to run out of the reserve capacitor energy stored on VER node by means of the charging boost regulator. In this way, an extended operation can take place even in case of battery lost. The ER switch implements a connection from the VER pin to the VIN node, supply input for the SYNCBOOST regulator and for internal power supplies. The ER switch is automatically activated upon entering the PASSIVE mode. Voltage difference between VIN and VER is monitored in order to prevent VER back-feeding when VIN exceeds VER by VER_SW_OV_TH. The ER switch is automatically deactivated upon the above mentioned overvoltage detection. During PASSIVE mode the discrete digital output pin COVRACT is activated to allow for external optional cross-over switch control (except during VINGOOD blanking state, where the COVRACT is deactivated). 44/277 DocID029257 Rev 1 L9680 Start-up and power control Figure 19. ER switch state diagram (56ZLWFK 77LPHRXW 325 ³'HSOR\PHQWLQSURJUHVV´ (5BVZLWFKB67%< 6WDUW7PV (5BVZLWFKB2)) 3DVVLYHBPRGH $1' (5B6:B29 3DVVLYHBPRGH 25 (5B6:B29 (5B6:,7&+B76' $1' ³GHSOR\PHQWQRWLQ SURJUHVV´ (5B6:,7&+B76' (5B6:,7&+B76' (5BVZLWFKB2))B27 (5BVZLWFKB21 (5B6:,7&+B76' $1' ³GHSOR\PHQWQRWLQSURJUHVV´ (5B6:B29 ZKHQ9,19(5!9HUBVZBRYBWK *$3*36 6.7 SYNCBOOST boost regulator The SYNCBOOST boost regulator also operates at 1.882 MHz allowing the user to select smaller less expensive external components. The regulator provides a 12 V/14.75 V nominal for the sync pulse feature used in PSI-5 bussed satellite sensor configuration. The regulator also provides the power for the SATBUCK regulator. The SyncBoost switching regulator uses a classical peak current mode control loop to properly regulate the output voltage and includes an over-voltage protection that immediately switch off the PowerMOS to protect the device. The regulator includes also a soft start circuit which apply a ramp on the over current threshold from the 40% of IOC_SYNCBST value to the maximum one with 16 steps and within 1024 μs. The soft start is restarted every time the regulator is enabled, namely there is a transition from the SYNCBOOST_OFF state to the SYNCBOOST_ON state. In normal operation, the SYNCBOOST regulator operates directly from battery providing a voltage level to operate the sync pulse driver circuit. Should the input voltage be greater than regulation point, the output voltage will track the input voltage less any drops in the external components. The boost regulator is enabled automatically by the power control state machine, but can be disabled on purpose via SPI command through the SYS_CTL(SYNCBST_EN) bit. The regulation point is fixed at a nominal 12 V at startup. User may increase the output regulation voltage to 14.75 V nominal by setting the SATV bit via a dedicated SPI command, should an extended voltage range be needed. Boost converter diagnostics include over voltage and under voltage, reported by the S_BST_NOK bit in the POWER_STATE register, and the circuit is fully protected against shorts. The integrated FET featuring the boost switch is protected against short to battery by means of a thermal shutdown circuit. When thermal fault is detected the FET is switched off and latched in this state until the related fault flag ERBST_OT in the FLTSR register is read. DocID029257 Rev 1 45/277 276 Start-up and power control L9680 In case of loss of ground the FET is not turned on. Loss of ground can be detected also when the FET is off thanks to a pull-up current present on the BSTGND pin. The FET will be automatically reactivated as soon as ground connection is restored. Over-voltage protection from load dump and inductive flyback is provided via an active clamp and a SYNC_Boost disable circuitry, see Figure 20. Figure 20. SYNCBOOST regulator block diagram 6<1&%67B&/$03 B(17+ 6<1&%67B ',6$%/( 7+ V\QFEVW BHQ 6<1&%2267 6<1&%676: 6<1&%67 'ULYHU &RQWURO 9,1 &RPS &/$03 %67*1' *$3*36 Figure 21. SYNCBOOST regulator state diagram 6<1&%2267 SRZHUPRGHFRQWURO ULVLQJHGJHRI6<1&%67B5(67$57$1' 6<6B&7/5(67$57B6<%67B6(/ 25 9,1B6<1&%67B5(67$57 $1' 6<6B&7/5(67$57B6<%67B6(/ 25 H[LWIURP(5B67$7( 25 63,UHFHLYHG6<6B&7/.((3B6<1&%67B21 6<1&%2267 7(032)) 32:(52))B02'( 256/((3B02'( 77LPHRXW 6<1&B%67B67%< 6WDUW7PV 6<1&%22672)) 9,1!9,1*22' $1' 6<6B&7/6<1&%67B(1 $1' %67*1'BORVV $1' 6<1&%67B',6$%/( $1' 6<1&%67B27 $1' 9,16<1&B',6 $1' 6<1&%67B29 9,19,1%$' 25 6<6B&7/6<1&%67B(1 25 %67*1'BORVV 25 6<1&%67B',6$%/( 25 9,16<1&B',6 25 6<1&%67B29 6<1&%67B27 6<1&%67B27 $1' ³GHSOR\PHQWQRWLQSURJUHVV´ 6<1&%67B5(67$57 ZKHQ6<1&%2267RXWSXWYROWDJH9V\QFEVWBUHVWDUWBWK 9,1B6<1&%67B5(67$57 ZKHQ9,1YROWDJH!9YLQBV\QFEVWBUHVWDUWBWK &KDQJHRI6<6B&7/.((3B6<1&%67B21ELWLVDXWRPDWLFDOO\GHQLHGZKHQ(5B67$7(LVDFWLYH ,Q6<1&%2267B7(03B2))VWDWHLI6<6B&7/.((3B6<1&%67B21 LVUHFHLYHGZHPRYHWR2))VWDWH 46/277 6<1&%67B27 6<1&%6727 5HVHW7 6<1&%226721 7UDQVLWLRQIURP581B67$7(WR(5 B67$7( $1'6<6B&7/.((3B6<1&%67B21 'HIDXOW6<6B&7/6<1&%67B(1 DW325 'HIDXOW6<6B&7/.((3B6<1&%67B21 DW325 DocID029257 Rev 1 *$3*36 L9680 6.8 Start-up and power control SATBUCK regulator The SATBUCK regulator provides a nominal 7.2 V regulated output voltage at startup for the remote satellite and wheel speed interface circuitry and the VCC buck regulator. The buck regulator is enabled automatically by the power control state machine. This regulator is protected against short circuits. Should the user need a higher voltage range for the remote sensor interface, a specific SPI command allows the output voltage to be increased at 9 V nominal by setting the SAT_V bit. Fault status is available through SPI in the Fault Status Register (FLTSR). The buck converter operates at 1.882 MHz allowing the user to select smaller less expensive external components. Moreover, the synchronous buck regulator integrates the external recirculation diode. Figure 22. SATBUCK regulator state diagram 32:(52))B02'( 256/((3B02'( 6$7%8&. SRZHUPRGHFRQWURO 6$7%XFNB21 6<1&%2267B2. $1' 9&&B29 $1' 6$7*1'BORVV 9&&B29 25 6$7*1'BORVV 6$7%XFNB21 6<1&%2267B2. ZKHQ9V\QFERRVW!9V\QFEVWBRN *$3*36 6.9 VCC buck regulator The VCC buck regulator also operates at 1.882 MHz and is user selectable to either 3.3 V or 5 V nominal output voltage. The user can select the output voltage through the VCCSEL pin. To select 5 V operation, the user must bias VCCSEL to a level higher than VTH2_H_VCCSEL for instance SyncBoost. For 3.3 V operation, the VCCSEL pin must be biased to a level lower than VTH2_L_VCCSEL. An internal weak pull down is connected to VCCSEL to ensure the input remains at ground potential in case of open pin. The internal power control state machine will read the VCCSEL input pin and latch the resulting state upon the SATBUCK voltage reaches the good value (SATBUCK_OK = 1). Upon latching the VCCSEL state, the VCC buck regulator cannot be changed by the user. The VCC regulator has over and under voltage detections and shutdown capability and it is also protected against short circuits. During start-up an internal pull up current is enabled in order to detect a potential VCC pin open fault trough the over voltage detection. This pull up current is disabled once in VCC_ON or VCC_SHUTDOWN states. During normal operation, VCC_ON state, the VCC pin open fault is quickly detected through the Under Voltage Detection Low to prevent any MCU damage. DocID029257 Rev 1 47/277 276 Start-up and power control L9680 An open VCC pin shall lead to an under voltage condition on VCC supply monitor. The SPI related signals (SCLK, MISO, MOSI, CS) or other digital nets shall not power the VCC pin due to back-feeding paths. Figure 23. VCC regulator state diagram 9&&%8&. SRZHUPRGHFRQWURO 32:(52))B02'( 25 6/((3B02'( 9&&B2)) 9&&SXOOXSGLVDEOHG $OO2XSXW%XIIHUGLVDEOHG 7WLPHRXW 6$7%8&.B2. $1' 9&&*1'BORVV 9&&BUDPSXS >9&&B89 259&&B89/ $1'7WLPHRXW@ 25 9&&B29 25 9&25(B29 25 9&&*1'BORVV 6WDUW7PV 9&&SXOOXSHQDEOHG 9&&B89 $1' 9&&B89/ $1' 7WLPHRXW 9&&B21 9&&SXOOXSGLVDEOHG $OO2XWSXW%XIIHUHQDEOHG 9&&B6+87'2:1 6WDUW7PV 9&&SXOOXSGLVDEOHG %XFNLVQRWUXQQLQJ 9&&B89/ 25 9&&B29 25 9&&*1'BORVV 9&25(B29 25 9&25(B89 $1'',6B9&25(021 9&&B89/ ZKHQ9&&9&&XYO 9&&B89 ZKHQ9&&9&&XY 9&&B29 ZKHQ9&&!9&&RY ',6B9&25(021 9&&6(/!9WKBYFFVHO 6$7%8&.B2. ZKHQ6$7%8&.!9VDWEFNBRN *$3*36 48/277 DocID029257 Rev 1 L9680 6.10 Start-up and power control VCOREMON external core voltage monitor The device includes the possibility to monitor the external core voltage of MCU in case an additional external regulator is used to provide the 1.2V rail. The internal power control state machine will read the VCCSEL input pin and latch the resulting state upon the VCCBUCK regulator enters in the VCC_ON state: if VCCSEL is lower than VTH1_L_VCCSEL the VCORE monitor will be enabled, otherwise, if VCCSEL is higher than VTH1_H_VCCSEL, the VCORE monitor will be disabled. In summary: VCCSEL < VTH1_L_VCCSEL (VCCSEL shorted to ground), to select VCC = 3.3 V and to enable the VCORE monitor VTH1_H_VCCSEL < VCCSEL < VTH2_L_VCCSEL (VCCSEL shorted to VCC), to select VCC = 3.3 V and to disable the VCORE monitor. VCCSEL > VTH2_H_VCCSEL (VCCSEL shorted to SYNCBOOST), to select VCC = 5 V and to disable the VCORE monitor. The VCORE monitor is enabled once the VCC regulator is in VCC_ON state, therefore the external MCU core voltage regulator (1.2 V) must reach the regulation within 4ms after the VCC regulator power-up. Upon latching the VCCSEL state, the VCOREMON activation cannot be changed by the user. In case of VCCSEL open pin, an internal pull down current would force VCCSEL to ground and then the VCORE monitor will be enabled function. 6.11 VSF regulator and control The L9680 provides a low current linear regulator that can be used in the system design to bias the external high side safing switch. The regulator output is 20 V nominal (configurable to 25 V via SPI command). VSF is enabled if any of the ARMxINT signal is asserted, as shown in Figure 24. The VSF regulator supply input is ERBOOST. Figure 24. VSF control logic 6$)(6(/ $50,17 $50,17 $50,17 $50,17 6$),1*67$7( $50B(1 96)B(1 ',$*67$7( '67(6796) $50,1*67$7( *$3*36 VSF voltage can be monitored by the user through the internal ADC. Characteristics for this function are shown in the electrical performance tables. DocID029257 Rev 1 49/277 276 Start-up and power control 6.12 L9680 Oscillators The device integrates two trimmed oscillators, both of them with spread spectrum capability selectable via the CLK_CNF register. The main oscillator runs at 16 MHz typ and is used to provide clock to the internal synchronous logic. Moreover, this frequency is divided down by factor 8.5 to generate clocks for the switching regulators (1.882 MHz typ). The auxiliary oscillator runs at 7.5 MHz typ and is used to monitor the main oscillator. In case the main oscillator frequency was lower than fOSC_LOW_TH threshold or higher than fOSC_HIGH_TH threshold, the condition is detected by the frequency monitor circuit and then latched into the CLKFRERR flag in the FLTSR register and a POR is issued. 6.13 Reset control The device provides reset logic to safely control system operation in the event of internal ECU failures. Several internal reset signals are generated depending on the type of failure detected. In Figure 25 the voltage monitoring diagram is shown. Figure 25. Internal voltage monitors 5HIHUHQFHIRU &RQWUROOLQJDOOVXSSOLHV 9%*5 5HIHUHQFH 9,179 9%*0 0RQLWRU 9%*B5($'< 9,179 0RQLWRU 9'' 9'' 0RQLWRU 9&25(SLQ 9&25( 0RQLWRU 9&& 9&& 0RQLWRU 0&8)$8/7%SLQ *1'68%[ 29B9,179 89B9,179 29B&9'' 89B&9'' 9&25(B29 9&25(B89 9&&B89 PV 2QHVKRW 3XOVHJHQ *1'$ 0RQLWRU *1'' *1'' 0RQLWRU 9&25(B(55 9&&B29 V 'HJOLWFK )LOWHU *1'$ 95(*B(55 9&&B(55 0&8)/7B(55 *1'$B(55 *1'B(55 %67*1' %67*1' 0RQLWRU *1''B(55 %67*1'BORVV *$3*36 An active low pin output (RESET pin) is driven from the L9680 to allow resetting of external devices such as the microcontroller, sensors, and other ICs within the ECU. 50/277 DocID029257 Rev 1 L9680 Start-up and power control Three internal reset signals are generated by the device: POR Power On Reset - This reset is asserted when a failure is detected in the internal supplies or bandgap circuits. When active, all other resets are asserted. WSM_RESET Watchdog State Machine Reset - This reset is generated when the POR is active or when a failure is detected in the VCC or VCORE supply. SSM_RESET System State Machine Reset - This reset is asserted when the POR or the WSM_RESET are active, or when a failure is detected in either Watchdog state machine, or again when the MCUFAULTB pin is active. The RESET pin is the active-low signal driven on the output pin, and is an inverted form of SSM_RESET. The cause of the RESET activation is latched and reported into the Fault Status Register FLTSR and cleared upon SPI reading. The reset generated by the MCUFLT_ERR can be masked by the MCU_FLT_TEST test mode signal. This allows verification of MCUFLT pin operation and, in turn, microcontroller fault conditions without asserting a reset. The MCURST bit is still set whether in test mode or not. The reset logic shall be controlled as shown in the diagram below: Figure 26. Reset control logic &/.)5(55 *1'B(55 9%*B5($'< 325 6833/<B325 95(*B(55 9&&B(55 :60B5HVHW 9&25(B(55 ',6B9&25(021 5HVHWBKROGBWLPH 0&8)/7B(55 0&8B660567 0&8B)/7B70 :'5(6(7VWDWH 660B5HVHW :'5(6(7VWDWH 5(6(7SLQ :'67233,1*VWDWH :'B660567 :'B70 6 63,B5HDG *$3*36 DocID029257 Rev 1 5 0&8567 51/277 276 SPI interfaces 7 L9680 SPI interfaces The L9680 system solution device has many user selectable features controlled through serial communications by the integrated microcontroller. The device features two SPI interfaces: one global SPI and one Remote Sensor SPI. The global SPI interface provides general configuration, control and status functions for the device, while the Remote Sensor SPI provides dedicated access to Remote Sensor Data and Status Registers. 7.1 SPI protocol Each SPI interface (Global and Remote Sensor) use their own dedicated set of 4 I/O pins: CS_G, SCLK_G, MOSI_G and MISO_G for Global SPI; CS_RS, SCLK_RS, MOSI_RS and MISO_RS for Remote Sensor SPI. Both the SPI interfaces use the same protocol described here below (the suffix ‘_X’ used in the SPI pin names below is intended to stand for either ‘_G’ or ‘_RS’ depending on the particular SPI interface considered) The IC SPI interface is composed by an input shift register, an output shift register and four control signals. MOSI_X is the data input to the input shift register. MISO_X is the data output from the output shift register. SCLK_X is the clock input used to shift data into the input shift register or out from the output one while CS_X is the active low chip select input. All SPI communications are executed in exact 32 bit increments. The general format of the 32 bit transmission for the SPI interface is shown in Table 5. Data sent to the IC (i.e. MOSI_X) consists of a target read register ID (RID), a target write register ID (WID), write data parity (WPAR) and 16 bits of data (WRITE). WRITE data is the data to be written to the target write register indicated by WID. Data returned from the IC (i.e. MISO_X) consists of a global status word (GSW), read data parity (RPAR) and 20 bits of data (READ). READ data will be the contents of the target read register as indicated by the RID bits. The parity bits WPAR and RPAR cover all the 32 bits of the MOSI and MISO frames, respectively. Odd parity type is used. Table 5. SPI MOSI and MISO frames layout SPI register R/W SPI_MOSI SPI_MISO SPI_MOSI SPI_MISO 31 GID 30 29 28 15 14 13 12 27 26 25 RID[6:0] GSW[10:0] 11 10 9 24 23 22 21 8 7 6 WRITE[15:0] READ[15:0] 5 20 19 WID[6:0] RPAR 4 3 18 17 16 WPAR READ[19:16] 2 1 0 The communications is controlled through CS_X, enabling and disabling communication. When CS_X is at logic high, all SPI communication I/O is tri-stated and no data is accepted. When CS_X is low, data is latched on the rising edge of SCLK_X and data is shifted on the falling edge. The MOSI_X pin receives serial data from the master with MSB first. Likewise for MISO_X, data is read MSB first, LSB last. The L9680 contains a data validation method through the SCLK_X input to keep transmissions with not exactly 32 bits from being written to the device. The SCLK_X input counts the number of received clocks and should the clock counter exceed or count fewer 52/277 DocID029257 Rev 1 L9680 SPI interfaces than 32 clocks, the received message is discarded and a SPI_FLT bit is flagged in the Global Status Word (GSW). The SPI_FLT bit is also set in case of parity error detected on the MOSI_X frame. Any attempt to access to a register with forbidden access mode (read or write) is not leading to changes to the internal registers but the SPI_FLT bit is not set in this case. 7.2 Global SPI register map The Global SPI interface consists of several 32-bit registers to allow for configuration, control and status of the IC as well as special manufacturing test modes. The register definition is defined by the read register ID (RID) and the write register ID (WID) as shown in Table 6. Global ID bit (GID) is used to extend available register addresses, but it is shared between RID and WID; only RID and WID with the same GID value can be addressed within the same SPI word. The operating states here show in which states the SPI command is processed. The L9680 checks the validity of the received WID and RID fields in the MOSI_G frame. Should a SPI write command with WID matching a writable register be received in an illegal operating state, the command will be discarded and the ERR_WID bit will be flagged in the next Global Status Word GSW. The ERR_WID flag is not set in case WID is addressing a read/only register. Should a SPI read command be received containing an unused RID address, the command will be discarded and the ERR_RID bit will be flagged in the current GSW. DocID029257 Rev 1 53/277 276 Global SPI register map Operating State(1) GID RID / WID Hex R/W Name Description Init R FLTSR Diag Ssafing Scrap Arming DocID029257 Rev 1 0 0 0 0 0 0 0 0 $00 Global fault status register 0 0 0 0 0 0 0 1 $01 R/W SYS_CFG Power supply configuration(2) X X X X X 0 0 0 0 0 0 1 0 $02 R/W SYS_CTL Register for power management X X X X X 0 0 0 0 0 0 1 1 $03 W SPI_SLEEP Sleep Mode command X X X X X 0 0 0 0 0 1 0 0 $04 R SYS_STATE Read register to report in which state the power control state machine is and also in which operating state the device is 0 0 0 0 0 1 0 1 $05 R POWER_STATE 0 0 0 0 0 1 1 0 $06 R/W DCR_0 X X X X 0 0 0 0 0 1 1 1 $07 R/W DCR_1 X X X X 0 0 0 0 1 0 0 0 $08 R/W DCR_2 X X X X 0 0 0 0 1 0 0 1 $09 R/W DCR_3 X X X X 0 0 0 0 1 0 1 0 $0A R/W DCR_4 X X X X 0 0 0 0 1 0 1 1 $0B R/W DCR_5 X X X X 0 0 0 0 1 1 0 0 $0C R/W DCR_6 X X X X 0 0 0 0 1 1 0 1 $0D R/W DCR_7 X X X X 0 0 0 0 1 1 1 0 $0E R/W DCR_8 X X X X 0 0 0 0 1 1 1 1 $0F R/W DCR_9 X X X X 0 0 0 1 0 0 0 0 $10 R/W DCR_A X X X X 0 0 0 1 0 0 0 1 $11 R/W DCR_B X X X X 0 0 0 1 0 0 1 0 $12 R/W DEPCOM 0 0 0 1 0 0 1 1 $13 R DSR_0 0 0 0 1 0 1 0 0 $14 R DSR_1 0 0 0 1 0 1 0 1 $15 R DSR_2 SPI interfaces 54/277 Table 6. Power state register (feedback on regulators' status and voltage thresholds) Deployment configuration register Deployment command register X X Deployment status register L9680 Global SPI register map (continued) L9680 Table 6. Operating State(1) GID RID / WID Hex R/W Name Description Init DocID029257 Rev 1 0 0 1 0 1 1 0 $16 R DSR_3 0 0 0 1 0 1 1 1 $17 R DSR_4 0 0 0 1 1 0 0 0 $18 R DSR_5 0 0 0 1 1 0 0 1 $19 R DSR_6 0 0 0 1 1 0 1 0 $1A R DSR_7 0 0 0 1 1 0 1 1 $1B R DSR_8 0 0 0 1 1 1 0 0 $1C R DSR_9 0 0 0 1 1 1 0 1 $1D R DSR_A 0 0 0 1 1 1 1 0 $1E R DSR_B 0 0 0 1 1 1 1 1 $1F R DCMTS01 0 0 1 0 0 0 0 0 $20 R DCMTS23 0 0 1 0 0 0 0 1 $21 R DCMTS45 0 0 1 0 0 0 1 0 $22 R DCMTS67 0 0 1 0 0 0 1 1 $23 R DCMTS89 0 0 1 0 0 1 0 0 $24 R DCMTSAB 0 0 1 0 0 1 0 1 $25 R/W 0 0 1 0 0 1 1 0 $26 R LP_GNDLOSS 0 0 1 0 0 1 1 1 $27 R VERSION_ID 0 0 1 0 1 0 0 0 $28 R/W 0 0 1 0 1 0 0 1 $29 0 0 1 0 1 0 1 0 $2A R/W WDTCR 0 0 1 0 1 0 1 1 $2B R/W 0 0 1 0 1 1 0 0 $2C 0 0 1 0 1 1 0 1 $2D R/W 0 0 1 0 1 1 1 0 $2E W R R SPIDEPEN WD_RETRY_CONF Deployment status register Deployment current monitor register Lock/Unlock command X Loss of ground fault for squib loops Device version Watchdog Retry Configuration X Microcontroller Fault test X Watchdog first level configuration X WD1T Watchdog first level key transmission WD_STATE Watchdog first and second level state CLK_CONF Clock configuration MCU_FLT_TEST SCRAP_SEED X Scrap Seed command X X X X X X X X X X X X X X SPI interfaces 55/277 0 Diag Ssafing Scrap Arming Global SPI register map (continued) Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 0 0 1 0 1 1 1 1 $2F W SCRAP_KEY Scrap Key command 0 0 1 1 0 0 0 0 $30 W SCRAP_STATE Scrap State command X 0 0 1 1 0 0 0 1 $31 W SAFING_STATE Safing State command X 0 0 1 1 0 0 1 0 $32 W WD2_RECOVER Watchdog second level recovery command 0 0 1 1 0 0 1 1 $33 R WD2_SEED Watchdog second level seed transmission 0 0 1 1 0 1 0 0 $34 W WD2_KEY 0 0 1 1 0 1 0 1 $35 W WD_TEST 0 0 1 1 0 1 1 0 $36 R/W SYSDIAGREQ Diagnostic command for system safing 0 0 1 1 0 1 1 1 $37 LPDIAGSTAT Diagnostic result register for deployment loops 0 0 1 1 1 0 0 0 $38 R/W LPDIAGREQ Diagnostic configuration command for deployment loops 0 0 1 1 1 0 0 1 $39 R/W SWCTRL 0 0 1 1 1 0 1 0 $3A R/W 0 X X X X X X X Watchdog second level key transmission X X X X X Watchdog first and second level test X X X X X X X X X DC sensor diagnostic configuration X X X X DIAGCTRL_A In WID is AtoD converter control register A. In RID is AtoD result A request. X X X X 0 1 1 1 0 1 1 $3B R/W DIAGCTRL_B In WID is AtoD converter control register B. In RID is AtoD result B request. X X X X 0 0 1 1 1 1 0 0 $3C R/W DIAGCTRL_C In WID is AtoD converter control register C. In RID is AtoD result C request. X X X X 0 0 1 1 1 1 0 1 $3D R/W DIAGCTRL_D In WID is AtoD converter control register D. In RID is AtoD result D request. X X X X 0 0 1 1 1 1 1 0 $3E 0 0 1 1 1 1 1 1 $3F R/W SW_REGS_CONF Configuration register for switching regulators X X X X 0 1 0 0 0 0 0 0 $40 0 1 0 0 0 0 0 1 $41 0 1 0 0 0 0 1 0 $42 R/W GPOCR 0 1 0 0 0 0 1 1 $43 R/W GPOCTRL0 X X X R SPI interfaces 56/277 Table 6. X X X General Purpose Output 0 control register X X L9680 General Purpose Output configuration Global SPI register map (continued) L9680 Table 6. Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 1 0 0 0 1 0 0 $44 R/W GPOCTRL1 General Purpose Output 1 control register X X X X X 0 1 0 0 0 1 0 1 $45 R/W GPOCTRL2 General Purpose Output 2 control register X X X X X 0 1 0 0 0 1 1 0 $46 GPOFLTSR General Purpose Output fault status register 0 1 0 0 0 1 1 1 $47 0 1 0 0 1 0 0 0 $48 R/W WSS_TEST WSS testmode request X 0 1 0 0 1 0 0 1 $49 0 1 0 0 1 0 1 0 $4A R/W RSCR0 PSI5/WSS configuration register X 0 1 0 0 1 0 1 1 $4B R/W RSCR1 X 0 1 0 0 1 1 0 0 $4C R/W RSCR2 X 0 1 0 0 1 1 0 1 $4D R/W RSCR3 X 0 1 0 0 1 1 1 0 $4E R/W RSCTRL X X X 0 1 0 0 1 1 1 1 $4F 0 1 0 1 0 0 0 0 $50 0 1 0 1 0 0 0 1 $51 0 1 0 1 0 0 1 0 $52 0 1 0 1 0 0 1 1 $53 0 1 0 1 0 1 0 0 $54 0 1 0 1 0 1 0 1 $55 0 1 0 1 0 1 1 0 $56 0 1 0 1 0 1 1 1 $57 0 1 0 1 1 0 0 0 $58 0 1 0 1 1 0 0 1 $59 0 1 0 1 1 0 1 0 $5A 0 1 0 1 1 0 1 1 $5B 0 1 0 1 1 1 0 0 $5C R Remote sensor control register X SPI interfaces 57/277 0 Global SPI register map (continued) Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 0 1 0 1 1 1 0 1 $5D 0 1 0 1 1 1 1 0 $5E 0 1 0 1 1 1 1 1 $5F 0 1 1 0 0 0 0 0 $60 0 1 1 0 0 0 0 1 $61 0 1 1 0 0 0 1 0 $62 0 1 1 0 0 0 1 1 $63 0 1 1 0 0 1 0 0 $64 R/W RS_AUX_CONF1 WSS Threshold configuration register 1 X 0 1 1 0 0 1 0 1 $65 R/W RS_AUX_CONF2 WSS Threshold configuration register 2 X 0 1 1 0 0 1 1 0 $66 R/W SAF_ALGO_CONF Safing Algorithm configuration register X 0 1 1 0 0 1 1 1 $67 0 1 1 0 1 0 0 0 $68 0 1 1 0 1 0 0 1 $69 0 1 1 0 1 0 1 0 $6A 0 1 1 0 1 0 1 1 $6B 0 1 1 0 1 1 0 0 $6C 0 1 1 0 1 1 0 1 $6D 0 1 1 0 1 1 1 0 $6E R/W LOOP_MATRIX_ARM1 Assignment of ARM 1 pin to which LOOPS X 0 1 1 0 1 1 1 1 $6F R/W LOOP_MATRIX_ARM2 Assignment of ARM 2 pin to which LOOPS X 0 1 1 1 0 0 0 0 $70 R/W LOOP_MATRIX_ARM3 Assignment of ARM 3 pin to which LOOPS X 0 1 1 1 0 0 0 1 $71 R/W LOOP_MATRIX_ARM4 Assignment of ARM 4 pin to which LOOPS X 0 1 1 1 0 0 1 0 $72 0 1 1 1 0 0 1 1 $73 R AEPSTS_ARM1 0 1 1 1 0 1 0 0 $74 R AEPSTS_ARM2 0 1 1 1 0 1 0 1 $75 R AEPSTS_ARM3 R ARM_STATE SPI interfaces 58/277 Table 6. Status of arming signals L9680 Arming pulse stretch timer value Global SPI register map (continued) L9680 Table 6. Operating State(1) GID RID / WID Hex R/W Name Description Init R AEPSTS_ARM4 Diag Ssafing Scrap Arming DocID029257 Rev 1 1 1 1 0 1 1 0 $76 Arming pulse stretch timer value 0 1 1 1 0 1 1 1 $77 0 1 1 1 1 0 0 0 $78 R/W PADTHRESH_HI 0 1 1 1 1 0 0 1 $79 R/W PADTHRESH_LO 0 1 1 1 1 0 1 0 $7A R/W LOOP_MATRIX_PSINH 0 1 1 1 1 0 1 1 $7B 0 1 1 1 1 1 0 0 $7C 0 1 1 1 1 1 0 1 $7D 0 1 1 1 1 1 1 0 $7E 0 1 1 1 1 1 1 1 $7F R/W SAF_ENABLE 1 0 0 0 0 0 0 0 $80 R/W SAF_REQ_MASK_1 X 1 0 0 0 0 0 0 1 $81 R/W SAF_REQ_MASK_2 X 1 0 0 0 0 0 1 0 $82 R/W SAF_REQ_MASK_3 X 1 0 0 0 0 0 1 1 $83 R/W SAF_REQ_MASK_4 X 1 0 0 0 0 1 0 0 $84 R/W SAF_REQ_MASK_5 X 1 0 0 0 0 1 0 1 $85 R/W SAF_REQ_MASK_6 X 1 0 0 0 0 1 1 0 $86 R/W SAF_REQ_MASK_7 1 0 0 0 0 1 1 1 $87 R/W SAF_REQ_MASK_8 1 0 0 0 1 0 0 0 $88 R/W SAF_REQ_MASK_9 X 1 0 0 0 1 0 0 1 $89 R/W SAF_REQ_MASK_10 X 1 0 0 0 1 0 1 0 $8A R/W SAF_REQ_MASK_11 X 1 0 0 0 1 0 1 1 $8B R/W SAF_REQ_MASK_12 X 1 0 0 0 1 1 0 0 $8C R/W SAF_REQ_MASK_13 X 1 0 0 0 1 1 0 1 $8D R/W SAF_REQ_MASK_14_pt1 X Passenger Inhibit Thresholds X X Assignment of PSINH signal to which LOOPS X Safing record enable X Safing record request mask X X X X X SPI interfaces 59/277 0 Global SPI register map (continued) Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 1 0 0 0 1 1 1 0 $8E R/W SAF_REQ_MASK_14_pt2 X 1 0 0 0 1 1 1 1 $8F R/W SAF_REQ_MASK_15_pt1 X 1 0 0 1 0 0 0 0 $90 R/W SAF_REQ_MASK_15_pt2 1 0 0 1 0 0 0 1 $91 R/W SAF_REQ_MASK_16_pt1 X 1 0 0 1 0 0 1 0 $92 R/W SAF_REQ_MASK_16_pt2 X 1 0 0 1 0 0 1 1 $93 R/W SAF_REQ_TARGET_1 X 1 0 0 1 0 1 0 0 $94 R/W SAF_REQ_TARGET_2 X 1 0 0 1 0 1 0 1 $95 R/W SAF_REQ_TARGET_3 X 1 0 0 1 0 1 1 0 $96 R/W SAF_REQ_TARGET_4 X 1 0 0 1 0 1 1 1 $97 R/W SAF_REQ_TARGET_5 X 1 0 0 1 1 0 0 0 $98 R/W SAF_REQ_TARGET_6 X 1 0 0 1 1 0 0 1 $99 R/W SAF_REQ_TARGET_7 X 1 0 0 1 1 0 1 0 $9A R/W SAF_REQ_TARGET_8 X 1 0 0 1 1 0 1 1 $9B R/W SAF_REQ_TARGET_9 X 1 0 0 1 1 1 0 0 $9C R/W SAF_REQ_TARGET_10 1 0 0 1 1 1 0 1 $9D R/W SAF_REQ_TARGET_11 X 1 0 0 1 1 1 1 0 $9E R/W SAF_REQ_TARGET_12 X 1 0 0 1 1 1 1 1 $9F R/W SAF_REQ_TARGET_13 X 1 0 1 0 0 0 0 0 $A0 R/W SAF_REQ_TARGET_14_pt1 X 1 0 1 0 0 0 0 1 $A1 R/W SAF_REQ_TARGET_14_pt2 X 1 0 1 0 0 0 1 0 $A2 R/W SAF_REQ_TARGET_15_pt1 X 1 0 1 0 0 0 1 1 $A3 R/W SAF_REQ_TARGET_15_pt2 X 1 0 1 0 0 1 0 0 $A4 R/W SAF_REQ_TARGET_16_pt1 X 1 0 1 0 0 1 0 1 $A5 R/W SAF_REQ_TARGET_16_pt2 X 1 0 1 0 0 1 1 0 $A6 R/W Safing record request target Safing record response mask X X X L9680 SAF_RESP_MASK_1 Safing record request mask SPI interfaces 60/277 Table 6. Global SPI register map (continued) Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 0 1 0 0 1 1 1 $A7 R/W SAF_RESP_MASK_2 X 1 0 1 0 1 0 0 0 $A8 R/W SAF_RESP_MASK_3 X 1 0 1 0 1 0 0 1 $A9 R/W SAF_RESP_MASK_4 X 1 0 1 0 1 0 1 0 $AA R/W SAF_RESP_MASK_5 X 1 0 1 0 1 0 1 1 $AB R/W SAF_RESP_MASK_6 X 1 0 1 0 1 1 0 0 $AC R/W SAF_RESP_MASK_7 X 1 0 1 0 1 1 0 1 $AD R/W SAF_RESP_MASK_8 X 1 0 1 0 1 1 1 0 $AE R/W SAF_RESP_MASK_9 X 1 0 1 0 1 1 1 1 $AF R/W SAF_RESP_MASK_10 1 0 1 1 0 0 0 0 $B0 R/W SAF_RESP_MASK_11 1 0 1 1 0 0 0 1 $B1 R/W SAF_RESP_MASK_12 X 1 0 1 1 0 0 1 0 $B2 R/W SAF_RESP_MASK_13 X 1 0 1 1 0 0 1 1 $B3 R/W SAF_RESP_MASK_14_pt1 X 1 0 1 1 0 1 0 0 $B4 R/W SAF_RESP_MASK_14_pt2 X 1 0 1 1 0 1 0 1 $B5 R/W SAF_RESP_MASK_15_pt1 X 1 0 1 1 0 1 1 0 $B6 R/W SAF_RESP_MASK_15_pt2 X 1 0 1 1 0 1 1 1 $B7 R/W SAF_RESP_MASK_16_pt1 X 1 0 1 1 1 0 0 0 $B8 R/W SAF_RESP_MASK_16_pt2 X 1 0 1 1 1 0 0 1 $B9 R/W SAF_RESP_TARGET_1 X 1 0 1 1 1 0 1 0 $BA R/W SAF_RESP_TARGET_2 X 1 0 1 1 1 0 1 1 $BB R/W SAF_RESP_TARGET_3 X 1 0 1 1 1 1 0 0 $BC R/W SAF_RESP_TARGET_4 1 0 1 1 1 1 0 1 $BD R/W SAF_RESP_TARGET_5 X 1 0 1 1 1 1 1 0 $BE R/W SAF_RESP_TARGET_6 X 1 0 1 1 1 1 1 1 $BF R/W SAF_RESP_TARGET_7 X Safing record response target X X X SPI interfaces 61/277 1 Safing record response mask L9680 Table 6. Global SPI register map (continued) Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 1 1 0 0 0 0 0 0 $C0 R/W SAF_RESP_TARGET_8 X 1 1 0 0 0 0 0 1 $C1 R/W SAF_RESP_TARGET_9 X 1 1 0 0 0 0 1 0 $C2 R/W SAF_RESP_TARGET_10 X 1 1 0 0 0 0 1 1 $C3 R/W SAF_RESP_TARGET_11 X 1 1 0 0 0 1 0 0 $C4 R/W SAF_RESP_TARGET_12 X 1 1 0 0 0 1 0 1 $C5 R/W SAF_RESP_TARGET_13 1 1 0 0 0 1 1 0 $C6 R/W SAF_RESP_TARGET_14_pt1 1 1 0 0 0 1 1 1 $C7 R/W SAF_RESP_TARGET_14_pt2 X 1 1 0 0 1 0 0 0 $C8 R/W SAF_RESP_TARGET_15_pt1 X 1 1 0 0 1 0 0 1 $C9 R/W SAF_RESP_TARGET_15_pt2 X 1 1 0 0 1 0 1 0 $CA R/W SAF_RESP_TARGET_16_pt1 X 1 1 0 0 1 0 1 1 $CB R/W SAF_RESP_TARGET_16_pt2 X 1 1 0 0 1 1 0 0 $CC R/W SAF_DATA_MASK_1 X 1 1 0 0 1 1 0 1 $CD R/W SAF_DATA_MASK_2 X 1 1 0 0 1 1 1 0 $CE R/W SAF_DATA_MASK_3 X 1 1 0 0 1 1 1 1 $CF R/W SAF_DATA_MASK_4 X 1 1 0 1 0 0 0 0 $D0 R/W SAF_DATA_MASK_5 X 1 1 0 1 0 0 0 1 $D1 R/W SAF_DATA_MASK_6 X 1 1 0 1 0 0 1 0 $D2 R/W SAF_DATA_MASK_7 1 1 0 1 0 0 1 1 $D3 R/W SAF_DATA_MASK_8 X 1 1 0 1 0 1 0 0 $D4 R/W SAF_DATA_MASK_9 X 1 1 0 1 0 1 0 1 $D5 R/W SAF_DATA_MASK_10 X 1 1 0 1 0 1 1 0 $D6 R/W SAF_DATA_MASK_11 X 1 1 0 1 0 1 1 1 $D7 R/W SAF_DATA_MASK_12 X 1 1 0 1 1 0 0 0 $D8 R/W SAF_DATA_MASK_13 X Safing record response target Safing record data mask SPI interfaces 62/277 Table 6. X X X L9680 Global SPI register map (continued) Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 1 0 1 1 0 0 1 $D9 R/W SAF_DATA_MASK_14_pt1 X 1 1 0 1 1 0 1 0 $DA R/W SAF_DATA_MASK_14_pt2 X 1 1 0 1 1 0 1 1 $DB R/W SAF_DATA_MASK_15_pt1 1 1 0 1 1 1 0 0 $DC R/W SAF_DATA_MASK_15_pt2 1 1 0 1 1 1 0 1 $DD R/W SAF_DATA_MASK_16_pt1 X 1 1 0 1 1 1 1 0 $DE R/W SAF_DATA_MASK_16_pt2 X 1 1 0 1 1 1 1 1 $DF R/W SAF_THRESHOLD_1 X 1 1 1 0 0 0 0 0 $E0 R/W SAF_THRESHOLD_2 X 1 1 1 0 0 0 0 1 $E1 R/W SAF_THRESHOLD_3 X 1 1 1 0 0 0 1 0 $E2 R/W SAF_THRESHOLD_4 X 1 1 1 0 0 0 1 1 $E3 R/W SAF_THRESHOLD_5 X 1 1 1 0 0 1 0 0 $E4 R/W SAF_THRESHOLD_6 X 1 1 1 0 0 1 0 1 $E5 R/W SAF_THRESHOLD_7 X 1 1 1 0 0 1 1 0 $E6 R/W SAF_THRESHOLD_8 1 1 1 0 0 1 1 1 $E7 R/W SAF_THRESHOLD_9 1 1 1 0 1 0 0 0 $E8 R/W SAF_THRESHOLD_10 X 1 1 1 0 1 0 0 1 $E9 R/W SAF_THRESHOLD_11 X 1 1 1 0 1 0 1 0 $EA R/W SAF_THRESHOLD_12 X 1 1 1 0 1 0 1 1 $EB R/W SAF_THRESHOLD_13 X 1 1 1 0 1 1 0 0 $EC R/W SAF_THRESHOLD_14 X 1 1 1 0 1 1 0 1 $ED R/W SAF_THRESHOLD_15 X 1 1 1 0 1 1 1 0 $EE R/W SAF_THRESHOLD_16 X 1 1 1 0 1 1 1 1 $EF R/W SAF_CONTROL_1 X 1 1 1 1 0 0 0 0 $F0 R/W SAF_CONTROL_2 1 1 1 1 0 0 0 1 $F1 R/W SAF_CONTROL_3 Safing record threshold Safing record control X X X X X X SPI interfaces 63/277 1 Safing record data mask L9680 Table 6. Global SPI register map (continued) Operating State(1) GID RID / WID Hex R/W Name Description Init Diag Ssafing Scrap Arming DocID029257 Rev 1 1 1 1 1 0 0 1 0 $F2 R/W SAF_CONTROL_4 X 1 1 1 1 0 0 1 1 $F3 R/W SAF_CONTROL_5 X 1 1 1 1 0 1 0 0 $F4 R/W SAF_CONTROL_6 X 1 1 1 1 0 1 0 1 $F5 R/W SAF_CONTROL_7 X 1 1 1 1 0 1 1 0 $F6 R/W SAF_CONTROL_8 X 1 1 1 1 0 1 1 1 $F7 R/W SAF_CONTROL_9 X 1 1 1 1 1 0 0 0 $F8 R/W SAF_CONTROL_10 1 1 1 1 1 0 0 1 $F9 R/W SAF_CONTROL_11 X 1 1 1 1 1 0 1 0 $FA R/W SAF_CONTROL_12 X 1 1 1 1 1 0 1 1 $FB R/W SAF_CONTROL_13 X 1 1 1 1 1 1 0 0 $FC R/W SAF_CONTROL_14 X 1 1 1 1 1 1 0 1 $FD R/W SAF_CONTROL_15 X 1 1 1 1 1 1 1 0 $FE R/W SAF_CONTROL_16 X 1 1 1 1 1 1 1 1 $FF R SAF_CC Safing record control SPI interfaces 64/277 Table 6. X Safing Record Compare Complete 1. A check mark indicates in which operating state a WRITE-command is valid. 2. KEEP_ERBOOST_ON, LOW_POWER_MODE, VSF_V and VINGOOD_FILT_SEL bits are writable in all states, the other bits of SYS_CFG are only writable in INIT state. L9680 L9680 7.3 SPI interfaces Global SPI tables A summary of all the registers contained within the global SPI map are shown below and are referenced throughout the specification as they apply. The SPI register tables also specify the effect of the internal reset signals assertion on each bit field (the symbol '-' is used to indicate that the register is not affected by the relevant reset signal'). Global SPI global status word The Global SPI of L9680 contains an 11-bit word that returns global status information. The Global Status Word (GSW) of the Global SPI is the most significant 11 bits of MISO_G data. Table 7. Global SPI Global Status Word MISO_G GSW 31 10 Name SPIFLT POR WSM SSM 0 0 Description 0 SPI Fault, set if previous SPI frame had wrong parity check or wrong number of bits, cleared upon read 0 No fault 1 Fault 30 9 DEPOK 0 0 0 General Deployment Successful Flag, logical OR of the corresponding CHxDS bits (bit 15) in DSRx Registers 0 All the DSRx-CHDS bits are 0 1 At least one of the DSRx-CHDS bits is 1 29 8 0 0 0 0 Unused 28 7 WDT/TM_S 0 0 0 State of WDT/TM pin 0 WDT/TM=0 1 WDT/TM=1 27 6 ERSTATE 0 0 0 Set when Powermode state machine is in ER state 0 Powermode state machine is not in ER state 1 Powermode state machine is in ER state 0 Fault present in Power State Register, logical OR between bits from 18 to 9 of POWER_STATE Register 0 All the bits from 18 to 9 in the POWER_STATE Registers are 0s 1 At least one of the bits from 18 to 9 in the POWER_STATE Registers is 1 1 Fault present in Fault Status Register (FLTSR), logical OR between all bits of FLTSR 0 All the bits in the Fault Status Register (FLTSR) are 0s 1 At least one of the bits in the Fault Status Register (FLTSR) is 1 0 ADC Conversion of request C or D has been completed so new results are available 0 No new data available 1 New data available 0 ADC Conversion of request A or B has been completed so new results are available 0 No new data available 1 New data available 26 25 24 23 5 4 3 2 POWERFLT FLT CONVRDY2 CONVRDY1 0 1 0 0 0 1 0 0 DocID029257 Rev 1 65/277 276 SPI interfaces L9680 Table 7. Global SPI Global Status Word (continued) MISO_G GSW 22 21 66/277 1 0 Name ERR_WID ERR_RID POR WSM SSM 0 0 0 0 Description 0 Write address of previous SPI frame is not permitted in current operating phase 0 No Error 1 Error 0 Read address received in the actual SPI frame is unused so data in the response is don't care 0 No Error 1 Error DocID029257 Rev 1 L9680 SPI interfaces Global SPI read/write register R Read: 0000 Write: - ERCHARGE_OT 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X WD2_WDR WD1_LO WD1_TM WD1_WDR MCURST WSMRST SSMRST VCORE_ERR WD2 retry cnt 0 - - POR 12 SSM Type: 13 WSM 00 14 POR ID: 15 CLKFRERR MCUFLT_TEST MISO 16 ERCHARGE_OT MOSI 17 WD2_TM 18 WD2_LO 19 OTPCRC_ERR Fault status register (FLTSR) ERBST_OT 7.3.1 ER charge over temperature bit Set when over-temp condition detected, cleared on SPI read or POR=1 0 No Fault 1 Fault MCUFLT_TEST 1 1 1 MCU FAULT test mode - reflects MCU_FLT_TM signal state 0 MCU FLT TM=0 1 MCU FLT TM=1 ERBST_OT 0 - - ER Boost over-temperature bit Set when over-temp condition detected, cleared on SPI read or POR=1 0 No Fault 1 Fault CLKFRERR 0 - - Internal oscillator cross-check error bit Set when osc. error detected, cleared on SPI read or SUPPLY_POR=1 0 No Fault 1 Fault WD2_retry_cnt[3:0] $0 $0 OTPCRC_ERR 0 - $0 Value of WD2 retry counter - OTP CRC error bit Set when OTP error detected (tested at release of POR), cleared by POR=1 0 No Fault 1 Fault WD2_LO 0 0 - WD2 lockout - reflects WD2 lockout state DocID029257 Rev 1 67/277 276 SPI interfaces L9680 0 WD2 Lockout inactive 1 WD2 Lockout active WD2_TM 0 0 0 WD2 test mode - reflects WD2TM signal state 0 WD2TM=0 1 WD2TM=1 WD2_WDR 0 0 - WD2 reset latch - set when WD2RESET or STOPPING states are entered, cleared upon read 0 WD2RST signal = 0 1 WD2RST signal = 1 WD1_LO 0 0 - WD1 lockout - reflects WD1 lockout state Set and cleared per Watchdog Timer Flow Diagram 0 WD1 Lockout inactive 1 WD1 Lockout active WD1_TM 0 0 0 WD1 test mode - reflects WD1TM signal state Set and cleared per Watchdog Timer Flow Diagram 0 WD1TM=0 1 WD1TM=1 WD1_WDR 0 0 - WD1 reset latch Set and cleared per Watchdog Timer Flow Diagram 0 WD1_WDR signal = 0 1 WD1_WDR signal = 1 MCURST 0 0 - MCU reset latch - set when MCUFLT pin goes low, cleared upon read 0 MCURST signal = 0 1 MCURST signal = 1 WSMRST 1 1 - Watchdog state machine reset Set when WSM reset goes to '1', cleared upon SPI read 0 WSM reset has not occurred 1 WSM reset has occurred SSMRST 1 1 1 Safing state machine reset Set when SSM reset goes to '1', cleared upon SPI read 0 SSM reset has not occurred 1 SSM Reset has occurred VCORE_ERR 68/277 0 - - VCOREMON pin status - set when VCOREMON pin goes out of range, reset upon read DocID029257 Rev 1 L9680 SPI interfaces 0 VCORMON in range (VCORE_UV<VCOREMON<VCORE_OV) 1 VCOREMON out of range (VCOREMON<VCORE_UV, or VCOREMON>VCORE_OV) POR 1 - - Power on Reset Set when POR goes to '1', cleared upon SPI read 0 POR reset has not occurred 1 POR Reset has occurred DocID029257 Rev 1 69/277 276 SPI interfaces RW Read: 0100 Write: 0002 EN_AUTO_SWITCH_OFF SSM Type: WSM 01 0 0 0 VINGOOD_FILT_SEL WD1_TO_DIS VINGOOD_FILT_SEL WD1_TO_DIS Enable auto switch off ISRC current source and DCS regulator after measurement completion 0 Auto switch off disabled 1 Auto switch off enabled LOW_POWER_MODE 0 - - Selection of over current detection for SYNCBOOST, SATBUCK and VCCBUCK 0 High current level 1 Low current level KEEP_ERBST_ON 0 0 0 ER Boost behaviour during ER state 0 ER Boost is disabled 1 ER Boost stay enabled PSINHSEL 70/277 1 1 1 PSINH engine mode select Updated by SSM_RESET or SPI write DocID029257 Rev 1 0 VSF_V 1 VSF_V 2 SAFESEL 3 SAFESEL 4 DCS_PAD_V 5 DCS_PAD_V 6 VMEAS 7 VMEAS 8 SQMEAS 9 SQMEAS 10 RSU_SYNCPULSE_SHIFT_CONF RSU_SYNCPULSE_SHIFT_CONF 0 POR ID: 0 11 HI_LEV_DIAG_TIME 0 12 HI_LEV_DIAG_TIME 0 X 13 PSINHSEL 0 14 PSINHSEL - 15 KEEP_ERBST_ON MISO 16 KEEP_ERBST_ON MOSI 17 LOW_POWER_MODE 18 LOW_POWER_MODE 19 EN_AUTO_SWITCH_OFF System configuration register (SYS_CFG) EN_AUTO_SWITCH_OFF 7.3.2 L9680 L9680 SPI interfaces 0 Internal 1 External HI_LEV_DIAG_TIME 0 0 0 Selection of duration of high level squib diagnostics 0 Short time (see high level diag diagram) 1 Long time (see high level diag diagram) RSU_SYNCPULSE_ SHIFT_CONF 0 0 0 Selection of sync pulses shift duration 0 Long time 1 Short time SQMEAS 00 00 00 Sample number in DC sensor, squib measurement and temperature conversions Updated by SSM_RESET or SPI write 00 01 10 11 VMEAS 00 00 8 samples 16 samples 4 samples 2 sample 00 Sample number in any other voltage measurement conversions Updated by SSM_RESET or SPI write 00 01 10 11 DCS_PAD_V 0 0 0 4 samples 16 samples 8 samples 1 sample Passenger inhibit measurement mode 0 Current 1 Voltage SAFESEL 1 1 1 Safing engine mode select Updated by SSM_RESET or SPI write 0 Internal safing engine 1 external safing engine DocID029257 Rev 1 71/277 276 SPI interfaces VSF_V L9680 0 0 0 VSF voltage select Updated by SSM_RESET or SPI write 0 20V 1 25V VINGOOD_FILT_SEL 0 - - Selector of filter time for VINGOOD going low (time is fixed to 3.5 μs for VINGOOD going high) 0 1 μs 1 3.5 μs WD1_TO_DIS 0 0 - Disable of initial 500ms timeout function of WD1 state machine Updated by WSM_RESET or SPI write 0 timeout function is enabled 1 timeout function is disabled 72/277 DocID029257 Rev 1 L9680 SPI interfaces RW Read: 0200 Write: 0004 RESTART_SYBST_SEL SSM Type: WSM 02 POR ID: 0 - - 4 3 SYNCBST_EN SPI_OFF x ERSWITCH_LIM_SEL SYBST_V SPI_OFF 0 ERSWITCH_LIM_SEL SYBST_V 7 2 1 0 SAT_V 5 VSUP_EN 8 SAT_V 6 ER_BST_EN 9 ER_BST_EN 10 ER_CUR_EN 11 ER_CUR_EN ER_BST_V 0 ER_BST_V 0 12 VBATMON_TH_SEL 0 13 VBATMON_TH_SEL 0 14 VIN_TH_SEL - 15 VIN_TH_SEL MISO 16 KEEP_SYNCBST_ON MOSI 17 KEEP_SYNCBST_ON 18 PD&VRCM_SEL 19 PD&VRCM_SEL System control register (SYS_CTL) RESTART_SYBST_SEL RESTART_SYBST_SEL 7.3.3 Selection of comparator used to restart sync boost in erstate (don't care in case SYS_CTL(KEEP_SYNCBST_ON) bit is high) 0 VIN comparator is used; syncboost is switched off entering erstate and switched on once VIN goes above VIN_fastslope threshold. 1 SYNCBST comparator is used; syncboost is switched off entering erstate and switched on when SYNCBST voltage falls down VSYNCBST_RESTART_TH threshold (this condition requires that SYNCBST voltage has been pulled up above the same threshold previously). PD&VRCM_SEL 0 0 0 Squib pull down current level and VRCM leakage to GND threshold selection 0 1 mA pull down current and 450 μA VRCM leakage to GND threshold 1 5 mA pull down current and 2 mA VRCM leakage to GND threshold KEEP_SYNCBST_ON 1 - - SYNC Boost behaviour during ER state 0 SYNC Boost is disabled entering in ER state 1 SYNC Boost stay enabled in ER state. If boost is OFF in ER state and this command is received during that state the boost is switched on. VIN_TH_SEL 0 0 0 VIN comparators threshold selector 0 VINGOOD= VINgood0 1 VINGOOD= VINgood1 DocID029257 Rev 1 73/277 276 SPI interfaces VBATMON_TH_SEL L9680 00 00 00 VBATMON comparators threshold selector 00 VINGOOD= VINgood0 01 VINGOOD= VINgood1 10 VINGOOD= VINgood2 11 VINGOOD= VINgood3 ER_BST_V 0 0 0 ER Boost voltage select Updated by SSM_RESET or SPI write 0 set 23V boost 1 set 33V boost ER_CUR_EN 00 00 00 ER charge / discharge control 00 Current sources off 01 ER charge enabled 10 ER discharge enabled 11 Current sources off ER_BST_EN 1 1 1 Boost enable Updated by SSM_RESET or SPI write 0 ER_BOOST OFF request 1 ER_BOOST ON request SYNCBST_EN 1 1 1 Syncboost enable Updated by SSM_RESET or SPI write 0 SYNC_BOOST OFF request 1 SYNC_BOOST ON request SPI_OFF 0 0 0 Go to POWER OFF state from POWERMODE SHUTDOWN state Updated by SSM_RESET or SPI write while in POWERMODE SHUTDOWN state 0 no effect 1 transition to POWER OFF state ERSWITCH_LIM_SEL 0 - - ERswitch current limitation select Updated by POR or SPI write 0 Low current limit 1 High current limit is no more available SYBST_V 0 0 0 Sync Boost voltage select Updated by SSM_RESET or SPI write 0 Low - syncboost=12V 1 High - syncboost=14.75V 74/277 DocID029257 Rev 1 L9680 SPI interfaces 0 SAT_V 0 0 SatBuck and Satellite Interface voltage select Updated by SSM_RESET or SPI write 0 Low - satbuck=7.2V 1 High - satbuck=9V 7.3.4 SPI Sleep command register (SPI_SLEEP) 19 18 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 W Read: - Write: 0006 POR Type: 0 - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SSM 0 03 N/A N/A N/A Non-latched command that allows transition into POWERMODE_SHUTDOWN state according to the Power Control State Flow Diagram SLEEP_MODE System status register (SYS_STATE) 16 - 0 0 0 04 Type: R Read: 0400 Write: POR ID: OPER_CTL_STATE[2:0] 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 POWER_CTL_STATE MOSI 17 OPER_CTL_STATE 18 SSM 19 MISO 15 $3C95X ID: 7.3.5 16 WSM MISO 17 - WSM MOSI 000 000 000 Reports Operating Control State Updated per Power Up Phases diagram 000 = INIT DocID029257 Rev 1 75/277 276 SPI interfaces L9680 001 = DIAG 010 = SAFING 011 = SCRAP 100 = ARMING 101 unused 110 unused 111 unused POWER_CTL_STATE[2:0] 000 - - Reports Power Control State Updated per Power Control State Flow Diagram 000 = AWAKE 001 = STARTUP 010 = RUN 011 = ER 100 = POWER MODE SHUTDOWN 101 unused 110 unused 111 unused 76/277 DocID029257 Rev 1 L9680 R Read: 0500 Write: - WAKEUP 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X ER_BST_NOK VCC_UV VCC_OV 0 ER_BST_ON ER_CHRG_ON ER_LCDIS_ON ER_HCDIS_ON ER_SW_ON S_BST_ACT SATBUCK_ACT VCC_ACT - - - VSF_ACT 13 SSM Type: 14 WSM 05 15 POR ID: VINBAD VBBAD MISO 16 WAKEUP MOSI 17 SATBUCK_NOK 18 S_BST_NOK 19 NOT_VINGOOD Power state register (POWER_STATE) NOT_VBGOOD 7.3.6 SPI interfaces WAKEUP pin status Set and cleared based on voltage 0 WAKEUP pin < WU_off 1 WAKEUP pin > WU_on VBBAD - - - VBATMON bad pin status Set and cleared based on voltage 1 VBATMON < VBBAD 0 VBATMON > VBBAD NOT_VBGOOD - - - VBATMON good pin status Set and cleared based on voltage 1 VBATMON < VBGOOD 0 VBATMON > VBGOOD VINBAD - - - VIN bad pin status Set and cleared based on voltage 0 VIN > VINBAD 1 VIN < VINBAD NOT_VINGOOD - - - VIN good pin status Set and cleared based on voltage 0 VIN > VINGOOD 1 VIN < VINGOOD S_BST_NOK - - - SYNCBOOST bad pin status DocID029257 Rev 1 77/277 276 SPI interfaces L9680 Set based on voltage, cleared on SPI read 1 V_SYNCBOOST < SYNCBOOST_OK 0 V_SYNCBOOST > SYNCBOOST_OK SATBUCK_NOK - - - SATBUCK bad pin status Set based on voltage, cleared on SPI read 1 V_SATBUCK < SATBUCK_OK 0 V_SATBUCK > SATBUCK_OK ER_BST_NOK - - - ERBOOST pin status Set and cleared based on voltage 1 V_ERBOOST < ERBOOST_OK 0 V_ERBOOST > ERBOOST_OK VCC_UV - - - VCC_UV status Set based on voltage, cleared on SPI read 0 VCC > VCC_UV 1 VCC < VCC_UV VCC_OV - - - VCC_OV status Set based on voltage, cleared on SPI read 0 VCC < VCC_OV 1 VCC > VCC_OV ER_BST_ON 0 - - ERBOOST_ON state Updated according to ER_BOOST Control Behavior diagram 0 RBOOST_OFF or ERBOOST_OT state or ER_BST_STBY state (boost not running) 1 ERBOOST_ON state (boost running) ER_CHRG_ON 0 0 0 ERCHARGE_ON state Updated according to ER_CHARGE Power Mode Control diagram 0 ERCHARGE_ON = 0 1 ERCHARGE_ON = 1 ER_LCDIS_ON 0 - - ER Low Current Discharge State Updated according to ER Low current discharge state diagram 0 ER_LCDIS_OFF 1 ER_LCDIS_ON 78/277 DocID029257 Rev 1 L9680 SPI interfaces ER_HCDIS_ON 0 - - ER High Current Discharge State Updated according to ER High Current discharge state diagram 0 ER_HCDIS_OFF 1 ER_HCDIS_ON ER_SW_ON 0 - - ER_SWITCH State Updated according to ER Switch state diagram 0 ER_SWITCH_OFF 1 ER_SWITCH_ON S_BST_ACT 0 - - SYNCBOOST Active state Updated according to SYNCBOOST Power Mode Control state diagram 0 SYNCBOOST supply in SYNCBOOST_OFF state 1 SYNCBOOST supply in SYNCBOOST_ON state SATBUCK_ACT 0 0 0 SATBUCK Active state Updated according to SATBUCK Power Mode Control state diagram 0 SATBUCK supply in SATBUCK_OFF state 1 SATBUCK supply in SATBUCK_ON state VCC_ACT 0 - - Buck Active state Updated according to VCC Power Mode Control state diagram 0 VCC supply in VCC_OFF or VCC_SHUTDOWN states 1 VCC supply in VCC_RAMPUP or VCC_ON states VSF_ACT 0 0 0 VSF Active state Updated according to VSF Control Logic diagram 0 VSF_EN = 0 1 VSF_EN = 1 DocID029257 Rev 1 79/277 276 SPI interfaces 7.3.7 L9680 Deployment configuration registers (DCR_x) MISO 16 - 0 0 0 0 15 14 13 12 X X X X Deploy_Time 0 0 0 0 Deploy_Time ID: 06 (DCR_0) 07 (DCR_1) 08 (DCR_2) 09 (DCR_3) 0A (DCR_4) 0B (DCR_5) 0C (DCR_6) 0D (DCR_7) 0E (DCR_8) 0F (DCR_9) 10 (DCR_A) 11 (DCR_B) Type: RW Read: 0600 (DCR_0) 0700 (DCR_1) 0800 (DCR_2) 0900 (DCR_3) 0A00 (DCR_4) 0B00 (DCR_5) 0C00 (DCR_6) 0D00 (DCR_7) 0E00 (DCR_8) 0F00 (DCR_9) 80/277 11 10 9 DocID029257 Rev 1 8 7 6 5 4 3 2 1 X 0 0 PD_CURR_CSR PD_CURR_CSR MOSI 17 Dep_expire_time Dep_expire_time 18 Dep_Current 19 Dep_Current Deployment Configuration Channel 0 (DCR_0) Deployment Configuration Channel 1 (DCR_1) Deployment Configuration Channel 2 (DCR_2) Deployment Configuration Channel 3 (DCR_3) Deployment Configuration Channel 5 (DCR_5) Deployment Configuration Channel 6 (DCR_6) Deployment Configuration Channel 7 (DCR_7) Deployment Configuration Channel 8 (DCR_8) Deployment Configuration Channel 9 (DCR_9) Deployment Configuration Channel A (DCR_A) Deployment Configuration Channel B (DCR_B) L9680 SPI interfaces 1000 (DCR_A) 1100 (DCR_B) SSM WSM 000C (DCR_0) 000E (DCR_1) 0010 (DCR_2) 0012 (DCR_3) 0014 (DCR_4) 0016 (DCR_5) 0018 (DCR_6) 001A (DCR_7) 001C (DCR_8) 001E (DCR_9) 0020 (DCR_A) 0022 (DCR_B) POR Write: Deploy_Time[5:0] 0000 0000 0000 Default deployment time = 0 us (no deployment, 8 us pulse output on ARM1 00 00 00 pin during PULSE TEST) Deployment time: actual deployment time (ms) = Deploy_Time*0.064ms (0.064ms/count up to 4.032ms max) Dep_Current[1:0] 00 00 00 Deployment Current limit select Updated by SSM_RESET or SPI write while in DIAG state 00 01 10 11 Dep_expire_time[1:0] 00 00 Unused (no deploy) 1.75A min 1.2A min Unused (no deploy) 00 Deploy command expiration timer select Updated by SSM_RESET or SPI write while in DIAG state 00 01 10 11 PD_CURR_CSR 0 0 0 500ms 250ms 125ms 0ms Pull down current control for Commmon SR connection Updated by SSM_RESET or SPI write 0 PD Current OFF only for channel selected for diagnostic measurement, ON for all other channel 1 PD Current OFF for both channels of the channel pair selected for diagnostic measurement, ON for all other channel DocID029257 Rev 1 81/277 276 SPI interfaces 0 0 0 0 0 0 0 0 12 Type: RW Read: 1200 Write: 0024 POR ID: CHxDEPREQ 7 6 5 4 3 2 1 0 CH0DEP CH0DEPREQ X 8 CH1DEP CH1DEPREQ X 9 CH2DEP CH2DEPREQ X 10 CH3DEP CH3DEPREQ X - 11 CH4DEP CH4DEPREQ 12 CH5DEP CH5DEPREQ 13 CH6DEP CH6DEPREQ 14 CH7DEP CH7DEPREQ 15 CH8DEP CH8DEPREQ MISO 16 CH9DEP CH9DEPREQ MOSI 17 CHADEP CHADEPREQ 18 CHBDEP CHBDEPREQ 19 SSM Deployment command (DEPCOM) WSM 7.3.8 L9680 N/A N/A N/A Channel x Deploy Request - non-latched channel-specific deploy request 0 No change to deployment control for channel x 1 Clear and start Expiration timer if in ARMING or SAFING state and in DEPLOY_ENABLED state CHxDEP 0 0 0 Channel x deployment expiration timer enable Set when SPI_DEPCOM(CHxDEPREQ=1) AND in ARMING or SAFING state AND in DEP_ENABLED state Cleared on SSM_RESET OR when in DEP_DISABLED state OR when Deploy Expiration Timer x reaches timeout threshold 1 Expiration timer enabled - Deploy command still valid 0 Expiration Timer disabled - Deploy command no more valid 82/277 DocID029257 Rev 1 L9680 7.3.9 SPI interfaces Deployment status registers (DSR_x) MISO 17 16 - 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 DCRxERR 18 CHxSTAT 19 MOSI CHxDS Deployment Status Channel 0 (DSR_0) Deployment Status Channel 1 (DSR_1) Deployment Status Channel 2 (DSR_2) Deployment Status Channel 3 (DSR_3) Deployment Status Channel 5 (DSR_5) Deployment Status Channel 6 (DSR_6) Deployment Status Channel 7 (DSR_7) Deployment Status Channel 8 (DSR_8) Deployment Status Channel 9 (DSR_9) Deployment Status Channel A (DSR_A) Deployment Status Channel B (DSR_B) ID: 13 (DSR_0) 14 (DSR_1) 15 (DSR_2) 16 (DSR_3) 17 (DSR_4) 18 (DSR_5) 19 (DSR_6) 1A (DSR_7) 1B (DSR_8) 1C (DSR_9) 1D (DSR_A) 1E (DSR_B) Type: R Read: 1300 (DSR_0) 1400 (DSR_1) 1500 (DSR_2) 1600 (DSR_3) 1700 (DSR_4) 1800 (DSR_5) 1900 (DSR_6) 1A00 (DSR_7) 1B00 (DSR_8) 1C00 (DSR_9) 1D00 (DSR_A) 1E00 (DSR_B) Write: - DocID029257 Rev 1 DEP_CHx_ExpTimer 83/277 276 WSM SSM CHxDS L9680 POR SPI interfaces 0 0 0 Channel x deployment successful Updated according to Deployment Driver Control Logic (set when deployment terminates on ch x due to deploy timer timeout, cleared on SSM_RESET OR when deployment starts on ch x) 0 Deployment not successful 1 Deployment successful CHxSTAT 0 0 0 Channel x deployment status Updated according to Deployment Driver Control Logic (set when deployment starts on ch x, cleared on SSM_RESET OR when deployment terminates due to deploy timer timeout, LS Over current OR GND Loss) 0 Deployment not in progress 1 Deployment in progress DCRxERR 0 0 0 Deployment configuration register error 0 Deploy configuration change accepted and stored in memory 1 Deploy configuration change rejected because deploy is in progress (or DEP_EXPIRE_TIME changed when in DEP_ENABLED state) DEP_CHx_ExpTimer[5:0] 0000 0000 0000 Channel x Deployment Expiration Timer value 8ms/count 00 00 00 Updated according to Deployment Driver Control Logic (Cleared on SSM_RESET OR when Exp Timer times out OR when SPI_DEPREQx is received while in DEP_ENABLED state AND in ARMING or SAFING states) 84/277 DocID029257 Rev 1 L9680 SPI interfaces 7.3.10 Deployment current monitor registers (DCMTSxy) Deployment Current Monitor Status Channel 0,1 (DDCMTS01) Deployment Current Monitor Status Channel 2,3 (DDCMTS23) Deployment Current Monitor Status Channel 4,5 (DDCMTS45) Deployment Current Monitor Status Channel 6,7 (DDCMTS67) Deployment Current Monitor Status Channel 8,9 (DDCMTS89) Deployment Current Monitor Status Channel A,B (DDCMTSAB) 19 18 0 0 MOSI MISO 17 16 0 0 - 15 14 X X 11 10 9 8 7 6 X X X X X X X X Type: R Read: 1F00 (DDCMTS01) 2000 (DDCMTS23) 2100 (DDCMTS45) 2202 (DDCMTS67) 2300 (DDCMTS89) 2400 (DDCMTSAB) Write: - 5 4 3 2 1 0 X X X X X X Current_Mon_Timer_x[7:0] SSM 1F (DDCMTS01) 20 (DDCMTS23) 21 (DDCMTS45) 22 (DDCMTS67) 23 (DDCMTS89) 24 (DDCMTSAB) WSM 12 Current_Mon_Timer_y[7:0] ID: POR 13 Current_Mon_Timer_y[7:0] $00 $00 $00 Channel y current monitor timer value corresponding to SPI command DCMTSxy. Set to default (cleared) on SSM_RESET or when a new deployment starts on channel y. Increments each 16μs while deployment current exceeds monitor threshold on channel y Current_Mon_Timer_x[7:0] $00 $00 $00 Channel x current monitor timer value corresponding to SPI command DCMTSxy. Set to default (cleared) on SSM_RESET or when a new deployment starts on channel x. Increments each 16μs while deployment current exceeds monitor threshold on channel y DocID029257 Rev 1 85/277 276 SPI interfaces 7.3.11 L9680 Deploy enable register (SPIDEPEN) 19 18 0 0 0 0 15 14 13 12 11 10 9 - 7 6 5 4 3 2 1 0 DEPEN_WR[15:0] 25 Type: RW Read: 2500 Write: 004A POR ID: DEPEN_WR[15:0] 8 DEPEN_STATE[15:0] SSM MISO 16 WSM MOSI 17 N/A N/A N/A Non-latched encoded value for LOCK / UNLOCK command $0FF0 LOCK - enter DEP_DISABLED state $F00F UNLOCK - enter DEP_ENABLED state. DEPEN_STATE[15:0] $0FF0 $0FF0 $0FF0Deploy Enabled State Updated according to Global SPI Deployment Enable State Diagram $0FF0 In DEP_DISABLED state $F00F In DEP_ENABLED state 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 GNDLOSSB GNDLOSSA GNDLOSS9 GNDLOSS8 GNDLOSS7 GNDLOSS6 GNDLOSS5 GNDLOSS4 GNDLOSS3 GNDLOSS2 GNDLOSS1 GNDLOSS0 MISO 15 SSM 19 18 MOSI WSM Deployment ground loss register (LP_GNDLOSS) POR 7.3.12 17 16 0 0 0 - 0 0 0 ID: 26 Type: R Read: 2600 Write: - GNDLOSSx Loop x Squib Ground loss Cleared upon SSM_RESET or SPI read. Set when GND loss is detected during deployment or loop diag's (HS sw test, LS sw test, squib resistance) 0 Loss of ground not detected 1 Loss of ground detected 86/277 DocID029257 Rev 1 L9680 7.3.13 SPI interfaces Device version register (VERSION_ID) 19 18 0 0 MOSI MISO 17 16 0 0 - R Read: 2700 Write: - DEVICE ID 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 SSM Type: 13 WSM 27 14 POR ID: 15 - - - DEVICE ID VERSN Identification of the device Static value - never updated 001 Low end 010 Medium end 011 High end VERSN - - - Identification of the silicon version Static value - never updated 000000 AA version 000001 AB version 001000 BA version 001001 BB version 010000 CA version 010001 CB version 010010 CC version DocID029257 Rev 1 87/277 276 SPI interfaces 7.3.14 L9680 Watchdog retry configuration register (WD_RETRY_CONF) 19 18 17 0 0 0 MOSI MISO 16 15 14 0 0 0 - RW Read: 2800 Write: 0050 10 9 8 7 6 5 4 3 2 1 0 WD2_ERR_TH WD2_RETRY_TH X X X X X WD1_RETRY_TH WD2_ERR_TH WD2_RETRY_TH 0 0 0 0 0 WD1_RETRY_TH SSM Type: 11 WSM 28 12 POR ID: 13 WD2_ERR_TH 4 4 - WD2 error counter threshold (number of W2 reset permitted before going to WD2_STOP state) WD2_RETRY_TH 4 4 - WD2 retry counter threshold (number of W2 errors permitted before asserting WD2_Lockout and increment WD2_ERRcnt) WD1_RETRY_TH 7 7 - WD1 retry counter threshold (number of WD errors permitted before latching WD1_LOCKOUT=1) Microcontroller fault test register (MCU_FLT_TEST) 19 18 0 0 MISO 16 15 14 13 12 11 10 0 0 0 0 0 0 0 0 - 29 Type: W Read: - Write: 0052 $0FF0 POR ID: MCU_FLT_TEST 9 8 7 0 0 0 5 4 3 2 1 0 0 0 0 0 0 0 0 MCU Fault Test Mode - Allows the masking of the MCUFLT_ERR and prevents reset $0FF0 Mask MCUFLT_ERR $F00F Do not mask MCUFLT_ERR 88/277 6 MCU_FLT_TEST Mode $0FF0 SSM MOSI 17 $0FF0WSM 7.3.15 DocID029257 Rev 1 L9680 Watchdog timer configuration register (WDTCR) 19 18 MOSI MISO 17 16 - 0 0 14 X 0 RW Read: 2A00 Write: 0054 SSM Type: 0 WSM 2A 0 POR ID: WD1_MODE 15 13 12 WD1_MODE WD1_MODE 7.3.16 SPI interfaces 0 0 - 11 10 9 8 7 6 5 4 3 2 WDTMIN[6:0] WDTDELTA[6:0] WDTMIN[6:0] WDTDELTA[6:0] 1 0 WD1 Mode Updated by WSM_RESET or SPI write while in WD1_INIT state 0 Fast WD1 mode - nominal 8μs timer resolution (2ms max value) 1 Slow WD1 mode - nominal 64μs timer resolution (16.3ms max value) WDTMIN[6:0] $32 $32 - WD1 window minimum value - resolution according to WD1_MODE bit ($32 = 400μs in WD1 fast mode) Updated by WSM_RESET or SPI write while in WD1_INIT state WDTMIN[6:0] $19 $19 - WD1 window delta value - WDTMAX=WDTMIN+WDTDELTA - resolution according to WD1_MODE bit ($19 = 200μs in WD1 fast mode) Updated by WSM_RESET or SPI write while in WD1_INIT state DocID029257 Rev 1 89/277 276 SPI interfaces 7.3.17 L9680 WD1 timer control register (WD1T) 19 18 0 0 MOSI MISO 17 16 0 0 - RW Read: 2B01 Write: 0056 WD1CTL[1:0] X X X 12 11 10 9 8 7 6 5 4 3 2 X X X X X X X X X X X WD1CTL[1:0] 0 0 0 0 0 0 WD1CTL[1:0] WD1_TIMER SSM Type: 13 WSM 2B 14 POR ID: 15 00 00 00 WD1 Control command 1 0 Updated by SSM_RESET or SPI write 00 NOP 01 Code 'A' 10 Code 'B' 11 NOP WD1_TIMER $00 $00 $00 WD1 Window timer value Cleared by SSM_RESET or by WD1 refresh, incremented every 8μs or 64μs while in WD1_RUN or WD1_TEST states 90/277 DocID029257 Rev 1 L9680 WD state register (WDSTATE) 18 MISO 17 16 0 0 0 2C Type: R Read: 2C00 Write: POR ID: 0 WD1_ERR_CNT[3:0] 0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 WD1_ERR_CNT[3:0] WD_STATE[2:0] WD2_ERR_CNT[3:0] WD2_STATE[2:0] SSM 19 MOSI WSM 7.3.18 SPI interfaces - Watchdog 1 error counter Updated according to Watchdog State Diagram WD1_STATE[2:0] 000 000 - Watchdog state Updated according to Watchdog State Diagram 000 INITIAL 001 RUN 010 TEST 011 RESET 100 OVERRIDE WD2_ERR_CNT[3:0] 0000 0000 - Watchdog 2 error counter Updated according to Watchdog State Diagram WD2_STATE[3:0] 0000 0000 - Watchdog state Updated according to Watchdog State Diagram 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 INITIAL OVERRIDE INITSEED RUN TEST QUAL LOCK STOPPING STOP RESET DocID029257 Rev 1 91/277 276 SPI interfaces Clock configuration register (CLK_CONF) 0 RW Read: 2D00 Write: 005A VCCBCK_F_SEL[1:0] X X X X X X 0 0 0 0 0 0 SSM Type: 10 WSM 2D 11 POR ID: 0 12 00 - - 9 8 7 6 VCCBuck switching frequency select Updated by POR or SPI write 00 1.88 MHz 01 2.13 MHz 10 2.00 MHz 11 2.00 MHz SATBCK_F_SEL[1:0] 00 - - SatBuck switching frequency select Updated by POR or SPI write 00 1.88 MHz 01 2.13 MHz 10 2.00 MHz 11 2.00 MHz SYBST_F_SEL[1:0] 00 - - Sync Boost switching frequency select Updated by POR or SPI write 00 1.88 MHz 01 2.13 MHz 10 2.00 MHz 11 2.00 MHz AUX_SS_DIS 1 - - Auxiliary oscillator Spread Spectrum disable Updated by POR or SPI write 0 Spread Spectrum enabled 1 Spread Spectrum disabled 92/277 DocID029257 Rev 1 5 4 3 2 1 0 ERBST_F_SEL ERBST_F_SEL[1:0] 0 13 MAIN_SS_DIS 0 14 MAIN_SS_DIS - 15 AUX_SS_DIS MISO 16 AUX_SS_DIS MOSI 17 SYBST_F_SEL SYBST_F_SEL[1:0] 18 SATBCK_F_SEL SATBCK_F_SEL[1:0] 19 VCCBCK_F_SEL VCCBCK_F_SEL[1:0] 7.3.19 L9680 L9680 SPI interfaces 0 MAIN_SS_DIS - - Main oscillator Spread Spectrum disable Updated by POR or SPI write 0 Spread Spectrum enabled 1 Spread Spectrum disabled ERBST_F_SEL[1:0] 00 - - ER Boost switching frequency select Updated by POR or SPI write 00 1.88 MHz 01 2.13 MHz 10 2.00 MHz 11 2.00 MHz Scrap seed read command register (SCRAP_SEED) 18 0 0 MOSI MISO 17 16 0 0 - 2E Type: R Read: - Write: 2E00 POR ID: 15 14 13 12 11 10 9 8 7 6 5 X X X X X X X X X X X 0 0 0 0 0 0 0 0 4 3 2 1 0 X X X X X SEED[7:0] SSM 19 WSM 7.3.20 N/A N/A N/A SEED[7:0] $00 $00 $00 Random scrap seed value - generated from a free-running 8-bit counter DocID029257 Rev 1 93/277 276 SPI interfaces Scrap key write command register (SCRAP_KEY) 18 0 0 MOSI MISO 17 16 0 0 - 2F Type: W Read: - Write: 005E POR ID: 15 14 13 12 11 10 9 8 X X X X X X X X 0 0 0 0 0 0 0 0 7 6 5 4 0 0 0 0 3 2 1 0 0 0 0 KEY[7:0] 0 SSM 19 WSM 7.3.21 L9680 N/A N/A N/A KEY[7:0] Scrap state entry command register (SCRAP_STATE) 19 18 MISO 17 16 15 14 13 12 11 10 9 0 0 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 $3535 0 30 Type: W Read: - Write: 0060 POR ID: 0 0 0 0 0 0 0 0 0 SSM MOSI WSM 7.3.22 $00 $00 $00 KEY value submitted to the SCRAP state machine (correct value is derived from the seed value using a simple logical inversion on the even-numbered bits (0, 2, 4, 6)) N/A N/A N/A Non-latched Scrap State entry command Enter Scrap state from DIAG state 94/277 DocID029257 Rev 1 L9680 Safing state entry command register (SAFING_STATE) 19 18 0 0 MISO 16 15 14 13 12 11 10 9 0 0 0 0 0 0 0 0 0 - 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 $ACAC 31 Type: W Read: - Write: 0062 POR ID: 0 0 SSM MOSI 17 WSM 7.3.23 SPI interfaces N/A N/A N/A Non-latched Safing State entry command Enter safing state from DIAG state and clear arming pulse stretch counter (if received in DIAG or SAFING state) WD2 recover write command register (WD2_RECOVER) 18 MOSI MISO 17 16 0 0 0 32 Type: W Read: - Write: 0064 POR ID: 0 15 14 13 12 11 10 9 8 X X X X X X X X 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 $AA 0 0 0 0 0 SSM 19 WSM 7.3.24 N/A N/A N/A Non-latched command to clear WD2_retry counter during WD2 LOCK state DocID029257 Rev 1 95/277 276 SPI interfaces WD2 seed read command register (WD2_SEED) 18 0 0 MOSI MISO 17 16 0 0 - 33 Type: R Read: - Write: 3300 POR ID: 15 14 X X 13 12 11 10 9 8 7 6 5 X X X X X X X X X WD2_PREV_KEY[7:0] 4 3 2 1 0 X X X X X WD2_SEED[7:0] SSM 19 WSM 7.3.25 L9680 N/A N/A N/A WD2_PREV_KEY[7:0] $0D $0D $0D Previous WD2 key value - stored key from previous comparison WD2_SEED[7:0] WD2 key write command register (WD2_KEY) 18 MOSI MISO 17 16 0 0 0 34 Type: W Read: - Write: 0068 POR ID: 0 15 14 13 12 11 10 9 8 X X X X X X X X 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 KEY[7:0] 0 0 0 0 0 SSM 19 WSM 7.3.26 $F0 $F0 $F0 Random WD2 seed value - generated from a free-running 8-bit counter N/A N/A N/A KEY[7:0] 96/277 Previous WD2 key value - stored key from previous comparison $0D $0D $0D (correct value is derived from WD2_KEY = WD2_SEED ‡ WD2_PREV_KEY + $01 where ‡ denotes a bit-wise XOR) DocID029257 Rev 1 L9680 WD test command register (WD_TEST) 19 18 0 0 MISO 16 15 14 13 0 0 0 0 0 - 12 11 10 9 8 7 6 5 0 0 0 0 0 0 WD1_TEST = $3C 35 Type: W Read: - Write: 006A POR ID: 0 0 4 3 2 1 0 0 0 WD2_TEST = $3C 0 0 0 SSM MOSI 17 WSM 7.3.27 SPI interfaces N/A N/A N/A $0D $0D $0D Non-latched WD1 and WD2 Test Commands WD1_TEST and WD2_TEST SPI command as described in Watchdog State Diagram DocID029257 Rev 1 97/277 276 SPI interfaces System diagnostic register (SYSDIAGREQ) 19 18 0 0 MISO 16 0 0 - 36 Type: RW Read: 3600 Write: 006C POR ID: WSM MOSI 17 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 X X X X X X X X X X X X DSTEST[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 DSTEST[3:0] 0 SSM 7.3.28 L9680 DSTEST[3:0] 0000 0000 0000 Diagnostic State Test selection Updated by SSM_RESET or SPI write while in DIAG state 0000 = all outputs inactive 0001 = ARM 1 pin active 0010 = ARM 2 pin active 0011 = ARM 3 pin active 0100 = ARM 4 pin active 0101 = PSINHB pin inactive (high) 0110 = VSF regulator active 0111 = HS squib driver FET active 1000 = LS squib driver FET active 1001 = Output deployment timing pulses on ARM1 (separated by 8 ms) 1010 = HS squib driver FET active to test full path (FET switched off by the comparator used in the deployment current timer monitor) 1011 - 1111 = all outputs inactive 98/277 DocID029257 Rev 1 L9680 R Read: 3700 Write: - DIAG_LEVEL 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X STG STB SQP 0 0 0 Diagnostic mode selector LEAK_CHSEL 11 SSM Type: 12 WSM 37 13 POR ID: FP 14 SBL 0 15 RES_MEAS_CHSEL/HIGH_LEV_DIAG_SELECTED TIP MISO 16 - DIAG_LEVEL MOSI 17 HSR_LO 18 HSR_HI 19 HS_DRV_OK Diagnostic result register for deployment loops (LPDIAGSTAT) FETON 7.3.29 SPI interfaces Not present for low level diagnostic Updated by SSM_RESET or SPI write to LPDIAGREQ 0 low level mode 1 high level mode TIP 0 0 0 High level diagnostic test is running Updated by SSM_RESET or Loops diagnostic state machine 0 High level diagnostic test is not running 1 High level diagnostic test is running FP 0 0 0 Fault present before requested diagnostic Updated by SSM_RESET or Loops diagnostic state machine 0 Fault not present before requested diagnostic 1 Fault present before requested diagnostic FETON 0 0 0 FET activation during diagnostic Updated by SSM_RESET or Loops diagnostic state machine or when HS or LS FET is activated during DIAG state DocID029257 Rev 1 99/277 276 SPI interfaces L9680 0 FET is off during diagnostic 1 FET is on during diagnostic HS_DRV_OK 0 0 0 FET Test Status Updated by SSM_RESET or Loops diagnostic state machine or when driver full path test is run test is run 0 HS squib driver full path test did not complete successfully 1 HS squib driver full path test complete successfully HSR_HI 0 0 0 HSR Diagnostic - HIGH Range Updated by SSM_RESET or Loops diagnostic state machine or when squib resistance test is run 0 HSR measurement < HSR HIGH value 1 HSR measurement > HSR HIGH value HSR_LO 0 0 0 HSR Diagnostic - Low Range Updated by SSM_RESET or Loops diagnostic state machine or when squib resistance test is run 1 HSR measurement< HSR LOW value 0 HSR measurement > HSR LOW value RES_MEAS_CHSEL[3:0] 0000 0000 0000 Channel selected for resistance measurement HIGH_LEV_DIAG_SELECTED[3:0] Updated by SSM_RESET or Loops diagnostic state machine or as determined by squib resistance channel selected 0000 = Ch 0 0000 No diagnostic selected 0001 = Ch 1 0001 VRCM CHECK 0010 = Ch 2 0010 Leakage CHECK 0011 = Ch 3 0011 Short Between Loops CHECK 0100 = Ch 4 0100 Unused 0101 = Ch 5 0101Squib resistance range CHECK 0110 = Ch 6 0110 Squib resistance measurement 0111 = Ch 7 0111 FET test 1000 = Ch 8 1000 - 1111 Unused 1001 = Ch 9 1010 = Ch A 1011 = Ch B 0100 - 1111 None Selected 100/277 DocID029257 Rev 1 L9680 SPI interfaces SBL 0 0 0 Short between loop state Updated by SSM_RESET or Loops diagnostic state machine 0 Short between squib loops is not present 1 Short between squib loops is present STG 0 0 0 Short to Ground Test Status Updated by SSM_RESET or Loops diagnostic state machine or as determined by squib leakage diagnostic 0 STG not detected 1 STG detected STB 0 0 0 Short to Battery Test Status Updated by SSM_RESET or Loops diagnostic state machine or as determined by squib leakage diagnostic 0 STB not detected 1 STB detected SQP 0 0 0 Squib PIN where leakage test has been performed Updated by SSM_RESET or Loops diagnostic state machine or as determined by squib leakage diagnostic 0 SRx 1 SFx LEAK_CHSEL[3:0] 0000 0000 0000 Channel selected for leakage measurement Updated by SSM_RESET or Loops diagnostic state machine or as determined by squib leakage diagnostic 0000 = Ch 0 0001 = Ch 1 0010 = Ch 2 0011 = Ch 3 0100 = Ch 4 0101 = Ch 5 0110 = Ch 6 0111 = Ch 7 1000 = Ch 8 1001 = Ch 9 1010 = Ch A 1011 = Ch B 1100 - 1111 None Selected DocID029257 Rev 1 101/277 276 SPI interfaces Loops diagnostic configuration command register for low level diagnostic (LPDIAGREQ) RW Read: 3800 Write: 0070 DIAG_LEVEL SSM Type: WSM 38 POR ID: 0 0 0 5 4 3 2 1 0 LEAK_CHSEL[3:0] 6 LEAK_CHSEL[3:0] 7 RES_MEAS_CHSEL[3:0]RES_MEAS_CHSEL[3:0] 8 VRCM[1:0] 9 VRCM[1:0] 10 ISINK 11 ISINK 0 12 ISRC [1:0] 0 13 ISRC [1:0] 0 - 0 14 PD_CURR 15 PD_CURR MISO 16 ISRC_CURR_SEL MOSI 17 ISRC_CURR_SEL 18 DIAG_LEVEL 19 DIAG_LEVEL 7.3.30 L9680 Diagnostic mode selector Updated by SSM_RESET or SPI write 0 low level mode 1 N/A - see description below ISRC_CURR_SEL 0 0 0 Selection of ISRC current value 0 40mA 1 8mA PD_CURR 0 0 0 Pull down current control Updated by SSM_RESET or SPI write 0 Request OFF only for channels connected to VRCM or ISINK or ISRC, ON for all other channels 1 Request OFF for all channels ISRC [1:0] 00 00 00 High side current source for channel selected in RES_MEAS_CHSEL[3:0] Updated by SSM_RESET or SPI write 00 = OFF 102/277 DocID029257 Rev 1 L9680 SPI interfaces 01 = ON 40 mA/ 8 mA current for channel selected in RES_MEAS_CHSEL, OFF on all other channels 10 = ON bypass current for channel selected in RES_MEAS_CHSEL, OFF ON all other channels 11 = ON ISRC 40mA or 8mA current for channel selected in RES_MEAS_CHSEL and connect the SRM Differential Amplifier to the other squib channel of the selected channel pair ISINK 0 0 0 Low Side current sink control (max 50mA) Updated by SSM_RESET or SPI write 0 All channels OFF 1 ON for channel selected by RES_MEAS_CHSEL[3:0], OFF on all other channels VRCM[1:0] 00 00 00 Voltage Regulator Current Monitor control Updated by SSM_RESET or SPI write 00 VRCM not connected 01 VRCM connected to SFx of channel selected by LEAK_CHSEL[3:0] 10 VRCM connected to SRx of channel selected by LEAK_CHSEL[3:0] and pull down current of the same channel disabled 11 VRCM connected to SRx of channel selected by LEAK_CHSEL[3:0] and pull down current of the same channel enabled (ISINK and ISRC must be switched off) RES_MEAS_CHSEL[3:0] 0000 0000 0000 Squib Resistance Measurement Channel select - selects the channel and muxes for the resistance test, and the channel for HS driver test (full path fet test) activation Updated by SSM_RESET or SPI write 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0100 Channel 4 0101 Channel 5 0110 Channel 6 0111 Channel 7 1000 Channel 8 1001 Channel 9 1010 Channel A 1011 Channel B 0100 - 1111 None Selected DocID029257 Rev 1 103/277 276 SPI interfaces L9680 LEAK_CHSEL[3:0] 0000 0000 0000 Squib Leakage Measurement Channel select - selects the channel and muxes for the leakage test, and the channel for HS/LS FET test activation. Updated by SSM_RESET or SPI write 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0100 Channel 4 0101 Channel 5 0110 Channel 6 0111 Channel 7 1000 Channel 8 1001 Channel 9 1010 Channel A 1011 Channel B 0100 - 1111 None Selected 104/277 DocID029257 Rev 1 L9680 SPI interfaces - 0 0 0 RW Read: 3800 Write: 0070 DIAG_LEVEL 12 11 10 9 8 X X X X X X X 0 0 0 0 0 0 0 SSM Type: 13 WSM 38 14 POR ID: 0 15 0 0 0 7 6 5 4 3 2 1 0 LOOP_DIAG_CHSEL[3:0] LOOP_DIAG_CHSEL[3:0] MISO 16 SQP MOSI 17 SQP 18 HIGH_LEVEL_DIAG_SEL HIGH_LEVEL_DIAG_SEL 19 DIAG_LEVEL Loops diagnostic configuration command register for high level diagnostic (LPDIAGREQ) DIAG_LEVEL 7.3.31 Diagnostic mode selector 0 0 N/A - see description above 1 1 high level mode HIGH_LEVEL_DIAG_SEL 000 000 000 Selection of high level squib diagnostic Updated by SSM_RESET or SPI write 000 No diagnostic selected 001 VRCM CHECK 010 Leakage CHECK 011 Short Between Loops CHECK 100 Unused 101 Squib resistance range CHECK 110 Squib resistance measurement 111 FET test SQP 0 0 0 Squib pin select for all leakage diagnostic Updated by SSM_RESET or SPI write DocID029257 Rev 1 105/277 276 SPI interfaces L9680 0 SRx 1 SFx LOOP_DIAG_CHSEL[3:0] 0000 0000 0000 Channel select - selects the channel and muxes for all squib diagnostic. Updated by SSM_RESET or SPI write 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0100 Channel 4 0101 Channel 5 0110 Channel 6 0111 Channel 7 1000 Channel 8 1001 Channel 9 1010 Channel A 1011 Channel B 1100 - 1111 None Selected MISO 16 - 0 0 0 RW Read: 3900 Write: 0072 PSINHPOL 12 11 10 9 8 X X X X X X X 0 0 0 0 0 0 0 SSM Type: 13 WSM 39 14 POR ID: 0 15 0 0 0 7 6 5 4 SWOEN MOSI 17 X X CHID[3:0] SWOEN 18 DCS_PDCURR DCS_PDCURR 19 PSINHPOL DC sensor diagnostic configuration command register (SWCTRL) PSINHPOL 7.3.32 3 2 1 0 0 CHID[3:0] Selector of in range/ out of range for passenger inhibit function 0 if result is inside thresholds the counter is initialized to start value 1 if result is outside thresholds the counter is initialized to start value DCS_PDCURR 0 0 0 Disable of all pull down current for DC sensor Updated by SSM_RESET or SPI write 106/277 DocID029257 Rev 1 0 L9680 SPI interfaces 0 OFF for channel under voltage or current measurement, ON for all other channels 1 OFF for all channels SWOEN 0 0 0 Switch Output Enable Updated by SSM_RESET or SPI write 0 OFF 1 ON CHID[3:0] 0000 0000 0000 Channel ID - selects DC sensor channel for output activation Updated by SSM_RESET or SPI write 0000 Channel 0 0001 Channel 1 0010 Channel 2 0011 Channel 3 0100 Channel 4 0101 Channel 5 0110 Channel 6 0111 Channel 7 1000 Channel 8 0100 - 1111 None Selected DocID029257 Rev 1 107/277 276 SPI interfaces 7.3.33 L9680 ADC request and data registers (DIAGCTRL_x) ADC A control command (DIAGCTRL_A) 19 18 MISO 17 16 NEWDATA_A MOSI 0 15 14 13 12 11 10 9 8 7 X X X X X X X X X 0 ID: 3A Type: RW Read: 3A00 Write: 0074 6 5 4 3 2 1 0 1 0 1 0 ADCREQ_A[6:0] ADCREQ_A[6:0] ADCRES_A[9:0] ADC B control command (DIAGCTRL_B) 19 18 MISO 16 NEWDATA_B MOSI 17 0 15 14 13 12 11 10 9 8 7 X X X X X X X X X 0 ID: 3B Type: RW Read: 3B00 Write: 0076 6 5 4 3 2 ADCREQ_B[6:0] ADCREQ_B[6:0] ADCRES_B[9:0] ADC C control command (DIAGCTRL_C) 19 18 MISO 17 - NEWDATA_C MOSI 0 0 ID: 3C Type: RW Read: 3C00 Write: 0078 108/277 16 15 14 13 12 11 10 9 8 7 X X X X X X X X X ADCREQ_C[6:0] DocID029257 Rev 1 6 5 4 3 2 ADCREQ_C[6:0] ADCRES_C[9:0] L9680 SPI interfaces ADC D control command (DIAGCTRL_D) 19 18 MISO 17 16 NEWDATA_D MOSI 0 14 13 12 11 10 9 8 7 X X X X X X X X X 0 RW Read: 3D00 Write: 007A SSM Type: WSM 3D 6 ADCREQ_D[6:0] POR ID: NEWDATA_x 15 0 0 0 5 4 3 2 1 0 ADCREQ_D[6:0] ADCRES_D[9:0] New data available from convertion Updated by SSM_RESET or ADC state machine 0 cleared on read 1 convertion finished ADCREQ_x[6:0] $00 $00 $00 ADC Request select command Updated by SSM_RESET or SPI write to DIAGCTRL_x Measurement $00 Unused $01 Ground Ref $02 Full scale Ref $03 DCSx voltage $04 DCSx current $05 DCSx resistance $06 Squib x resistance $07 Internal BG reference voltage (BGR) $08 Internal BG monitor voltage (BGM) $09 Vcore $0A Temperature $0B DCS 0 voltage $0C DCS 1 voltage $0D DCS 2 voltage $0E DCS 3 voltage $0F DCS 4 voltage $10 DCS 5 voltage $11 DCS 6 voltage $12 DCS 7 voltage $13 DCS 8 voltage DocID029257 Rev 1 109/277 276 SPI interfaces L9680 $14 Vb voltage of ER ESR measure (valid only for ADCREQ_x field of MISO response when ESR measure results are available) $15 Va voltage of ER ESR measure (valid only for ADCREQ_x field of MISO response when ESR measure results are available) $16 Vc voltage of ER ESR measure (valid only for ADCREQ_x field of MISO response when ESR measure results are available) $20 VBATMON pin voltage $21 VIN pin voltage $22 Internal analog supply voltage (VINT) $23 Internal digital supply voltage (VDD) $24 ERBOOST pin voltage $25 SYNCBOOST pin voltage $26 VER pin voltage $27 SATBUCK voltage $28 VCC voltage $29 WAKEUP pin voltage $2A VSF pin voltage $2B WDTDIS pin voltage $2C GPOD0 pin voltage $2D GPOS0 pin voltage $2E GPOD1 pin voltage $2F GPOS1 pin voltage $30 GPOD2 pin voltage $31 GPOS2 pin voltage $32 RSU0 pin Voltage $33 RSU1 pin Voltage $34 RSU2 pin Voltage $35 RSU3 pin Voltage $36 SS0 pin voltage $37 SS1 pin voltage $38 SS2 pin voltage $39 SS3 pin voltage $3A SS4 pin voltage $3B SS5 pin voltage $3C SS6 pin voltage $3D SS7 pin voltage $3E SS8 pin voltage $3F SS9 pin voltage $40 SSA pin voltage $41 SSB pin voltage $46 SF0 $47 SF1 $48 SF2 $49 SF3 $4A SF4 $4B SF5 $4C SF6 $4D SF7 110/277 DocID029257 Rev 1 L9680 SPI interfaces $4E SF8 $4F SF9 $50 SFA $51 SFB ADCRES_x[9:0] $000 $000 $000 10-bit ADC result value corresponding to ADCREQ_x request Updated by SSM_RESET or ADC state machine RW Read: 3F00 Write: 007E LOW_ERBST_ILIM_ERON SSM Type: WSM 3F POR ID: 0 - - 2 1 0 ERBST_PH_SEL[1:0] 3 ERBST_PH_SEL 4 SYBST_PH_SEL[1:0] 5 SYBST_PH_SEL 6 SATBCK_PH_SEL[1:0] ERBST_FORCE_F_SLOPE ERBST_FORCE_F_SLOPE 7 SATBCK_PH_SEL 8 VCCBCK_PH_SEL[1:0] 9 VCCBCK_PH_SEL 10 SYBST_FORCE_F_SLOPE SYBST_FORCE_F_SLOPE VCCBCK_LS_ON_DELAY 11 VCCBCK_LS_ON_DELAY 0 12 SATBCK_LS_ON_DELAY 0 13 SATBCK_LS_ON_DELAY 0 - 0 14 EN_SAT_GNDLOSS_DET 15 EN_SAT_GNDLOSS_DET MISO 16 EN_VCC_GNDLOSS_DET MOSI 17 EN_VCC_GNDLOSS_DET 18 LOW_ERBST_ILIM_ERON 19 SATBCK_FORCE_F_SLOPE SATBCK_FORCE_F_SLOPE Configuration register for switching regulators (SW_REGS_CONF) LOW_ERBST_ILIM_ERON 7.3.34 ERBoost current limitation behavior selection Updated by POR or SPI write 0 ERBoost current limitation is NOT reduced if ER Switch is activated 1 ERBoost current limitation is reduced if ER Switch is activated EN_VCC_GNDLOSS_DET 0 - - New VCC ground loss detection enable Updated by POR or SPI write 0 run time ground loss detection disabled 1 run time ground loss detection enabled EN_SAT_GNDLOSS_DET 0 - - New SAT ground loss detection enable Updated by POR or SPI write 0 run time ground loss detection disabled DocID029257 Rev 1 111/277 276 SPI interfaces L9680 1 run time ground loss detection enabled SATBCK_LS_ON_DELAY 0 - - SATBuck low side activation delay Updated by POR or SPI write 0 No delay is applied 1 Delay is applied VCCBCK_LS_ON_DELAY 0 - - SVCCBuck low side activation delay Updated by POR or SPI write 0 No delay is applied 1 Delay is applied SATBCK_FORCE_F_SLOPE 0 - - SatBuck fast slope selection Updated by POR or SPI write 0 Fast slope activation depends on VIN voltage 1 Fast slope is forced ON SYBST_FORCE_F_SLOPE 0 - - SyncBoost fast slope selection Updated by POR or SPI write 0 Fast slope activation depends on VIN voltage 1 Fast slope is forced ON ERBST_FORCE_F_SLOPE 0 - - ER Boost fast slope selection Updated by POR or SPI write 0 Fast slope activation depends on VIN voltage 1 Fast slope is forced ON VCCBCK_PH_SEL[1:0] 11 - - VCCBuck phase shifting selection (if switching frequency is different respect to another regulator, the phase shift between them is not guaranteed) Updated by POR or SPI write 00 0 ns switching ON shift respect to t0 01 125 ns switching ON shift respect to t0 10 250 ns switching ON shift respect to t0 11 375 ns switching ON shift respect to t0 SATBCK_PH_SEL[1:0] 10 - - SatBuck phase shifting selection (if switching frequency is different respect to another regulator, the phase shift between them is not guaranteed) Updated by POR or SPI write 00 0 ns switching ON shift respect to t0 01 125 ns switching ON shift respect to t0 10 250 ns switching ON shift respect to t0 11 375 ns switching ON shift respect to t0 112/277 DocID029257 Rev 1 L9680 SPI interfaces SYBST_PH_SEL[1:0] 01 - - SyncBoost phase shifting selection (if switching frequency is different respect to another regulator, the phase shift between them is not guaranteed) Updated by POR or SPI write 00 0 ns switching ON shift respect to t0 01 125 ns switching ON shift respect to t0 10 250 ns switching ON shift respect to t0 11 375 ns switching ON shift respect to t0 ERBST_PH_SEL[1:0] 00 - - ER Boost phase shifting selection (if switching frequency is different respect to another regulator, the phase shift between them is not guaranteed) Updated by POR or SPI write 00 0 ns switching ON shift respect to t0 01 125 ns switching ON shift respect to t0 10 250 ns switching ON shift respect to t0 11 375 ns switching ON shift respect to t0 18 MOSI MISO 17 16 - 0 0 0 RW Read: 4200 Write: 0084 GPOxLS 12 11 10 9 8 7 6 5 4 3 X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 0 0 0 0 0 SSM Type: 13 WSM 42 14 POR ID: 0 15 0 0 0 2 1 0 GPO0LSGPO0LS 19 GPO1LSGPO1LS Global configuration register for GPO driver function (GPOCR) GPO2LSGPO2LS 7.3.35 GPO driver configuration bit Updated by SSM_RESET or SPI write 0 High-side Driver configuration for GPOx (ER_BOOST_OK is required to enable GPO as HS) 1 Low-side Driver configuration for GPOx (ER_BOOST_OK is not required to enable GPO as LS) DocID029257 Rev 1 113/277 276 SPI interfaces 7.3.36 L9680 GPOx control register (GPOCTRLx) Channel 0 (GPOCTRL0) Channel 1 (GPOCTRL1) Channel 2 (GPOCTRL2) 19 18 MOSI MISO 17 16 0 0 0 0 15 14 13 12 11 10 9 8 7 6 X X X X X X X X X X GPOxPWM[5:0] 0 0 0 0 0 0 0 0 0 0 GPOxPWM[5:0] ID: 43 (GPOCTRL0) 44 (GPOCTRL1) 45 (GPOCTRL2) Type: RW Read: 4300 (GPOCTRL0) 4400 (GPOCTRL1) 4500 (GPOCTRL2) Write: 0086 (GPOCTRL0) 0088 (GPOCTRL1) 008A (GPOCTRL2) POR GPOxPWM WSM 5 3 2 SSM 000000 000000 000000 6 bit value for PWM% with scaling of 1.6% per count Updated by SSM_RESET or SPI write 114/277 4 DocID029257 Rev 1 1 0 L9680 SPI interfaces R Read: 4600 Write: - GPO2DISABLE 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X GPO2OFFOPN GPO2SHORT GPO1TEMP GPO1LIM GPO1ONOPN GPO1OFFOPN GPO1SHORT GPO0TEMP GPO0LIM GPO0ONOPN GPO0OFFOPN GPO0SHORT SSM Type: 13 WSM 46 14 POR ID: 0 15 1 1 1 GPO2LIM GPO1DISABLE MISO 16 GPO2DISABLE MOSI 17 GPO2TEMP 18 GPOS_NOT_CONF 19 GPO2ONOPN GPO fault status register (GPOFLTSR) GPO0DISABLE 7.3.37 GPO 2 disable state 0 GPO enable to work 1 GPO disabled due to thermal fault or configuration not received or ERBOOST not OK (only HS mode) GPO1DISABLE 1 1 1 GPO 1 disable state 0 GPO enable to work 1 GPO disabled due to thermal fault or configuration not received or ERBOOST not OK (only HS mode) GPO0DISABLE 1 1 1 GPO 0 disable state 0 GPO enable to work 1 GPO disabled due to thermal fault or configuration not received or ERBOOST not OK (only HS mode) GPOS_NOT_CONF 1 1 1 GPOs configuration status 0 GPOs configured (activation is permitted) 1 GPOs not yet configured (activation is denied) GPO2TEMP 0 0 0 GPO 2Thermal Fault Cleared as reported in GPO-Over Temp diagram, set by detection circuit 0 Fault not detected 1 Fault detected DocID029257 Rev 1 115/277 276 SPI interfaces GPO2LIM L9680 0 0 0 GPO 2 Current Limit Flag Cleared by SSM_RESET or SPI read, set by detection circuit while ON 0 Fault not detected 1 Fault detected GPO2ONOPN 0 0 0 GPO 2 Open Detection Cleared by SSM_RESET or SPI read, set by detection circuit while ON 0 Fault not detected 1 Fault detected GPO2OFFOPN 0 0 0 GPO 2 Open detection in OFF condition Cleared by SSM_RESET or SPI read, set by detection circuit while OFF 0 Fault not detected 1 Fault detected GPO2SHORT 0 0 0 GPO 2 Short Detection in OFF condition (short to battery in HS mode, short to ground in LS mode) Cleared by SSM_RESET or SPI read, set by detection circuit while OFF 0 Fault not detected 1 Fault detected GPO1TEMP 0 0 0 GPO 1 Thermal Fault Cleared as reported in GPO-Over Temp diagram, set by detection circuit 0 Fault not detected 1 Fault detected GPO1LIM 0 0 0 GPO 1 Current Limit Flag Cleared by SSM_RESET or SPI read, set by detection circuit while ON 0 Fault not detected 1 Fault detected GPO1ONOPN 0 0 0 GPO 1 Open Detection Cleared by SSM_RESET or SPI read, set by detection circuit while ON 0 Fault not detected 1 Fault detected GPO1OFFOPN 0 0 0 GPO 1 Open detection in OFF condition Cleared by SSM_RESET or SPI read, set by detection circuit while OFF 0 Fault not detected 1 Fault detected 116/277 DocID029257 Rev 1 L9680 SPI interfaces GPO1SHORT 0 0 0 GPO 1 Short Detection in OFF condition (short to battery in HS mode, short to ground in LS mode) Cleared by SSM_RESET or SPI read, set by detection circuit while OFF 0 Fault not detected 1 Fault detected GPO0TEMP 0 0 0 GPO 0 Thermal Fault Cleared as reported in GPO-Over Temp diagram, set by detection circuit 0 Fault not detected 1 Fault detected GPO0LIM 0 0 0 GPO 0 Current Limit Flag Cleared by SSM_RESET or SPI read, set by detection circuit while ON 0 Fault not detected 1 Fault detected GPO0ONOPN 0 0 0 GPO 0 Open Detection OK Cleared by SSM_RESET or SPI read, set by detection circuit while ON 0 Fault not detected 1 Fault detected GPO0OFFOPN 0 0 0 GPO 0 Open detection in OFF condition Cleared by SSM_RESET or SPI read, set by detection circuit while OFF 0 Fault not detected 1 Fault detected GPO0SHORT 0 0 0 GPO 0 Short Detection in OFF condition (short to battery in HS mode, short to ground in LS mode) Cleared by SSM_RESET or SPI read, set by detection circuit while OFF 0 Fault not detected 1 Fault detected DocID029257 Rev 1 117/277 276 SPI interfaces Wheel speed sensor test request register (WSS_TEST) 19 18 MOSI MISO 17 16 0 0 0 0 ID: 48 Type: RW Read: 4800 Write: 0090 POR WSSSEL [6:0] 15 14 13 12 11 10 9 X X X X X X X WSSSEL [6:0] X 0 0 0 0 0 0 0 WSSSEL [6:0] X WSM 8 7 6 5 4 1 0 000000 000000 000000 Wheel Speed Sensor Selection - code below uniquely selects one of the four WSx outputs to place a static output level on 0 0 0 WSx Output Test Value 1 Output for selected WSx set 'high' 0 Output for selected WSx set 'low' 118/277 2 SSM 1010011 WSS Test Mode for WS3 Output 1010101 WSS Test Mode for WS2 Output 1011001 WSS Test Mode for WS1 Output 1010110 WSS Test Mode for WS0 Output all other WSS Test Mode disabled WSSTP 3 WSSTPWSSTP 7.3.38 L9680 DocID029257 Rev 1 L9680 7.3.39 SPI interfaces PSI5/WSS configuration register for channel x (RSCRx) RW Read: 4A00 (RSCR0) 4B00 (RSCR1) 4C00 (RSCR2) 4D00 (RSCR3) Write: 0094 (RSCR0) 0096 (RSCR1) 0098 (RSCR2) 009B (RSCR3) 2 1 WSFILT[3:0] STS[3:0] 3 WSFILT[3:0] STS[3:0] 4 AVG/SSDIS 5 AVG/SSDIS 6 RSPTEN 7 RSPTEN 8 BLKTxSEL 9 SSM Type: 10 WSM 4A (RSCR0) 4B (RSCR1) 4C (RSCR2) 4D (RSCR3) POR ID: 11 BLKTxSEL 0 12 TSxDIS 0 13 TSxDIS 0 14 FIX_THRESH - 0 15 FIX_THRESH MISO 16 PERIOD_MEAS_DISABLEPERIOD_MEAS_DISABLE MOSI 17 REDUCED_RANGE 18 REDUCED_RANGE 19 BLOCK_CURR_IN_MSG BLOCK_CURR_IN_MSG PSI5/WSS configuration register for channel 0 (RSCR0) PSI5/WSS configuration register for channel 1 (RSCR1 PSI5/WSS configuration register for channel 2 (RSCR2) PSI5/WSS configuration register for channel 3 (RSCR3 0 0 Tracking speed of base and delta current 0 PSI5 configured channel REDUCED_RANGE 0 0 Fast tracking of Ibase if rx_sat_pre_filt is low; Slow tracking otherwise. Fast tracking of Idelta if rx_sat_pre_filt is high; Blocked otherwise. 1 Fast tracking of Ibase if current is less than (Ibase+(Idelta/4)); Slow tracking otherwise. Fast tracking of Idelta if current is higher than (top current -(Idelta/4)); Slow otherwise. DocID029257 Rev 1 119/277 276 SPI interfaces BLOCK_CURR_IN_MSG L9680 0 0 0 Tracking enable of base and delta current during message transmission 0 Ibase tracking is enabled during blanking and after start bits recognition. Idelta tracking is disabled during blanking and enabled after start bits recognition. 1 Ibase tracking is enabled during blanking and disabled after start bits recognition. Idelta tracking is disabled during blanking and enabled after start bits recognition PERIOD_MEAS_DISABLE 0 0 0 Disabling of start bits period measure to decode following bits 0 Period is measured 1 Period is not measured (default is used) FIX_THRESH 0 0 0 PSI5 selection of fixed or auto adaptive thresholds 0 auto adaptive threshold 1 fixed threshold (threshold is latched when this bit is set to high, we recommend to set this bit before enabling of the interface) TSxDIS 0 0 0 Time Slot Control Disable 0 Slot control enabled 1 Slot control disabled BLKTxSEL 0 0 0 Blanking Time Selection 0 Blanking time = 5ms 1 Blanking time = 10ms WSFILT[3:0] 0010 0010 0010 Wheel speed filter time selection RSPTEN 0 0 0 189k: 125k: (16+x)*Tosc (24+x)*Tosc Tosc=1/16MHz Pass Through mode Enable 0 Off 1 On AVG/SSDIS 0 0 0 Current average enable during message transmission 0 Off (base and delta work as configured with bits 12, 14, 15) 1 On: base is freezed during data message and during blanking time and delta is averaged during message (fcut of the filter=2500 Hz) while is freezed during blanking time. 120/277 DocID029257 Rev 1 L9680 SPI interfaces STSx[3:0] 0000 0000 0000 Sensor Type Selection 0000 Synchronous PSI5, parity, 8-bit, 125k (P8P-500/3L) 0001 Synchronous PSI5, parity, 8-bit, 189k (P8P-500/3H) 0010 Synchronous PSI5, parity, 10-bit, 125k (P10P-500/3L) 0011 Synchronous PSI5, parity, 10-bit, 189k (P10P-500/3H) 0100 unused (default automatically selected) 0101 unused (default automatically selected) 0110 unused (default automatically selected) 0111 unused (default automatically selected) 1000 NA 1001 NA 1010 NA 1011 NA 1100 unused (default automatically selected) 1101 unused (default automatically selected) 1110 unused (default automatically selected) 1111 unused (default automatically selected) Wheel speed configured channel REDUCED_RANGE 0 0 0 Tracking speed of base and delta current X NA BLOCK_CURR_IN_MSG 0 0 0 Tracking enable of base and delta current during message transmission X NA PERIOD_MEAS_DISABLE 0 0 0 Disabling of start bits period measure to decode following bits X NA FIX_THRESH 0 0 0 PSI5 selection of fixed or auto adaptive thresholds 0 auto adaptive threshold 1 fixed thresholds (configured through SPI registers) TSxDIS 0 0 0 Time Slot Control Disable X NA BLKTxSEL 0 0 0 Blanking Time Selection X NA WSFILT[3:0] 0010 0010 0010 Wheel speed filter time selection (500ns per bit) 0000 8 us - - - - 500ns/bit 1111 15.5μs: DocID029257 Rev 1 121/277 276 SPI interfaces RSPTEN L9680 0 0 0 Pass Through mode Enable (only for PWM 2-edges sensors) 0 Off 1 On AVG/SSDIS 0 0 0 WSx output pulses disabled in case of Standstill condition (valid only for PWM Encoded 2 edges sensors) 0 WSx enabled during Standstill 1 WSx disabled during Standstill STSx[3:0] 0000 0000 0000 Sensor Type Selection 0000 NA 0001 NA 0010 NA 0011 NA 0100 unused (default automatically selected) 0101 unused (default automatically selected) 0110 unused (default automatically selected) 0111 unused (default automatically selected) 1000 Two-Level, Standard 1001 Three-Level, VDA 1010 PWM Encoded, 2-Level, 2 edges/tooth 1011 PWM Encoded, 2-Level, 1 edge/tooth 1100 unused (default automatically selected) 1101 unused (default automatically selected) 1110 unused (default automatically selected) 1111 unused (default automatically selected) 122/277 DocID029257 Rev 1 L9680 0 0 R/W Read: 4E00 Write: 009C CHxEN 10 9 8 X X X X X X X X 0 0 0 0 0 0 0 0 SSM Type: 11 WSM 4E 12 POR ID: 0 13 0 0 0 7 6 5 4 3 2 1 0 SYNC0ESYNC0E 0 14 CH0EN CH0EN - 15 SYNC1ESYNC1E MISO 16 CH1EN CH1EN MOSI 17 SYNC2ESYNC2E 18 CH2EN CH2EN 19 SYNC3ESYNC3E Remote sensor control register (RSCTRL) CH3EN CH3EN 7.3.40 SPI interfaces Channel x Output enable Updated by SSM_RESET or SPI write 0 Off 1 On SYNCxEN 0 0 0 Channel x Sync Pulse Enable 0 Off 1 On DocID029257 Rev 1 123/277 276 SPI interfaces WSS Threshold configuration register 1 (RS_AUX_CONF1) 18 0 0 0 0 - 64 Type: R/W Read: 6400 Write: 00C8 POR ID: WSS_LOW_THRESH [7:0] 7.3.42 13 12 11 10 9 8 7 6 5 4 3 2 X X X X X X X X WSS_LOW_THRESH [7:0] 0 0 0 0 0 0 0 0 WSS_LOW_THRESH [7:0] 1 0 $33 $33 $33 Low threshold setting in case of fixed threshold is selected (93,75 μA +/-9% each LSB). Low threshold = ($36+WSS_LOW_THRESH)*93,75 μA) 18 MOSI 17 16 0 0 0 65 Type: R/W Read: 6500 Write: 00CB POR ID: WSS_LOW_THRESH [7:0] 124/277 14 WSS Threshold configuration register 2 (RS_AUX_CONF2) 19 MISO 15 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 X X X X X X X X WSS_LOW_THRESH [7:0] 0 0 0 0 0 0 0 0 WSS_LOW_THRESH [7:0] 1 0 SSM MISO 16 WSM MOSI 17 SSM 19 WSM 7.3.41 L9680 $34 $34 $34 Delta threshold setting in case of fixed threshold is selected (93,75 μA +/-9% each LSB). High threshold = ($6C+WSS_LOW_THRESH+WSS_OFFSET_THRESH)*93,75 μA) DocID029257 Rev 1 L9680 Safing algorithm configuration register (SAF_ALGO_CONF) - 0 0 0 R/W Read: 6600 Write: 00CC NO_DATA SSM Type: WSM 66 14 POR ID: 0 15 0 0 0 X 0 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ADD_VAL ADD_VAL MISO 16 SUB_VAL SUB_VAL MOSI 17 ARMP_TH ARMP_TH 18 ARMN_THARMN_TH 19 NO_DATA NO_DATA 7.3.43 SPI interfaces Event counter no data select Updated by SSM_RESET or SPI write while in DIAG state 0 Event counter reset to 0 if CC=0 or (ABS value of response > limit determined by LIM_SELx) and LIM_ENx=1 when SPI read of SAF_CC bit is performed (end of sample cycle) 1 Event counter decremented by SUB_VAL if CC=0 or (ABS value of response > limit determined by LIM_SELx) and LIM_ENx=1 when SPI read of SAF_CC bit is performed (end of sample cycle) ARMN_TH 0011 0011 0011 Negative event counter threshold to assert arming Updated by SSM_RESET or SPI write while in DIAG state 0000 Negative event counter disabled ARMP_TH 0011 0011 0011 Positive event counter threshold to assert arming Updated by SSM_RESET or SPI write while in DIAG state 0000 Positive event counter disabled SUB_VAL 011 011 011 Decremental step size of the event counter Updated by SSM_RESET or SPI write while in DIAG state ADD_VAL 001 001 001 Incremental step size of the event counter Updated by SSM_RESET or SPI write while in DIAG state DocID029257 Rev 1 125/277 276 SPI interfaces 0 0 R Read: 6A00 Write: - ARMINT_x 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 SSM Type: 11 WSM 6A 12 POR ID: 0 13 ARMINT_1 0 14 ARMINT2 - 15 ARMINT_3 MISO 16 ARMINT_4 MOSI 17 ACL_VALID 18 ACL_PIN_STATE 19 PSINH_EXP_TIME Arming signals register (ARM_STATE) PSINHINT 7.3.44 L9680 - - - State of armint signals Updated per Safing Engine output logic diagram in case of internal safing engine otherwise is the echo of ARMx pins ACL_VALID 0 0 0 Valid ACL detection 0 Cleared when ACL_BAD=2 1 Set when ACL_GOOD=3 ACL_PIN_STATE - - - Echo of ACL pin PSINH_EXP_TIME 0 0 0 State of PSINH expiration timer 0 If timer is 0 1 If timer is counting PSINHINT - - - State of PSINHINT signal Updated per PSINH output logic diagram in case of internal engine otherwise is the echo of PSINH pin inverted 126/277 DocID029257 Rev 1 L9680 7.3.45 SPI interfaces ARMx assignment registers to specific Loops (LOOP_MATRIX_ARMx) X 0 0 0 0 8 7 6 5 4 3 2 1 0 ARMx_L0 ARMx_L0 X 9 ARMx_L1 ARMx_L1 X 10 ARMx_L2 ARMx_L2 0 X 11 ARMx_L3 ARMx_L3 0 12 ARMx_L4 ARMx_L4 0 13 ARMx_L5 ARMx_L5 0 14 ARMx_L6 ARMx_L6 - 15 ARMx_L7 ARMx_L7 MISO 16 ARMx_L8 ARMx_L8 MOSI 17 ARMx_L9 ARMx_L9 18 ARMx_LA ARMx_LA 19 ARMx_LB ARMx_LB Assignment of ARM1 to specific loops (LOOP_MATRIX_ARM1) Assignment of ARM2 to specific loops (LOOP_MATRIX_ARM2) Assignment of ARM3 to specific loops (LOOP_MATRIX_ARM3) Assignment of ARM4 to specific loops (LOOP_MATRIX_ARM4) RW Read: 6E00 (LOOP_MATRIX_ARM1) 6F00 (LOOP_MATRIX_ARM2) 7000 (LOOP_MATRIX_ARM3) 7100 (LOOP_MATRIX_ARM4) Write: 00DC (LOOP_MATRIX_ARM1) 00DE (LOOP_MATRIX_ARM2) 00E0 (LOOP_MATRIX_ARM3) 00E2 (LOOP_MATRIX_ARM4) ARMx_Ly SSM Type: WSM 6E (LOOP_MATRIX_ARM1) 6F (LOOP_MATRIX_ARM2) 70 (LOOP_MATRIX_ARM3) 71 (LOOP_MATRIX_ARM4) POR ID: 0 0 0 Configures ARMx for Loop_y Updated by SSM_RESET or SPI write while in DIAG state 0 ARMx signal is not associated with Loopy 1 ARMx signal is associated with Loopy DocID029257 Rev 1 127/277 276 SPI interfaces 7.3.46 L9680 ARMx enable pulse stretch timer status (AEPSTS_ARMx) ARM1 enable pulse stretch timer status (AEPSTS_ARM1) ARM2 enable pulse stretch timer status (AEPSTS_ARM2) ARM3 enable pulse stretch timer status (AEPSTS_ARM3) ARM4 enable pulse stretch timer status (AEPSTS_ARM4) 19 18 MOSI MISO 17 16 0 0 0 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 R Read: 7300 (AEPSTS_ARM1) 7400 (AEPSTS_ARM2) 7500 (AEPSTS_ARM3) 7600 (AEPSTS_ARM4) Write: SSM Type: WSM 73 (AEPSTS_ARM1) 74 (AEPSTS_ARM2) 75 (AEPSTS_ARM3) 76 (AEPSTS_ARM4) POR ID: Timer Count[9:0] Timer Count $000 $000 $000 10-bit ARMing Enable Pulse Stretcher timer value Cleared by SSM_RESET Loaded with initial value based on ARMx bit and DWELL[1:0] of SAF_CONTROL_y while safing is met for record y provided current value is < DWELL[1:0] value Decremented every 2ms while > 0 Contains remaining pulse stretcher timer value 128/277 DocID029257 Rev 1 L9680 Passenger inhibit upper threshold for DC sensor 0 (PADTHRESH_HI) 18 0 0 MOSI MISO 17 16 0 0 - 78 Type: RW Read: 7800 Write: 00F0 POR ID: 15 14 13 12 11 10 9 8 7 6 5 4 3 X X X X X X PADTHRESH_HI 0 0 0 0 0 0 PADTHRESH_HI 2 1 0 SSM 19 WSM 7.3.47 SPI interfaces PADTHRESH_HI $000 $000 $000 Upper threshold - measurements above this upper value will assert the PSINH signal and deactivate loops identified in the PSINH mask Passenger inhibit lower threshold for DC sensor 0 (PADTHRESH_LO) 18 MISO 17 16 0 0 0 79 Type: RW Read: 7900 Write: 00F2 POR ID: 0 15 14 13 12 11 10 X X X X X X 9 8 7 6 PADTHRESH_LO 5 4 3 0 0 0 0 0 0 PADTHRESH_LO 2 1 0 SSM 19 MOSI WSM 7.3.48 PADTHRESH_LO $3FF $3FF $3FF Lower threshold - measurements below this lower value will assert the PSINH signal and deactivate loops identified in the PSINH mask DocID029257 Rev 1 129/277 276 SPI interfaces PSINH_L7 PSINH_L7 PSINH_L6 PSINH_L6 PSINH_L5 PSINH_L5 PSINH_L0 PSINH_L0 0 12 11 10 9 8 7 6 5 4 3 2 1 0 EN_SAF1 EN_SAF1 1 PSINH_L1 PSINH_L1 2 EN_SAF2 EN_SAF2 0 3 PSINH_L2 PSINH_L2 0 4 EN_SAF3 EN_SAF3 0 5 PSINH_L3 PSINH_L3 PSINH_Ly 6 EN_SAF4 EN_SAF4 00F4 0 7 PSINH_L4 PSINH_L4 Write: 0 8 EN_SAF5 EN_SAF5 7A00 0 9 EN_SAF6 EN_SAF6 Read: 0 10 EN_SAF7 EN_SAF7 RW X SSM Type: X WSM 7A X POR ID: 0 X 11 EN_SAF8 EN_SAF8 0 12 PSINH_L8 PSINH_L8 0 13 EN_SAF9 EN_SAF9 0 14 PSINH_L9 PSINH_L9 - 15 EN_SAF10EN_SAF10 MISO 16 EN_SAF11 EN_SAF11 MOSI 17 PSINH_LBPSINH_LB 18 EN_SAF12EN_SAF12 19 PSINH_LAPSINH_LA Assignment of PSINH signal to specific Loop(s) (LOOP_MATRIX_PSINH) EN_SAF13EN_SAF13 7.3.49 L9680 Configures PSINH for Loop_y 0 PSINH signal is not associated with Loopy 1 PSINH signal is associated with Loopy Safing records enable register (SAF_ENABLE) MOSI MISO 17 16 0 0 - 0 0 RW Read: 7F00 Write: 00FE EN_SAFx SSM Type: WSM 7F 14 POR ID: 15 0 0 0 13 EN_SAF14EN_SAF14 18 EN_SAF15EN_SAF15 19 EN_SAF16EN_SAF16 7.3.50 Safing Record enable Updated by SSM_RESET or SPI write 0 Disable 1 Enable 130/277 DocID029257 Rev 1 L9680 7.3.51 SPI interfaces Safing records request mask registers (SAF_REQ_MASK_x) Safing record request mask for record 1 (SAF_REQ_MASK_1) Safing record request mask for record 2 (SAF_REQ_MASK_2) Safing record request mask for record 3 (SAF_REQ_MASK_3) Safing record request mask for record 4 (SAF_REQ_MASK_4) Safing record request mask for record 5 (SAF_REQ_MASK_5) Safing record request mask for record 6 (SAF_REQ_MASK_6) Safing record request mask for record 7 (SAF_REQ_MASK_7) Safing record request mask for record 8 (SAF_REQ_MASK_8) Safing record request mask for record 9 (SAF_REQ_MASK_9) Safing record request mask for record 10 (SAF_REQ_MASK_10) Safing record request mask for record 11 (SAF_REQ_MASK_11) Safing record request mask for record 12 (SAF_REQ_MASK_12) Safing record request mask for record 13 (SAF_REQ_MASK_13) Safing record request mask for record 14_pt1 (SAF_REQ_MASK_14)_pt1 Safing record request mask for record 14_pt2 (SAF_REQ_MASK_14)_pt2 Safing record request mask for record 15_pt1 (SAF_REQ_MASK_15)_pt1 Safing record request mask for record 15_pt2 (SAF_REQ_MASK_15)_pt2 Safing record request mask for record 16_pt1 (SAF_REQ_MASK_16)_pt1 Safing record request mask for record 16_pt2 (SAF_REQ_MASK_16)_pt2 19 18 MOSI MISO 17 16 15 14 13 12 11 0 0 10 9 8 7 6 5 4 3 2 1 0 SAF_REQ_MASKx[15:0] 0 0 SAF_REQ_MASKx[15:0] ID: 80 (SAF_REQ_MASK_1) 81 (SAF_REQ_MASK_2) 82 (SAF_REQ_MASK_3) 83 (SAF_REQ_MASK_4) 84 (SAF_REQ_MASK_5) 85 (SAF_REQ_MASK_6) 86 (SAF_REQ_MASK_7) 87 (SAF_REQ_MASK_8) 88 (SAF_REQ_MASK_9) 89 (SAF_REQ_MASK_10) 8A (SAF_REQ_MASK_11) 8B (SAF_REQ_MASK_12) 8C (SAF_REQ_MASK_13) 8D (SAF_REQ_MASK_14_pt1 8E (SAF_REQ_MASK_14_pt2) 8F (SAF_REQ_MASK_15_pt1) 90 (SAF_REQ_MASK_15_pt2) 91 (SAF_REQ_MASK_16_pt1) 92 (SAF_REQ_MASK_16_pt2) Type: RW Read: 8000 (SAF_REQ_MASK_1) 8100 (SAF_REQ_MASK_2) DocID029257 Rev 1 131/277 276 SPI interfaces L9680 8200 (SAF_REQ_MASK_3) 8300 (SAF_REQ_MASK_4) 8400 (SAF_REQ_MASK_5) 8500 (SAF_REQ_MASK_6) 8600 (SAF_REQ_MASK_7) 8700 (SAF_REQ_MASK_8) 8800 (SAF_REQ_MASK_9) 8900 (SAF_REQ_MASK_10) 8A00 (SAF_REQ_MASK_11) 8B00 (SAF_REQ_MASK_12) 8C00 (SAF_REQ_MASK_13) 8D00 (SAF_REQ_MASK_14_pt1 8E00 (SAF_REQ_MASK_14_pt2) 8F00 (SAF_REQ_MASK_15_pt1) 9000 (SAF_REQ_MASK_15_pt2) 9100 (SAF_REQ_MASK_16_pt1) 9200 (SAF_REQ_MASK_16_pt2) SSM WSM 8000 (SAF_REQ_MASK_1) 8002 (SAF_REQ_MASK_2) 8004 (SAF_REQ_MASK_3) 8006 (SAF_REQ_MASK_4) 8008 (SAF_REQ_MASK_5) 800A (SAF_REQ_MASK_6) 800C (SAF_REQ_MASK_7) 800E (SAF_REQ_MASK_8) 8010 (SAF_REQ_MASK_9) 8012 (SAF_REQ_MASK_10) 8014 (SAF_REQ_MASK_11) 8016 (SAF_REQ_MASK_12) 8018 (SAF_REQ_MASK_13) 801A (SAF_REQ_MASK_14_pt1 801C (SAF_REQ_MASK_14_pt2) 801E (SAF_REQ_MASK_15_pt1) 8020 (SAF_REQ_MASK_15_pt2) 8022 (SAF_REQ_MASK_16_pt1) 8424 (SAF_REQ_MASK_16_pt2) POR Write: SAF_REQ_MASKx[15:0] $0000 $0000 $0000 Safing Request Mask for safing record x - 16-bit request mask that is bitwise ANDed with MOSI data from SPI monitor Updated by SSM_RESET or SPI write while in DIAG state 132/277 DocID029257 Rev 1 L9680 7.3.52 SPI interfaces Safing records request target registers (SAF_REQ_TARGET_x) Safing record request mask for record 1 (SAF_REQ_TARGET_1) Safing record request mask for record 2 (SAF_REQ_TARGET_2) Safing record request mask for record 3 (SAF_REQ_TARGET_3) Safing record request mask for record 4 (SAF_REQ_TARGET_4) Safing record request mask for record 5 (SAF_REQ_TARGET_5) Safing record request mask for record 6 (SAF_REQ_TARGET_6) Safing record request mask for record 7 (SAF_REQ_TARGET_7) Safing record request mask for record 8 (SAF_REQ_TARGET_8) Safing record request mask for record 9 (SAF_REQ_TARGET_9) Safing record request mask for record 10 (SAF_REQ_TARGET_10) Safing record request mask for record 11 (SAF_REQ_TARGET_11) Safing record request mask for record 12 (SAF_REQ_TARGET_12) Safing record request mask for record 13 (SAF_REQ_TARGET_13) Safing record request mask for record 14_pt1 (SAF_REQ_TARGET_14)_pt1 Safing record request mask for record 14_pt2 (SAF_REQ_TARGET_14)_pt2 Safing record request mask for record 15_pt1 (SAF_REQ_TARGET_15)_pt1 Safing record request mask for record 15_pt2 (SAF_REQ_TARGET_15)_pt2 Safing record request mask for record 16_pt1 (SAF_REQ_TARGET_16)_pt1 Safing record request mask for record 16_pt2 (SAF_REQ_TARGET_16)_pt2 19 18 MOSI MISO 17 16 15 14 13 12 11 0 0 10 9 8 7 6 5 4 3 2 1 0 SAF_REQ_TARGET[15:0] 0 0 SAF_REQ_TARGET[15:0] ID: 93 (SAF_REQ_TARGET_1) 94 (SAF_REQ_TARGET_2) 95 (SAF_REQ_TARGET_3) 96 (SAF_REQ_TARGET_4) 97 (SAF_REQ_TARGET_5) 98 (SAF_REQ_TARGET_6) 99 (SAF_REQ_TARGET_7) 9A (SAF_REQ_TARGET_8) 9B (SAF_REQ_TARGET_9) 9C (SAF_REQ_TARGET_10) 9D (SAF_REQ_TARGET_11) 9E (SAF_REQ_TARGET_12) 9F (SAF_REQ_TARGET_13) A0 (SAF_REQ_TARGET_14_pt1 A1 (SAF_REQ_TARGET_14_pt2) A2 (SAF_REQ_TARGET_15_pt1) A3 (SAF_REQ_TARGET_15_pt2) A4 (SAF_REQ_TARGET_16_pt1) A5 (SAF_REQ_TARGET_16_pt2) Type: RW Read: 9300 (SAF_REQ_TARGET_1) 9400 (SAF_REQ_TARGET_2) DocID029257 Rev 1 133/277 276 SPI interfaces L9680 9500 (SAF_REQ_TARGET_3) 9600 (SAF_REQ_TARGET_4) 9700 (SAF_REQ_TARGET_5) 9800 (SAF_REQ_TARGET_6) 9900 (SAF_REQ_TARGET_7) 9A00 (SAF_REQ_TARGET_8) 9B00 (SAF_REQ_TARGET_9) 9C00 (SAF_REQ_TARGET_10) 9D00 (SAF_REQ_TARGET_11) 9E00 (SAF_REQ_TARGET_12) 9F00 (SAF_REQ_TARGET_13) A000 (SAF_REQ_TARGET_14_pt1 A100 (SAF_REQ_TARGET_14_pt2) A200 (SAF_REQ_TARGET_15_pt1) A300 (SAF_REQ_TARGET_15_pt2) A400 (SAF_REQ_TARGET_16_pt1) A500 (SAF_REQ_TARGET_16_pt2) SSM WSM 8026 (SAF_REQ_TARGET_1) 8028 (SAF_REQ_TARGET_2) 802A (SAF_REQ_TARGET_3) 802C (SAF_REQ_TARGET_4) 802E (SAF_REQ_TARGET_5) 8030 (SAF_REQ_TARGET_6) 8032 (SAF_REQ_TARGET_7) 8034 (SAF_REQ_TARGET_8) 8036 (SAF_REQ_TARGET_9) 8038 (SAF_REQ_TARGET_10) 803A (SAF_REQ_TARGET_11) 803C (SAF_REQ_TARGET_12) 803E (SAF_REQ_TARGET_13) 8040 (SAF_REQ_TARGET_14_pt1 8042 (SAF_REQ_TARGET_14_pt2) 8044 (SAF_REQ_TARGET_15_pt1) 8246 (SAF_REQ_TARGET_15_pt2) 8048 (SAF_REQ_TARGET_16_pt1) 804A (SAF_REQ_TARGET_16_pt2) POR Write: SAF_REQ_TARGET[15:0 $0000 $0000 $0000 Safing Request target for safing record x - 16-bit request target that is compared to the bit-wise AND result of the SAF_REQ_MASKx and MOSI data from SPI monitor Updated by SSM_RESET or SPI write while in DIAG state 134/277 DocID029257 Rev 1 L9680 7.3.53 SPI interfaces Safing records response mask registers (SAF_RESP_MASK_x) Safing record response mask for record 1 (SAF_RESP_MASK_1) Safing record response mask for record 2 (SAF_RESP_MASK_2) Safing record response mask for record 3 (SAF_RESP_MASK_3) Safing record response mask for record 4 (SAF_RESP_MASK_4) Safing record response mask for record 5 (SAF_RESP_MASK_5) Safing record response mask for record 6 (SAF_RESP_MASK_6 Safing record response mask for record 7 (SAF_RESP_MASK_7)) Safing record response mask for record 8 (SAF_RESP_MASK_8) Safing record response mask for record 9 (SAF_RESP_MASK_9) Safing record response mask for record 10 (SAF_RESP_MASK_10) Safing record response mask for record 11 (SAF_RESP_MASK_11) Safing record response mask for record 12 (SAF_RESP_MASK_12) Safing record response mask for record 13 (SAF_RESP_MASK_13) Safing record response mask for record 14_pt1 (SAF_RESP_MASK_14_pt1) Safing record response mask for record 14_pt2 (SAF_RESP_MASK_14_pt2) Safing record response mask for record 15_pt1 (SAF_RESP_MASK_15_pt1) Safing record response mask for record 15_pt2 (SAF_RESP_MASK_14_pt2) Safing record response mask for record 16_pt1 (SAF_RESP_MASK_16_pt1) Safing record response mask for record 16_pt2 (SAF_RESP_MASK_16_pt2) 19 18 MOSI MISO ID: 17 16 15 14 13 12 11 0 0 10 9 8 7 6 5 4 3 2 1 0 SAF_RESP_MASKx[15:0] 0 0 SAF_RESP_MASKx[15:0] A6 (SAF_RESP_MASK_1) A7 (SAF_RESP_MASK_2 A8 (SAF_RESP_MASK_3 A9 (SAF_RESP_MASK_4 AA (SAF_RESP_MASK_5 AB (SAF_RESP_MASK_6 AC (SAF_RESP_MASK_7 AD (SAF_RESP_MASK_8 AE (SAF_RESP_MASK_9 AF (SAF_RESP_MASK_10 B0 (SAF_RESP_MASK_11 B1 (SAF_RESP_MASK_12 B2 (SAF_RESP_MASK_13) B3 (SAF_RESP_MASK_14_pt1) B4 (SAF_RESP_MASK_14_pt2) B5 (SAF_RESP_MASK_15_pt1) B6 (SAF_RESP_MASK_15_pt2) DocID029257 Rev 1 135/277 276 SPI interfaces L9680 B7 (SAF_RESP_MASK_16_pt1 B8 (SAF_RESP_MASK_16_pt2 Type: RW Read: 804C (SAF_RESP_MASK_1) 804E (SAF_RESP_MASK_2 8050 (SAF_RESP_MASK_3 8052 (SAF_RESP_MASK_4 8054 (SAF_RESP_MASK_5 8056 (SAF_RESP_MASK_6 8058 (SAF_RESP_MASK_7 805A (SAF_RESP_MASK_8 805C (SAF_RESP_MASK_9 805E (SAF_RESP_MASK_10 8060 (SAF_RESP_MASK_11 8062 (SAF_RESP_MASK_12 8064 (SAF_RESP_MASK_13) 8066 (SAF_RESP_MASK_14_pt1) 8068 (SAF_RESP_MASK_14_pt2) 806A (SAF_RESP_MASK_15_pt1) 806C (SAF_RESP_MASK_15_pt2) 806E (SAF_RESP_MASK_16_pt1 8070 (SAF_RESP_MASK_16_pt2 SSM Write: WSM A600 (SAF_RESP_MASK_1) A700 (SAF_RESP_MASK_2 A800 (SAF_RESP_MASK_3 A900 (SAF_RESP_MASK_4 AA00 (SAF_RESP_MASK_5 AB00 (SAF_RESP_MASK_6 AC00 (SAF_RESP_MASK_7 AD00 (SAF_RESP_MASK_8 AE00 (SAF_RESP_MASK_9 AF00 (SAF_RESP_MASK_10 B000 (SAF_RESP_MASK_11 B100 (SAF_RESP_MASK_12 B200 (SAF_RESP_MASK_13) B300 (SAF_RESP_MASK_14_pt1) B400 (SAF_RESP_MASK_14_pt2) B500 (SAF_RESP_MASK_15_pt1) B600 (SAF_RESP_MASK_15_pt2) B700 (SAF_RESP_MASK_16_pt1 B801 (SAF_RESP_MASK_16_pt1 POR Read: SAF_RESP_MASKx[15:0] 0000 0000 0000 Safing Response Mask for safing record x - 16-bit response mask that is bit- wise ANDed with MISO data from SPI monitor 16-bit request target that is compared to the bit-wise AND result of the SAF_REQ_MASKx and MOSI data from SPI Updated by SSM_RESET or SPI write while in DIAG state 136/277 DocID029257 Rev 1 L9680 7.3.54 SPI interfaces Safing records response mask registers (SAF_RESP_TARGET_x) Safing record response target for record 1 (SAF_RESP_TARGET_1) Safing record response target for record 2 (SAF_RESP_TARGET_2) Safing record response target for record 3 (SAF_RESP_TARGET_3) Safing record response target for record 4 (SAF_RESP_TARGET_4) Safing record response target for record 5 (SAF_RESP_TARGET_5) Safing record response target for record 6 (SAF_RESP_TARGET_6) Safing record response target for record 7 (SAF_RESP_TARGET_7) Safing record response target for record 8 (SAF_RESP_TARGET_8) Safing record response target for record 9 (SAF_RESP_TARGET_9) Safing record response target for record 10 (SAF_RESP_TARGET_10) Safing record response target for record 11 (SAF_RESP_TARGET_11) Safing record response target for record 11 (SAF_RESP_TARGET_12) Safing record response target for record 13 (SAF_RESP_TARGET_13) Safing record response target for record 14_pt1 (SAF_RESP_TARGET_14)_pt1 Safing record response target for record 14_pt2 (SAF_RESP_TARGET_14)_pt2 Safing record response target for record 15_pt1 (SAF_RESP_TARGET_15)_pt1 Safing record response target for record 15_pt2 (SAF_RESP_TARGET_15)_pt2 Safing record response target for record 16_pt1 (SAF_RESP_TARGET_16)_pt1 Safing record response target for record 16_pt2 (SAF_RESP_TARGET_16)_pt2 19 18 MOSI MISO ID: 17 16 15 14 13 12 11 0 0 10 9 8 7 6 5 4 3 2 1 0 SAF_RESP_TARGETx[15:0] 0 0 SAF_RESP_TARGETx[15:0] B9 (SAF_RESP_TARGET_1) BA (SAF_RESP_TARGET_2 BB (SAF_RESP_TARGET_3 BC (SAF_RESP_TARGET_4 BD (SAF_RESP_TARGET_5 BE (SAF_RESP_TARGET_6 BF (SAF_RESP_TARGET_7 C0 (SAF_RESP_TARGET_8 C1 (SAF_RESP_TARGET_9 C2 (SAF_RESP_TARGET_10 C3 (SAF_RESP_TARGET_11 C4 (SAF_RESP_TARGET_12 C5 (SAF_RESP_TARGET_13 C6 (SAF_RESP_TARGET_14_pt1 C7 (SAF_RESP_TARGET_14_pt2 C8 (SAF_RESP_TARGET_15_pt1 C9 (SAF_RESP_TARGET_15_pt2 CA (SAF_RESP_TARGET_16_pt1 CB (SAF_RESP_TARGET_16_pt2 DocID029257 Rev 1 137/277 276 SPI interfaces L9680 B900 (SAF_RESP_TARGET_1) BA00 (SAF_RESP_TARGET_2 BB00 (SAF_RESP_TARGET_3 BC00 (SAF_RESP_TARGET_4 BD00 (SAF_RESP_TARGET_5 BE00 (SAF_RESP_TARGET_6 BF00 (SAF_RESP_TARGET_7 C000 (SAF_RESP_TARGET_8 C100 (SAF_RESP_TARGET_9 C200 (SAF_RESP_TARGET_10 C300 (SAF_RESP_TARGET_11 C400 (SAF_RESP_TARGET_12 C500 (SAF_RESP_TARGET_13 C600 (SAF_RESP_TARGET_14_pt1 C700 (SAF_RESP_TARGET_14_pt2 C800 (SAF_RESP_TARGET_15_pt1 C900 (SAF_RESP_TARGET_15_pt2 CA00 (SAF_RESP_TARGET_16_pt1 CB00 (SAF_RESP_TARGET_16_pt2) Write: 8072 (SAF_RESP_TARGET_1) 8074 (SAF_RESP_TARGET_2 8076 (SAF_RESP_TARGET_3 8078 (SAF_RESP_TARGET_4 807A (SAF_RESP_TARGET_5 807C (SAF_RESP_TARGET_6 807E (SAF_RESP_TARGET_7 8080 (SAF_RESP_TARGET_8 8082 (SAF_RESP_TARGET_9 8084 (SAF_RESP_TARGET_10 8086 (SAF_RESP_TARGET_11 8088 (SAF_RESP_TARGET_12 808A (SAF_RESP_TARGET_13 808C (SAF_RESP_TARGET_14_pt1 808E (SAF_RESP_TARGET_14_pt2 8090 (SAF_RESP_TARGET_15_pt1 8092 (SAF_RESP_TARGET_15_pt2 8094 (SAF_RESP_TARGET_16_pt1 CB00 (SAF_RESP_TARGET_16_pt2) SSM Read: WSM RW POR Type: SAF_RESP_TARGETx[15:0] 0000 0000 0000 Safing Response target for safing record x - 16-bit response target that is compared to the bit-wise AND result of the SAF_RESP_MASKx and MISO data from SPI monitor Updated by SSM_RESET or SPI write while in DIAG state 138/277 DocID029257 Rev 1 L9680 7.3.55 SPI interfaces Safing records data mask registers (SAF_DATA_MASK_x) Safing record data mask for record 1 (SAF_DATA_MASK_1) Safing record data mask for record 2 (SAF_DATA_MASK_2) Safing record data mask for record 3 (SAF_DATA_MASK_3) Safing record data mask for record 4 (SAF_DATA_MASK_4) Safing record data mask for record 5 (SAF_DATA_MASK_5) Safing record data mask for record 6 (SAF_DATA_MASK_6) Safing record data mask for record 7 (SAF_DATA_MASK_7) Safing record data mask for record 8 (SAF_DATA_MASK_8) Safing record data mask for record 9 (SAF_DATA_MASK_9) Safing record data mask for record 10 (SAF_DATA_MASK_10) Safing record data mask for record 11 (SAF_DATA_MASK_11) Safing record data mask for record 12 (SAF_DATA_MASK_12) Safing record data mask for record 13 (SAF_DATA_MASK_13) Safing record data mask for record 14 (SAF_DATA_MASK_14_pt1) Safing record data mask for record 14 (SAF_DATA_MASK_14_pt2) Safing record data mask for record 15 (SAF_DATA_MASK_15_pt1) Safing record data mask for record 15 (SAF_DATA_MASK_15_pt2) Safing record data mask for record 16 (SAF_DATA_MASK_16_pt1) Safing record data mask for record 16 (SAF_DATA_MASK_16_pt2) 19 18 MOSI MISO ID: 17 16 15 14 13 12 11 0 0 10 9 8 7 6 5 4 3 2 1 0 SAF_DATA_MASKx[15:0] 0 0 SAF_DATA_MASKx[15:0] CC (SAF_DATA_MASK_1) CD (SAF_DATA_MASK_2) CE (SAF_DATA_MASK_3) CF (SAF_DATA_MASK_4) D0 (SAF_DATA_MASK_5) D1 (SAF_DATA_MASK_6) D2 (SAF_DATA_MASK_7) D3 (SAF_DATA_MASK_8) D4 (SAF_DATA_MASK_9) D5 (SAF_DATA_MASK_10) D6 (SAF_DATA_MASK_11) D7 (SAF_DATA_MASK_12) D8 (SAF_DATA_MASK_13) D9 (SAF_DATA_MASK_14_pt1) DA (SAF_DATA_MASK_14_pt2) DB (SAF_DATA_MASK_15_pt1) DC (SAF_DATA_MASK_15_pt2) DocID029257 Rev 1 139/277 276 SPI interfaces L9680 DD (SAF_DATA_MASK_16_pt1) DE (SAF_DATA_MASK_16_pt2) CC00 (SAF_DATA_MASK_1) CD00 (SAF_DATA_MASK_2) CE00 (SAF_DATA_MASK_3) CF00 (SAF_DATA_MASK_4) D000 (SAF_DATA_MASK_5) D100 (SAF_DATA_MASK_6) D200 (SAF_DATA_MASK_7) D300 (SAF_DATA_MASK_8) D400 (SAF_DATA_MASK_9) D500 (SAF_DATA_MASK_10) D600 (SAF_DATA_MASK_11) D700 (SAF_DATA_MASK_12) D800 (SAF_DATA_MASK_13) D900 (SAF_DATA_MASK_14_pt1) DA00 (SAF_DATA_MASK_14_pt2) DB00 (SAF_DATA_MASK_15_pt1) DC00 (SAF_DATA_MASK_15_pt2) DD00 (SAF_DATA_MASK_16_pt1) DE00 (SAF_DATA_MASK_16_pt2) Write: 8099 (SAF_DATA_MASK_1) 809A (SAF_DATA_MASK_2) 809C (SAF_DATA_MASK_3) 809E (SAF_DATA_MASK_4) 80A0 (SAF_DATA_MASK_5) 80A2 (SAF_DATA_MASK_6) 80A4 (SAF_DATA_MASK_7) 80A6 (SAF_DATA_MASK_8) 80A8 (SAF_DATA_MASK_9) 80AA (SAF_DATA_MASK_10) 80AC (SAF_DATA_MASK_11) 80AE (SAF_DATA_MASK_12) 80B0 (SAF_DATA_MASK_13) 80B2 (SAF_DATA_MASK_14_pt1) 80B4 (SAF_DATA_MASK_14_pt2) 80B6 (SAF_DATA_MASK_15_pt1) 80B8 (SAF_DATA_MASK_15_pt2) 80BA (SAF_DATA_MASK_16_pt1) 80BC (SAF_DATA_MASK_16_pt2) SSM Read: WSM RW POR Type: SAF_DATA_MASKx[15:0] 0000 0000 0000 Safing Data Mask for safing record x - 16-bit data mask that is bit-wise ANDed with MISO data from SPI monitor Updated by SSM_RESET or SPI write while in DIAG state 140/277 DocID029257 Rev 1 L9680 7.3.56 SPI interfaces Safing record threshold registers (SAF_THRESHOLD_x) Safing record threshold for record 1 (SAF_THRESHOLD_1) Safing record threshold for record 2 (SAF_THRESHOLD_2) Safing record threshold for record 3 (SAF_THRESHOLD_3) Safing record threshold for record 4 (SAF_THRESHOLD_4) Safing record threshold for record 5 (SAF_THRESHOLD_5) Safing record threshold for record 6 (SAF_THRESHOLD_6) Safing record threshold for record 7 (SAF_THRESHOLD_7) Safing record threshold for record 8 (SAF_THRESHOLD_8) Safing record threshold for record 9 (SAF_THRESHOLD_9) Safing record threshold for record 10 (SAF_THRESHOLD_11) Safing record threshold for record 12 (SAF_THRESHOLD_12) Safing record threshold for record 13 (SAF_THRESHOLD_13) Safing record threshold for record 14 (SAF_THRESHOLD_14) Safing record threshold for record 15 (SAF_THRESHOLD_15) Safing record threshold for record 16 (SAF_THRESHOLD_16) 19 18 MOSI MISO 17 16 15 14 13 12 0 0 11 10 9 8 7 6 5 4 3 2 1 0 SAF_THRESHOLDx[15:0] 0 0 SAF_THRESHOLDx[15:0] ID: DF (SAF_THRESHOLD_1) E0 (SAF_THRESHOLD_2) E1 (SAF_THRESHOLD_3) E2 (SAF_THRESHOLD_4) E3 (SAF_THRESHOLD_5) E4 (SAF_THRESHOLD_6) E5 (SAF_THRESHOLD_7) E6 (SAF_THRESHOLD_8) E7 (SAF_THRESHOLD_9) E8 (SAF_THRESHOLD_10) E9 (SAF_THRESHOLD_11) EA (SAF_THRESHOLD_12) EB (SAF_THRESHOLD_13) EC (SAF_THRESHOLD_14) ED (SAF_THRESHOLD_15) EE (SAF_THRESHOLD_16) Type: RW Read: DF00 (SAF_THRESHOLD_1) E000 (SAF_THRESHOLD_2) E100 (SAF_THRESHOLD_3) E200 (SAF_THRESHOLD_4) E300 (SAF_THRESHOLD_5) E400 (SAF_THRESHOLD_6) E500 (SAF_THRESHOLD_7) E600 (SAF_THRESHOLD_8) DocID029257 Rev 1 141/277 276 SPI interfaces L9680 E700 (SAF_THRESHOLD_9) E800 (SAF_THRESHOLD_10) E900 (SAF_THRESHOLD_11) EA00 (SAF_THRESHOLD_12) EB00 (SAF_THRESHOLD_13) EC00 (SAF_THRESHOLD_14) ED00 (SAF_THRESHOLD_15) EE00 (SAF_THRESHOLD_16) SSM WSM 80BE (SAF_THRESHOLD_1) 80C0 (SAF_THRESHOLD_2) 80C2 (SAF_THRESHOLD_3) 80C4 (SAF_THRESHOLD_4) 80C6 (SAF_THRESHOLD_5) 80C8 (SAF_THRESHOLD_6) 80CA (SAF_THRESHOLD_7) 80CC (SAF_THRESHOLD_8) 80CE (SAF_THRESHOLD_9) 80D0 (SAF_THRESHOLD_10) 80D2 (SAF_THRESHOLD_11) 80D4 (SAF_THRESHOLD_12) 80D6 (SAF_THRESHOLD_13) 80D8 (SAF_THRESHOLD_14) 80DA (SAF_THRESHOLD_15) 80DB (SAF_THRESHOLD_16) POR Write: SAF_THRESHOLD_x $FFFF $FFFF $FFFF Safing threshold for safing record x - 16-bit threshold used for safing data comparison Updated by SSM_RESET or SPI write while in DIAG state 142/277 DocID029257 Rev 1 L9680 7.3.57 SPI interfaces Safing control x registers (SAF_CONTROL_x) ID: EF (SAF_CONTROL_1) F0 (SAF_CONTROL_2) F1 (SAF_CONTROL_3) F2 (SAF_CONTROL_4) F3 (SAF_CONTROL_5) F4 (SAF_CONTROL_6) F5 (SAF_CONTROL_7 F6 (SAF_CONTROL_8) F7 (SAF_CONTROL_9) F8 (SAF_CONTROL_10) F9 (SAF_CONTROL_11) FA (SAF_CONTROL_12) FB (SAF_CONTROL_13) FC (SAF_CONTROL_14) FD (SAF_CONTROL_15) FE (SAF_CONTROL_16) Type: RW Read: EF00 (SAF_CONTROL_1) F000 (SAF_CONTROL_2) F100 (SAF_CONTROL_3) DocID029257 Rev 1 5 4 ARM2x 3 2 1 0 ARM1x 6 CSx[2:0] IFx ARM1x 7 ARM2x 8 ARM3x 9 ARM3x ARMSELx 10 ARM4x 0 11 ARM4x 0 12 DWELLx[1:0] DWELLx[1:0] 0 ARMSELx 13 COMBx 0 14 COMBx - 15 LIM Enx MISO 16 LIM Enx MOSI 17 LIM SELx 18 SPIFLDSELx SPIFLDSELx 19 LIM SELx Safing control registers for record 1 (SAF_CONTROL_1) Safing control registers for record 2 (SAF_CONTROL_2) Safing control registers for record 3 (SAF_CONTROL_3) Safing control registers for record 4 (SAF_CONTROL_4) Safing control registers for record 5 (SAF_CONTROL_5) Safing control registers for record 6 (SAF_CONTROL_6) Safing control registers for record 7 (SAF_CONTROL_7) Safing control registers for record 8 (SAF_CONTROL_8) Safing control registers for record 9 (SAF_CONTROL_9) Safing control registers for record 10 (SAF_CONTROL_10) Safing control registers for record 11 (SAF_CONTROL_11) Safing control registers for record 12 (SAF_CONTROL_12) Safing control registers for record 13 (SAF_CONTROL_13) Safing control registers for record 14 (SAF_CONTROL_14) Safing control registers for record 15 (SAF_CONTROL_15) Safing control registers for record 16 (SAF_CONTROL_16) CSx[2:0] IFx 143/277 276 SPI interfaces L9680 F200 (SAF_CONTROL_4) F300 (SAF_CONTROL_5) F400 (SAF_CONTROL_6) F500 (SAF_CONTROL_7 F600 (SAF_CONTROL_8) F700 (SAF_CONTROL_9) F800 (SAF_CONTROL_10) F900 (SAF_CONTROL_11) FA00 (SAF_CONTROL_12) FB00 (SAF_CONTROL_13) FC00 (SAF_CONTROL_14) FD00 (SAF_CONTROL_15) FE00 (SAF_CONTROL_16) SSM ARMSELx WSM 80DE (SAF_CONTROL_1) 80E0 (SAF_CONTROL_2) 80E2 (SAF_CONTROL_3) 80E4 (SAF_CONTROL_4) 80E6 (SAF_CONTROL_5) 80E8 (SAF_CONTROL_6) 80EA (SAF_CONTROL_7 80EC (SAF_CONTROL_8) 80EE (SAF_CONTROL_9) 80F0 (SAF_CONTROL_10) 80F2 (SAF_CONTROL_11) 80F4 (SAF_CONTROL_12) 80F6 (SAF_CONTROL_13) 80F8 (SAF_CONTROL_14) 80FA (SAF_CONTROL_15) 80FC (SAF_CONTROL_16) POR Write: 00 00 00 ARMINT select for safing recode x - correlates A Updated by SSM_RESET or SPI write while in DIAG state 00 ARMP OR ARMN 01 ARMP 10 ARMN 11 ARMP OR ARMN SPIFLDSELx 0 0 0 SPI field select for safing record x - determines which 16-bit field in long SPI messages (>31 bit) to use for response on MISO of SPI monitor. In case of messages less than 32 bits this bit is don't care. Updated by SSM_RESET or SPI write while in DIAG state. Updated by SSM_RESET or SPI write while in DIAG state 0 First 16 bits of SPI MISO frame used for Response Mask and Data Mask bit-wise AND 1 Last 16 bits of SPI MISO frame used for Response Mask and Data Mask bit-wise AND 144/277 DocID029257 Rev 1 L9680 SPI interfaces LIM SELx 0 0 0 Data range limit select for safing record x - When enabled, determines the range limit used for incoming sensor data Updated by SSM_RESET or SPI write while in DIAG state 0 8-bit data range limit - incoming |data| >120d is not recognized as valid data 1 10-bit data range limit - incoming |data| > 480d is not recognized as valid data LIM Enx 0 0 0 Data range limit enable for safing record x Updated by SSM_RESET or SPI write while in DIAG state 0 Data range limit disabled 1 Data range limit enabled COMBx 0 0 0 Combine function enable for safing record x Updated by SSM_RESET or SPI write while in DIAG state 0 Combine function disabled 1 Combine function enabled For record pairs = x,x+1, the comparison for record x uses |data(x) + data(x+1)| and the comparison for record x+1 uses |data(x) data(x+1)| Record pairs are 1,2; 3,4; 5,6; 7,8; 9,10; 11,12 DWELLx[1:0] 00 00 00 Safing dwell extension time select for safing record x Updated by SSM_RESET or SPI write while in DIAG state 00 2048 ms 01 256 ms 10 32 ms 11 0 ms ARM4x 0 0 0 ARM4INT select for safing record x - correlates safing result to ARM4INT Updated by SSM_RESET or SPI write while in DIAG state 0 Safing record x not assigned to ARM4INT 1 Safing record x assigned to ARM4INT ARM3x 0 0 0 ARM3INT select for safing record x - correlates safing result to ARM3INT Updated by SSM_RESET or SPI write while in DIAG state 0 Safing record x not assigned to ARM3INT 1 Safing record x assigned to ARM3INT ARM2x 0 0 0 ARM2INT select for safing record x - correlates safing result to ARM2INT Updated by SSM_RESET or SPI write while in DIAG state 0 Safing record x not assigned to ARM2INT 1 Safing record x assigned to ARM2INT ARM1x 0 0 0 ARM1INT select for safing record x - correlates safing result to ARM1INT Updated by SSM_RESET or SPI write while in DIAG state DocID029257 Rev 1 145/277 276 SPI interfaces L9680 0 Safing record x not assigned to ARM1INT 1 Safing record x assigned to ARM1INT CSx[2:0] 000 000 SPI Monitor CS select for safing record x Updated by SSM_RESET or SPI write while in DIAG state 000 000 None selected for record x 001 SAF_CS0 selected for record x 010 SAF_CS1 selected for record x 011 SAF_CS2 selected for record x 100 SAF_CS3 selected for record x 101 CS_RS selected for record x 110 None selected for record x 111 None selected for record x IFx 0 0 0 SPI format select for safing record x - selects response protocol for SPI monitor Updated by SSM_RESET or SPI write while in DIAG state 0 Out of frame response for record x 1 In Frame response for record x R Read: FF00 Write: - CC_xx 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0CC_6 0CC_5 CC_4 CC_3 CC_2 CC_1 SSM Type: 9 WSM FF 10 POR ID: 0 11 0CC_7 0 12 0CC_8 0 13 0CC_9 0 14 0CC_10 - 15 0CC_11 MISO 16 0CC_12 MOSI 17 0 0 0 0CC_14 18 0CC_15 19 0CC_13 Safing record compare complete register (SAF_CC) 0CC_16 7.3.58 Indicates compare complete status of each of the 16 safing records, and defines the end of the sample cycle for safing Cleared by SSM_RESET or upon SPI read, set by safing engine when request, response mask and target registers match the incoming SPI frame 0 Compare not completed for record x 1 Compare completed for record x 146/277 DocID029257 Rev 1 L9680 SPI interfaces 7.4 Remote sensor SPI register map The Remote Sensor SPI interface consists of twelve 32-bit read registers (one for each logical channel) to allow for access to decoded sensor data and fault registers. The registers are addressed by the read register ID and the Global ID bit. The L9680 checks the validity of the received RID field in the MOSI_RS frame. Should a SPI read command be received containing an unused RID address, the command will be discarded and the ERR_RID bit will be flagged in the current GSW. Table 8. Remote sensor SPI register map Operating State GID RID / WID Hex R/W Name Description Init Diag Safing Scrap Arming 0 1 0 1 0 0 0 0 $50 R RSDR0 0 1 0 1 0 0 0 1 $51 R RSDR1 0 1 0 1 0 0 1 0 $52 R RSDR2 0 1 0 1 0 0 1 1 $53 R RSDR3 0 1 0 1 0 1 0 0 $54 R RSDR4 0 1 0 1 0 1 0 1 $55 R RSDR5 0 1 0 1 0 1 1 0 $56 R RSDR6 0 1 0 1 0 1 1 1 $57 R RSDR7 0 1 0 1 1 0 0 0 $58 R RSDR8 0 1 0 1 1 0 0 1 $59 R RSDR9 0 1 0 1 1 0 1 0 $5A R RSDR10 0 1 0 1 1 0 1 1 $5B R RSDR11 0 1 0 1 1 1 0 0 $5C R RSTHR0_L 0 1 0 1 1 1 0 1 $5D R RSTHR1_L 0 1 0 1 1 1 1 0 $5E R RSTHR2_L 0 1 0 1 1 1 1 1 $5F R RSTHR3_L 0 1 1 0 0 0 0 0 $60 R RSTHR0_H 0 1 1 0 0 0 0 1 $61 R RSTHR1_H 0 1 1 0 0 0 1 0 $62 R RSTHR2_H 0 1 1 0 0 0 1 1 $63 R RSTHR3_H 0 1 1 0 1 0 1 0 $6A R ARM_STATE Arming signals status register SAF_CC Safing record compare complete register 1 1 1 1 1 1 1 1 $FF R Remote sensor data/status registers (PSI-5 or WSS) Remote sensor (PSI-5 or WSS) Remote sensor current 2 registers (WSS only) DocID029257 Rev 1 147/277 276 SPI interfaces 7.5 L9680 Remote sensor SPI tables A summary of all the registers contained within the remote sensor SPI map are shown below and are referenced throughout the specification as they apply. The SPI register tables also specify the effect of the internal reset signals assertion on each bit field (the symbol ‘-‘is used to indicate that the register is not affected by the relevant reset signal’). 7.5.1 Remote sensor SPI global status word The Remote Sensor SPI of L9680 contains an 11-bit word that returns global status information. The Global Status Word (GSW) of the Remote Sensor SPI is the most significant 11 bits of MISO_RS data. Table 9. GSW - Remote sensor SPI global status word MISO_RS GSW Name POR WSM SSM Description SPI Fault, set if previous SPI frame had wrong parity check or wrong number of bits, cleared upon read ‘ 31 10 SPIFLT 0 0 0 0 No fault 1 Fault 30 9 0 0 0 0 Unused Remote Sensor Interface Fault Present, logical OR of the corresponding FLTBIT bits (bit 15) for all faults but NODATA 29 8 RSFLT 0 0 0 0 All the RSDRx-FLTBIT bits are 0 1 At least one of the RSDRx-FLTBIT bits is 1 and the associated fault code is different from NODATA 28 7 0 0 0 0 Unused 27 6 0 0 0 0 Unused 26 5 0 0 0 0 Unused 25 4 0 0 0 0 Unused 24 3 0 0 0 0 Unused 23 2 0 0 0 0 Unused 22 1 0 0 0 0 Unused 21 0 ERR_RI D Read address received in the actual SPI frame is unused so data in the response is don't care 0 0 0 0 No Error 1 Error 148/277 DocID029257 Rev 1 L9680 SPI interfaces 7.6 Remote sensor SPI read/write registers 7.6.1 Remote sensor data/fault registers (RSDRx @FLT = 0) PSI5/WSS Remote Sensor 0 Data and Fault Flag Register ch 0, slot 1 / ch 0 (RSDR0) PSI5/WSS Remote Sensor 1 Data and Fault Flag Register ch 1, slot 1 / ch 1 (RSDR1) PSI5/WSS Remote Sensor 2 Data and Fault Flag Register ch 2, slot 1 / ch 2 (RSDR2) PSI5/WSS Remote Sensor 3 Data and Fault Flag Register ch 3, slot 1 / ch 3 (RSDR3) PSI5 configuration register for channel 0, slot 2 (RSDR4) PSI5 configuration register for channel 1, slot 2 (RSDR5) PSI5 configuration register for channel 2, slot 2 (RSDR6) PSI5 configuration register for channel 3, slot 2 (RSDR7) PSI5 configuration register for channel 0, slot 2 (RSDR8) PSI5 configuration register for channel 1, slot 2 (RSDR9) PSI5 configuration register for channel 2, slot 2 (RSDR10) PSI5 configuration register for channel 3, slot 2 (RSDR11) 19 18 17 16 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x MISO_RS CRC 0 FLT=0 13 MISO_RS CRC FLT=0 14 STDSTL MOSI_RS 15 Latch_D0 On/Off Bit 15 = 0 NO FAULT Condition ID: 50 (RSDR0) 51 (RSDR1) 52 (RSDR2) 53 (RSDR3) 54 (RSDR4) 55 (RSDR5) 56 (RSDR6) 57 (RSDR7) 58 (RSDR8) 59 (RSDR9) 5A (RSDR10) 5B (RSDR11) Type: R Read: 5000 (RSDR0) 5100 (RSDR1) 5200 (RSDR2) 5300 (RSDR3) 5400 (RSDR4) 5500 (RSDR5) 5600 (RSDR6) LCID [3:0] LCID [1:0] DocID029257 Rev 1 DATA [9:0] DATA [11:0] 149/277 276 SPI interfaces L9680 5700 (RSDR7) 5800 (RSDR8) 5900 (RSDR9) 5A00 (RSDR10) 5B00 (RSDR11) WSM SSM POR Write: - - PSI5 configured channel CRC[2:0] - CRC based on bits [16:0] Updated based on bits [16:0] FLT 1 1 1 Fault Status - Depending on Fault Status, the DATA bits are defined differently Cleared when all of the following bits are '0': STG, STB, CURRENT_HI, OPENDET, RSTEMP, INVALID, SLOT_ERROR, NODATA Set when any of the following bits are '1': STG, STB, CURRENT_HI, OPENDET, RSTEMP, INVALID, SLOT_ERROR, NODATA 0 No fault 1 Fault On/Off 0 0 0 Channel On/Off Status Cleared by SSM_RESET or when channel is commanded OFF via SPI RSCTRL or when the STG bit is set or the RSTEMP bit is set Set when channel is commanded ON by SPI RSCTRL 0 Off 1 On LCID[3:0] - - - Logical Channel ID Updated based on SPI read request 0000 0001 0010 0100 0101 0110 1000 1001 1010 1100 1010 1110 RSU0 RSU0 RSU0 RSU1 RSU1 RSU1 RSU2 RSU2 RSU2 RSU3 RSU3 RSU3 SLOT1 SLOT2 SLOT3 SLOT1 SLOT2 SLOT3 SLOT1 SLOT2 SLOT3 SLOT1 SLOT2 SLOT3 DATA[9:0] $000 $000 $000 10-bit data from Manchester decoder 150/277 DocID029257 Rev 1 L9680 SPI interfaces Cleared by SSM_RESET or SPI read or when channel is commanded OFF via SPI RSCTRL updated when a valid PSI5 frame is received Wheel speed configured channel (RSDR0, RSDR1, RSDR2, RSDR3) CRC[2:0] - - - CRC based on bits [16:0] Updated based on bits [16:0] STDSTL 0 0 0 Standstill indication (valid only for VDA sensor or PWM 2 edges) 1 Standstill 0 Valid Sensor Signal FLT 1 1 1 Fault Status - Depending on Fault Status, the DATA bits are defined differently Cleared when all of the following bits are '0': STG, STB, CURRENT_HI, OPENDET, RSTEMP, INVALID, PULSE OVERFLOW ERROR, NODATA Set when any of the following bits are '1': STG, STB, CURRENT_HI, OPENDET, RSTEMP, INVALID, PULSE OVERFLOW ERROR, NODATA 0 No Fault 1 Fault Latch_D0 0 0 0 Logical Channel ID 0 no prior bit0 faults 1 prior message(s) contained bit0 fault LCID[1:0] Logical Channel ID 00 01 10 11 RSU0 RSU1 RSU2 RSU3 DATA[11:0] $000 $000 $000 12-bit data from wheel speed decoder VDA Data Format DATA [7:0] Counter bits DATA [11:8] Counter bits PWM Data Format DATA [8:0] Pulse Data bits DocID029257 Rev 1 151/277 276 SPI interfaces 7.6.2 L9680 Remote sensor data/fault registers w/o fault (RSDRx @ FLT=1) PSI5/WSS Remote Sensor 0 Data and Fault Flag Register ch 0, slot 1 / ch 0 (RSDR0) PSI5/WSS Remote Sensor 1 Data and Fault Flag Register ch 1, slot 1 / ch 1 (RSDR1) PSI5/WSS Remote Sensor 2 Data and Fault Flag Register ch 2, slot 1 / ch 2 (RSDR2) PSI5/WSS Remote Sensor 3 Data and Fault Flag Register ch 3, slot 1 / ch 3 (RSDR3) PSI5 configuration register for channel 0, slot 2 (RSDR4) PSI5 configuration register for channel 1, slot 2 (RSDR5) PSI5 configuration register for channel 2, slot 2 (RSDR6) PSI5 configuration register for channel 3, slot 2 (RSDR7) PSI5 configuration register for channel 0, slot 2 (RSDR8) PSI5 configuration register for channel 1, slot 2 (RSDR9) PSI5 configuration register for channel 2, slot 2 (RSDR10) PSI5 configuration register for channel 3, slot 2 (RSDR11) 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X INVALID NODATA X X INVALID NODATA X X MISO_RS (PSI5) CRC X MISO_RS (WSS) CRC X ID: 50 (RSDR0) 51 (RSDR1) 52 (RSDR2) 53 (RSDR3) 54 (RSDR4) 55 (RSDR5) 56 (RSDR6) 57 (RSDR7) 58 (RSDR8) 59 (RSDR9) 5A (RSDR10) 5B (RSDR11) Type: R Read: 5000 (RSDR0) 5100 (RSDR1) 5200 (RSDR2) 5300 (RSDR3) 5400 (RSDR4) 5500 (RSDR5) 5600 (RSDR6) 152/277 LCID [3:0] LCID [1:0] STG STB STG STB DocID029257 Rev 1 SLOT_ERROR SLOT_ERROR 11 On/Off 12 On/Off 13 FLT=1 - 14 RSTEMP 15 FLT=1 MOS_RSI 16 RSTEMP 17 OPENDET 18 CURRENT_HI CURRENT_HI 19 OPENDET Bit 15 = 1 FAULTED condition L9680 SPI interfaces 5700 (RSDR7) 5800 (RSDR8) 5900 (RSDR9) 5A00 (RSDR10) 5B00 (RSDR11) SSM CRC[2:0] WSM POR Write: - - - CRC based on bits [16:0] Updated based on bits [16:0] FLT 0 0 0 Fault Status Cleared when all of the following bits are '0': STG, STB, CURRENT_HI, OPENDET, RSTEMP, NODATA, INVALID, SLOT ERROR, PULSE OVERFLOW ERROR Set when any of the following bits are '1': STG, STB, CURRENT_HI, OPENDET, RSTEMP, NODATA, INVALID, SLOT ERROR, PULSE OVERFLOW ERROR 0 No fault 1 Fault On/Off 0 0 0 Channel On/Off Status Cleared by SSM_RESET or when channel is commanded OFF via SPI RSCTRL or when the STG bit is set or the RSTEMP bit is set Set when channel is commanded ON by SPI RSCTRL 0 Off 1 On LCID[0:3] 0000 0000 0000 Logical Channel ID Updated based on SPI read request 0000 RSU0 SLOT1 0001 RSU0 SLOT2 0010 RSU0 SLOT3 0100 RSU1 SLOT1 0101 RSU1 SLOT2 1 0110 RSU1 SLOT3 1000 RSU2 SLOT1 1001 RSU2 SLOT2 1010 RSU2 SLOT3 1100 RSU3 SLOT1 1101 RSU3 SLOT2 1110 RSU3 SLOT3 DocID029257 Rev 1 153/277 276 SPI interfaces STG L9680 0 0 0 Short to Ground (in current limit condition) Cleared by SSM_RESET or when channel is commanded OFF via SPI RSCTRL 0 No fault 1 Fault STB 0 0 0 Short to Battery Cleared by SSM_RESET or SPI read or when channel is commanded OFF via SPI RSCTRL - not cleared by channel OFF caused by STG or RSTEMP Set when channel voltage exceeds VSUP for a time greater than TSTBTH 0 No fault 1 Fault CURRENT_HI 0 0 0 Current High Cleared by SSM_RESET or SPI read or when channel is commanded OFF via SPI RSCTRL Set when channel current exceeds ILKGG for a time determined by an up/down counter 0 No fault 1 Fault OPENDET 0 0 0 Open Sensor Detected Cleared by SSM_RESET or SPI read or when channel is commanded OFF via SPI RSCTRL Set when channel current exceeds ILKGB for a time determined by an up/down counter 0 No fault 1 Fault RSTEMP 0 0 0 Over temperature detected Cleared by SSM_RESET or when channel is commanded OFF via SPI RSCTRL Set when over-temp condition is detected 0 No fault 1 Fault INVALID 154/277 0 0 0 Invalid Data DocID029257 Rev 1 L9680 SPI interfaces Cleared by SSM_RESET or SPI read or when channel is commanded OFF via SPI RSCTRL or if one of the following is set: STG, STB, CURRENT_HI, OPEN_DET, RSTEMP, SLOT ERROR (PSI5), PULSE OVERFLOW ERROR (WSS) or if a new valid data is received Set in PSI5 configuration when two valid start bits are received and a Manchester error (# of bits, bit timing) or parity error is detected Set in WSS configuration when parity error is detected (when this check is feasible). Valid only for VDA sensor. 0 No fault 1 Fault NODATA 1 1 1 No Data in buffer Cleared when a valid PSI5/WSS frame is received or if one of the following is set: STG, STB, CURRENT_HI, OPEN_DET, RSTEMP, SLOT ERROR, PULSE OVERFLOW ERROR, INVALID Set upon SPI read of RSDRx and none of the following bits are set: STG, STB, CURRENT_HI, OPEN_DET, RSTEMP, SLOT ERROR, PULSE OVERFLOW ERROR, INVALID 0 No fault 1 Fault PULSE OVERFLOW ERROR 0 0 0 Pulse duration counter overflow (valid only for PWM 2 edges sensors) Cleared by SSM_RESET or SPI read or when channel is commanded OFF via SPI RSCTRL 0 No fault 1 Fault SLOT ERROR 0 0 0 Slot error fault (valid only for PSI5 sensors Cleared by SSM_RESET or SPI read or when channel is commanded OFF via SPI RSCTRL or if one of the following is set: STG, STB, CURRENT_HI, OPEN_DET, RSTEMP or if a new valid data is received Set in case of slot control enabled and frame not completely inside slot or more than one frame inside the slot 0 No fault 1 Fault DocID029257 Rev 1 155/277 276 SPI interfaces 7.6.3 L9680 Remote sensor x current registers y (RSTHRx_y) Remote sensor 0, base current and delta to calculate 1st top current (RSTHR0_L) Remote sensor 1, base current and delta to calculate 1st top current (RSTHR1_L Remote sensor 2, base current and delta to calculate 1st top current (RSTHR2_L Remote sensor 3, base current and delta to calculate 1st top current (RSTHR3_L Remote sensor 0 (only for WSS), delta to calculate 2nd top current (RSTHR0_H) Remote sensor 1 (only for WSS), delta to calculate 2nd top current (RSTHR1_H Remote sensor 2 (only for WSS), delta to calculate 2nd top current (RSTHR2_H Remote sensor 3 (only for WSS), delta to calculate 2nd top current (RSTHR3_H 19 18 MOSI 17 - MISO_RS MISO_RS 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X DELTA 1ST TOP [9:0] 0 0 0 0 0 0 R Read: 5C00 (RSTHR0_L) 5D00 (RSTHR1_L) 5E00 (RSTHR2_L) 5F00 (RSTHR3_L) 6000 (RSTHR0_H) 6100 (RSTHR1_H) 6200 (RSTHR2_H) 6300 (RSTHR3_H Write: - BASE CURRENT [9:0] 0 0 0 DELTA 2ND TOP [9:0] SSM Type: WSM 5C (RSTHR0_L) 5D (RSTHR1_L) 5E (RSTHR2_L) 5F (RSTHR3_L) 60 (RSTHR0_H) 61 (RSTHR1_H) 62 (RSTHR2_H) 63 (RSTHR3_H POR ID: 0 BASE CURRENT [9:0] $A1 $A1 $A1 PSI5/WSS base current measured by internal converter (93.75 μA ±9% each LSB). DELTA 1ST TOP $103 $103 $103 PSI5/WSS delta measured by internal converter respect to base current [19:10] (93.75 μA ±9% each LSB) to get top current. Low threshold = base current+(DELTA_1ST_TOP/2) in case of WSS or PSI5 without current averaged algorithm (bit 4 of RSRCx register equal to 0). Low threshold = base current+(DELTA_1ST_TOP) in case of PSI5 with current averaged algorithm (bit 4 of RSRCx register equal to 1). 156/277 DocID029257 Rev 1 L9680 SPI interfaces DELTA 2ND TOP [9:0] $7 $103 $103 WSS delta measured by internal converter respect to base current (93.75 μA ±9% each LSB) to get second top current. High threshold = ((base current+DELTA_1ST_TOP)+(base current+DELTA_2ND_TOP))/2. 0 0 R Read: 6A00 Write: - ARMINT_x 10 9 8 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X 0 0 0 0 0 0 0 0 SSM Type: 11 WSM 6A 12 POR ID: 0 13 ARMINT_1 0 14 ARMINT_2 - 15 ARMINT_3 MISO 16 ARMINT_4 MOSI 17 ACL_VALID 18 ACL_PIN_STATE 19 PSINH_EXP_TIME Arming signals register (ARM_STATE) PSINHINT 7.6.4 - - - State of ARMINT signals Updated per Safing Engine output logic diagram in case of internal safing engine otherwise is the echo of ARMx pins ACL_VALID 0 0 0 Valid ACL detection 0 Cleared when ACL_BAD=2 1 Set when ACL_GOOD=3 ACL_PIN_STATE - - - Echo of ACL pin PSINH_EXP_TIME 0 0 0 State of PSINH expiration timer 0 If timer is 0 1 If timer is counting PSINHINT - - - State of PSINHINT signal Updated per PSINH output logic diagram in case of internal engine otherwise is the echo of PSINH pin inverted DocID029257 Rev 1 157/277 276 SPI interfaces R Read: $FF01 Write: $80FE CC_xx 7 6 5 4 3 2 1 0 X X X X X X X X X X X X X X X X CC_5 CC_4 CC_3 CC_2 CC_1 SSM Type: 8 WSM FF 9 POR ID: 10 CC_6 0 11 CC_7 0 12 CC_8 0 13 CC_9 0 14 CC_10 - 15 CC_11 MISO/ MISO_RS 16 CC_12 MOSI/ MOSI_RS 17 0 0 0 CC_14 18 CC_15 19 CC_13 Safing record compare complete register (SAF_CC) CC_16 7.6.5 L9680 Indicates compare complete status of each of the 16 safing records, and defines the end of the sample cycle for safing Cleared by SSM_RESET or upon SPI read, set by safing engine when request, response mask and target registers match the incoming SPI frame 0 Compare not completed for record x 1 Compare completed for record x 158/277 DocID029257 Rev 1 L9680 8 Deployment drivers Deployment drivers The squib deployment block consists of 12 independent high side drivers and 12 independent low side drivers. Squib deployment logic requires a deploy command received through SPI communications and either an arming condition processed by safing logic or a proper ARMx input pin assessment, depending on whether the internal safing engine is used or not. Both conditions must exist in order for the deployment to occur. Once a deployment is initiated, it can only be terminated by an SSM_RESET event. L9680 allows all 12 squib loops to be deployed at the very same time or in other possible timing sequence. Deployment drivers are capable of granting a successful deployment also in case of short to ground on low-side circuit (SRx pins). Firing voltage capability across high side circuit is maximum 25 V. High side and low side drivers account for a maximum series total resistance of 2 . Each loop is granted for a minimum number of deployments of 50, under all normal operating conditions and with a deployment repetition time higher than 10s. Both the High and the Low side FET drivers are equipped with passive gate turn-off circuitries to guarantee the FETs are kept in off state also when the device is unpowered or during power-up/down transients. 8.1 Control logic A block diagram representing the deployment driver logic is shown below. Deployment driver logic features include: Deploy command logic Deployment current selection Deployment current monitoring and deploy success feedback Diagnostic control and feedback Figure 27. Deployment driver control blocks 3URJUDPPDEOH /RRS $VVLJQPHQWV '(3&20 'HSOR\PHQW &RPPDQG5HJLVWHU $50 '&5 'HSOR\PHQW&RQILJXUDWLRQ 5HJLVWHU 'HSOR\ 5HTXHVW 9DOLGDWLRQ ; +LJK 6LGH )(7 6)[ ; 65[ '&076[ 'HSOR\&XUUHQW 0RQLWRU6WDWXV 'HSOR\PHQW &RQWURO 7LPLQJ '&5 'HSOR\PHQW &RQILJXUDWLRQ 5HJLVWHU ,QW([WVDILQJHQJLQH LQWFON ,7+'(3/ &XUUHQW 0RQLWRU '&5 'HSOR\PHQW &RQILJXUDWLRQ 5HJLVWHU 'HSOR\PHQW6WDWXV 5HJLVWHU '65[ /RZ 6LGH )(7 $50 ; ; 3URJUDPPDEOH /RRS $VVLJQPHQWV 6DILQJ(QJLQH 7ULVWDWHHQDEOHU ,QW([WVDILQJHQJLQH *$3*36 DocID029257 Rev 1 159/277 276 Deployment drivers L9680 Figure 28. Deployment driver control logic - Enable signal $50,1*67$7( $1$/2* ',$*67$7( 'HSOR\PHQW /3',$*5(4/($.B&+6(/[ '67(67+6)(7B7(67 %/2&. 36,1+,17 36,1+B/[ $50,17 $50B/[ (1$%/(B+6[ $50,17 $50B/[ $50,17 $50B/[ $50,17 $50B/[ 6$)(6(/ (1$%/(B/6[ 6$),1*67$7( ',$*67$7( /3',$*5(4/($.B&+6(/[ '67(67/6)(7B7(67 *$3*36 Figure 29. Deployment driver control logic - Turn-on signals $50,1*67$7( ([SLUDWLRQ 7LPHU 6$),1*67$7( '(3B(1$%/('67$7( 6 63,B'(35(4[ 5 6605(6(7 '(3B',6$%/('67$7( 8S&WU (;3B7KUHVK (1 &/5 6 &+['(3 &+[67$7 5 '(3B7KUHVK 8S &WU (1$%/(B+6[ (1$%/(B/6[ 6 ',$*67$7( '67(6738/6( 5 (1 &/5 /6B29(5B&85[ *1'B/266[ 'HSOR\ 7LPHU 6605(6(7 6 5 &+['6 +6B21[ '67(67+6)(7B7(67 /3',$*5(4/($.B&+6(/[ /6B21[ '67(67/6)(7B7(67 $1$/2* 'HSOR\PHQW%/2&. *$3*36 160/277 DocID029257 Rev 1 L9680 Deployment drivers The high level block diagram for the deployment drivers is shown below: Figure 30. Deployment driver block 66[\ 5 Pȍ 5 3DVVLYH 6ZLWFK RII $FWLYH 6ZLWFK RII 23ZLWKVZLWFKLQJ 2IIVHWFRPSHQVDWLRQ (QDEOH B+6[ 5 66[\ 23SKDVH 23SKDVH 5 [,5() 6)[ 2SHQWRVKRUWFRPS Q) 7R GHSOR\ FXUUHQW ! FRXQWHU 5VTXLE 65[ 9FODPS !9 ,SXOOGRZQ +6B21 9,179 Q) 6DPHSRZHU WUDQVLVWRU /6B21 ,5() P$ (1B,6,1. 9,179 3DVVLYH 6ZLWFK RII /6B2&B&RPS ,OLPLW P$ W\S 6*[\ /RVVJURXQG GLRGH (QDEOH B/6[ $FWLYH 6ZLWFK RII *1'68% 9,179 /6B/RVV B*QG *$3*36 8.1.1 Deployment current selection Deployment current is programmed for all channels using the Deploy Configuration Register (DCRx) shown in Section 7.3.7. The deploy time selection allows the device to deploy for a time up to 4.032 ms. Careful considerations should be done in order to avoid damage on the squib driver section for excessive thermal heat. In order to prevent device damage, it is suggested to avoid excessive voltage drop between SSxy and SFxy. In case the 1.75 A deployment current level is selected, the voltage drop across the pins should be limited to maximum 17 V for deployment times longer than 0.7 ms and up to 2 ms and 15 V up to 3.2 ms. In case 1.2 A is selected, the voltage drop should be limited to maximum 22 V for deployment times longer than 2 ms and up to 3.2 ms. 8.1.2 Deploy command expiration timer Deploy commands are received for all channels using SPI communications. Once a deploy command is received, it will remain valid for a specified time period selected in the Deployment configuration registers (DCR_x). The deploy status and deploy expiration timer can be read through the Deployment status registers (DSR_x). The deploy expiration timer is selectable via 2 bits and the maximum programmable time is 500 ms nominal. DocID029257 Rev 1 161/277 276 Deployment drivers 8.1.3 L9680 Deployment control flow Deployment control logic requires the following conditions to be true to successfully operate a deployment: POR = 0 SSM to be either in Safing State or Arming State a valid arming condition processed by safing logic or ARMx signals to be set (depending on selection of internal or external safing engine) channel-specific deploy command request bits to be set via SPI in the Deploy command Register (DEPCOM) a global deployment state has to be active, as described in the following figure. Figure 31. Global SPI deployment enable state diagram 660B5HVHW '(3B',6$%/(' 63,B63,'(3(1'(3(1B:5 63,B63,'(3(1'(3(1B:5 81/2&. /2&. '(3B(1$%/(' '!0'03 In case a multiple deployment request would be needed, i.e. deploying the same channel in sequence, a toggle on DEP_DISABLED has to be performed and a new DEPCOM command on the same channel has to be sent. The SPI DEPCOM command is ignored if the device is in the DEP_DISABLED state and the deploy command is not set. While in DEP_ENABLED state, the following functionalities that could be active are forced to their reset state: All squib and DC sensor diagnostic current or voltage sources All squib, DC sensor and ADC diagnostic MUX settings, state machine, etc. The SPI_LOCK and SPI_UNLOCK signals are available in the SPIDEPEN command: High-side and Low-side enablers (ARMx) are assigned to the desired channels by means of the programmable loop matrix. Loop matrix registers are 4, one for each ARMx signals. In each loop matrix register 12 bits are present to associate independently loops with ARMx signals. In case external safing is selected LOOP_MATRIX_ARM4 register is don't care because ARM4 pin is used to arm the low side of all loops without association matrix. Deploy commands in the Deploy Command Register (DEPCOM) are channel specific. Deployment requires a valid arming condition from safing logic or ARMx signals to be set any time before, during or after the specific sequence of deploy commands is received. It is feasible for a deploy command to be received without a valid arming condition from safing logic or the ARMx being set. In this case, the deploy command will be terminated according 162/277 DocID029257 Rev 1 L9680 Deployment drivers to the Deploy command expiration timer. Likewise, a valid arming condition signal can be set without receiving a Deploy Command. In this case, the enabling signals will remain active according to the Arming Enable Pulse Stretch Timer or the ARMx enabling state. The Arming Enable Pulse Stretch Timers is available in the AEPSTS register. 8.1.4 Deployment current monitoring A current comparator is used to indicate when the output current from the HSD, SFx, exceeds the deployment current threshold, ITHDEPL. The timer signal remains active and increments while the current meets the programmed deploy current as set in the Deploy Configuration Register. The deploy current counter value is stored in the Deploy Current Monitor Timer Register XY (DCMTSxy). There is a unique timer register for each channel. If the deploy current falls below the specified current threshold momentarily and recovers, the deploy current counter will pause during the drop-out and continue once the current exceeds the threshold. The deploy current counter will not be reset by the presence or absence of current in the deployment channel. Figure 32. Current monitor counter behavior 1RUPDO RSHUDWLRQ ,6)[ 7LPHUSDXVH 7LPHUFRQWLQXHVIURPW ,7+'(3/ W W W W '!0'03 The deploy current counter is reset to $0000 as soon as a toggle on DEP_DISABLED is performed and a new DEPCOM command on the same channel is received. 8.1.5 Deployment success Deploy success flag is set when the deploy timer elapses. This bit (CHxDS) is contained in the Deploy Status Register. Within the Global Status Word register (GSW), a single bit (DEPOK) is also set once any of the 12 deployment channels sets a deploy success flag. 8.2 Energy reserve - deployment voltage One deployment voltage source pin is used for adjacent channels (e.g. SS23 for channels 2 and 3). These pins are directly connected to the high side drivers for each channel. 8.3 Deployment ground return L9680 is hosted in a particular frame allowing squib driver ground feedback to be connected to an internal ground ring. This ring is electrically connected to the package exposed pad and to the GNDSUB1 and GNDSUB2 pins. Connection to these two pins is made by means of a strong metal layer, therefore this connection is sufficient for all deployments occurring DocID029257 Rev 1 163/277 276 Deployment drivers L9680 simultaneously, even in case of only one out of the three possible connections being available. 8.4 Deployment driver protections 8.4.1 Delayed low-side deactivation To control voltage spikes at the squib pins during drivers deactivation at the end of a deployment, the low side driver is switched off after tdepl_ls-dly delay time with respect to the high side deactivation. 8.4.2 Low-side voltage clamp The Low side driver is protected against overvoltage at the SRx pins by means of a clamping structure as shown in Figure 30. When the Low side driver is turned off, voltage transients at the SRx pin may be caused by squib inductance. In this case a low side FET drain to gate clamp will reactivate the low side FET allowing for residual inductance current recirculation, thus preventing potential low side FET damage by overvoltage. 8.4.3 Short to battery The Low side driver is equipped with current limitation and overcurrent protection circuitry. In case of short to battery at the squib pins, the short circuit current is limited by the Low side driver to ILIMSRx. If this condition lasts for longer than tLIM deglitch filter time then the low and high-side drivers will be switched off and latched in this state until a new deployment is commanded after SPI_DEPEN is re-triggered. 8.4.4 Short to ground The squib driver is designed to stand a short to ground at the squib pins during deployment. In particular, the current flowing through the short circuit is limited by the high side driver (deployment current) and the high-side FET is sized to handle the related energy. In case the short to ground during deployment occurs after an open circuit, a protection against damage is also available. The high side current regulator would have normally reacted to the open circuit by increasing the Vgs of the high side FET. Thanks to a dedicated fast comparator detecting the open condition, the driver is able to discharge the FET gate quickly in order to reduce current overshoot and prevent potential driver damage when the short to ground occurs. 8.4.5 Intermittent open squib A dedicated protection is also available in case of intermittent open load during deployment. In this case, if load is restored after an open circuit, due to slow reaction of the high-side current regulation loop, the current through the squib is limited only to ILIMSRx by the low side driver. If this condition lasts for longer than tLIMOS then the high side is turned off for tHSOFFOS and then reactivated. By this feature, intermittent open squib and short to battery faults may be distinguished and handled properly by the drivers. 164/277 DocID029257 Rev 1 L9680 8.5 Deployment drivers Diagnostics The L9680 provides the following diagnostic feedback for all deployment channels: High voltage leakage test for oxide isolation check on SFx and SRx Leakage to battery and ground on both SFx and SRx pins with or without a squib Short between loops diagnostics Squib resistance measurement with leakage cancellation and selectable range (10/50 Ω) High squib resistance with range from 500 Ω to 2000 Ω SSxy, SFx and VER voltage status High and Low side FET diagnostics High side driver diagnostics Loss of ground return diagnostics High Side Safing FET diagnostics The above diagnostic results are processed through a 10 bit Analog to digital algorithmic converter. These tests can be addressed in two different ways, with a high level approach or a low-level one. The main difference between the two approaches is that with the low level approach the user is allowed to precisely control the diagnostic circuitry, also deciding the proper timings involved in the different tests. On the other hand, the high level approach is an automatic way of getting diagnostic results for which an internal state machine is taking care of instructions and timings. The following is block diagram of the Squib Diagnostics. DocID029257 Rev 1 165/277 276 Deployment drivers L9680 Figure 33. Deployment loop diagnostics 9(5SLQ IURP(QHUJ\5HVHUYH 6<1&%2267 6DILQJ WUDQVLVWRU ,65&B&855B6(/ ,65& P$ 6$7%8&. 66[\ %\SDVV Q) 6TXLEUHVLVWDQFHPHDVXUH V\VWHPHUURU 9JQG RU 9%DW 6)[ 5/HDN 9UHI Y Q) [1 $WR' 6TXLEORRS GULYHUDQG GLDJQRVWLF EORFNV 5VTXLE ȍWRȍ (0,ORZSDVV ILOWHU 9RXW ELW 7RWHUU /6% /6% 9 9RIIVHW +9DQDORJ08; *DLQ YVXSSO\ 9JQG RU 9%DW 65[ ,SXOOGRZQ , P$ 6TXLEUHVLVWRU+,*+ 5/HDN 6KRUWWR*1' 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ Q) 6TXLEUHVLVWRU/2: 6*[ 9UHI Y ,6,1. *1'$ ,OLPLW P$ 6KRUWWR%$7 5OHDN !.ȍQRGHWHFWLRQ 5OHDN .ȍGHWHFWLRQ *$3*36 95&0YROWDJHUHJXODWRUFXUUHQWPRQLWRU The leakage diagnostic includes short to battery, short to ground and shorts between loops. The test is applied to each SFx and SRx pin so shorts can be detected regardless of the resistance between the squib pins. 8.5.1 Low level diagnostic approach In this approach, each of the test steps described in the sections below requires user intervention by issuing the proper SPI command. High voltage leakage test for oxide isolation check This test is mandatory to address possible leakages that could not be experienced at low voltages on SFx or SRx pins. The Isource current generator (ISRC) is enabled on the chosen SFx pin. To confirm that the SFx pin has then reached a suitable voltage level, a dedicated ADC measurement on the SFx pin can be requested. Once this test is performed, a leakage test on SFx and SRx pins can be issued to double check possible leakages. Leakage to battery/ground diagnostics Prior to the real test, the Voltage Regulator Current Monitor block (VRCM) has to be tested and validated. The validation of VRCM goes into verifying both the short to battery and short to ground flags. The Isource current generator (ISRC) is first connected to SFx pin to raise its voltage to SYNCBOOST. Then, the Voltage Regulator Current Monitor block (VRCM) is enabled and 166/277 DocID029257 Rev 1 L9680 Deployment drivers connected to the selected SFx pin. The Isink current limited switch (ISNK) is turned off, as well as the pull-down current generator. If the VRCM block works properly, the short to battery flag would be asserted. Then, the Isink current limited switch (ISNK) is connected to SRx pin, the Voltage Regulator Current Monitor block (VRCM) is enabled and connected to the selected SRx pin. The Isource current generator (ISRC) is turned off, as well as the pull-down current generator. If the VRCM block works properly, the short to ground flag would be asserted. Figure 34. SRx pull-down enable logic /3',$*5(43'B&855 +6B21[ (1B3'B&855[ /6B21[ /3',$*5(4 ,65& RU /3',$*5(4 5(6B0($6B&+6(/[ /3',$*5(4,61. /3',$*5(4 95&0 RU /3',$*5(4 /($.B&+6(/[ /3',$*5(4 ',$*B/(9(/ /3',$*5(4 /223B',$*B&+6(/[ DQG *$3*36 /3',$*5(4+,*+B/(9(/ B',$*B6(/ Once the VRCM block is validated, the real leakage tests can be performed. ISRC and ISNK currents have to be kept switched off. The VRCM shall be connected to the desired pin (either SFx or SRx pins); by doing this, also the pull-down current on the selected SRx pin is automatically deactivated). During the test, if no leakage is present the voltage on the selected SFx or SRx pin will be forced by the VRCM to the VREF level and no current is detected or sourced by the VRCM. If there is leakage to ground or battery, the VRCM will sink or source current trying to maintain VREF. Two current comparators, ISTB and ISTG, will detect the abnormal current flow and the relative flags will be given in the LPDIAGSTAT. These flags are not latched and report the real time status of the relevant comparators in case of low-level leakage diagnostic test. Voltage conversion is not required to have these flags updated. In LPDIAGSTAT register are also reported the channel and the pin (SFx or SRx) under test, respectively with LEAK_CHSEL and SQP bit fields. The pull-down currents on the other SRx pins are still active. Therefore, the leakage test that would show a leakage to ground may be depending on a real leakage on the pin under test or on a short between loops. DocID029257 Rev 1 167/277 276 Deployment drivers L9680 Short between loops diagnostics In case the previous test has reported a leakage to ground fault, the short between loops diagnostics shall be run. The same procedure is followed as described for normal leakage tests except the fact that in this case all the pull-down current generators have to be deactivated (not only the one for the pin under test), by means of the PD_CURR bit in the Diagnostic Request Register (LPDIAGREQ). If a leakage or ground fault is not present, then the channel under test has a short to another squib loop. Table 10. Short between loops diagnostics decoding Channel leakage diagnostics with PD_CURR on (for other channels than the one under test Channel leakage diagnostics with PD_CURR off (for all channels) No fault No fault Short to battery STB fault STB fault Short to ground STG fault STG fault Short between loops STG fault No fault Fault condition on squib channel No shorts The condition of two open channels, i.e. without squib resistance connecting SFx to SRx, that have a short between loops on SFx cannot be detected. If only one of the two shorted SFx pins is open, the fault will be indicated on the open channel. Squib resistance measurement During a resistance measurement, a two-step process is performed. At the first step, both ISRC current generator and ISNK current limited switch are enabled and connected to the selected SFx and SRx channel, through ISRC, ISRC_CURR_SEL, ISNK and RES_MEAS_CHSEL bit fields in the Loop Diagnostic Request Register (LPDIAGREQ). The ISRC current can be configured to either 40 mA or 8 mA nominal value through the ISRC_CURR_SEL bit in the LPDIAGREQ register providing the user with two different measurement range options. A differential voltage is created between the SFx and SRx pin based on the ISRC current and squib resistance between the pins. The SPI interface will provide the first resistance measurement voltage (Vdiff1) based on the amplifying factor of the differential amplifier and a 10 bit internal ADC conversion. The second measurement step (bypass measurement) is performed redirecting ISRC to the selected SRx pin, while keeping ISNK on; this way, the differential amplifier and following ADC will output the offset measurement through SPI (Vdiff2). Microcontroller is then allowed to calculate the mathematical difference between first and second measurements to obtain the real squib resistance value. R SQ R LKG_SF R SQ - + ------------------------------------------- V LKG_SF – V SRx_RM + V diff 1 = G RSQ I SRC_* ------------------------------------------ R LKG_SF + R SQ R LKG_SF + R SQ + G RSQ V off _RSQ G RSQ R SQ - V LKG_SF – V SRx_RM + G RSQ V off _RSQ V diff 2 = ------------------------------------------R LKG_SF + R SQ V diff 1 – V diff 2 R SQ = ---------------------------------------- (assuming RLKG_SF >> RSQ) G RSQ I SRC_* 168/277 DocID029257 Rev 1 L9680 Deployment drivers The simplification in the calculation method reported above can result in some amount of error that is already incorporated in the overall tolerance of the squib resistance measurement reported in the electrical parameters table. Values of each measurement step can be required addressing the proper ADCREQx code in Section 7.3.33: ADC request and data registers (DIAGCTRL_x). This calculation is tolerant to leakages and, thanks to a dedicated EMI low-pass filter, also to high frequency noises on squib lines. Moreover, L9680 features a slew rate control on the ISRC current generator to mitigate emissions. High squib resistance diagnostics With this test, the device is able to understand if the squib resistance value is below 200 Ω, between 500 Ω and 2000 Ω or beyond 5000 Ω. During a high squib resistance diagnostics, VRCM and ISNK are enabled and connected respectively to SFx and SRx on the selected channel. VREF voltage level will be output on SFx. Current flowing on SFx will be measured and compared to ISRlow and ISRhigh thresholds to identify if the resistance is above or below RSRlow or RSRhigh levels. The results are reported in the LPDIAGSTAT register. The relative flags (HSR_HI and HSR_LO) are not latched and reflect the current status of the comparators. High and low side FET diagnostics This couple of tests can only be run during the diagnostic mode of the power-up sequence Figure 10. Tests are performed individually for HS driver or LS driver, with two dedicated commands. Prior to either the HS or LS FET diagnostics being run, the VRCM has to be first enabled. Within the command to enable the VRCM, also the channel onto which the FET test will be run has to be selected with the LEAK_CHSEL bit field. Running the leakage diagnostics with the appropriate delay time prior to either the HS or LS FET diagnostics will precondition the squib pin to the appropriate voltage level. When the FET diagnostic command is issued with the Diagnostic Register SPI command (SYSDIAGREQ), the VRCM flags will be cleared, the VRCM deglitch filter time is switched from the leakage diagnostic deglitch filter time (TFLT_LKG) to the FET test deglitch filter time (TFLT_LKGB_FT) for both HS and LS and the output of the VRCM deglitch filter is now allowed to disable the appropriate HS or LS squib driver during FET test. The device monitors the current through the VRCM. If the FET is working properly, this current will exceed IHS_FET_TH or ILS_FET_TH current threshold, respectively for HS or LS FET test for the deglitch filter time of TFLT_LKGB_FT, and the driver under test is turned off immediately and automatically. If there is a substantial leakage fault to Vbat or GND present during the FET test, leading this leakage current to exceed the IHS_FET_TH or ILS_FET_TH current threshold, for the deglitch filter time of TFLT_LKGB_FT, then the driver under test is turned off immediately and automatically, and the corresponding VRCM flag, STG or STB, is set. If the current does not exceed the current threshold, the test will be terminated and the driver is anyway turned off within TFETTIMEOUT. DocID029257 Rev 1 169/277 276 Deployment drivers L9680 Table 11. HS FET TEST VRCM Flags Result STG STB 0 0 FET test fail 0 1 FET test pass OR Leakage to Vbat 1 0 FET test disabled due to Leakage to Gd 1 1 State not possible Table 12. LS FET TEST VRCM Flags Result STG STB 0 0 FET test fail 0 1 FET test disabled due to Leakage to Vbat 1 0 FET test pass OR Leakage to GND 1 1 State not possible During TFETTIMEOUT period, the bit stating that the FET is enabled will be set (FETON=1) and will be cleared as soon as the FET is switched back off. For all conditions the current on SFx/SRx pins will not exceed the VRCM current limitation value (ILIM_VRCM_SINK or ILIM_VRCM_SRC). There may be higher currents on the squib lines due to the presence of filter capacitors. During these FET tests, energy available to the squib is limited to less than EFET_TEST. For high side FET diagnostics, if no faults were indicated in the preceding leakage diagnostics then a normal result would be [STB=1, STG=0]. If the returned result for the high side FET test is not as the previous then either the FET is not functional, a short to ground occurred during the test, or there is a missing SSxy connection for that channel. For low side FET diagnostics if no faults were indicated in the preceding leakage diagnostics then a normal result would be [STB=0, STG=1]. If the returned result for the low side FET test is not as the previous then either the FET is not functional or a short to battery occurred during the test. In case of ground loss the low-side FET diagnostic would not indicate a FET fault. The VRCM flags will be given in the LPDIAGSTAT register. The status of the VRCM flags after FET test is latched and can be cleared upon either LPDIAGREQ or SYSDIAGREQ SPI commands. Finally, after FET test is completed, the VRCM deglitch filter time is switched from the FET test deglitch filter time (TFLT_LKGB_FT) to the leakage diagnostic test deglitch filter time 170/277 DocID029257 Rev 1 L9680 Deployment drivers (TFLT_LKG) for both HS and LS and the output of the VRCM deglitch filter is now not allowed to disable the appropriate HS or LS squib driver anymore. High side driver diagnostics This test is intended to verify the proper functionality of the HS FET driver, but also the external squib connection and other internal circuitries. First, the ISNK current has to be activated via the LPDIAGREQ register; the channel onto which the ISNK current is activated has to be selected with the RES_MEAS_CHSEL bit field. Then, the HS FET related to the loop channel as indicated in the RES_MEAS_CHSEL bit field is activated with the dedicated DSTEST code for the HS squib driver test in the Diagnostic Register SPI command (SYSDIAGREQ). In such condition, the HS driver will control the FET current to a level ILIM_HS_FET much lower than the usual deployment current. The HS_DRV_OK flag will be set accordingly to the test result in the LPDIAGSTAT register, as soon as the deployment current monitoring comparator will detect that the current through the HS FET exceeds the diagnostic current threshold, 90%*ILIM_HS_FET. Loss of ground return diagnostics This diagnostics is available during a squib measurement or a high side driver diagnostics. This test is based on the voltage drop across the ground return, if the voltage drop exceeds SGxy_OPEN, ground connection is considered as lost. Should the ground connection on the squib driver circuit be missing, the bit related to the channel under test by the two above diagnostics will be activated in the LP_GNDLOSS register. The flag is latched after a proper filter time TFLT_SGOPEN and cleared upon read. High side safing FET diagnostics This test has to be issued during the Diag state of the power-up sequence (Figure 10). Safing FET has to be switched on with the proper code in DSTEST bit field of the SYSDIAGREQ. Therefore, when the command is received, the device will activate VSF regulator to supply the external safing FET controller. The user can measure the voltage levels of both the VSF regulator and the SSxy nodes. If the safing FET is properly switched on, the voltage on SSxy will be regulated. The measurement request is done via Diagnostic Control command (DIAGCTRLx), while results will be reported through ADCRESx bit fields. Deployment Timer diagnostic This test allows verifying the correct functionality and duration of the timers used to control the deployment times. This test can be executed only when the IC is in the Diag state by setting the appropriate code in the DSTEST field of the SYSDIAGREQ register. When the test is launched, the IC sequentially triggers the activation of the deployment timers of the various channels (each of them separated by 8ms idle time) and outputs the relevant waveform to the ARM1 output discrete pin. See the sequence detail in Figure 35. The μC can therefore test the deployment times by measuring the duration of the high pulses sent by the IC on the ARM1 pin. The deployment time configuration used during this test is the latest one programmed in the DCRx registers. In case the test is run on a channel with no DCRx deployment time previously configured, a default 8 μs high pulse is output on ARM for the relevant channel. DocID029257 Rev 1 171/277 276 Deployment drivers L9680 Figure 35. Deployment timer diagnostic sequence 660B5(6(7 38/6(B7(67[ 37B705 7SXOVHBSHULRG 38/6(B7(67DOOBFK[ 37B2)) 37B705 7SXOVHBSHULRG 37B705 38/6(B7(67RWKHU 38/6(B7(67 IRU7SXOVHBKLJK 37 37B705 7SXOVHBSHULRG 37B705 38/6(B7(67RWKHU 38/6(B7(67 IRU7SXOVHBKLJK 37B:$,7 )URPDQ\VWDWH ',$*VWDWH63,B6<65(4'67(67 38/6( 38/6(B7(67[ 37 37B705 7SXOVHBSHULRG 37B705 38/6(B7(67RWKHU 38/6(B7(67 IRU7SXOVHBKLJK 37 37 37 37 37B705 7SXOVHBSHULRG 37 37B705 38/6(B7(67RWKHU 37 38/6(B7(67Q IRU7SXOVHBKLJK 37 37 37 37 37B705 7SXOVHBSHULRG 37B705 38/6(B7(67RWKHU 38/6(B7(67 IRU7SXOVHBKLJK 37B705 7SXOVHBSHULRG 37B705 38/6(B7(67RWKHU 38/6(B7(67 IRU7SXOVHBKLJK 37B705 7SXOVHBSHULRG 37B705 38/6(B7(67RWKHU 38/6(B7(67 IRU7SXOVHBKLJK *$3*36 Squib diagnostics with common SRx connected loops In case of two SRx pins are intentionally connected together, the PD_CURR_CSR bit of the Deployment Configuration register (DCR_x, where x = 0, 2, 4, 6, 8, A) must be used to indicate which loop pairs have the common SRx connection. The purpose of this additional bit is to control the pull-down current on each channel to be consistent with or without the Common SRx connected loops. When the DCR_x(PD_CURR_CSR) bit is set for one loop pair and the Deployment diagnostic is run on that loop pair, the pull-down current is disabled on both channels of the loop pair selected. For the squib channel pair with common SRx connection, to understand if the two SFx pins are shorted together, the squib resistance measurement must be required with the following setting: LPDIAGREQ[12:11]=11. In this way the ISRC current generator is enabled on the channel selected by RES_MEAS_CHSEL[3:0] bits while the Differential Operational Amplifier is connected on the other channel of the squib channel pair. If the short between the two SFx pin is not present then the Squib resistance measurement results will be close to 0, otherwise it will be half the real squib resistance. Loop diagnostics control and results registers Diagnostic tests and channels for each test are controlled through the Loop Diagnostic Request Register (LPDIAGREQ), diagnostic results are stored in the Loop Diagnostic Status Register (LPDIAGSTAT). 172/277 DocID029257 Rev 1 L9680 Deployment drivers 8.5.2 High level diagnostic approach In this approach, the test steps described in the sections below are coded into a dedicated state machine that helps reducing the user intervention to a minimum. The high-level diagnostic commands are contained in the LPDIAGREQ, LOOP_DIAG_SEL, and LOOP_DIAG_CHSEL registers. The high-level diagnostic response is available in the LPDIAGSTAT register. The concept is depicted in the following figures. Figure 36. High level loop diagnostic flow1 ,OWLEVELDIAGNOSTICISSELECTEDBIT OF,0$)!'2%1ISLOW/2ANINVALID HIGHLEVELDIAGNOSTICISSELECTED/2WE AREIN$%0?%.!",%$STATE 4)0 ,EAKAGETESTTIMEELAPSED 3",FLAGISASSERTEDIF34' ISNOMOREPRESENT ,EAKAGEISDETECTEDDUETO THEFACTTHAT&%4SWORK PROPERLY/2&%4TEST TIMEOUTELAPSED $)!'?/&& .EWHIGHLEVELDIAGNOSTICREQUEST BITOF,0$)!'2%1ISHIGH 62#-CHECKTIMEELAPSED !.$62#-#(%#+TEST ISSELECTED/262#-FAILS 4)0 7AITENAUGHTIMETO BESURETHATALL CURRENTSANDVOLTAGES SUPPLIESSTARTIN/&&STATE 7!)4?/&& /FFTIMES ,ATCH34"34'FLAGS &0IF,%!+!'%OR &%44TESTSARESELECTED /FFTIMEELAPSED!.$NEW DIAGNOSTICREQUESTIS 62#-?#(%#+/2 ,%!+!'%/23",/2 &%4TESTS 62#-?#(%#+ &%44%34 4)0 &%4TESTTIMEOUTS %NABLE62#$ISABLE)32#AND)3).+ %NABLE(3OR,3&%4IFALSO $34%34OR ,EAKAGETESTTIMEELAPSED !.$&%4TESTISSELECTED !.$./LEAKAGEISPRESENT ,EAKAGETESTTIMEELAPSED !.$,%!+!'%TEST/2 3",ANDNOLEAKAGEIS PRESENT/2&%4TESTAND LEAKAGEISPRESENT ,ATCH34"34'FLAGS &0IF&%4TESTISSELECTED 4)0 ,%!+!'%?4%34? %NABLE62#$ISABLE)32#AND ,EAKAGETESTTIMES )3).+ $ISABLE!,,PULL DOWNCURRENTS 62#-CHECKTIMESS 4)0 %NABLE62#$ISABLE)32#AND)3).+ ,EAKAGETESTTIMEELAPSED !.$3",ISSELECTED !.$LEAKAGEISPRESENT ,%!+!'%?4%34? ,EAKAGETESTTIMES 4)0 %NABLE62#$ISABLE)32#AND)3).+ '!0'03 DocID029257 Rev 1 173/277 276 Deployment drivers L9680 Figure 37. High level loop diagnostic flow2 ,OWLEVELDIAGNOSTICISSELECTEDBIT OF,0$)!'2%1ISLOW/2ANINVALID HIGHLEVELDIAGNOSTICISSELECTED/2WE AREIN$%0?%.!",%$STATE %NDOFCONVERSION 3TORERESULTIN!$#2%3" $)!'?/&& 4)0 2ESISTANCERANGETESTTIMEELAPSED ,ATCH(32?()(32?,/FLAGS 315)"2%32!.'% 4%34 .EWHIGHLEVELDIAGNOSTICREQUEST BITOF,0$)!'2%1ISHIGH /FFTIMEELAPSED!.$NEW DIAGNOSTICREQUESTIS315)" 2%3)34!.#%2!.'%TEST 4)0 7AITENOUGHTIMETO BESURETHATALL CURRENTSANDVOLTAGES SUPPLIESSTARTIN/&&STATE 7!)4?/&& 2ESISTANCERANGETEST SETTINGTIMESS 4)0 %NABLE62#%NABLE)3).+ /FFTIMES /FFTIMEELAPSED!.$NEW DIAGNOSTICREQUESTIS 315)"2%3)34!.#%MEASURETEST %NDOFSETTINGTIME 315)"2%3-%!3 #/.6 315)"2%3-%!3 #/.6 %NDOFCONVERSION 3TORERESULTIN!$#2%3! %NDOFSETTINGTIME 315)"2%3-%!3 3%44,% 4)0 %NABLE)32#ON3&X %NABLE)3).+ 2ESISTANCETEST SETTINGTIMESS 315)"2%3-%!3 3%44,% 4)0 2ESISTANCETEST %NABLE)3).+ SETTINGTIMESS %NABLE)32# "90!33)32#ON32X '!0'03 174/277 DocID029257 Rev 1 L9680 9 Remote sensor interface Remote sensor interface The L9680 contains 4 remote sensor interfaces, capable of supporting PSI-5 protocol (synchronous mode, increased voltage, extended range) and active wheel speed sensors. A simplified block diagram of the interface is shown below. The interface supply is given on the SATBUCK pin (refer to Figure 3: Power supply block diagram). The circuitry consists of a power interface that mirrors current flowing in the external sensor and transmits this current information to the decoder, which produces a digital value for each remote sensor channel. The voltage at the RSUx pins can be limited by the power interface in case of SATBUCK supply overvoltage to protect the external sensors. Decoded data are then output through the Remote Sensor Data Registers (RSDRx). Received signals can be processed to the corresponding discrete logic output pin WS0-WS3. The power interface also contains error detection circuitry. When a fault is detected, the error code is stored in a global SPI data buffer in the Remote Sensor Data Registers (RSDRx). Figure 38. Remote sensor interface logic blocks 5HPRWH6HQVRU&RQILJXUDWLRQ5HJ56&5[ 5HPRWH6HQVRU&RQWURO5HJ56&75/ 5HPRWH6HQVRU'DWDDQG)DXOW5HJ;56'5[ 0DQFKHVWHU 'HFRGHU )DXOW 'HWHFWLRQ 3RZHU ,QSXW 3URWHFWLRQ ; 568[ *$3*36 Remote sensor configuration can be addressed via the Remote Sensor Configuration Registers (RSCRx). Some of the bit fields in the RSCRx registers are available depending on the chosen configuration, remote sensor rather than wheel speed sensors. In particular, TSxDIS bit allows overriding the time slot control for PSI5 I/F and BLKTxSEL allows selection between 5ms and 10ms for the blanking time applied to the current limitation fault detection each time a channel is activated. The Remote Sensor Control Register (RSCTRL) allow for interface channels to be switched on and Off and for Sync Pulse control via SPI. The remote sensor interface reports both data information and fault information in the Remote Sensor Data Register (RSDRx). The device accommodates for a total of 12 data registers. Independent data registers are defined for each remote sensor interface and are formatted differently based on whether the interfaces are programmed for PSI-5 remote sensor functions or active wheel speeds. In the VDA sensor communication, data bit D0 in the RSDRx register might be used by the sensor as a fault bit. Therefore, this bit is latched as D0_L in order to detect whether a fault has occurred: the eight data bits are updated every speed pulse so intermittent fault conditions could be lost. This bit is cleared-upon-read. If the device detects an error on the sensor interface, the MSB in RSDRx (FLTBIT) will be set to '1' and the following bits will be used to report the detected errors. Otherwise, the register will contain only data information. Detailed information on data and fault reporting are explained in the following sections. DocID029257 Rev 1 175/277 276 Remote sensor interface L9680 When a fault condition is detected, the RSFLT bit of the global status word (GSW) is set to 1. Faults other than Short to Ground and Over-temperature will only clear after read, not by the disabling of channel. Data are cleared upon reading the RSDRx register. 9.1 PSI5 mode All channels are compliant to the PSI-5 v1.3 specification as described below: Two-wire current interface Manchester coded digital data transmission High data transmission speeds of 125 kbps and 189 kbps Variable data word length (8 & 10 bit only) 1-bit parity Synchronous operating mode with 3 time slots An example of the data format for one possible PSI-5 protocol configuration is shown below. Data size and the error checking may vary, but the presence of 2 sync start bits (referenced below as sync bits) and 2 TGap time is consistent regardless. Figure 39. PSI-5 remote sensor protocol (10-bit, 1-bit parity $ATA4RANSMISSION 4'!0 FRAMEDURATION 3 3 $ $ $ $ $ $ $ $ $ $ 0 -ANCHESTER#ODE 4RANSMISSIONOFX% X%B 4")4 9.1.1 '!0'03 Functional description The Remote Sensor Interface block provides a hardware connection between the microcontroller and up to twelve remote sensors (maximum three per channel). Each channel is independent on the others, and is not influenced by possible fault conditions occurring on other channels, such as short circuits to ground or to vehicle battery. Each channel is supplied by a current limited DC voltage derived from SATBUCK, and monitors the current sunk from its supply in order to extract encoded data. The remote sensor modulates the current draw to transmit Manchester-encoded data back to the receiver. The current level detection threshold for all channels is internally computed by the IC in order to adapt the signal level to the sensors quiescent current. All channels can be enabled or disabled independently via SPI commands. The operational status of all channels can also be read via SPI command. All channels support individual selective sync-pulse control to allow communication back to the remote sensor via syncpulse voltage modulation as described in the PSI5 v1.3 specification. 176/277 DocID029257 Rev 1 L9680 Remote sensor interface The message bits are encoded using a Manchester format, in which logic values are determined by a current transition in the middle of the bit time. When configured for PIS5 sensors each interface supports Manchester 2 encoding as shown in Figure 40. When configured for VDA sensors the protocol supported is Manchester 1. Figure 40. Manchester bit encoding %LWWLPH 3TARTBITS ,OGICgg &XUUHQW µ¶ ,OGICgg µ¶ µ¶ µ¶ µ¶ -ANCHESTER 03) '!0'03 The sensor input filter time, deglitch filter, (delay until a threshold crossing is detected) can be configured in 15 steps. Filters can be selected individually for each channel, through the Remote Sensor Configuration Register, WSFILT bits The received message data are stored in input data registers that are read out by the microcontroller via the SPI interface. For PSI5, three data registers per channel are used to store remote sensor messages received during timeslots 1, 2, and 3 respectively. Each register is updated after a certain delay (TWRITE_EN_DELAY ) from the end of relative sensor message. All the bits inside the registers itself are simultaneously updated upon reception of the remote sensor message to prevent partial frame data from being sampled via the SPI interface. After the data for a given channel is read via the SPI interface, subsequent requests for data from this channel will result in an error response. To allow for sampling synchronization of remote sensor data with the software in the microcontroller, the Remote sensor Interface block includes sync-pulse circuitry to signal initiation of sampling in the remote sensor. The sync-pulse is output to the remote sensors in the form of an increased voltage level on the RSUx pins when sampling is to be conducted. The higher voltage level required for the sync-pulse is sourced from the SYNCBOOST boost regulator. Pulse shaping is used to limit the slew rate of the pulses to reduce EMI. Feedback protection is provided to prevent fault conditions on one channel from affecting the others during sync-pulse generation. The microcontroller schedules the activation of the sync pulses to the four channels by providing a periodic signal to the SATSYNC pin. When a rising edge is detected on SATSYNC pin, the Remote sensor Interface block outputs sync pulses on channels RSU0-RSU3 in sequence to reduce the average current inrush to the remote sensors as shown in Figure 41. The voltage source in the Remote Sensor Interface block can source and sink current and is used to discharge the bus capacitance at the end of the sync pulse. The pull down device used to sink current is current limited. DocID029257 Rev 1 177/277 276 Remote sensor interface L9680 Figure 41. Remote sensor synchronization pulses 6$76<1& 6$7)' 6$7)' 6$7)' 6$7)' *$3*36 L9680 supports three time slots in a sync period with associated RSDRx registers. The messages received within one sync period are routed to the corresponding RSDRx register associated to each time slot. A time slot control is performed to check if the incoming messages fall within the valid time slots reported in Table 62 and sketched in Figure 42 If the end of the received message occurs after the end of the checked outside a valid time slot, a SLOT_ERROR fault will be detected and stored in the related RSDRx register. If two messages end within the same slot, the second message will be assigned to that slot, regardless its validity. The time slot control can be disabled by setting the TSxDIS bit in the RSCRx register. Figure 42. PSI5 slot timing control 6$76<1&3,1 6<1&38/6((1$%/( W 7B(6B 7B/6B 36,IUDPHV )URP6DWHOOLWH 7B((B 7B/(B7B(6B 7B/6B 6ORW 7B((B 7B/(B 7B(6B 7B/6B 6ORW 7B((B 7B/(B 6WRSELWQRW LQFOXGHG 6ORW 7BVBHQGBFORVXUHPLQ 7BVBHQGBFORVXUHPD[ 7BVBHQGBFORVXUHPLQ 7BVBHQGBFORVXUHPD[ 7BVBHQGBFORVXUHPLQ 7BVBHQGBFORVXUHPD[ )UDPHHQG 'HWHFWZLQGRZV 7BVBHQGBRSHQPLQ 7BVBHQGBRSHQPD[ 5HFHLYHU 5HVSRQVH (UURU6ORW 7BVBHQGBRSHQPLQ 7BVBHQGBRSHQPD[ 9DOLG 6ORW (UURU6ORW 7BVBHQGBRSHQPLQ 7BVBHQGBRSHQPD[ 9DOLG 6ORW (UURU 6ORW 9DOLG 6ORW (UURU6ORW *$3*36 178/277 DocID029257 Rev 1 L9680 Remote sensor interface The remote sensor interface is also able to detect faults occurring on the sensor interface. The Remote Sensor Data Register (RSDRx) will report multiple fault flags. When the number of bits decoded is incorrect (either too many or too few), a bit error is indicated. When any bit error is detected (bit time, too many bits, too few bits), the decoder will revert to the minimum bit time of the selected range and the message is discarded. Error bit INVALID is an OR-ed combination of the following errors: Start bit error outside of selected operating range Data length error or stop bit error Parity Error of received Remote sensor Message Bit time error (a data bit edge is not received inside the expected time window) 9.1.2 Sensor data integrity: LCID and CRC Each RSDRx data register contains a Logical Channel ID which is a 4/2-bit field for remote sensors used to link the received data to the corresponding logical channel number. Each RSDRx register contains also a CRC bit field computed on the data packet for data integrity check. To satisfy functional safety requirements LCID, DATA and CRC bit fields propagate through the same data path as a single item to the SPI output. The polynomial calculation implemented for PSI5 data is described as in PSI5 specification g(x)=1+x+x^3 with initialization value equal to ‘111’. Below are the equations to calculate the CRC in combinatorial way. CRC[2] = CRCext[0]+D[0]+D[1]+D[3]+D[6]+D[7]+D[8]+D[10]+D[13]+D[14]+D[15] CRC[1] = CRCext[2]+D[0]+D[1]+D[2]+D[4]+D[7]+D[8]+D[9]+D[11]+D[14]+D[15]+D[16] CRC[0] = CRCext[1]+CRCext[0]+D[0]+D[2]+D[5]+D[6]+D[7]+D[9]+D[12]+D[13]+D[14]+D[16] Where D[16:0]= RSDR[16:0] and CRCext[n] are the starting seed values (all '1'). 9.1.3 Detailed description Manchester decoding The Manchester decoder will support remote sensor communication as per PSI specification rev 1.3 for the modes configurable via the STS bits in the RSCRx registers. The Manchester Decoder checks the duty-cycle and period of the start bits to determine their validity, depending on the configuration of the PERIOD_MEAS_DISABLE bit in the RSCRx registers. The expected time windows for the mid bit transitions of each subsequent bit within the received frame are determined by means of the internal oscillator time base. Glitches shorter than 25% of the minimum bit time duration are rejected. DocID029257 Rev 1 179/277 276 Remote sensor interface L9680 Figure 43. Manchester decoder state diagram 5(6(7B'(&2'(5Æ 6WUREH 5(6(7B&17 ,'/( 7 3(5,2'BB 6WUREH5(&B(1' 6WUREH 5(6(7B&17 FKHFN3$5,7<B(55 7 7 5,6,1*B('*(Æ 3(5,2'BB 6WUREH 5(6(7B&17 7 6WUREH5(6(7B&17 $1<DQG3(5,2'BB 6WUREH 5(6(7B&17 7D 7 $1<DQG 3(5,2'BBRUQRW ),567 % 6WUREH 0$1<%,76 6WUREH 5(6(7B&17 :$,7 7*$3 3HULRGBBDQG$1<B('*(Æ 6WUREH5(6(7B&17 $ $ 7E 3HULRGBBDQGQRW$1<B('*( (5525 % % 67$57%,7 '(7 ( & 7 ' ILUVWSXOVHGXW\F\FOHFKHFN )$//,1*B('*(EHIRUHSHULRGBB Æ 6WUREH5(6(7B&17 7 7D 5,6,1*B('*(3HULRGBBÆ 6WUREH5(6(7B&17 3(5,2'BB DQG$1< VWUREH&+(&.B7,0( 7E 6WUREH5(6(7B&17 3(5,2'BB DQGQRW$1< VWUREH &+(&.B7,0( 7 $1<DQG QRW 3(5,2'BB DQG QRW ),567B('*( 6WUREH 5(6(7B&17 6WUREH &+(&.B7,0( $ % ( '$7$5(& 7 ' 7 $1<DQG 3(5,2'BBDQG 67$7( &B1% 6WUREH 5(6(7B&17 6WUREH 1(;7%,7 5,6,1*DQG3(5,2'BB 6WUREH5(6(7B&17 & 7 $1<DQG QRW3(5,2'BB DQG 3(5,2'BBDQGQRW 67$7( &B1% 6WUREH 5(6(7B&17 6WUREH1(;7%,7 'DWD)LOW 5,6,1*B('*( )$//,1*B('*( $1< &B1% 67$7( %LW&RXQWHU 3HULRGBB 3HULRGBB 3HULRGBB ),567B('*( 180/277 )LOWHUHG5DZ'DWD 5;6$7IURP&XUUHQW'HPRGXODWRU DIWHUGHJOLWFKHU 'DWD)LOWQQ ³´ 'DWD)LOWQQ ³´ 5,6,1*B('*(RU)$//,1*B('*( ELWIUDPHFRQILJXUDWHG " ^#,'/(#67$7%,7'(7#767$7(#7[( #:$,7[)#(5525` 5(6(7B&17"%LW&RXQWHU %LW&RXQWHU! %LW3HULRG %LW&RXQWHU! %LW3HULRG *$3*36 %LW&RXQWHU! %LW3HULRG 3HULRGBB"$1<" ),567B('*(DIWHUDGHOD\RI7FN 5HPDUNQRWDFRPELQDWRULDOVLJQDO DocID029257 Rev 1 L9680 Remote sensor interface A Manchester Decoder Error occurs if one or more of the following are true: Two valid start bits are detected, and at least one of the expected 13 mid-bit transitions are not detected Two valid start bits are detected, and more than 13 mid-bit transitions are detected When the number of bits decoded is incorrect (either too many or too few), a bit error is indicated. When any bit error is detected (bit time, too many bits, too few bits), the decoder will revert to the minimum bit time of the selected range and the message is discarded. The Manchester decoder re-initializes at the start of each timeslot, such that remote sensor frames violating timeslot boundaries will result in the setting of a Manchester Error. All errors are readable through the Sensor Fault Status Register and the RSFLT bit in the Global Status Word Register. When a valid message is correctly decoded, the 10/8 data bits are stored into the appropriate RSDRx register together with the related LCID. The RSDRx register contains the 10/8 bits data as they are received from the sensor (no data range check/mask is done at this stage). The 8-bit data word is right-justified inside the 10-bit data field in the RSDRx registers. Current sensor w/ auto-adjust trip current The current sensor is responsible for translating the current drawn by the sensor into a digital state. Each remote sensor channel has a dedicated current sensor. The current flowing through the RSU power stage is internally downscaled by a factor 100, sent to a 10 bits A/D converter and digitally processed to extract both the sensor quiescent and delta currents. The delta current threshold for signal detection can either be fixed or auto-adjusted to the actual calculated sensor delta current, depending on the FIX_THRESH bit setting in the RSCRx registers. The current trip point is dynamically determined by adding the delta current threshold (fixed/auto-adjusted) to the quiescent current (auto-adjusted). The RSU current is compared against the current trip point to determine the current demodulator digital output. A logic '1' represents the sensor current above the current trip point. The current demodulator output is fed into the Manchester decoder and optionally to the WSx discrete output pins, depending on the configuration of the RSPTEN bit in the RSCRx registers. Thanks to the quiescent and delta current tracking features the receiver is capable to automatically adapt to different nominal sensor currents and/or to be tolerant to sensor current drifts over lifetime. Both the sensor quiescent and delta current tracking algorithms can be configured by setting appropriately the REDUCED_RANGE, BLOCK_CURR_IN_MSG and AVG/SSDIS bits in the RSCRx registers. DocID029257 Rev 1 181/277 276 Remote sensor interface 9.2 L9680 Active wheel speed sensor The remote sensor interface circuit conditions and decodes active wheel speed sensor signals with various pulse widths and output currents. The following sensor types are supported and selected through the Remote Sensor Configuration Register (RSCR) Standard active 2-level wheel speed sensors (7/14 mA) Three level (7/14/28 mA) VDA compliant sensor with direction and air gap information (‘Requirement Specification for Standardized Interface for Wheel Speed Sensor with Additional Information’, Version 2.0) PWM encoded 2-level sensors with 2 edges per tooth (see data sheet Infineon® IC TLE4942/BOSCH DF11) PWM encoded 2-level sensors with 1 edge per tooth (see data sheet Allegro® ATS651LSH/BOSCH DF11) Received wheel speed frames from all the above sensors are decoded into signals suitable for the microcontroller through the four WSx output pins (WS0-WS3). Specific information is shown in Figure 44. For all sensors, other than the standard active 2- level sensor, additional sensor data (diagnostics, etc…) are decoded and available within the Remote Sensor Data Registers (RSDR0, RSDR1, RSDR3, RSDR4). If standard active 2- level sensor is selected the content of the Remote Sensor Data Registers will be NO DATA fault. Only for 2-level sensors (STD or PWM encoded) the user may choose to have all sensor data processed through the microcontroller by selecting pass through mode, WSPTEN, within the Remote Sensor Configuration Register (RSCR). In pass through mode, the remote sensor interface simply transforms the incoming sensor current pulses to digital voltage pulses on the WSx pins, no decoding is performed. The sensor input filter time, deglitch filter (delay until a threshold crossing is detected) can be configured in 15 steps. Filters can be selected individually for each channel, through the Remote Sensor Configuration Register, WSFILT bits. For PWM encoded sensors with 2 edges per tooth not in pass through mode, the standstill signal can be processed directly to the WSx output pins. This is done in the Remote Sensor Configuration Register, SSEN bit. Since the decoder has to measure the pulses in order to determine, whether they are standstill pulses or not, the first standstill pulse will always be seen on the WSx output pins and the first not stand-still pulse after a stand-still period will be suppressed. For 3-levels VDA sensors the device performs parity check on the received data frame. In case a parity error is detected, the INVALID fault bit of the RSDRx register will be set. Data from the sensor are not latched: last incoming frame overwrites the previous one once validated. Faults coming from diagnostic (i.e. over current, short to ground or battery) are latched until the microcontroller reads them. Sensor signal decoding is done according to two possible algorithms: Auto-adjusting current trip points. With this option, the IC is able to find sensor DC current value (named IB0) in the range from 2.5 mA to 21 mA (default is 7 mA). The IC is also able to detect the current value of the data pulse and compute the first threshold (named Ith1): Ith1 = IB0 + Ith1/2 where Ith1 is in the range from 5 mA to 9.3 mA (default is 7 mA). 182/277 DocID029257 Rev 1 L9680 Remote sensor interface Besides, in case of VDA selected, the ASIC is also able to recognize the current value of the speed pulse by computing a second threshold (named Ith2): Ith2 = IB0 + Ith1 + Ith2/2 where Ith2 in the range from 10 mA to 18.6 mA (default is 14 mA) Fixed current trip points where the thresholds are set via SPI. The default value for first threshold is 9.8 mA and for second threshold is 19.6 mA Figure 44. Wheel speed sensor protocols P$ 7KUHHOHYHOFXUUHQW 9'$FRPSOLDQWVHQVRU ZLWK0DQFKHVWHUHQFRGHG LQIRUPDWLRQ , 7+ P$ KLJK KLJK ORZ KLJK ORZ KLJK KLJK KLJK KLJK , 7+ P$ GE GE GE GE GE GE GE GE S , 7+RSHQ :6[SLQ 'DWDDQGGLDJQRVWLFE\63,7KUHHOHYHOVHQVRUVKDYHHLJKWGDWDELWVDQGDSDULW\ELWZKLFKDUHZULWWHQLQWRWKHUHJLVWHUXSRQ UHFHLYLQJ$WKLJKHUVSHHGQRWDOOELWVFDQEHWUDQVPLWWHG7KHGDWDUHJLVWHUIRUHDFKZKHHOFRQWDLQVWKHQXPEHURIGDWDELWV UHFHLYHGEHWZHHQWZRVSHHGSXOVHV P$ 7ZROHYHOFXUUHQW 6WDQGDUGFRPSOLDQWVHQVRU ZLWKRQO\VSHHGLQIRUPDWLRQ , 7+ P$ :6[SLQ 'DWDE\:6[SLQ3DVVWKURXJKPRGH P$ 7ZROHYHOFXUUHQW3:0 2QHSXOVHSHUWRRWKZLWKGDWD HQFRGHGLQSXOVHZLGWK , VULJKWURWDWLRQ P$ 7+ VOHIWURWDWLRQ V V V V 3DVVWKURXJKPRGH :6[SLQ 'DWDE\:6[SLQDQGGXW\F\FOHE\63, QRUPDOPRGH P$ 7ZROHYHOFXUUHQW3:0 7ZRSXOVHVSHUWRRWKZLWK GDWDDQGGLDJQRVWLFHQFRGHG LQSXOVHZLGWK , 7+ P$ V Q[V 3DVVWKURXJKPRGH :6[SLQ 'DWDE\:6[SLQDQGGXW\F\FOHE\63, QRUPDOPRGH *$3*36 DocID029257 Rev 1 183/277 276 Remote sensor interface 9.2.1 L9680 Wheel speed data register formats When programmed as a wheel speed sensor interface, only four data registers are used (Remote Sensor Data Register RSDR0-RSDR3). Independent data registers are defined for each wheel speed channel and their contents are determined by sensor type. Three level VDA sensors have eight data bits and. At fast wheel speed not all bits may be transmitted by the sensor: the IC is able both to process normal or either truncated frames by providing together with data, a 4 bit counter to inform the microcontroller about the number of received valid bits. For PWM encoded sensors, each pulse length is written to the sensor data register with a typical resolution of 5 μs per bit. In case of pulse width duration equal or higher than TSTANDSTILL_TH_L and less or equal than TSTANDSTILL_TH_H2, the standstill condition will be recognized and bit 15 in the corresponding register will be set. The register is updated when a PWM falling edge is detected; in case of stuck-at 1 of the PWM signal the register is updated when the counter reaches the overflow value (0x1FF): in this case the standstill bit not set and the counter in overflow will signal a fault to the microcontroller. 9.2.2 Test mode In order test the input structures of the connected microcontroller, the L9680 features a wheel speed test mode that allows test patterns to be applied on the four wheel speed outputs WS0-WS3. The test mode can be entered via SPI and the test patterns can also be controlled via SPI commands. Test patterns can be composed only of static high or low signals, which can be selected via SPI. For failsafe reasons only one channel at a time can be switched into test mode. 9.3 Remote sensor interface fault protection 9.3.1 Short to ground, current limit Each output is short circuit protected by an independent current limit. Should the output current level reach or exceed the ILIMTH for a time period greater than TILIMTH or the remote sensor interface the output stage is disabled. An internal up-down counter will count in 25 μs increment up to TILIMTH. The filter time is chosen in order to avoid false current limit detection for in-rush current that may happen at interface switch-on. When the output is turned off due to current limit, the appropriate fault code STG is set in the Remote Sensor Data Register (RSDR). The fault timer latch is cleared when the sensor channel is first disabled and then re-enabled through the Remote Sensor Control Register (RSCTRL). This fault condition does not interfere neither with the normal operation of the IC, nor with the operation of the other channels. When a sensor fault is detected, the RSFLT bit of the GSW is set indicating a fault occurred and can be decoded by addressing the RSDR register. In order to fulfill the blanking time requirement at channel activation as per PSI-5 specification, a dedicated masking time is applied to the current limitation fault detection each time a channel is activated. 184/277 DocID029257 Rev 1 L9680 9.3.2 Remote sensor interface Short to battery All outputs are independently protected against a short to battery condition. Short to battery protection disconnects the channel from its supply rail to guarantee that no adverse condition occurs within the IC. The short-to-battery detection circuit has input offset voltage (10mV, minimum) to prevent disconnecting of the output under an open circuit condition. A short to battery is detected when the output RSUx pin voltage increases above SATBUCK or SYNCBOOST (depending on operation) supply pin voltage for a TSTBTH time. An internal up-counter will count in 1.5 μs increment up to TSTBTH. The counter will be cleared if the short condition is not present for at least 1.5 μs. The channel in short to battery is not shut down by this condition. Other channels are not affected in case of short of one output pin. As in the case previously described, the STB fault code can be read from RSDR bits and any fault will set the RSFLT bit of the global status word register (GSW). The STB bit is cleared upon read or upon channel disabled via SPI RSCTRL register. 9.3.3 Cross link The device provides also the capability of a cross link check between outputs, in order to reveal conditions where two output channels are in short. This functionality is allowed by enabling one output channel, while asking for voltage measurement on any of the other ones. 9.3.4 Leakage to battery, sensor open The sensor interface offers also open sensor detection. The auto-adjusting counter for remote sensor current sensing will drop to 0 in case the current flowing through RSUx pin is lower than 2.5 mA typ. The OPENDET fault flag is asserted when the fault condition lasts for longer than TRSUOP_FILT deglitch filter time. This fault flag can be read from RSDR bits and any fault will set the RSFLT bit of the global status word register (GSW). The channel in this condition is not shutdown. This fault bit is cleared upon read or upon channel disabled via SPI RSCTRL register. 9.3.5 Leakage to ground The sensor interface offers as well the detection of a leakage to ground condition, that will possibly raise the sensor current higher than 42 mA/12 mA typ in PSI5/WSS modes respectively. The CURRENT_HI fault flag is asserted when the fault condition lasts for longer than TRSUCH_FILT deglitch filter time. This fault flag can be read from RSDR bits and any fault will set the RSFLT bit of the global status word register (GSW). The channel in this condition is not shutdown. This fault bit is cleared upon read or upon channel disabled via SPI RSCTRL register. 9.3.6 Thermal shutdown Each output is protected by an independent over-temperature detection circuit should the remote sensor interface thermal protection be triggered the output stage is disabled and a corresponding thermal fault is latched and reported through the RSTEMP flag in the Remote Sensor Data Register (RSDRx). The thermal fault flag is cleared when the sensor channel is first disabled and then re-enabled through the Remote Sensor Configuration Register (RSCRx). DocID029257 Rev 1 185/277 276 Watchdog timers 10 L9680 Watchdog timers This device offers a 2-level watchdog control approach. The first control level is given by means of a temporal watchdog (WD1). The WD1 window times are SPI programmable and a couple of specific codes have to be written within this window in order to serve the WD1 control. The second control level is featured by an algorithmic seed/key watchdog (WD2). Unlike the temporal watchdog, the algorithmic watchdog service must be maintained before a timeout occurs, i.e. there is no restriction on refreshing the watchdog too early. Both WD1 and WD2 watchdog functionalities can be tested trough the WD_TEST SPI command. 10.1 Temporal watchdog (WD1) The temporal watchdog ensures the system software is operating correctly by requiring periodic service from the microcontroller at a programmable rate. This service (watchdog refresh) must occur within a time window, and if serviced too early or too late will enter an error state reported via the FLTSR register (WD1_WDR bit). The overall WD1 functionality is described in the state diagram reported in Figure 45. Figure 45. WD1 Temporal watchdog state diagram :60B5HVHW )URPDQ\VWDWH :'B/2&.287 :'B:'5 :'B(55B&17 :'B(55B7+B:( :'B660567250&8B660567 IURPDQ\VWDWH :'770!9:'B29(55,'($1' 63,:'B7(67 :'B/2&.287 PV :'B:'5 PV$1' :'B7295 :'B/2&.287 :'B(55B&17 :'5(6(7 :'B(5525 :'B/2&.287 :'B(55B&17 :' 29(55,'( :',1,7,$/ :'581 :'UHIUHVK2. :'UHIUHVK2. :'B:'5 :'B(55B7+B:( ,I:'B(55B&17:'B5(75<B7+ :'B/2&.287 63,:'B7(67 :'7(67 :'B(5525 *$3*36 Following the description of the WD1 states and signals (most of them reported in related SPI registers) 186/277 DocID029257 Rev 1 L9680 Watchdog timers Table 13. Watchdog timer status description State/Signal WD1 INITIAL Description Default state entered from startup. While in this state, no watchdog service is required, and the IC may stay in this state indefinitely. For system safety, all arming signals are disabled during this state to prevent deployment. WD1 RUN Normal run time state where WD1 service is required. WD1 TEST A special state used to test the watchdog function. Normally, this state will only be checked once per power cycle by the software, but there is no inherent restriction in the watchdog logic preventing periodic testing. This state allows testing of the watchdog without setting WD1_LOCKOUT=1, which can only be cleared via WSM reset. Deployment is inhibited when the WD state machine is in this state. WD1 RESET State entered when a WD1_ERROR occurs. This is a timed-duration state that is automatically exited after 1ms. A special state used to disable watchdog functionality for development purposes. WD1 OVERRIDE Other logic within the IC can use this state to emulate the WD1 RUN state without the need to service WD1. WSM_RESET Signal used to reset the WD1 state machine to the WD1 INITIAL state and all signals to their inactive values WD1_refresh OK Signal that is asserted only if the watchdog is refreshed ('A' - 'B' or 'B' - 'A' seq.) within the WD1 time window WD1_ERROR Signal that is asserted if the watchdog refresh fails to occur during the WD1 time window. WD1_WDR Watchdog Reset – latched signal that is activated whenever a watchdog error is qualified. For WD1, this occurs when WD1 service is required, but not received. This signal is SPI-readable. WD1_TM Test Mode – a signal that indicates that WD1 is being tested. This signal is SPIreadable. A latched signal activated if an unexpected WD1 error occurs. This signal is WD1_LOCKOUT permanently latched when set (until WSM_RESET). When set, all arming signals are disabled, preventing deployment. This signal is SPI-readable. SPI command used to enter WD1 TEST state from WD1 RUN state, or to enter SPI_WD1_TEST WD1 OVERRIDE state from INITIAL state if WDT/TM pin voltage is greater than the threshold. This command has no effect in other states. 10.1.1 Watchdog timer configuration The watchdog timer can be configured on two different frequency modes: Fast watchdog with maximum range of 2ms and a resolution of 8 μs; Slow watchdog with maximum range of 16.3ms and a resolution of 64 μs. The watchdog window times are SPI programmable. The configuration of watchdog timer frequency and window times can be done by setting the Watchdog Timer Configuration Register (WDTCR) with the appropriate values. However, this configuration is accepted only when the device is in the Init operating state, as shown in Figure 10. As soon as the device enters in Diag state, the watchdog control is enabled and the watchdog configuration is fixed and cannot be changed anymore. DocID029257 Rev 1 187/277 276 Watchdog timers 10.1.2 L9680 Watchdog timer operation While in the WD1_INITIAL state, watchdog service must begin or a SPI command with WD1_TO_DIS=1 must be received within the first 500 ms. If the WD1 Timeout Disable bit is set, the device can stay in the WD1_INITIAL state indefinitely without watchdog service. To refresh WD1, the logic must receive a Watchdog Timer Register (WD1T) SPI command containing the expected key value within the WD1 time window (WDTMIN+WDTDELTA). If it is received too early, too late the WD1_ERROR signal will be asserted. The WD1_ERROR will not be asserted in case a SPI command containing the Watchdog Timer Register (WD1T) with an incorrect key value is received at any time relative to the window. This allows the system software to repeatedly transmit the key value until it needs to change to the correct key value. Upon reception of the correct key within the window, the logic will reset the watchdog timer to create a new window. The timer is cleared upon writing code 'A' and code 'B' (either in 'A' - 'B' or 'B' - 'A' sequences) to the WD1CTL [1:0] bits, in the WD1T register. The watchdog timer value can be read via the WD1T register. Figure 46. Watchdog timer refresh diagram 660B5(6(7 :',1,7 63,B:'B% 63,B:'B$ :'$ :'% 63,B:'B% 705 6WUREH:'UHIUHVK2. :'% 705!0,1 63,B:'B$ 705 6WUREH:'UHIUHVK2. 63,B:'B$ 705 6WUREH:'UHIUHVK2. :'$ 705!0,1 63,B:'B% 705 6WUREH:'UHIUHVK2. 705!0$;25 >7050,163,B:'B$@ 705!0$;25 >7050,163,B:'B%@ :'B(5525 '!0'03 188/277 DocID029257 Rev 1 L9680 10.2 Watchdog timers Algorithmic watchdog (WD2) The algorithmic watchdog (WD2) is intended to protect higher software layers, and as such requires servicing at a much slower rate and allows for software jitter as compared with WD1. Additionally, WD2 is not implemented as a window watchdog, but is a maximum-time watchdog, where refresh is accepted at any time before the timer expires. The overall WD2 functionality is described in the following state diagram: Figure 47. Algorithmic watchdog timer flow diagram :60B5(6(7)URPDQ\VWDWH :'B/2&.287 :'B:'5 :'B5HWU\ :'B(55FQW :'B70 6((' ) 35(9B.(< ' :'B(55B7+B:( :'B5(75<B7+B:( 0&8B66056725:'B5(6(7$1'127:'67233,1*25:'6723 :'B70 6((' ) 35(9B.(< ' 63,:'B7(67 :'B/2&.287 :' 29(55,'( :',1,7 63,B:'B.(< WDUJNH\ 705 6((' 6(('&75 WDUJNH\ IQ6(('35(9B.(< 705!0$; 63,B:'B.(< WDUJNH\ ,1,76((' 705 6((' 6(('&75 WDUJNH\ IQ6(('35(9B.(< :'B:'5 :'B/2&.287 :'BUHWU\ :'B(55B7+B:( :'B5(75<B7+B:( 63,:'B7(67 :'B70 63,B:'B.(< WDUJNH\ 705 6((' 6(('&75 WDUJNH\ IQ6(('35(9B.(< 705!0$; 705 :'B5HWU\ :'7(67 705!0$; 705 :'B5HWU\ :'581 63,B:'B.(< WDUJNH\ 705 6((' 6(('&75 WDUJNH\ IQ6(('35(9B.(< 7:'7B567 :'B:'5 :'B70 :'48$/ 63,B:'B.(< WDUJNH\ 705 6((' 6(('&75 WDUJNH\ IQ6(('35(9B.(< :'B5HWU\!:'B5(75<B7+ :'B(55FQW :'B/2&.287 63,B:'B5(&29(5 :'BUHWU\ :'B/2&.287 :' 67233,1* :'/2&. :'B(55FQW!:'B(55B7+ :'B:'5 63,B:'B.(< WDUJNH\ 7:'7B567 705 6((' 6(('&75 WDUJNH\ IQ6(('35(9B.(< 705!0$; :'6723 :'5(6(7 705!0$; *$3*36 DocID029257 Rev 1 189/277 276 Watchdog timers L9680 Following the description of the WD2 states and signals (most of them available through SPI registers) Table 14. WD2 states and signals State / Signal Description WD2 INIT Default state entered from startup or after a SSM reset (if not in WD2 STOP state). WD2 OVERRIDE WD2 INITSEED Special state used to disable WD2 watchdog functionality. State entered when the correct default key is received in INIT state. Here the timer starts to count waiting for the real first key. WD2 RUN Normal run-time state where WD2 service is required. WD2 TEST A special state used to test the watchdog function. Normally, this state will only be checked once per power cycle by the software, but there is no inherent restriction in the watchdog logic preventing periodic testing. This state allows testing of the watchdog without affecting WD2 error (no reset is generated, WD2_LOCKOUT stay low). Only WD2_WDR latch could be set to 1, in this way μC is able to verify the functionality of the watchdog. WD2 QUAL A state used to qualify a number of WD2_ERROR occurrences before action is taken. The intent is to use this state to permit a retry strategy to account for software jitter. WD2 LOCK A state entered after the allowed retries have been exhausted. This is where action is taken due to WD2 service failure. WD2 STOPPING This is a timed-duration state that is automatically exited after 1ms WD2 STOP A state used to prevent continual recovery of WD2 errors using the WD2_KEY key mechanism to restart watchdog service. WD2 RESET State entered when a WD2_ERROR occurs after having been qualified in the WD2_QUAL state (when all retries are exhausted), or when testing the WD2. This is a timed-duration state that is automatically exited after 1ms. WSM_RESET Watchdog State Machine reset – used to force a transition to the WD2 INIT state and reset all signals to their inactive states WD2_RETRY Counter that tracks the number of retry attempts. It is incremented each time the logic detects a WD2 error while qualifying the error. WD2_WDR Watchdog Reset – latched signal that is activated whenever a watchdog error is qualified. For WD2, this occurs when WD2 service not received after all retry attempts have previously failed. This signal is SPI-readable. WD2_TM Test Mode – a signal that indicates that WD2 is being tested. This signal is SPI-readable. WD2_LOCKOUT A latched signal that is activated on startup, or whenever a WD2 error is fully qualified (all retry attempts have failed). Recovery is still possible after this is set going into WD2 RUN state. This signal drives the WD2_LOCKOUT output pin. This signal is SPI-readable. SPI_WD2_TEST SPI command used to enter WD2_TEST state or to enter WD2 OVERRIDE state from INIT. TMR2 Timer to count the maximum time limit to receive the correct key SPI_WD2_RECOVER SPI command used to clear retry counter WD2_ERR_CNT 190/277 Counter that tracks the number of WD2 error occurred DocID029257 Rev 1 L9680 Watchdog timers To refresh WD2, the logic must receive a WD2_KEY command containing the expected key value before the WD2 timer expires. If it is received too late the refresh criteria have not been met. The WD2 error is asserted if the refresh does not occur before the end of the timeout. The WD2 error is not asserted if it receives continuously a WD2_KEY command with the correct key. This allows the system software to repeatedly transmit the correct key value at any rate faster than the required timeout. Upon reception of the correct key, the logic will generate a new seed value, then calculate a new key using the new seed and reset the watchdog timer to create a new timeout. When in WD2 INITSEED state, the three steps above are executed anyway. The seed is latched from a free-running counter that starts when WSM is released. The WD2_KEY command is used for transmission of the watchdog key, while WD2_SEED command is used to read the new seed and the previous key. The SEED is generated by latching the value from a free-running counter. The free-running seed counter runs at a rate of fWD2_SEED as specified in Table 29. The key value and seed value are 8-bits in length. The key shall be calculated as follows: (KEY = SEED ‡ PrevKEY + $01) where ‡ denotes a bit-wise XOR operation 10.3 Watchdog reset assertion timer Upon either a WD1 or a WD2 watchdog reset, the watchdog logic will momentarily assert the RESET pin for time duration TWDT1_RST / TWDT2_RST. When the RESET pin has been asserted through the watchdog reset assertion timer, stored faults are maintained and can be read by the microcontroller via SPI following the RESET period. 10.4 Watchdog timer disable input (WDT/TM) This input pin has a passive and active pull-down and is used to disable the watchdog timer. The state of this pin can be read by SPI through the WDT/TM_S bit in the GSW register. When WDT/TM pin is asserted, the watchdog timer is disabled, the timer is reset to its starting value and no faults are generated. The WDT/TM input pin must not be biased HIGH (WDT/TM > VWDTDIS_TH) prior to POR in order to have a proper start-up. DocID029257 Rev 1 191/277 276 DC sensor interface 11 L9680 DC sensor interface L9680 implements a circuitry able to interface with a variety of positioning sensors. The sensors that can be connected to the device are Hall-effect, resistive or simple switches. Range of measurements is: Resistive sensor: 65 Ωto 3 kΩ Hall-effect sensor: 1 mA to 2 0 mA. Within the above ranges, accuracy of ±15% is granted. A reduced accuracy is given in the range 1 mA to 2 mA. Hall sensor and switch interface block diagram is shown below. Figure 48. DC sensor interface block diagram 6<1&%2267 %ORFNVVKDUHGPXOWLSOH[HG DPRQJWKHWKHGLIIHUHQWFKDQQHOV 9%* ,'&6 $[5 5 ,OLP 5 9,179 5 ,'&6 5 08; $'&0$,1 92))B'&6 '&6[ 5 9LQ ELWV 9UHI 9UHI Y Q)·Q) ,5()B'&6 ,3'B'&6 9*1' 9 9LQ ELWV 9UHI $'&,'&6 *$3*36 The global SPI contains several bits to control and configure the interface. The SWOEN bit is used to enable the output voltage on DCSx pins. The channel to be activated can be chosen by accordingly setting CHID bits. The interface activation is started and switched off upon user SPI command. Alternatively it could be configured via the SYS_CFG(EN_AUTO_SWITCH_OFF) bit to automatically switch off as soon as the measurement is complete, in case of current or resistance measurements; this would help preventing thermal conditions. The interface would not auto-switched off in case of voltage measurement, instead. 192/277 DocID029257 Rev 1 L9680 DC sensor interface The voltage and current for the selected channel are made available to the main ADC by selecting the proper channel and enabling the measurement process by dedicated DIAGCTRLx commands. The device offers the capability to actively keep all the DCSx lines discharged by means of a weak pull down. The pull down is active by default on all channels and it is deactivated in either of the following cases: 1. when the voltage source is active on the relevant channel 2. when a voltage measurement is requested on the relevant channel 3. if SPI bit SWCTRL(DCS_PD_CURR) is set (global pull-down disable for all channels) In case of Hall-effect sensors, a single current measurement is processed. The current load needed for regulating the pin is internally reflected to a reference resistance, whose voltage drop is then measured through the internal ADC converter. When resistive or switch sensors are used, a more complex measurement is performed. In a first step the current information as above described is provided. Then, also the information on the voltage level achieved on the output pin is provided via ADC. By processing these two values, the micro-controller can understand the resistive value. The DCSx voltage is internally rescaled by a voltage divider into the ADC converter voltage range as shown in Figure 48. Additionally a positive voltage offset is internally applied to the scaled voltage in order to allow voltage measurement capability for DCSx down to -1V. In order to get accurate resistive information even in case of an external ground voltage shift on the sensor of up to +/-1V, the voltage measurement step actually needs two DCSx voltage measurements. A first voltage measurement has to be done with selection of 6.25V on the output channel and a second one with the regulator switched off. The difference between the two measurements will cancel out the offsets (both external ground shift and internal offset). The DCSx current and voltage can be retrieved from ADC readings according to the following formulas and related parameters specified in the Electrical Characteristics section. I REF_DCS I DCSx = 100 ------------------------- DIAGCTRLn ADCRESn @DIAGCTRL(ADCREQn = $04 ADC RES 2 ADC REF_hi V DCSx = RATIO VDCSx ------------------------------ DIAGCTRLn ADCRESn – V OFF_DCSx – ADC RES 2 – VOFF_DCSx · (RATIOVDCSx –1) @DIAGCTRLn(ADCREQn) = $03 The DCSx sensor resistance can be calculated according to the following formula: V DCSx V DCSx @(SWCTRL(SWOEN)=1 – V DCSx @(SWCTRL(SWOEN)=0 R sensor = --------------------- = --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------x I DCSx I DCSx @SWCTRL(CHID) = x The device provides also the capability of a cross link check between outputs, in order to reveal conditions where two output channels are in short. This functionality is allowed by enabling one output channel, while asking for voltage measurement on any of the other ones. DocID029257 Rev 1 193/277 276 DC sensor interface L9680 Each output is protected against Overload conditions by current limit Ground offset between the ECU and the loads of up to ±1 V. Loss of ECU battery Loss of ground Unpowered shorts to battery Shorts to ground 11.1 Passenger inhibit interface L9680 provides a feature to deactivate passenger restraint devices based on a preprogrammed mask. It generates a signal (PSINHINT) based on microcontroller-initiated measurements performed on DC Sensor channel 0. The PSINHINT signal is bitwise ANDed with the LOOP_MATRIX_PSINH mask register, allowing selective deactivation of squib loops independent of microcontroller control. This signal is also inverted and output on the PSINHB pin of the IC to activate externally controlled squib loops. Figure 49. Passenger inhibit logic diagram 6:&75/&+,' µ¶ 6<6B&)*'&6B3$'B9 $'&5(4B\>@ '&6[B, $'&5(4B\>@ '&6[B9 6$),1*VWDWH '&621 1(:'$7$B\ $'&5(6B\>@ ,QZLQGRZ 3$'7+5(6+B/2 'RZQ&75 B 6(7 WRV B 3$'7+5(6+B+, 6605(6(7 36,1+B32/ 2XWVLGHZLQGRZLQK ,QVLGHZLQGRZLQK '(3B',6$%/('VWDWH &/5 (1 +] 36,1+,17 ',$*VWDWH '67(6736,1+ 36,1+% 36,1+6(/ *$3*36 An upper and lower threshold is preprogrammed via SPI by writing the desired 10-bits values into the PADTHRESH_HI and PADTHRESH_LO registers during the Diag state. These thresholds define the measurement window where the passenger restraints are active. Any measurement outside this window will result in the assertion of the PSINHINT signal (as described below), thereby deactivating the squib loops identified in the PSINH mask. The PSINH mask is also preprogrammed during the Diag state. 194/277 DocID029257 Rev 1 L9680 DC sensor interface Another control (DCS_PAD_V bit in SYS_CFG register) is preprogrammed to select either a voltage measurement or a current measurement on DCS0 for this purpose. The automated control of the PSINHINT signal occurs when the microcontroller runs diagnostic testing of the DCS0 interface. A 1 second timer is included to ensure the diagnostic test is run periodically. When the timer expires (down-counts to 0), the PSINHINT signal is asserted. When the measurement of the DCS0 voltage or DCS current (as selected by the DCS_PAD_V bit) is taken, and the value falls within the preprogrammed window, the timer will be reloaded. If the measurement is outside the window, the timer will not be reloaded, and it will continue to count down until it expires, resulting in activation of PSINHINT. For testing purposes, the PSINHINT can be controlled directly via SPI while in DIAG state using the Diag State Test Selection (DSTEST) register. DocID029257 Rev 1 195/277 276 Safing logic L9680 12 Safing logic 12.1 Safing logic overview The integrated safing logic uses data from on-board and remote locations by decoding the various SPI communications between the interfaces and the main microcontroller. The safing logic has several programmable features enabling its ability to decode SPI transmissions and can process data from up to 16 sensors. The operating mode involves simple symmetrical data threshold comparisons, with the use of symmetrical or asymmetrical counters. A high level diagram is shown in the figure below. Please note that this top-level diagram is simplified, and references more detailed flowcharts to show a) message decoding, b) valid data limits, c) effects of the 'combine' function, d) comparison to thresholds and arming, and e) the setting of the 'compare complete bit. Four independent arming outputs, ARM1INT, ARM2INT, ARM3INT and ARM4INT, are also mapped internally to any of the integrated squib drivers. Figure 50. Top level safing engine flow chart '&8,&6DILQJ/RJLF 7RS/HYHO 67$57 1 63,B06* 5HFHLYHG" < &6B* 63,B6$)B&& 5HDG" < 1 &KHFNVZKHWKHUUHTXHVWDQGUHVSRQVH DUHJRRGIRUHDFKELWVDILQJUHFRUG WDNLQJLQWRDFFRXQW,)ELW'HWHUPLQHV '$7$WDNLQJLQWRDFFRXQW63,)/'6(/ ELW &KHFNVZKHWKHUUHTXHVWDQGUHVSRQVH DUHJRRGIRUHDFKELWVDILQJUHFRUG WDNLQJLQWRDFFRXQW,)ELW 8SGDWHVHYHQWFRXQWHUV LIQRGDWDUHFHLYHG FOHDUV&&ELWV $ * 06*'(& &&B5($' % + % VHW$50,17DQG $50,17PDQDJHGZHOO WLPHUV $50,1* 06*'(& & &KHFNVZKHWKHUGDWDLVZLWKLQUDQJHLI FRQILJXUHG & 9$/'$7 ' &RQYHUWVGDWDWREHFRPSDUHGLQWR FRPELQHGGDWDVXPDQGGLIIHUHQFHLI FRQILJXUHG ' &20%,1( ( ( &RPSDUH'$7$WRWKUHVKROGV XSGDWH HYHQWFRXQWHUV &203$5( ) *$3*36 196/277 DocID029257 Rev 1 L9680 12.2 Safing logic SPI sensor data decoding Sensor data is regularly communicated with the main microcontroller through multiple SPI messages. The L9680 monitors SPI traffic on MISO_RS bus. Since not all communications between sensors and the microcontroller contain data, it is important for the decoder to properly sort the communications and extract only the targeted data. The solution involves defining specific masking functions, contained within independent safing records, programmed by the user. The following figures detail the SPI message decoding methodology and the ensuing comparisons of valid sensor data to the programmed thresholds. Figure 51. Safing engine – 32-bit message decoding flow chart L 6DILQJ5HFRUGLQGH[ 65 65 65 65 $ 06*'(& L (1B6$)L " 1 < 1 &&>L@ " < &6>L@ FVBDFWLYH" 1 < ,)>L@ " 1 UHTBRN>L@ " < 1 < 63,)/'6(/>L@" QG 63,)/'6(/>L@" VW VW 1 QG 5(637$5*>L@ VW>0,62@ 5(630$6.>L@ 5(637$5*>L@ QG>0,62@ 5(630$6.>L@ < PDWFK>L@ UHTBRN>L@ < GDWDUHVXOW>L@ VW>0,62@ '$7$0$6. >L@ 1 1 5(637$5*>L@ QG>0,62@ 5(630$6.>L@ < < GDWDUHVXOW>L@ VW>0,62@ '$7$0$6. >L@ GDWDUHVXOW>L@ QG>0,62@ '$7$0$6. >L@ PDWFK>L@ 5(637$5*>L@ VW>0,62@ 5(630$6.>L@ 1 PDWFK>L@ UHTBRN>L@ GDWDUHVXOW>L@ QG>0,62@ '$7$0$6. >L@ PDWFK>L@ 5(47$5*>L@ 06>026,@ 5(40$6.>L@" PDWFK>L@ PDWFK&&>L@ UHTBRN>L@ 1 < PDWFK>L@ PDWFK&&>L@ 5(47$5*>L@ 06>026,@ 5(40$6.>L@" PDWFK>L@ 1 < L 1 L 1" UHTBRN>L@ 1 / 1 / 1 / % < DocID029257 Rev 1 UHTBRN>L@ 2XWSXWVWR9$/'$7IXQFWLRQ GDWDUHVXOW>L@ UHTBRN>L@ PDWFK>L@ *$3*36 197/277 276 Safing logic L9680 Figure 52. Safing engine – 16-bit Message decoding flow chart % L " /VNLSVELW UHFRUGV < 1 L 6DILQJ5HFRUGLQGH[ 65 65 65 65 L 06*'(& L 1" 1 / 1 // < 1 (1B6$)L " & 1 < 1 &&>L@ " < &6>L@ FVBDFWLYH" 1 < ,)>L@ " 1 1 < UHTBRN>L@ " < UHTBRN>L@ 5(637$5*>L@ 0,62 5(630$6.>L@ 5(637$5*>L@ 0,62 5(630$6.>L@ 1 < < GDWDUHVXOW>L@ 0,62 '$7$0$6. >L@ 0DWFK>L@ GDWDUHVXOW>L@ 0,62 '$7$0$6. >L@ 5(47$5*>L@ 026, 5(40$6.>L@" 5(47$5*>L@ 026, 5(40$6.>L@" 1 < PDWFK>L@ 1 PDWFK>L@ 1 < PDWFK>L@ PDWFK>L@ UHTBRN>L@ UHTBRN>L@ 2XWSXWVWR9$/'$7IXQFWLRQ GDWDUHVXOW>L@ PDWFK>L@ L *$3*36 198/277 DocID029257 Rev 1 L9680 Safing logic Figure 53. Safing engine - Validate data flow chart L 6DILQJ5HFRUGLQGH[ 65 65 65 65 9$/'$7 & L 0DWFK>L@ &20%>L@ < 1 1 &KHFNVIRUFRPELQDEOH UHFRUGV = / = / = / L= &20%>L@ < &KHFNVIRURGGLQGLFHV 1 0RGL < 1 0DWFK>L@ 0DWFK&&>L@ < 1 0DWFK>L@ 0DWFK&&>L@ < &&>L@ 1 &&>L@ " < < /,0(1>L@ " 1 /,06(/>L@ " < 1 $EV GDWDUHVXOW>L@ G" $EV GDWDUHVXOW>L@ G" 1 1 < < YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ YDOGDW>L@ YDO&&>L@ L L < L /" 1 L 1 L 1" 1 / 1 / 1 / < ' 2XWSXWVWR&20%,1( IXQFWLRQ &&>L@ YDOGDW>L@ YDO&&>L@ *$3*36 DocID029257 Rev 1 199/277 276 Safing logic L9680 Figure 54. Safing engine - Combine function flow chart L 6DILQJ5HFRUGLQGH[ 65 65 65 65 ' &20%,1( L 9DO&&>L@ YDO&&>L@ " 1 < &20%>L@ " 1 < WHPS GDWDUHVXOW>L@ GDWDUHVXOW>L@ WHPSGDWDUHVXOW>L@ 1 &20%>L@ " < WHPS GDWDUHVXOW>L@ GDWDUHVXOW>L@ WHPSGDWDUHVXOW>L@ L L 1 1 / 1 / 1 / L 1" < ( 2XWSXWVWR&203$5(IXQFWLRQ GDWDUHVXOW>L@ &&>L@ FRPS>L@ *$3*36 200/277 DocID029257 Rev 1 L9680 Safing logic Figure 55. Safing engine threshold comparison ( &203$5( L 1 9DOGDW>L@ " < GDWDUHVXOW>L@ 6$)B7+5(6+>L@ GDWDUHVXOW>L@ 6$)B7+5(6+>L@ 1 326B&2817>L@ 326B&2817>L@ 68%B9$/ 326B&2817>L@ 326B&2817>L@ $''B9$/ 326B&2817>L@ " 1(*B&2817>L@ 1(*B&2817>L@ $''B9$/ 1 1(*B&2817>L@ 1(*B&2817>L@ 68%B9$/ 1(*B&2817>L@ " < < 1 12B'$7$ " < < < 1 326B&2817>L@ 326B&2817>L@ 68%B9$/ 1(*B&2817>L@ 1(*B&2817>L@ 68%B9$/ 1(*B&2817>L@ 326B&2817>L@ 1(*B&2817>L@ " 326B&2817>L@! $503B7+" 1 1(*B&2817>L@! $501B7+" 1 1 1(*B&2817>L@ $501B7+ 326B&2817>L@ " 1 < 1(*B&2817>L@ < < 326B&2817>L@ $503B7+ 1(*B&2817>L@ 326B&2817>L@ < 326B&2817>L@ 0DWFK>L@ YDOGDW>L@ L L < L 1 L /" < 1 1 / 1 / 1 / L 1" < ) *$3*36 DocID029257 Rev 1 201/277 276 Safing logic L9680 Figure 56. Safing engine - Compare complete * &&B5($' L < &&>L@ " 1 1 12B'$7$>L@ " < 326B&2817>L@ 326B&2817>L@ 68%B9$/ 1(*B&2817>L@ 1(*B&2817>L@ 68%B9$/ 1(*B&2817>L@ " 1 1(*B&2817>L@ 326B&2817>L@ " 1 < 1(*B&2817>L@ < 326B&2817>L@ 326B&2817>L@ &&>L@ YDO&&>L@ PDWFK&&>L@ L < L /" 2XWSXWV &&>L@ PDWFK>L@ PDWFK&&>L@ 326B&2817>L@ 1(*B&2817>L@ 1 L 1 L 1" 1 / 1 / 1 / < + *$3*36 202/277 DocID029257 Rev 1 L9680 Safing logic Each safing record has SPI accessible registers defined in the SPI command tables and summarized below: Request Mask and Request Target - to understand what sensor the microcontroller is addressing Response Mask and Response Target - to identify the sensor response Data Mask - to extract relevant sensor data from the response. – Sensor data is extracted as a bit-wise AND result of the SAF_DATA_MASKx and monitored RS_MISO data. The configuration of the set bits of the DATAMASK must be contiguous for both 16-bit and 32-bit records. The 32-bit records are comprised of Part1 as MSW and Part2 as LSW. – The extracted data is then right justified into a 16/32 bit register for 16/32 bit safing records, respectively, prior to further processing steps which assume data is signed should be "using two's complement representation". Safing Threshold - specific value that sets the comparator limit for successful arming Control: – IF, In Frame - to indicate serial data response is ‘in frame’. There are two types of potential serial data responses, ‘in frame’ and ‘out of frame’. – CS - to align safing record with a specific SPI CS. The device contains 5 SPI CS inputs for the safing function (CS_RS, SAF_CSx) – ARM - there are four internal arming signals, each active record is assigned or mapped to any arming signal. Several safing records can be mapped to a single arming output. ARMx outputs can be enabled also simultaneously. – Dwell - Once an arming condition is detected, the safing record remains armed for the specified dwell time. – Comb (Combined Data) - specific solution for dual axis high-g sensors specifically oriented off-axis. – LimEn (Limit Enable) - to enable PSI5 out-of-range control. – LimSel (Limit Select) - to select PSI5 out-of-range thresholds between 8-bit and 10-bit protocol. – SPIFLDSEL (SPI Field Select) - to determine which 16-bit field in long SPI messages (>31 bit) to use for response on MISO of SPI monitor. Don't care for messages less than 32 bits. If input packet matches multiple safing records, the safing engine should process all of them and treat them independently. Safing record can only be evaluated on the first matching input packet. Any further data packet matches are ignored (i.e. once CC is set, record can't be processed until CC is cleared) The En (Record Enable) bit for any record is programmable as on or off at any time and will enable/disable the record itself upon the following SATSYNC. All CC bits are available in one register (SAF_CC) for access in one single SPI read. After ARMing is achieved and CC is set, no further messages are considered until CC is cleared via read. Safing Engine must not process sensor data in any state but Safing state (refer to Figure 10). All safing records are cleared on SSM RESET. DocID029257 Rev 1 203/277 276 Safing logic L9680 Comb (Combined Data) bit allows combining X and Y for off-axis oriented sensors. In this case, it is typical for such orientations to add or subtract the sensor response to translate the sensor signal to an on-axis response. Only couples of 16-bit long records have this feature (i.e. 1&2, 3&4, 5&6, 7&8, 9&10, 11&12). Records are added and subtracted and results compare against two thresholds. Safing engine will process data as follows: Use record(n) and record(n+1), where n = 1, 3, 5, 7, 9, 11. The matching inputs used for math combinations are processed only after both are captured. The sum of the two matching inputs will be compared to the threshold of record(n). The difference of the two records will be compared to the threshold of record(n+1). If the Comb feature was enabled on only one of the two records in a couple, math would be performed only on it as shown in Figure 55 Example of Combine Function operation: Table 15. Example of combine function operation Record # Combine Bit Data Resulting value Record Threshold ARMSELx Configuration ARMINTx Result Record 1 0 12 12 48 ARMP 0 Record 2 0 50 50 48 ARMP 1 Record 3 0 12 12 48 ARMP 0 Record 4 1 50 50 – 12 = 38 48 ARMP 0 Record 5 1 12 12 + 50 = 62 48 ARMP 1 Record 6 0 50 50 48 ARMP 1 Record 7 1 12 12 + 50 = 62 48 ARMP 1 Record 8 1 50 50 – 12 = 38 48 ARMP 0 Record 9 1 50 50 + 12 = 62 -24 ARMN 0 Record 10 1 12 12 – 50 = -38 -24 ARMN 1 All items in the safing records, except En(Record Enable) bit, can be configured only in Diag state (refer to Figure 10). Additionally, the global bit to select internal or external safing engine is set in Init state. 12.3 In-frame and out-of-frame responses Some sensors will communicate data within the current communication frame while others will send data on the next communication frame. Sometimes this is sensor specific and sometimes this is due to the amount of data to be transmitted. A simplified diagram shows the basic communication differences of in and out of frame responses. In-frame example: 204/277 DocID029257 Rev 1 L9680 Safing logic Figure 57. In-frame example -/3) 2EQUESTN -)3/ 3TATUS 5NUSED 2ESPONSEN '!0'03 At least one bit needed to allow for synchronization between clock domains (SPI clock and system clock). Out-of-frame example: Figure 58. Out-of-frame example -/3) 2EQUESTN 2EQUESTN -)3/ 2EQUESTN 2ESPONSEN '!0'03 Synchronization between clock domains relies upon inter-frame gap. 12.4 Safing state machine operation State machine operation is disabled when the safing state machine reset signal is active as described in the power supply diagnostics and controls section of this document. The outputs of the state machine are ARMxREQ. As previously stated, there is a maximum of 16 safing records available to the state machine. Inputs to the safety state machine are programmed safing records and sensor data. The configuration of the state machine is common to all sensors. 12.4.1 Simple threshold comparison operation In this mode, sensor data received through the sensor SPI interface and validated by the safing record is passed to the safing algorithm. The simple threshold comparison algorithm compares the received data to two thresholds, SAF_TH (positive threshold) and (-SAF_TH) (negative threshold). If the sensor data is greater than SAF_TH or is less than (-SAF_TH) then and event is flagged and the event counter is incremented based on the programmed value of ADD_VAL. If sensor data does not trigger the SAF_TH comparators, the counter is decremented by SUB_VAL. SUB_VAL is programmed by the user and can be same or different than ADD_VAL. This feature allows for an asymmetrical counter function making the system either more or less sensitive to sensor data. Since sensor data can indicate a positive or negative event, the algorithm maintains separate event counters, POS_COUNT and NEG_COUNT. ADD_VAL and SUB_VAL programmed values are the same for both event counters. On each sensor sample, the event counters, POS_COUNT and NEG_COUNT, are updated based on the SAF_TH comparators. Likewise, each event counter is compared with a corresponding arming threshold. In this case, POS_COUNT value is compared to ARMP_TH and NEG_COUNT to ARMN_TH. ARMP_TH and ARMN_TH are programmable thresholds set by the user. The compared result will set ARMP and ARMN to either ‘1’ or ‘0’ depending on the comparison status. If ARMP_TH or ARMN_TH are set to 0, the arming will be activated immediately entering in safing state. DocID029257 Rev 1 205/277 276 Safing logic L9680 POS_COUNT and NEG_COUNT are not updated if microcontroller stops reading SAF_CC bits (this must be avoided otherwise ARMING set and reset will not be possible). By way of the assignment of the ADD_VAL, SUB_VAL, ARMP_TH and ARMN_TH settings, the safing engine can be configured to assert arming for either a simple accumulation of COUNTs in a non-consecutive manner, or it could be set to require some number of consecutive samples. 12.5 Safing engine output logic (ARMxINT) SPI messages are monitored and mapped to specific safing records. Each safing record is configured with its own threshold, dwell time and the appropriate ARMxINT signal to activate if safing criteria are met. Any enabled safing record can be programmed to an arming signal. All safing records arming status is logically ‘OR'd’ to its programmed arming signal. For example, if safing records 1, 2, 4 are programmed to ARMINT1 and the records are enabled, any of the records can set the ARMINT1 signal. Configuration of safing record mapping to ARMxINT signals is specified in the in the SAF_CONTROL_x register (refer to Table 67). While in Diag state, L9680 allows diagnostics of the squib driver HS and LS FETs, ARM pins, VSF output and firing timers. The ARM and VSF output tests are mutually exclusive. For safety purposes, the safing logic circuitry is physically separated from the circuitry that contains the deployment logic. 206/277 DocID029257 Rev 1 L9680 Safing logic Figure 59. Safing engine arming flow diagram 67$57 L 326B&2817>L@ ! $503B7+" 1 1(*B&2817>L@ ! $501B7+" < 1 $503 < $503 $501 $506(/>L@ RU" $506(/>L@ RU" < $501 1 < 1 7,0(5B&17[LVDELW GRZQFRXQWHUDOZD\V UXQQLQJDWPV 1 $50>L@ 7,0(5B&17 ':(//>L@ $50>L@ 7,0(5B&17 ':(//>L@ < 1 7,0(5B&17[FRQWURO H[WHQGVWRIRUKLJKPLG < 7,0(5B&17 ':(//>L@ 7,0(5B&17 ':(//>L@ L 7,0(5B&17 !" 1 L 1" 1 7,0(5B&17 !" < 1 $50[,17FRQWUROH[WHQGV WRIRUKLJKPLG < $50,17 $50,17 $50,17 $50,17 < 1 / 1 / 1 / *$3*36 DocID029257 Rev 1 207/277 276 Safing logic L9680 Figure 60. Safing engine diagnostic logic 6&/.B56 026,B56 0,62B56 &6B56 6$)B&6 6$)B&6 6$)B&6 6$)B&6 63,'HFRGH 7KUHVKROG &RPSDUH 3XOVH 6WUHWFK '6B7(6796) ',$*67$7( $505(4 '67(67$50 '67(6738/6( 38/6(B7(67 38/6(B7(67 $505(4 '67(67$50 $505(4 '67(67$50 $505(4 '67(67$50 $50,1*67$7( *$3*36 A configurable mask for each internal ARMxINT signal is available for all of the integrated deployment loops. The un-masked ARMxINT signal for each loop will enable the respective loop drivers. Activation of VSF (regulation rail for High Side Safing FET) occurs upon ARMxINT. Actual High Side Safing FET activation still requires microcontroller signal. L9680 is able to provide arming signals to external deployment loops by means of four discrete output ARMx pins. 208/277 DocID029257 Rev 1 L9680 Safing logic Figure 61. ARMx input/output control logic 660B5(6(7 :'B/2&.287 :'B581 :'B/2&.287 :'B29(55,'( 3XOVHWHVW37B[VWDWH [ :$,7RU $50,17 $505(4 $50 $50,17 $505(4 6DILQJ (QJLQH $50 $50,17 $505(4 $50 $50,17 $505(4 $50 6$)(6(/ *$3*36 12.5.1 Arming pulse stretch Upon a valid command processed by the safing logic, the Dwell bit to stretch the arming time assertion (dwell time) applies to each safing record and is used to help safe the deployment sequence to avoid undesired behaviour. Once dwell time has started, it will continue, regardless of the En (Record Enable) bit. Dwell will be truncated in case of SSM reset. Dwell values in the safing records are transferred to the ARMx signals. A dedicated counter is designed for each ARMx output pin. If different dwell values are assigned to the same ARMx, the longer value is used. Dwell times can only be extended, not reduced. If the remaining dwell time is less than the new dwell extension setting, the new setting will be loaded into the dwell counter. Dwell times are user programmable. The behaviour of the pulse stretch timer is shown below. DocID029257 Rev 1 209/277 276 Safing logic L9680 Figure 62. Pulse stretch timer example $UPLQJ6DILQJ/RJLF 3URFHVVHGUHVXOW $UPLQJ(QDEOH 3XOVH6WUHWFK 3XOVH6WUHWFK7LPH /HVV7KDQ3XOVH 6WUHWFK7LPH 3XOVH6WUHWFK 7LPH '!0'03 The Arming Enable Pulse Stretch Timer status is available in the AEPSTS register. 12.6 Additional communication line The ACL pin is the Additional Communication Line input that provides a means of safely activating the arming outputs (ARMx and VSF) for disposal of restraints devices at the end of vehicle life. The handshake sequence for activating the Arming outputs is illustrated in Figure 63. The strategy involves generation of a seed value from within the L9680 device using a freerunning 8-bit counter running at fSCRAP_SEED rate, where it can be read by the microcontroller. The microcontroller uses it to generate an 8-bit key value. When the seed value is read (SPI SCRAP_SEED command), L9680 also freezes the seed value and computes its own key, which is used for comparison to the key subsequently submitted by the microcontroller. The key value is submitted by the microcontroller using the SCRAP_KEY command, and successful reception of this command with a key value matching the internally calculated key allows the successful completion of the first handshake. After that, in case a second handshake (seed-key) completes successfully and if a valid ACL is detected (as described below) the L9680 transitions from Scrap state to Arming state. To remain in Arming state the microcontroller must periodically refresh L9680 with the SCRAP_KEY command containing the correct key value in the data field of the command, and L9680 must also receive the correct ACL signal. This must occur before the scrap timeout timer expires (TSCRAP_TIMEOUT). The scrap key is derived from the seed value using a simple logical inversion on the even-numbered bits (0, 2, 4, 6). From a logical standpoint, this is equivalent to a bit-wise XOR of the seed value with 0x55. While the SSM is in Arming state, the arming outputs are asserted (ARMx=1, VSF on). If the periodic scrap key is incorrect, or not received before the timeout expires, or the ACL is not correctly received, the SSM reverts back to the Scrap state, and the arming outputs are deactivated. 210/277 DocID029257 Rev 1 L9680 Safing logic Figure 63. Scrap SEED-KEY state diagram 660B5(6(725 1276&5$3VWDWH25$50,1*VWDWH 6&5$3,1,7 YDOLGBVFUDS 63,B6&5$3B6((' 6((' 6(('&75 7DUJNH\ IQ6((' ZURQJ63,B6&5$3B.(< 6&5$3705!76FUDSBWLPHRXW 25ZURQJ63,B6&5$3B.(< ),5676((' YDOLGBVFUDS 63,B6&5$3B6((' 6((' 6(('&75 7DUJNH\ IQ6((' 63,B6&5$3B.(< WDUJNH\ 6&5$3705 ),567.(< YDOLGBVFUDS 63,B6&5$3B.(< WDUJNH\ 63,B6&5$3B6((' 6((' 6(('&75 7DUJNH\ IQ6((' 6(&21'6((' YDOLGBVFUDS 63,B6&5$3B.(< WDUJNH\ 6&5$3705 63,B6&5$3B6((' 6((' 6(('&75 7DUJNH\ IQ6((' 63,B6&5$3B.(< WDUJNH\ .(< YDOLGBVFUDS 63,B6&5$3B6((' 6((' 6(('&75 7DUJNH\ IQ6((' 63,B6&5$3B.(< WDUJNH\ 6&5$3705 6((' YDOLGBVFUDS 63,B6&5$3B6((' 6((' 6(('&75 7DUJNH\ IQ6((' *$3*36 Figure 64. Scrap ACL state diagram 660B5(6(725 1276&5$3VWDWH$1'127$50,1*VWDWH $&/*22' $&/%$' $&/705 5LVLQJHGJH $&/705 $&/*22' $&/%$' $&/705!7DFOBOR ULVLQJHGJH $&/*22' $&/%$' $&/705 $&/+,*+ )DOOLQJHGJH $&/705!7RQBDFOBOR $&/705!7RQBDFOBKL25 )DOOLQJHGJH$&/7,0(5 7RQBDFOBOR 5LVLQJHGJH25 $&/705!7DFOBKL $&/705 $&/*22' $&/%$' $&//2: $&/705!7DFOBKL $&/*22' $&/%$' $&/705 $&/(5525 *$3*36 DocID029257 Rev 1 211/277 276 Safing logic L9680 A specific waveform needs to be present on ACL input in order to instruct L9680 to arm all deployment loops. L9680 is designed to support the Additional Communication Line (ACL) aspect of the ISO-26021 standard, which requires an independent hardwired signal (ACL) to implement the scrapping feature. The disposal signal may come from either the vehicle's service connector, or the systems main microcontroller, depending on the end customer's requirements. The arming function monitors the disposal PWM input (ACL pin) for a command to arm all loops for vehicle end-of-life airbag disposal. The disposal signal characteristic is shown in Figure 65. To remain in Arming state, at least three cycles of the ACL signal must be qualified (in addition to the periodic KEY value being received from the microcontroller). For the device to qualify the periodic ACL signal, the period and duty cycle are checked. Two consecutive cycles of invalid disposal signal are to be received to disqualify the ACL signal. If the logic detects that the signal is incorrect or missing while in Scrap state, the device will stay in Scrap state; would it happen in Arming state, it will transition to Scrap state immediately. Figure 65. Disposal PWM signal &\FOHWLPH 2QWLPH '!0'03 The disposal PWM signal cycle time and on time parameters can be found in the electrical parameters tables. 212/277 DocID029257 Rev 1 L9680 13 General purpose output (GPO) drivers General purpose output (GPO) drivers The L9680 contains three General Purpose Output (GPO) drivers configurable either as high-side or low-side modes. The drivers can be independently controlled in ON-OFF mode or in PWM mode setting the desired duty cycle value through the GPO Control Register (GPOCTRLx). For low side driver configuration, the GPODx pin is the drain connection of an internal MOSFET and is the current sink for the output driver. The GPOSx pin is the source connection of the internal MOSFET and is externally connected to ground. For high side driver configuration, the GPODx pin will be connected to battery and GPOSx pin will be connected to load's high side. Figure 66. GPO driver and diagnostic block diagram *32)/765*32[',6$%/( *32&5*32[/6 660B5(6(7 5 *32)/765*32[6+257 *32)/765*32[7(03 3:0&7/ *32&5*32[/6 (1 21 (5%2267B2. 9287B*32[B2/ 3:0B&/. N+]V ,2)) *32&75/[>@ 6 ,2))!,65&B7+ 6 ,2)),6,1.B7+B[ 63,:,' µ*32&5¶ &7/ *32)/765*32[2))231 5 *32'[ ,'6 287 ,'6!,2&B*32 ,'6,2/B*32 *326[ 6 *32)/765*32[21231 5 6 *32)/765*32[2& 63,5,' µ*32)/765¶ 5 660B5(6(7 *$3*36 The drivers are configured in one of the two modes through the GPO Configuration Register (GPOCR) register. This hardware configuration is only allowed during the Init and Diag states. When configured as high-side, the drivers need ER Boost voltage to be above the VERBST_OK threshold to be enabled. The default state of all drivers is off. The drivers can be independently activated via SPI control bits on GPO Control Register (GPOCTRLx). In addition, a set point on the GPOCTRLx will control the output drivers in PWM with a 125Hz frequency. If PWM control is desired, user should set the needed set point in the GPOxPWM bits of the GPOCTRLx while activating the interface. When all bits are set to '0', the GPOx output will be disabled. DocID029257 Rev 1 213/277 276 General purpose output (GPO) drivers L9680 PWM control is based on a 125Hz frequency. 6 bits of GPOCTRLx are reserved to this mode, in order to control the drivers with 64 total levels from a 0% to a full 100% duty cycle. When both GPO channels are used in PWM Mode at the same frequency they are synchronized to provide parallel configuration capability. PWM control is implemented through a careful slew rate control to mitigate EMC emissions while operating the interface. The driver output structure is designed to stand -1V on its terminals and a +1V reverse voltage across source and drain. The GPO driver is protected against short circuits and thermal overload conditions. The output driver contains diagnostics available in the GPO Fault Status Register (GPOFLTSR). All faults except for thermal overload will be latched until the GPOFLTSR register is read. Thermal overload faults will remain active after reading the GPOFLTSR register should the temperature remain above the thermal fault condition. For current limit faults, the output driver will operate in a linear mode (ILIM) until a thermal fault condition is detected. Figure 67. GPO Over temperature logic 2YHUWHPS'HWHFW 6 6 5 *32)/765*32[7(03 5 63,*32&75/[>@ 660B5(6(7 63,5,' µ*32)/765¶ 660B5(6(7 *$3*36 The device offers also an open load diagnostics while in ON state. The diagnostics is run comparing the current through the output stage with a reference threshold IOpenLoad: should the output current be lower than the threshold, the open detection flag is asserted. The device is also able to detect a fault condition during the OFF state by means of the Voltage Regulator Current Monitor (VRCM) block. During the OFF state the VRCM block tries to force a voltage VOUT_GPOx_OL (2.5 V) on GPOD pin if LS mode is selected (with a current limitation of ILIM_GPOD_SRC/SINK) or on GPOS pin if the HS mode is selected (with a current limitation of ILIM_GPOS_SRC/SINK) and, at the same, it compares the current sourced or sunk in order to detect if a fault on GPO pins is present. The diagnostic in OFF state is able to detect the open load in both HS and LS modes, the short to ground fault in LS mode and the short to battery fault in HS mode: Table 16. Short to ground fault in LS mode LS MODE GPOxSHORT GPOxOFFOPN 214/277 Interpretation IOFF > ISRC_TH 1 0 Short to ground - ISINK_TH_LS < IOFF < ISRC_TH 0 1 Open IOFF < - ISINK_TH_LS 0 0 Normal DocID029257 Rev 1 L9680 General purpose output (GPO) drivers Table 17. Short to battery fault in HS mode HS MODE GPOxSHORT GPOxOFFOPN Interpretation IOFF > ISRC_TH 0 0 Normal - ISINK_TH_HS < IOFF < ISRC_TH 0 1 Open IOFF < - ISINK_TH_HS 1 0 Short to battery DocID029257 Rev 1 215/277 276 System voltage diagnostics 14 L9680 System voltage diagnostics L9680 has an integrated dedicated circuitry to provide diagnostic feedback and processing of several inputs. These inputs are addressed with an internal analog multiplexer and made available through the SPI digital interface with the Diagnostic Data commands. In order to avoid saturation of high voltage internal signals, an internal voltage divider is used. Figure 68. ADC MUX *$3*36 The diagnostics circuitry is activated by four SPI Diagnostics Control commands (DIAGCTRLx); each of them can address all the available nodes to be monitored, except for what mentioned in Table 18. DIAGCTRLx SPI command bit fields are structured in the following way: DIAGCTRL_A (ADDRESS HEX 3A) 19 18 17 16 15 14 13 12 11 10 9 8 7 MOSI MISO NEWDATA_A 216/277 x 0 0 x x x x x x ADCREQ_A[6:0] DocID029257 Rev 1 x x 6 5 4 3 2 ADCREQ_A[6:0] ADCRES_A[9:0] 1 0 L9680 System voltage diagnostics DIAGCTRL_B (ADDRESS HEX 3B) 19 18 17 16 15 14 13 12 11 10 9 8 7 MOSI MISO x NEWDATA_B 0 0 x x x x x x x 6 5 x 4 3 2 1 0 1 0 1 0 ADCREQ_B [6:0] ADCREQ_B [6:0] ADCRES_B [9:0] DIAGCTRL_C (ADDRESS HEX 3C) 19 18 17 16 15 14 13 12 11 10 9 8 7 MOSI x MISO NEWDATA_C 0 0 x x x x x x x 6 5 x 4 3 2 ADCREQ_C [6:0] ADCREQ_C [6:0] ADCRES_C [9:0] DIAGCTRL_D (ADDRESS HEX 3D) 19 18 17 16 15 14 13 12 11 10 9 8 7 MOSI x MISO NEWDATA_D 0 0 x x x x x x ADCREQ_D [6:0] x x 6 5 4 3 2 ADCREQ_D [6:0] ADCRES_D [9:0] ADCREQ[A-D] bit fields, used to address the different measurements offered, are listed in Table 18 for reference. L9680 diagnostics is structured to take four automatic conversions at a time. In order to get four measurements, four different SPI commands have to be sent (DIAGCTRL_A, DIAGCTRL_B, DIAGCTRL_C and DIAGCTRL_D), in no particular order. In case the voltage to be measured is not immediately available, the desired inputs for conversion have to be programmed by SPI in advance, to allow them to attain a stable voltage value. This case applies to the squib resistance measurement and diagnostics (refer to Loop diagnostics control and results registers) and to the DC sensor measurement (refer to Section 11). CONVRDY_0 bit in GSW is equal to (NEWDATA_A or NEWDATA_B), while CONVRDY_1 bit in GSW corresponds to (NEWDATA_C or NEWDATA_D). Each NEWDATAx flag is asserted when conversion is finished and cleared when result is read out. However result is cleared only when new result for that register is available. When a new request is received it is queued if other conversions are ongoing. The conversions are executed in the same order as their request arrived. The queue is 4 measures long so it's possible to send all 4 requests at the same time and then wait for the results. If a DIAGCTLRx command is received twice, the second conversion request will overwrite the previous one. Requests are sent to the L9680 IC via the ADC measurement Registers (ADCREQx) as shown in Table 18. All diagnostics results are available on the ADCRESx registers, when addressed by the related ADCREQx register (e.g. data requested by ADCREQA would be written to ADCRESA). DocID029257 Rev 1 217/277 276 System voltage diagnostics L9680 Table 18. Diagnostics control register (DIAGCTRLx) ADC Request (ADCREQx) ADC Results (ADCRESx) Voltage Measurement Selection Bit[6:0] Hex Bit[9:0] 0 0 0 0 0 0 0 $00 Unused 0 0 0 0 0 0 1 $01 ADC ground reference VADC_GROUND 0 0 0 0 0 1 0 $02 ADC Test Pattern 2 VADC_FULLSCALE 0 0 0 0 0 1 1 $03 DC Sensor ch. selected, Voltage DCSV_selected 0 0 0 0 1 0 0 $04 DC Sensor ch. selected, Current DCSI_selected (1) 0 0 0 0 1 0 1 $05 DC Sensor ch. selected, Resistance DCSV and DCSI selected 0 0 0 0 1 1 0 $06 Squib measurement loop selected Voutx 0 0 0 0 1 1 1 $07 Internal reference Voltage VBGR 0 0 0 1 0 0 0 $08 Internal reference monitor Voltage VBGM 0 0 0 1 0 0 1 $09 VCOREMON voltage VCOREMON 0 0 0 1 0 1 0 $0A Temperature Measurement TEMP 0 0 0 1 0 1 1 $0B DC Sensor ch 0, Voltage DCSV_0 0 0 0 1 1 0 0 $0C DC Sensor ch 1, Voltage DCSV_1 0 0 0 1 1 0 1 $0D DC Sensor ch 2, Voltage DCSV_2 0 0 0 1 1 1 0 $0E DC Sensor ch 3, Voltage DCSV_3 0 0 0 1 1 1 1 $0F DC Sensor ch 4, Voltage DCSV_4 0 0 1 0 0 0 0 $10 DC Sensor ch 5, Voltage DCSV_5 0 0 1 0 0 0 1 $11 DC Sensor ch 6, Voltage DCSV_6 0 0 1 0 0 1 0 $12 DC Sensor ch 7, Voltage DCSV_7 0 0 1 0 0 1 1 $13 DC Sensor ch 8, Voltage DCSV_8 0 0 1 0 1 0 0 $14 VB voltage of ER ESR measure(2) VB (2) VA VC 0 0 1 0 1 0 1 $15 VA voltage of ER ESR measure 0 0 1 0 1 1 0 $16 VC voltage of ER ESR measure(2) 0 0 1 0 1 1 1 $17 Unused 0 0 1 1 0 0 0 $18 Unused 0 0 1 1 0 0 1 $19 Unused 0 0 1 1 0 1 0 $1A Unused 0 0 1 1 0 1 1 $1B Unused 0 0 1 1 1 0 0 $1C Unused 0 0 1 1 1 0 1 $1D Unused 0 0 1 1 1 1 0 $1E Unused 0 0 1 1 1 1 1 $1F Unused 0 1 0 0 0 0 0 $20 VBATMON pin voltage 218/277 DocID029257 Rev 1 VBATMON L9680 System voltage diagnostics Table 18. Diagnostics control register (DIAGCTRLx) (continued) ADC Request (ADCREQx) ADC Results (ADCRESx) Voltage Measurement Selection Bit[6:0] Hex Bit[9:0] 0 1 0 0 0 0 1 $21 VIN pin voltage VIN 0 1 0 0 0 1 0 $22 Internal analog supply voltage (VINT3V3) VINT3V3 0 1 0 0 0 1 1 $23 Internal digital supply voltage (CVDD) CVDD 0 1 0 0 1 0 0 $24 ERBOOST pin voltage ERBOOST 0 1 0 0 1 0 1 $25 SYNCBOOST pin voltage SYNCBOOST 0 1 0 0 1 1 0 $26 VER pin voltage VER 0 1 0 0 1 1 1 $27 SATBUCK voltage SATBUCK 0 1 0 1 0 0 0 $28 VCC voltage VCC 0 1 0 1 0 0 1 $29 WAKEUP pin voltage WAKEUP 0 1 0 1 0 1 0 $2A VSF pin voltage VSF 0 1 0 1 0 1 1 $2B WDTDIS pin voltage WDTDIS 0 1 0 1 1 0 0 $2C GPOD0 pin voltage GPOD0 0 1 0 1 1 0 1 $2D GPOS0 pin voltage GPOS0 0 1 0 1 1 1 0 $2E GPOD1 pin voltage GPOD1 0 1 0 1 1 1 1 $2F GPOS1 pin voltage GPOS1 0 1 1 0 0 0 0 $30 GPOD2 pin voltage GPOD2 0 1 1 0 0 0 1 $31 GPOS2 pin voltage GPOS2 0 1 1 0 0 1 0 $32 RSU0 pin Voltage RSU0 0 1 1 0 0 1 1 $33 RSU1 pin Voltage RSU1 0 1 1 0 1 0 0 $34 RSU2 pin Voltage RSU2 0 1 1 0 1 0 1 $35 RSU3 pin Voltage RSU3 0 1 1 0 1 1 0 $36 SS0 pin voltage SS0 0 1 1 0 1 1 1 $37 SS1 pin voltage SS1 0 1 1 1 0 0 0 $38 SS2 pin voltage SS2 0 1 1 1 0 0 1 $39 SS3 pin voltage SS3 0 1 1 1 0 1 0 $3A SS4 pin voltage SS4 0 1 1 1 0 1 1 $3B SS5 pin voltage SS5 0 1 1 1 1 0 0 $3C SS6 pin voltage SS6 0 1 1 1 1 0 1 $3D SS7 pin voltage SS7 0 1 1 1 1 1 0 $3E SS8 pin voltage SS8 0 1 1 1 1 1 1 $3F SS9 pin voltage SS9 1 0 0 0 0 0 0 $40 SSA pin voltage SSA 1 0 0 0 0 0 1 $41 SSB pin voltage SSB DocID029257 Rev 1 219/277 276 System voltage diagnostics L9680 Table 18. Diagnostics control register (DIAGCTRLx) (continued) ADC Request (ADCREQx) ADC Results (ADCRESx) Voltage Measurement Selection Bit[6:0] Hex Bit[9:0] 1 0 0 0 0 1 0 $42 Unused - 1 0 0 0 0 1 1 $43 Unused - 1 0 0 0 1 0 0 $44 Unused - 1 0 0 0 1 0 1 $45 Unused - 1 0 0 0 1 1 0 $46 SF0 pin voltage SF0 1 0 0 0 1 1 1 $47 SF1 pin voltage SF1 1 0 0 1 0 0 0 $48 SF2 pin voltage SF2 1 0 0 1 0 0 1 $49 SF3 pin voltage SF3 1 0 0 1 0 1 0 $4A SF4 pin voltage SF4 1 0 0 1 0 1 1 $4B SF5 pin voltage SF5 1 0 0 1 1 0 0 $4C SF6 pin voltage SF6 1 0 0 1 1 0 1 $4D SF7 pin voltage SF7 1 0 0 1 1 1 0 $4E SF8 pin voltage SF8 1 0 0 1 1 1 1 $4F SF9 pin voltage SF9 1 0 1 0 0 0 0 $50 SFA pin voltage SFA 1 0 1 0 0 0 1 $51 SFB pin voltage SFB 1. The DC sensor resistance measurement can only be addressed through DIAGCRTL_A command. Results are available through DIAGCTRL_A and DIAGCTRL_B, where ADCRES_A will contain DCSI and ADCRES_B will contain DCSV. 2. Valid only for ADCREQ_x field of MISO response when ESR measure results are available. Proper scaling is necessary for various measurements. The divider ratios vary by measurement and are summarized by function in the table below. Table 19. Diagnostics divider ratios Divider Ratio Measurements 15:1 220/277 VER X ERBOOST X VSF X SSxy X SFx X 10:1 GPODx X GPOSx X SYNCBOOST X VIN X DocID029257 Rev 1 7:1 4:1 1:1 L9680 System voltage diagnostics Table 19. Diagnostics divider ratios (continued) Divider Ratio Measurements 15:1 10:1 VBATMON X WAKEUP X 7:1 SATBUCK X WDT/TM X RSUx X 4:1 VCC X CVDD X VINT X 1:1 VCOREMON X Bandgap (BGR/BGM) X For measurements other than voltage (current, resistance, temperature etc.) the ranges are specified in the electrical parameters section of the relevant block. 14.1 Analog to digital algorithmic converter The device hosts an integrated 10 bit Analog to Digital converter, running at a clock frequency of 16 MHz. The ADC output is processed by a D to D converter with the following functions: Use of trimming bits to recover additional gain error due to resistor dividers mismatch; Digital low-pass filtering; Conversion from 12 to 10 bits. 10 bits data are filtered inside the digital section. The number of samples that are filtered vary depending on the chosen conversion. As per Section 7.3.2, the number of used samples in converting DC sensor, squib or temperature measurements defaults to 8. The number of samples for all other measurements defaults to 4. The sample number can be configured by accessing the SYS_CFG register. After low pass filter, the residual total error is ±4 LSB. This error figure applies to the case of a ideal reference voltage: the spread of reference voltage causes a proportional error in the conversion output. The reference voltage of the ADC is set to 2.5 V. The conversion time is comprised of several factors: the number of measurements loaded into the queue, the number of samples taken for any one measurement, and the various settling times. An example of conversion time calculation for a full ADC request queue is reported in Figure 69. The timings reported in Figure 69 are nominal ones, min/max values can be obtained by considering the internal oscillator frequency variation reported in the DC characteristics section. DocID029257 Rev 1 221/277 276 System voltage diagnostics L9680 Figure 69. ADC conversion time ',$*&75/B$ 3UH $'& 67 B 6 & ',$*&75/B% ,4 67 B 6 & ',$*&75/B& ,4 67 B 6 & ',$*&75/B' ,4 67 B 6 & 3RVW $'& 3UH$ '& ,QLWLDO$'&6HWWOLQJ7LPH X V 6 R I6DPSOHVGHIDXOW IRUYROWDJHRQO\PHDVXUHPHQWV 7B 6 & 6 LQJOH6DPSOH&RQYHUVLRQ7LPH X V ,4 ,QWUD4 XHXH6HWWOLQJ7LPH X V 3RVW$ '& ) LQDO$'&6HWWOLQJ7LPH X V '!0'03 222/277 DocID029257 Rev 1 L9680 15 Temperature sensor Temperature sensor The L9680 provides an internal analog temperature sensor. The sensor is aimed to have a reference for the average junction temperature on silicon surface. The sensor is placed far away from power dissipating stages and squib deployment drivers. The output of the temperature sensor is available via SPI through ADC conversion, as shown in Table 18. The formula to calculate temperature from ADC reading is the following one: ADC REF 220 - DIAGCTRLn ADCRESn – 0.739 T C = 180 – --------------- ---------------------- 1.652 ADC RES 2 @ DIAGCTRLn(ADCREQn) = 0Ahex All parametric requirements for this block can be found in specification tables. DocID029257 Rev 1 223/277 276 Electrical characteristics 16 L9680 Electrical characteristics Every parameter in this chapter is fulfilled down to VINGOOD(max). No device damage is granted to occur down to VINBAD(min). GNDA pin is used as ground reference for the voltage measurements performed within the device, unless otherwise stated. All table or parameter declared ‘Design Info’ are not tested during production testing 16.1 Configuration and control All electrical characteristics are valid for the following conditions unless otherwise noted. -40 °C Ta +95 °C. Table 20. Configuration and control DC specifications No Symbol Min Typ 1 VNOV Normal Operating Voltage Design Info Depending on power supply configuration 6 13 18 V 2 VJSV Jump Start Voltage Design Info 40°C ≤ Ta ≤ 50°C 18 - 26 V 3 VLDV Load Dump Voltage Transient Design Info 26.5 - 40 V 4 WU_mon WAKEUP Monitor threshold GNDSUBx as ground reference - - 1.5 V 5 WU_off WAKEUP Off threshold GNDSUBx as ground reference Vin = 5.5 V and 35 V 2 2.5 3 V 6 WU_on WAKEUP On threshold GNDSUBx as ground reference Vin = 5.5 V and 35 V 4 4.5 5 V 7 WURPD WAKEUP Pull-down Resistor GNDSUBx as ground reference 120 300 480 kΩ 8 VBGOOD0 SYS_CTL(VBATMON_TH_SEL)=00 or 11 5.5 5.75 6 V 9 VBBAD0 SYS_CTL(VBATMON_TH_SEL)=00 or 11 5 5.25 5.5 V 10 VBGOOD1 VBATMON Thresholds SYS_CTL(VBATMON_TH_SEL)=01 6.45 6.7 6.95 V 11 VBBAD1 SYS_CTL(VBATMON_TH_SEL)=01 5.95 6.2 6.45 V 12 VBGOOD2 SYS_CTL(VBATMON_TH_SEL)=10 7.5 7.75 8 V 13 VBBAD2 SYS_CTL(VBATMON_TH_SEL)=10 7 7.25 7.6 V 224/277 Parameter Conditions DocID029257 Rev 1 Max Unit L9680 Electrical characteristics Table 20. Configuration and control DC specifications (continued) No Symbol 13b ΔVBGOOD2_VBBAD2 Parameter Conditions VBATMON delta thresholds Min Typ 300 - 600 mV Device OFF -5 - 5 μA Device ON Design Info 20 24 30 μA VBGOOD2_VBBAD2 Max Unit 14 ILKG_VBATMON_OFF 15 ILKG_VBATMON_ON 16 RPD_VBATMON VBATMON pull-down resistance Device ON VBATMON < 10V Design Info 125 250 375 kΩ 17 ILKG_VBATMON_TOT VBATMON total input leakage ILKG_VBATMON_ON + RPD_VBATMO VBATMON = 18V 35 - 180 μA 18 VINGOOD0 SYS_CTL(VIN_TH_SEL)=0 5 5.25 5.5 V 19 VINBAD0 20 VINGOOD1 21 VINBAD1 22 VINFASTSLOPE_H 23 VINFASTSLOPE_L 24 VINFASTSLOPE_HYS 25 VINSYNC_DIS_L 26 27 28 VBATMON input leakage VIN Good and VIN Bad SYS_CTL(VIN_TH_SEL)=0 Thresholds SYS_CTL(VIN_TH_SEL)=1 4.5 4.75 5 V 6.05 6.3 6.55 V SYS_CTL(VIN_TH_SEL)=1 5.55 5.8 6.05 V - 9.3 9.8 10.3 V - 9 9.5 10 V - 0.2 0.3 0.4 V SYS_CTL(SYBST_V) =0 12.2 - 13.6 V 15 - 16.2 V 5 - 300 mV Device OFF VIN = 40V -10 - 10 μA Device ON VIN = 12V - - 40 mA External VIN capacitor Design Info 1 - 13(1) μF VIN Thresholds used to change Boost regulator transition time VIN SyncBoost Disable SYS_CTL(SYBST_V) = 1 Thresholds SYS_CTL(SYBST_V) = 0 / 1 VIN SYNC_DIS_LYS Guaranteed by design VIN SYNC_DIS_HYS VINSYNC_DIS_H ILKG_VIN_OFF VIN input current 29 ILKG_VIN_ON 30 CVIN DocID029257 Rev 1 225/277 276 Electrical characteristics L9680 Table 20. Configuration and control DC specifications (continued) No Symbol 31 ILKG_VER_OFF 32 ILKG_VER_ON_L Parameter Conditions VER Input Leakage Min Typ Max Unit Device OFF VER = 40V -5 - 50 μA Device ON ERBOOST > VER ER Charge OFF 50 - 200 μA Device ON ERBOOST < VER ER Charge OFF 100 - 500 μA 33 ILKG_VER_ON_H 34 VWDTDIS_TH WDT/TM threshold Test go no go 10 12 14 V 35 VWDTDIS_HYST WDT/TM hysteresis Design Info 0.2 0.4 0.5 V 36 IPD_WDTDIS WDT/TM Pull Down Resistance VWDTDIS ≤ 5V 20 45 70 μA 37 VTH1_H_VCCSEL_ 38 VTH1_L_VCCSEL - 1.30 1.55 1.80 V - 1.05 1.25 1.45 V VCCSEL Input Voltage Thresholds 1 39 VHYS1_VCCSEL - 0.2 - - V 40 VTH2_H_VCCSEL_ - 5.9 6.4 6.9 V 41 VTH2_L_VCCSEL - 5.6 6.1 6.6 V - 0.2 - - V VCCSEL= SATBUCK 20 45 70 μA VCCSEL Input Voltage Thresholds 2 42 VHYS2_VCCSEL 43 IPD_VCCSEL 226/277 VCCSEL Pull Down Current DocID029257 Rev 1 L9680 Electrical characteristics Table 20. Configuration and control DC specifications (continued) No 44 Symbol ITOTLKG_BAT Parameter Conditions Room Temp WAKEUP = 0 All following pins at 13V: Battery Line Total Input VBATMON, VIN, ERBSTSW, Leakage ERBOOST, SYNCBSTSW, SYNCBOOST Min Typ Max Unit - - 35 μA - - 150 ºC Min Typ Guaranteed by design 45 TJ Junction Temperature Design Info 1. Bigger capacitor can be used in case an external switch is used in parallel to the ER-Switch. Table 21. Configuration and control AC specifications No Symbol Parameter 1 TFLT_VBATMONTH VBATMON thresholds deglitch filter time - 26 30 34 μs 2 TFLT_VINGOOD_UP VIN Good thresholds deglitch filter time rising edge - 3 3.5 4 μs 3 TFLT_VINGOOD_DO VIN Good thresholds deglitch filter time falling edge SYS_CFG(VINGOOD_FILT_SEL) = 0 - 1 - μs 4 TFLT_VINGOOD_DO VIN Good thresholds deglitch filter time falling edge SYS_CFG(VINGOOD_FILT_SEL) = 1 3 3.5 4 μs VIN Bad thresholds TFLT_VINBAD_DOWN deglitch filter time falling edge - 3 3.5 4 μs VIN Bad thresholds deglitch filter time rising edge - 26 30 34 μs VIN Good Thresholds blanking time - 26 30 34 μs VIN SyncBoost TFLT_VINSYNCDIS_D Disable deglitch filter time OWN falling edge - 3.3 - 4.2 μs VIN SyncBoost Disable deglitch filter time rising edge - 9.5 - 11 μs 6 WN_L WN_H 7 TFLT_VINBAD_UP 8 TVINGOOD_BLK 9 10 TFLT_ VINSYNCDIS _UP Conditions DocID029257 Rev 1 Max Unit 227/277 276 Electrical characteristics L9680 Table 21. Configuration and control AC specifications (continued) No Symbol 11 TFLT_WAKEUP 12 TLATCH_WAKEUP 13 228/277 TPWRUP Parameter Conditions Min Typ Max Unit Wakeup deglitch filter time - 0.95 1.05 1.15 ms Wakeup latch time - 9.7 ms Power-up Delay Time – Wake-up to RESET released - - DocID029257 Rev 1 10.8 11.9 - 10 ms L9680 Electrical characteristics Table 22. Open ground detection DC specifications No Symbol Parameter Conditions / Comments Min Typ Max Unit 1 GNDAOPEN GNDA open threshold GNDSUBx=0 100 200 300 mV 2 GNDDOPEN GNDD open threshold GNDSUBx=0 100 200 300 mV 3 BSTGNDOPEN BSTGND open threshold GNDSUBx=0 100 200 300 mV 4 IPU_BSTGND BSTGND pull-up current ER BOOST OFF and SYNC BOOST OFF 130 - 270 μA 5 SATGNDOPEN SATGND open threshold GNDSUBx=0 100 200 300 mV 6 IPU_SATGND SATGND pull-up current SATBUCK OFF 80 120 160 μA 7 VCCGNDOPEN VCCGND open threshold GNDSUBx=0 100 200 300 mV 8 IPU_VCCGND VCCGND pull-up current VCC BUCK OFF 80 120 160 μA Table 23. GND_OPEN_AC - Open ground detection DC specifications No Symbol 1 TFLT_GNDREFOPEN GNDA and GNDD Open Deglitch Filter Time 2 BSTGND, SATGND, TFLT_GNDREGOPEN VCCGND Open Deglitch Filter Time 16.2 Parameter Condition Min Typ Max Unit - 7 11 16 μs - 1.9 2.3 2.7 μs Internal analog reference All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C ≤ Ta ≤ +95 °C VINBAD0(min) ≤ VIN ≤ 35 V Table 24. Internal analog reference N° Symbol 1 VBG1 2 VBG2 3 VADC_GROUND 4 Parameter Condition Min Typ Max Unit Bandgap reference Vin = 5.5 V and 35 V -1% 1.2 +1% V Bandgap monitor Vin = 5.5 V and 35 V -1% 1.2 +1% V ADC Ground reference ADC total error included 90 104 120 mV -1.5% 2.5 +1.5% V VADC_FULLSCALE ADC Full scale reference - DocID029257 Rev 1 229/277 276 Electrical characteristics 16.3 L9680 Internal regulators All electrical characteristics are valid for the following conditions unless otherwise noted. -40 °C Ta +95 °C, VINGOOD0 VIN 35 V Table 25. Internal regulator DC specifications No Symbol Parameter 1 VOUT_VINT3V3 VINT3V3 output voltage 2 VOV_VINT3V3 3 Condition Min Typ Max Unit Vin = 5.5 V, 12 V and 35 V 3.14 3.3 3.46 V VINT3V3 over voltage - 3.47 - 3.7 V VUV_VINT3V3 VINT3V3 under voltage - 2.97 - 3.13 V 4 VOUT_CVDD CVDD output voltage - 3.14 3.3 3.46 V 5 IOUT_CVDD CVDD current capability External load is not allowed - - 50 mA 6 ILIM_CVDD CVDD current limit - 80 - - mA 7 VOV_CVDD CVDD over voltage - 3.47 - 3.7 V 8 VUV_CVDD CVDD under voltage - 2.7 - 2.9 V 9 CCVDD CVDD output capacitance Design info 60 100 140 nF Min Typ Max Unit Table 26. Internal regulators AC specifications No Symbol 1 TFLT_ VINT_CVDD_OV Internal regulator over voltage deglitch filter time - 7 11 16 μs 2 TFLT_VINT_CVDD_UV Internal regulator under voltage deglitch filter time - 7 11 16 μs 230/277 Parameter Comment DocID029257 Rev 1 L9680 16.4 Electrical characteristics Watchdog All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V Table 27. Temporal watchdog timer AC specifications (WD1) No Symbol Parameter 1 TWDT1_TIMEOUT 2 TWDT1_RST Condition Temporal watchdog timeout Min Typ Max Unit - - 2.00 ms - - 16.3 ms 0.9 1.0 1.1 ms - Temporal watchdog reset time - Table 28. Algorithmic watchdog timer DC specifications (WD2) No Symbol Parameter 1 VOH_WD2LCKOUT 2 VOL_WD2LCKOUT Condition WD2LockOut output voltage Min Typ Max Unit ILOAD = -0.5 mA VCC-0.6 - VCC V ILOAD = 2.0 mA 0 - 0.4 V Min Typ Max Unit Table 29. Algorithmic watchdog timer AC specifications (WD2) No Symbol Parameter Condition 1 TWDT2_TIMEOUT Algorithmic watchdog timeout - 45 50 55 ms 2 TWDT2_RST Algorithmic watchdog reset time - 0.9 1.0 1.1 ms 3 TRISE_ WD2LCKOUT WD2LockOut rise time 50 pF load, 20%-80% - - 1.0 μs 4 TFALL_ WD2LCKOUT WD2LockOut fall time 50 pF load, 20%-80% - - 1.0 μs - - f osc --------512 - MHz 5 fWD2_SEED WD2 Seed Counter Rate DocID029257 Rev 1 231/277 276 Electrical characteristics 16.5 L9680 Oscillators All electrical characteristics are valid for the following conditions unless otherwise noted: --40 °C Ta +95 °C, 3.14 CVDD 3.46. Table 30. Oscillators specifications N # 1 2 3 4 5 6 Symbol Min Typ Max Unit 15.2 16 16.8 MHz fMOD_OSC Main SPI_CLK_CNF(MAIN_SS_DIS=0) oscillator modulation Design Info frequency - f osc ---------128 - MHz IMOD_OSC Main oscillator SPI_CLK_CNF(MAIN_SS_DIS=0) modulation index 2 4 6 % 7.125 7.5 7.875 MHz fMOD_AUX Aux SPI_CLK_CNF(AUX_SS_DIS=0) oscillator modulation Design Info frequency - f osc_AUX -----------------------128 - MHz IMOD_AUX Aux oscillator SPI_CLK_CNF(AUX_SS_DIS=0) modulation index 2 4 6 % fOSC fAUX Parameter Main oscillator average frequency Aux oscillator average frequency Condition - - Main oscillator fOSC_LOW_ low 7 frequency TH detection threshold - 128 ---------- f AUX_MIN 68 - 128 ---------- f AUX_MAX MHz 68 Main oscillator fOSC_HIGH_ high 8 frequency TH detection threshold - 79 ------ f AUX_MIN 32 - 79 ------ f AUX_MAX MHz 32 232/277 DocID029257 Rev 1 L9680 16.6 Electrical characteristics Reset All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V, VCCx(min) VCCx VCCx(max), VCC = 3.3 V or 5 V Table 31. Reset DC specifications No Symbol 1 VOH_RESET 2 VOL_RESET 3 RPD_RESET 4 Parameter Comment Min Typ Max Unit ILOAD = -1. mA VCC-0.4 - VCC V ILOAD = 2.0 mA 0 - 0.4 V RESET pull down resistance - 65 100 135 kΩ VCOREUV VCOREMON under voltage threshold - 1.08 1.11 1.14 V 5 VCOREOV VCOREMON over voltage threshold - 1.26 1.29 1.32 V 6 RPD_VCORE VCOREMON pull down resistance - 65 100 135 kΩ 7 VIH_ MCUFLT MCUFAULTB high level input voltage - 2 - - V 8 VIL_ MCUFLT MCUFAULTB Low level Input Voltage - - - 0.8 V 9 IPD_MCUFLT MCUFAULTB Pull Down Current MCUFAULTB= VCC 20 45 70 μA RESET output voltage Table 32. Reset AC specifications No Symbol Parameter Comment Min Typ 1 TRISE_RESET Rise time - - 1.00 μs 2 TFALL_RESET Fall time - - 1.00 μs 3 THOLD_RESET Reset hold time - 0.45 0.5 0.55 ms 4 TFLT_VCOREOV VCOREMON over voltage deglitch filter time - 27 30 33 μs 5 TFLT_VCOREUV VCOREMON under voltage deglitch filter time 27 30 33 μs 6 TFLT_MCUFAULTB MCUFAULTB Deglitch filter time 9 10 11 μs 50 pF load, 20%-80% - DocID029257 Rev 1 Max Unit 233/277 276 Electrical characteristics 16.7 L9680 SPI interface All electrical characteristics are valid for both Global and Remote Sensor SPI and for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V, VCCx(min) VCCx VCCx(max), VCC = 3.3 V or 5 V Table 33. Global and remote sensor SPI DC specifications No Symbol Min Typ Max Unit 1 VIH_CS_G VIH_CS_RS CS_x High level Input Voltage - 2 - - V 2 VIL_CS_G VIL_CS_RS CS_x Low level Input Voltage - - - 0.8 V 3 IPU_CS_G IPU_CS_RS CS_x Pull Up Current CS_x = 0V -70 -45 -20 μA 4 VIH_MOSI_G VIH_MOSI_RS MOSI_x High level Input Voltage - 2 - - V 5 VIL_MOSI_G VIL_MOSI_RS MOSI_x Low level Input Voltage - - - 0.8 V 6 IPD_MOSI_G IPD_MOSI_RS MOSI_x Pull Down Current MOSI_x = VCC 20 45 70 μA 8 VIH_SCLK_G VIH_SCLK_RS SCLK_x High level Input Voltage - 2 - - V 9 VIL_SCLK_G VIL_SCLK_RS SCLK_x Low level Input Voltage - - - 0.8 V 10 IPD_SCLK_G IPD_SCLK_RS SCLK_x Pull Down Current SCLK_x = VCC 20 45 70 μA 12 VOH_MISO_G VOH_MISO_RS MISO_x High level Output Voltage ILOAD = -800 μA VCC -0.5 - VCC V 13 VOL_MISO_G VOL_MISO_RS MISO_x Low level Output Voltage ILOAD = 2.0 mA - - 0.4 V 14 ILKG_MISO_G ILKG_MISO_RS MISO_x Output Leakage Tri-state leakage -10 - 10 μA 15 VIH_MISO_RS MISO_RS High level Input Voltage - 2 - - V 16 VIL_MISO_RS MISO_RS Low level Input Voltage - - - 0.8 V 234/277 Parameter Comment DocID029257 Rev 1 L9680 Electrical characteristics Table 34. SPI AC specifications No Symbol Parameter Comments / Conditions Min Typ 1 FSCLK SPI transfer frequency 2 TSCLK 3 - - 8 SCLK_x period - 123.8 - - ns TLEAD Enable lead time - 250 - - ns 4 TLAG Enable lag time - 50 - - ns 5 THIGH_SCLK SCLK_x high time - 40 - - ns 6 TLOW_SCLK SCLK_x low time - 40 - - ns 7 TSETUP_MOSI MOSI_x input setup time - 20 - - ns 8 THOLD_MOSI MOSI_x input hold time - 20 - - ns 9 TACC_MISO MISO_x access time - - 60 ns 10 TDIS_MISO MISO_x disable time - - 100 ns 11 TVALID_MISO MISO_x output valid time - - 30 ns 12 THOLD_MISO MISO_x Output Hold Time 80 pF load; Design Info 0 - - ns 13 TNODATA SCLK_x hold time - 20 - - ns 14 TFLT_CS CS_x noise glitch rejection time - 50 - 300 ns 15 TNODATA SPI interframe time - 400 - - ns 80 pF load Max Unit 8.08 MHz 16 TSETUP_MISO_RS MISO_RS Input Setup Time - 20 - - ns 17 THOLD_MISO_RS MISO_RS Input Hold Time - 20 - - ns Note: All timing is shown with respect to 10% and 90% of the actual delivered VCC voltage. Figure 70. SPI timing diagram &6B[ 6&/.B[ 026,B[ 0,62B[ /6%,1 '$7$ 06%,1 06%287 '$7$ /6%287 '21¶7 &$5( *$3*36 DocID029257 Rev 1 235/277 276 Electrical characteristics 16.8 L9680 ERBoost regulator All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V. Table 35. ERBoost regulator DC specifications No Symbol Parameter 1 VO_ERBST Boost output voltage 2 3 IO_ERBST Conditions Min Typ Max Unit Across all line and IO_BST load (steady state) SYS_CTL(ER_BST_V)=0 22.6 23.8 25 V Across all line and IO_BST load (steady state) 1SYS_CTL(ER_BST_V)=1 31.65 33 35 V Boost output current - 0.1 - 70 mA -8% - 8% % -8% - 8% % 4 dVSR_ac Line transient response All line, load; dt=100us; BST33V = 0/1 Design Info 5 dVLR_ac Load transient response All line, load; dt=100us; BST33V = 0/1 Design Info 6 RDSON_ERBST Power switch resistance - - - 1 Ω 7 IOC_ERBST - 650 - 1350 mA 8 IOC_ERBST_ERON ER Switch activated AND SW_REGS_CONF(LOW_E RBST_ILIM_ERON) = 1 125 - 600 mA 9 ILKG_ERBST_OFF -5 - +5 μA 60 - 200 μA 1.5 - 2.4 mA 10 Over current detection ERBOOST=40V Power-off or Sleep Mode ILKG_ERBST_ON ERBOOST input current Active or Passive Mode ERBoost reg. enabled ERBSTSW > ERBoost > VER ER Charge OFF VSF regulator OFF Any GPO channel not enabled Guarantee by design 11 ILKG_ERBST_ON_wGPO 236/277 Active or Passive Mode ERBoost reg. enabled ERBSTSW > ERBoost > VER ER Charge OFF VSF regulator OFF All GPO channel activated DocID029257 Rev 1 L9680 Electrical characteristics Table 35. ERBoost regulator DC specifications (continued) No Min Typ Max Unit BST33V = 0 18 20 22 V BST33V = 1 26 28 30 V SYS_CTL(ER_BST_V) = 0 22.6 - 25 V SYS_CTL(ER_BST_V) = 1 31.65 - 35 V 1.6 2.2 2.5 V Voltage difference between ERBSTSW and VERBSTSW – VERBOOST 17 VERBST_CLAMP_EN_TH ERBOOST to activate the ER Boost CLAMP 2.7 3.3 3.7 V 18 TJSD_ERBST - 150 175 190 °C 19 THYS_TSDERBST - 5 10 15 °C Min Typ Max Unit - 1.8 1.882 2.0 MHz 10% to 90% voltage on ERBSTSW VIN ≥ VINFASTSLOPE_H = 10.3 V Iload = 6 0mA SYS_CTL(ER_BST_V) = 1 Guaranteed by Design 15 - 35 ns TRISE_ERBSTSW_FAST TFALL_ERBSTSW_FAST 10% to 90% voltage on ERBSTSW VIN = VINFASTSLOPE_L =9 V 5 - 15 ns TON_ERBST CERBOOST = 2.2 μF Vin =12V, IO_ERBST= 5mA SYS_CTL(ER_BST_V) = 1 Measured from CS_G edge to VO_ERBST(min) 50 - 500 μs - 27 30 33 μs 12 13 14 15 16 Symbol VERBST_OK Parameter ERBOOST voltage threshold VERBST_OV ERBOOST Over Voltage threshold VERBST_DIS_TH Voltage difference between VIN and ERBOOST to deactivate the ER Boost regulator Thermal shutdown Conditions VIN – ERBOOST Table 36. ERBoost regulator AC specifications No Symbol 1 FSW_ERBST 2 3 4 5 TRISE_ERBSTSW_SLOW TFALL_ERBSTSW_SLOW Parameter ERBOOST switching frequency ERBSTSW transition time ERBOOST charge-up time Deglitch filter on TFLT_VIN_ERBST_COMP VIN_ERBoost comparator Conditions DocID029257 Rev 1 237/277 276 Electrical characteristics L9680 Table 36. ERBoost regulator AC specifications (continued) No Symbol 6 TFLT_TSD_ERBST 7 Parameter TSOFTST_ERBST Conditions Min Typ Max Unit Thermal shutdown filter time - - - 10 μs ERBOOST Soft-start Time Design Info. Time from activation of ERBOOST when overcurrent is 40% of IOC_ERBST (IOC_ERBST_ERON) to instant when overcurrent is 100% of IOC_ERBST (IOC_ERBST_ERON) - - 1075 μs Min Typ Max Unit Table 37. ERBOOST Converter external components design info No Symbol 1 LERBST 2 ESLERBST 3 CBLK_ERBST 4 Component Conditions Inductance - 8 10 12 μH Inductance resistance - - - 0.1 Ω 1 2.2 - μF - 50 mΩ Output bulk capacitance to Min cap value including ensure regulator stability derating factors ESRCBLK_ERBST Bulk capacitor ESR - 5 VFSTR_ERBST Steering diode forward voltage IF=100 mA - - 0.85 V 6 ILKGSTR_ERBST Steering diode reverse leakage Ta = 95 °C - - 3 mA 238/277 DocID029257 Rev 1 L9680 16.9 Electrical characteristics ER CAP current generators and diagnostic All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V, 8 V ≤ ERBOOST. Table 38. ER CAP current generators and diagnostic DC specifications No Symbol Min Typ Max Unit 1 IER_CHARGE 60 65 70 mA 2 IER_DISCHARGE_LOW ER discharge low level current VER 6V 60 65 70 mA 3 IER_DISCHARGE_HIGH ER discharge high level current VER 8V 589 640 691 mA 4 RDSON_ERCHARGE ER charge power resistance (VERBOOST - VVER)/IVER IVER = 10mA - - 20 Ω 5 VERRANGE VER voltage measurement range 20 - 35 V 6 VERACC VER voltage measurement VERRANGE accuracy -8 - +8 % 7 ERCAPRANGE Energy reserve capacitor measurement range Design Info - - 10 mF 8 ERCAPACC Energy reserve capacitor measurement accuracy VERMIN = 2 V -7 - +7 % 9 ERCAP_ESRRANGE Energy reserve capacitor ESR measurement range - 200 - 600 mΩ 10 ERCAP_ESRACC Energy reserve capacitor ESR measurement accuracy All errors included except the offset one (OFFER_ESR) -20 +20 % 11 GER_ESR 12 OFFER_ESR 13 TJSD_ERBST 14 THYS_TSDERBST 15 VVER_VBATMON_TH Parameter ER charge current Conditions ERBOOST 8 V ERBOOST – VER 2 V Energy Reserve Capacitor ESR Measurement Gain -13% 3 +13% V/V 70 - 160 mΩ - 150 175 190 °C - 5 10 15 °C 1.6 2.2 2.5 V Energy Reserve Capacitor Design Info ESR Measurement Offset ER charge thermal shutdown Voltage difference between VER and VBATMON to activate the ER Discharge in passive mode VER - VBATMON DocID029257 Rev 1 239/277 276 Electrical characteristics L9680 Table 39. ER CAP current generators and diagnostic AC specifications No Symbol 1 TON_ERCAP Energy reserve capacitor CVER 10mF nominal, charge-up time BST33V = 0, Design Info 2 TESR_DIAG Total duration time from SPI ER CAP ESR diagnostic command to ADC results duration availability 3 TFLT_TSD_ERCHARGE 16.10 Parameter Conditions Thermal shutdown filter time - Min Typ Max Unit - - 4 s -5% 225 +5% μs - - 10 μs ER switch All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V. Table 40. ER Switch DC specifications No Symbol 1 RDSON_ERSW 2 ILIM_ERSW 3 VER_SW_OV_TH 4 TJSD_ERSW 5 THYS_TSDERSW Parameter Conditions Min Typ Max Unit Power switch resistance - 0.5 - 3 Ω ER switch current limit - 608 810 980 mA ER switch Over Voltage threshold ER switch turned off when VIN > VER + VER_SW_OV_TH 10 - 200 mV - 150 175 190 °C - 5 10 15 °C Max Unit Thermal shutdown Table 41. ER Switch AC specifications No Symbol 1 TON_ERSW 2 Parameter Conditions ER turn-on time (time to reach either RDSON_ERSW or CVIN = 10 μF ILIM_ERSW) TFLT_TSD_ERSW Thermal shutdown filter time - 3 240/277 TBLK_ERSW ER switch activation blanking time after thermal shutdown - DocID029257 Rev 1 Min - - 5 μs - - 10 μs - 1 - ms L9680 Electrical characteristics 16.11 COVRACT All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V; VINGOOD(max) VIN 35 V; VCCx(min) VCCx VCCx(max); VCC = 3.3 V or 5 V Table 42. COVRACT DC specifications No Symbol 1 VOH_COVRACT 2 VOL_COVRACT 3 IREV_COVRACT Parameter Conditions COVRACT output voltage Reverse current short high voltage Min Typ Max Unit ILOAD = -0.5 mA VCC -0.6 - VCC V ILOAD = 2.0 mA 0 - 0.4 V COVRACT = 40 V VCC = 3.3 V - - 1 mA Min Typ Max Unit Table 43. COVRACT AC specifications No Symbol Parameter Conditions 1 TRISE_COVRACT Rise time 50 pF load, 20%-80% - - 1.00 μs 2 TFALL_COVRACT Fall time 50 pF load, 20%-80% - - 1.00 μs 16.12 SYNCBOOST converter All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN VINSYNC_DIS_X(min) Table 44. SYNCBOOST converter DC specifications No Symbol Parameter 1 VO_SYNCBST SYNCBOOST output voltage 2 3 IO_SYNCBST_VL_IH 4 IO_SYNCBST_VL_IL 5 IO_SYNCBST_VH_IH SYNCBOOST output current Conditions Min Typ Max Unit Across all line and load, steady state SYS_CTL(SYBST) = 0 11.40 12 - V Across all line and load (steady state) SYS_CTL(SYBST) = 1 14.00 14.75 - V SYS_CTL(SYBST_V) = 0 SYS_CFG(LOW_POWER_M ODE) = 0 20 - 360 mA SYS_CTL(SYBST_V) = 0 SYS_CFG(LOW_POWER_M ODE) = 1 20 - 240 mA SYS_CTL(SYBST_V) = 1 SYS_CFG(LOW_POWER_M ODE) = 0 20 - 290 mA DocID029257 Rev 1 241/277 276 Electrical characteristics L9680 Table 44. SYNCBOOST converter DC specifications (continued) No Symbol 6 IO_SYNCBST_VH_IL 7 dVSR_ac 8 dVLR_ac 9 RDSON_SYNCBST 10 IOC_SYNCBST_HIGH 11 IOC_SYNCBST_LOW 12 ILKG_SYNCBOOST SYNCBOOST leakage 13 ILKG_SYNCBSTSW 14 15 16 Parameter Conditions Min Typ Max Unit SYS_CTL(SYBST_V) = 0 SYS_CFG(LOW_POWER_M ODE) = 1 20 - 190 mA -8% - 8% % -8% - 8% % - - 0.5 Ω SYS_CFG(LOW_POWER_ MODE) = 0 1.6 - 3.2 A SYS_CFG(LOW_POWER_ MODE) = 1 1.5 - 2.6 A SYNCBOOST=40V Device off - - 10 μA SYNCBSTSW leakage SYNCBSTSW=40V Device off - - 20 μA VSYNCBST_OK SYNCBOOST voltage threshold - 9 10 11 V VSYNCBST_OV SYNCBOOST Over Voltage threshold - 22 23 24 V VSYNCBST_DIS_TH Voltage difference between VIN and SYNCBOOST to deactivate the SYNC Boost regulator VIN – SYNCBOOST 1.6 2.2 2.5 V 2.7 3.3 3.7 V SYS_CTL(RESTART_SYBST _SEL) = 0 Voltage threshold on VIN pin 9 - 10.3 V SYS_CTL(RESTART_SYBST _SEL) = 1 Voltage threshold on SYNCBOOST pin 19 20 21 V SYNCBOOST output current All line, load; dt = 100 μs; Line transient response SYS_CTL(SYBST) = 0/1 Design Info Power switch resistance - Over current detection of integrated MOS Voltage difference between SYNCBSTSW VSYNCBSTSW –VSYNCBOOST 17 VSYNCBST_CLAMP_EN_TH and SYNCBOOST to activate the SYNC Boost CLAMP 18 VVIN_SYNCBST_RESTART_TH Voltage threshold to restart Syncboost regulator during ER State 19 VSYNCBST_RESTART_TH 20 TJSDERSYNCBST Thermal shutdown - 150 175 190 C 21 THYS_TSDSYNCBST Thermal shutdown hysteresis - 5 10 15 °C 242/277 DocID029257 Rev 1 L9680 Electrical characteristics Table 45. SYNCBOOST converter AC specifications No Symbol Parameter 1 FSW_SYNCBST 2 TRISE_SYNCBSTSW_SLOW TFALL_SYNCBSTSW_SLOW Min Typ Max Unit 1.8 1.882 2.0 MHz 10% to 90% voltage on SYNCBSTSW VIN = VINFASTSLOPE_H Design Info 15 - 30 ns 10% to 90% voltage on SYNCBSTSW VIN = VINFASTSLOPE_L Design Info 5 - 20 ns - - 1075 μs SYNCBST switching frequency SYNCBSTSW transition time 3 Conditions TRISE_SYNCBSTSW_FAST TFALL_SYNCBSTSW_FAST 4 TSOFTST_SYNCBST SYNCBST Softstart Time Design Info. Time from activation of SYNCBOOST when overcurrent is 40 % of IOC_SYNCBST_HIGH (IOC_SYNCBST_LOW) to instant when overcurrent is 100% of IOC_SYNCBST_HIGH (IOC_SYNCBST_LOW) 5 TFLT_TSD_SYNCBST Thermal shutdown filter time - - - 10 μs TBLK_SYNCSW Sync boost activation blanking time after thermal shutdown - - 1 - ms 6 Table 46. SYNCBOOST converter external components design info No Symbol 1 LSYNCBST 2 ESLSYNCBST 3 CBLK_SYNCBST 4 Component Conditions Min Typ Max Unit Inductance Min 4.7 μH nominal 3.76 - - μH Inductance resistance - - - 0.1 Ω Output bulk capacitance Min 2.2 μF nominal 1.76 - - μF - - - 50 mΩ ESRCBLK_SYNCBST Bulk capacitor ESR 5 VFSTR Steering diode forward voltage IF = 1 A - - 0.5 V 6 ILKGSTR Steering diode reverse leakage Ta = 95 °C - - 3 mA DocID029257 Rev 1 243/277 276 Electrical characteristics 16.13 L9680 SATBUCK converter All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35V, VSYNCBST_OK SYNCBOOST Table 47. SATBUCK converter DC specifications No Symbol 1 VO_SATBCK 2 Parameter SATBUCK output voltage Conditions Min Typ Max Unit Across all line and load, steady state SAT_V = 0 6.92 7.2 7.48 V Across all line and load, steady state SAT_V = 1 8.64 9 9.36 V 3 IO_SATBCK_VH_IH SAT_V =0 LOW_POWER_MODE = 0 20 - 450 mA 4 IO_ SATBCK _VH_IL SAT_V =0 LOW_POWER_MODE = 1 20 - 300 mA 5 IO_ SATBCK _VL_IH SAT_V =1 LOW_POWER_MODE = 0 20 - 390 mA 6 IO_ SATBCK _VL_IL SAT_V =1 LOW_POWER_MODE = 1 20 - 240 mA 7 dVSR_ac Line transient response All line, load; dt=100 μs; SAT_V = 0/1 Design Info -4% - 4% % 8 dVLR_ac Load transient response All line, load; dt=100 μs; SAT_V = 0/1 Design Info -4% - 4% % 9 RDSON_SATBCK_HS High side power switch resistance - - - 0.6 Ω 10 RDSON_SATBCK_LS Low side power switch resistance - - 0.6 Ω 11 IOC_HS_SATBCK_HI 12 IOC_HS_SATBCK_LO 13 14 IOCP_LS_SATBCK_LO Low side positive over current detection I 15 IOCN_LS_SATBCK_HI 16 IOCN_LS_SATBCK_LO 17 VSATBCK_OK_LOW 18 VSATBCK_OK_HIGH SATBUCK output current High side over current detection OCP_LS_SATBCK_HI 244/277 Low side negative over current detection SATBUCK voltage threshold LOW_POWER_MODE = 0 0.83 1.1 1.37 A LOW_POWER_MODE = 1 0.53 0.7 0.9 A 1 - 100 mA VSATBCKSW ≥ 0 FAST SLOPE 100 240 350 mA VSATBCKSW = 0 LOW_POWER_MODE = 0 0.94 1.25 1.56 A VSATBCKSW = 0 LOW_POWER_MODE = 1 0.64 0.85 1.06 A SYS_CTL(SAT_V) = 0 6.2 6.5 6.8 V SYS_CTL(SAT_V) = 1 7.7 8.1 8.5 V VSATBCKSW ≥ 0 VSYNCBST < VSYNCBST_RESTART_TH DocID029257 Rev 1 L9680 Electrical characteristics Table 48. SATBUCK converter AC specifications No Symbol Parameter 1 FSW_SATBCK Conditions SATBUCK switching frequency TRISE_SATBCKSW 2 _SLOW TFALL_SATBCKSW _SLOW SATBCKSW transition time TRISE_SATBCKSW 3 _FAST TFALL_SATBCKSW _FAST 4 TSOFTST_SATBCK SATBUCK soft start time Min Typ - 1.8 1.882 2.0 MHz 10% to 90% voltage on SATBCKSW VSYNCBST < VSYNCBST_RESTART_TH Design Info 10 - 25 ns 10% to 90% voltage on SATBCKSW VSYNCBST > VSYNCBST_RESTART_TH Design Info 5 - 15 0.50 - 2 ms From 10% to 90% Max Units Table 49. SATBUCK converter external components design info No Symbol 1 LSATBCK 2 3 4 Component Conditions Min Typ Max Unit 3.76 - - μH Inductance Min 4.7 μH nominal ESRLSATBCK Inductance Resistance - - - 0.25 Ω CBLK_SATBCK Output Bulk Capacitance Min 4.7 μH nominal 3 - 30 μF - - - 50 mΩ ESRCBLK_SATBCK Bulk Capacitor ESR 16.14 VCC regulator All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V, VSATBCK_OK SATBUCK VUV_VCOREMON VCOREMON VOV_VCOREMON Table 50. VCC converter DC specifications No Symbol Parameter 1 VO_VCC 2 VCCBUCK Output Voltage Conditions Min Typ Max Units Across all line and load, steady state VCCSEL < VTH1_L_VCCSEL 3.20 3.3 3.40 V Across all line and load, steady state VCCSEL = > VTH1_H_VCCSEL 4.85 5 5.15 V DocID029257 Rev 1 245/277 276 Electrical characteristics L9680 Table 50. VCC converter DC specifications (continued) No Symbol Min Typ Max Units 3 IO_VCC3V_HI VCCSEL < VTH1_L_VCCSEL LOW_POWER_MODE = 0 20 - 420 mA 4 IO_VCC3V_LO VCCSEL < VTH1_L_VCCSEL LOW_POWER_MODE = 1 20 - 230 mA 5 IO_VCC5V_HI VCCSEL > VTH1_H_VCCSEL LOW_POWER_MODE = 0 20 - 270 mA 6 dVSR_ac Line transient response All line, load; dt=100 μs; Design Info -4% - 4% % 7 dVLR_ac Load transient response All line, load; dt=100 μs; Design Info -4% - 4% % 8 RDSON_VCCBCK_HS High side power switch resistance - - - 0.6 9 RDSON_VCCBCK_LS Low side power switch resistance - - - 0.6 10 IOC_HS_VCCBCK_HI SYS_CFG(LOW_POWER_ MODE) = 0 0.59 0.75 0.9 A 11 IOC_HS_VCCBCK_LO SYS_CFG(LOW_POWER_ MODE) = 1 0.4 0.56 0.7 A 12 IOCP_LS_VCCBCK VVCCBCKSW > 0 SYS_CFG(LOW_POWER_ MODE) = 0 / 1 1 - 100 mA VVCCBCKSW = 0 LOW_POWER_MODE = 0 0.67 0.9 1.13 A VVCCBCKSW = 0 LOW_POWER_MODE = 1 0.49 0.65 0.82 A - 100 150 200 μA VCCSEL < VTH2_L_VCCSEL 3.43 - 3.6 V VCCSEL > VTH2_H_VCCSEL 5.25 - 5.50 V VCCSEL < VTH2_L_VCCSEL 3.0 - 3.17 V VCCSEL > VTH2_H_VCCSEL 4.5 - 4.75 V - 1.8 2 2.2 V 13 IOCN_LS_VCCBCK_HI 14 IOCN_LS_VCCBCK_LO 15 IOF_VCC 16 VCCOV3V 17 VCCOV5V 18 VCCUV3V 19 VCCUV5V 20 VCCUVL 246/277 Parameter Conditions VCCBUCK output current High side over current detection Low side positive over current detection Low side negative over current detection Open feedback current on VCC VCC over voltage detection VCC under voltage detection high VCC under voltage detection low DocID029257 Rev 1 L9680 Electrical characteristics Table 51. VCC converter AC specifications No Symbol 1 FSW_VCCBCK Parameter Conditions VCCBUCK switching frequency - Min Typ Max Units 1.8 1.882 2.0 MHz 8 - 20 ns 2 TRISE_VCCBCKSW VCCBCKSW transition time TFALL_VCCBCKSW 10% to 90% voltage on VCCBCKSW Design Info 3 TSOFTST_VCCBCK VCCBUCK soft start time From 10% to 90% 0.5 - 2 ms - 27 30 33 μs VCC reg in VCC_RAMPUP state 1.5 2 2.5 μs 4 5 VCC over voltage detection deglitch filter time TFLT_VCCOV VCC Over voltage TFLT_VCCOV_RAMPUP detection deglitch filter time during VCC_RAMPUP state 6 TFLT_VCCUV VCC under voltage detection deglitch filter time - 27 30 33 μs 7 TFLT_VCCUVL VCC under voltage low detection deglitch filter time - 1.5 2 2.5 μs Min Typ Max Unit 3.76 - - μH Table 52. VCC converter external components design info No Symbol 1 LVCCBCK 2 3 4 Component Conditions Inductance Min 4.7 μH nominal ESRLVCCBCK Inductance resistance - - - 0.25 Ω CBLK_VCCBCK Output bulk capacitance Min 4.7 μF nominal 3 - 30 μF - - - 50 mΩ ESRCBLK_VCCBCK Bulk capacitor ESR 16.15 VSF regulator All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35V, VSF + 2V ERBOOST Table 53. VSF regulator DC specifications No Symbol Parameter 1 VSF Output voltage 2 Conditions Min Typ Max Unit All line, load, IO_VSF up to 6mA SYS_CGF(VSF_V)= 0 18 20 22 V All line, load, IO_VSF up to 6mA Only in case SYS_CTL(ER_BST_V)=1 SYS_CGF(VSF_V) = 1 23 25 27 V 3 ILIM_VSF Output load current limit VSF = 0 7 10 13 mA 4 VDO_VSF Drop-out voltage V(ERBOOST-VSF) - - 2 V 5 CVSF Output capacitance Design Info 2.9 - 14 nF DocID029257 Rev 1 247/277 276 Electrical characteristics L9680 Table 53. VSF regulator DC specifications (continued) No 6 Symbol Parameter Conditions ILKG_VSF_OFF VSF input leakage Min Typ Max Unit Device OFF -5 - 5 μA 7 RPD_VSF VSF pull-down resistance Device ON VSF regulator OFF; VSF = 25V 60 125 220 kΩ 8 IPD_VSF VSF pull-down current Device ON VSF regulator ON; Design Info 34 40 46 μA Device ON VSF regulator ON VSF = 25V SYS_CGF(VSF_V)= 1 147 230 462 μA Min Typ Max Unit - - 100 μs 9 IPD_VSF_TOT VSF total pull-down current Table 54. VSF regulator AC specifications No Symbol 1 TON_VSF 16.16 Parameter Conditions CVSF = 14 nF Measured from VSF_EN=1 to VSF inside regulation limits VSF turn on time Deployment drivers All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35V, 6V SSxy 35V, SSxy - SFx 25V. Table 55. Deployment drivers – DC specifications No 1 Symbol Parameter Conditions Min Typ Max Unit R = 2 ohms Considering 9mA as not detected leakage with a 1kOhm equivalent resistance from SFx to GND 1.33 1.4 1.6 A R = 2 ohms, 9V ≤ SSxy Considering 13.5mA as not detected leakage with a 1kOhm equivalent resistance from SFx to GND, 1.94 1.99 2.3 A Deployment Current Counter Threshold - IDEPL x* 90% - - A IDEPL_LO Deployment Current 2 IDEPL_HI 3 ITH_DEPL 4 IOC_SR Low side Over Current Detection - 2.2 3.1 4.0 A 5 ILIM_SR Low side Current Limitation - 2.2 3.1 4.0 A 248/277 DocID029257 Rev 1 L9680 Electrical characteristics Table 55. Deployment drivers – DC specifications (continued) No Symbol Parameter 6 ΔILIM_OC_SR Difference between Current Limitation and OC Threshold 7 Combined High side MOS + RDSON_HSLS Low side MOS On Resistances 8 IREV_SF 9 ILKG_SS_OFF 10 11 Reverse Current on SFx ILKG_SS_ON_ 1CH ILKG_SS_ON SSxy leakage current 12 13 ILKG_SS_CH_ ARMED ILKG_SS_2CH _ARMED Conditions Min Typ Max Unit 0.1 - - mA Ta = 95°C - - 2 Ω Without device malfunction(1) Not to be tested in series production - - -100 mA Device OFF SSxy ≤ 35 V SFx=SFy=0 -10 - 10 μA Device ON SSxy ≤ 35 V SFx = 0 SSxy Leakage current of each channel Not Tested 70 100 130 μA Device ON SSxy ≤ 35 V SFx = SFy = 0 Total SSxy leakage current with both x and y channels NOT armed (= 2 * 100μA) 140 200 260 μA Device ON SSxy ≤ 35 V SFx = 0 Total SSxy leakage current with only one channel armed (=520 + 100 μA) 450 620 850 μA Device ON SSxy ≤ 35 V SFx = SFy = 0 Total SSxy leakage current with both x and y channels armed (= 2* 520 μA) Not Tested 884 1040 1196 μA ILIM_SR - IOC_SR DocID029257 Rev 1 249/277 276 Electrical characteristics L9680 Table 55. Deployment drivers – DC specifications (continued) No Symbol 14 ILKG_SF_ON_ 15 ILKG_SF_ON_ 16 17 18 Parameter Min Typ Max Unit Device ON, SYNCBOOST = SSxy = 35V, SFx = 0V -5 - 5 μA Device ON, SYNCBOOST = SSxy = 35V, SFx = 35V -5 - 50 μA Device OFF SYNCBOOST = open, SSxy = open but all SSxy pins connected, SFx = 0V -5 - 5 μA Device OFF SYNCBOOST = open, SSxy = open but all SSxy pins connected, SFx = 35V -5 - 50 μA Device ON, SYNCBOOST = SSxy = 35V, SRx = 0V-35 - - 50 μA DEVICE OFF, SYNCBOOST = open, SSxy = open but all SSxy pins connected, SRx pull down current OFF SRx=0V-20V - - 50 μA DEVICE OFF, SYNCBOOST = open, SSxy = open but all SSxy pins connected, SRx pull down current OFF SRx=35V - - 30 μA - 35 - 40 V Load Inductance Maximum load inductance Design Info(2) 0 - 56 μH 13 - 455 nF Load Capacitance Maximum capacitance to GND Design Info 13 - 455 nF 0V 35V ILKG_SF_OFF SF Leakage Current _0V ILKG_SF_OFF _35V ILKG_SR_ON 19 SR Leakage Current ILKG_SR_OFF 20 21 VSR_CLAMP SR voltage clamp 22 LDEPL 23 CSFx 24 250/277 Conditions CSRx DocID029257 Rev 1 L9680 Electrical characteristics Table 55. Deployment drivers – DC specifications (continued) No Symbol 25 CSSxy SSxy Capacitance 26 RSFLx 27 Parameter Conditions Min Typ Max Unit Maximum capacitance to GND connected directly to SSxy pin Design Information - - 10 nF Load Impedance Design Info - - 6.5 Ω Wire Length Squib Loops containing a clock spring shall be limited to a maximum length of 3m 1 - 10 m 28 RWirex Wire Resistance Design Info 16.8 - 63.4 mΩ/ m 29 LWirex Wire Inductance Design Info 0.6 - 1.8 μH/ m 30 RCSx Clock Spring Resistance Maximum number of clock springs is 3 for any IC Design Info 0 - 0.7 Ω 31 LCSx Clock Spring Inductance Design Info 0 - 42.9 μH 32 kL_CS1 – Clock Spring Coupling Design Info 0.739 - 0.903 - 33 LEMI Squib EMI protection Design Info 0 - 7.7 μH 1. L_CS2 In case of an unsupplied device and shorted deployment pins (e.g. to battery voltage), the dynamic reverse current through the high side power stage depends on CSSxy. 2. LDEPL could be calculated in the following way: Non-Clock Spring Loops: LDEPL(max) = LWire(10m*2) + LEMI = (3.6uH/m * 10m) + 7.7uH =43.7uH Clock Spring Loops: LWire(3m*2) + 2*LCSx + LEMI - (2*kL_CX*SQRT(L_CS1*L_CS2)) = = (3.6uH/m * 3m) + 2 * 42.9uH + 7.7uH (2 * 0.739 * 42.9uH) = 40.9uHClock Spring Loops with short to ground LDEPL(max) = LWire(3m) + LCSx + LEMI = (1.8uH/m * 3m) + 42.9uH + 7.7uH = 56uH. DocID029257 Rev 1 251/277 276 Electrical characteristics L9680 Figure 71. Deployment drivers diagram %3$%-)0ROTECTION 3YSTEM7IRING)MPEDANCE 3QUIB%-) 0ROTECTION #LOCK3PRING )MPEDANCE 2?#3 3QUIB,OAD ,?#3 3&X #?3&X 2?7IRE ,?%-) ,?7IRE 2?3QUIB K,?#3,?#3 7IRE,ENGHTM 32X 2?7IRE ,?7IRE #?32X 2?#3 ,?#3 '!0'03 Table 56. Deployment drivers – AC specifications No Symbol Parameter Conditions 1 2 TDEPL DCR_x(Dep_Current) = IDEPL_LO ≥1.209A rising to 1.209A falling; TDEPL = DCR_x(Deploy_Time)* TDEP_TIME_RES - TDEL_IDEP Deployment time 3 Min Typ DCR_ x(Depl oy_Ti me)* TDEP _TIM E_RE S - 65 - - Max DCR _x(D eploy _Tim e)* TDEP Unit ms _TIME _RES - 4 TDEP_TIME_RES DCR_x Deploy_Time resolution - - 1024 ------------f osc - μs 5 TDEP_CC_RES Deployment current counter resolution - 256 ---------f osc - μs 6 TRISE_IDEPL Rise time 10% - 90% of IDEPL - - 32 μs 7 TDEL_IDEP - - 65 μs 8 TFALL_IDEPL Fall time 90% - 10% IDEPL - - 32 μs TDEL_SD_LS Low side shutdown delay time (with respect to high-side deactivation) 50 - - μs 9 252/277 SSxy = 25 V, RSQ = 2.2 ohm, C = 22 nF L = 44 μH Delay time SPI_CS to 90% IDEPL - DocID029257 Rev 1 L9680 Electrical characteristics Table 56. Deployment drivers – AC specifications No Symbol Parameter Min Typ Max Unit TFLT_ILIM_LS Low side overcurrent to low side deactivation deglitch time in short to battery condition 80 100 120 μs TFLT_OS_LS Low side overcurrent to high side deactivation deglitch time in case of intermittent open to squib condition 11 - - 20 μs 12 TOFF_OS_HS High side OFF time in case of intermittent open to squib condition 4 - 12 μs 10 Conditions - 16.17 Deployment driver diagnostic 16.17.1 Squib resistance measurement All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0(max) VIN 35 V, 6 V SSxy 35 V, 7 V SYNCBOOST 35 V. Table 57. Deployment drivers diagnostics - Squib resistance measurement No Symbol Parameter Conditions Min Typ Max Unit 1 RSQ_RANGE_1 Squib resistance range 1 LPDIAGREQ(ISRC_CURR_ SEL) = 0 0 - 10.0 Ω 2 RSQ_RANGE 2 Squib resistance range 2 LPDIAGREQ(ISRC_CURR_ SEL) = 1 0 - 50.0 Ω 3 GRSQ Squib resistance measurement Differential amplifier gain VOUT_RSQ = GRSQ x [(VSF VSR)] + Voff_RSQ -2% 5.2 +2% V/V 4 Voff_RSQ Squib resistance measurement Differential amplifier offset VOUT_RSQ = GRSQ x [(VSF – VSR)] + Voff_RSQ 200 - 400 mV 5 ISRC_HI_SF ISRC_HI_SR Squib resistance measurement High current source LPDIAGREQ(ISRC_CURR_ SEL) = 0 LPDIAGREQ(ISRC) = ‘01’ or ‘10’ -5% 40 +5% mA 6 ISRC_LO_SF ISRC_LO_SR Squib resistance measurement Low current source LPDIAGREQ(ISRC_CURR_ SEL) = 1 LPDIAGREQ(ISRC) =’01’ or ‘10’ -10% 8 +10% mA 7 ISRC_DELTA Squib Resistance Measurement Delta Current Source ISRC_HI_x - ISRC_LO_x -5% 32 +5% mA DocID029257 Rev 1 253/277 276 Electrical characteristics L9680 Table 57. Deployment drivers diagnostics - Squib resistance measurement (continued) No Symbol Parameter Min Typ Max Unit 8 SRISRC Squib resistance measurement current source slew-rate - 3 7.5 12 mA/μs 9 VSRx_RM SRx voltage during resistance measurement LPDIAGREQ(ISRC)=”01” or “10” LPDIAGREQ(ISINK)=1 0.4 0.7 1.2 V 10 ISINK_HI_SR SRx current sink limit high LPDIAGREQ(ISRC_CURR_ SEL) = 0 LPDIAGREQ(ISINK) = 1 50 75 100 mA 11 ISINK_LO_SR SRx current sink limit low LPDIAGREQ(ISRC_CURR_ SEL) = 1 LPDIAGREQ(ISINK) = 1 10 17.5 25 mA 12 IPD_SR_L SYS_CTL(PD&VRCM_SEL) = 0 0.7 1 1.3 mA 13 IPD_SR_H SYS_CTL(PD&VRCM_SEL) = 1 4.5 6 7.5 mA 14 RLKG_SF SFx leakage resistance Design info 1 - - kΩ 15 VLKG_SF SFx leakage voltage source Design info -1 - 18 V -8% - +8 % 50 - 100 kHz SRx current pull down Conditions 16 RSQ_ACC Squib resistance measurement accuracy After software calculation All errors included RSQ between 1.0 Ω and 10.0 Ω With High Current Source (40 mA) 17 - EMI input low-pass filter Design Info 254/277 DocID029257 Rev 1 L9680 Electrical characteristics 16.17.2 Squib leakage test (VRCM) All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V, 3.14 ≤ CVDD ≤ 3.46 Table 58. Squib Leakage Test (VRCM) No Symbol 1 2 3 VOUT_VRCM Parameter Conditions Output Voltage on SF or SR pins during Leakage test Detection threshold, leakage to GND ILKG_GSQ_TH_L 4b 5 ILKG_GSQ_TH_H 6 TFLT_LKG 7 Leakage to GND deglitch filter time RLKG_BSQ_TH Detection threshold, leakage to battery 8a ILKG_BSQ_TH 8b 9 TFLT_LKG 10 ILIM_VRCM_SRC 11 ILIM_VRCM_SINK 12 VSHIFT Typ Max Unit -10% 2.5 +10% V 1.9 - 2.5 V 1 - 10 kΩ Equivalent to resistance range SYS_CTL(PD&VRCM_SEL) = 0 -15.5 -25 °C ≤ Tj ≤ +150 °C % guaranteed by design/characterization 450 +15.5 % μA Equivalent to resistance range SYS_CTL(PD&VRCM_SEL) = 0 -17% -40 °C ≤ Tj ≤ +150 °C 450 +15.5 % μA SYS_CTL(PD&VRCM_SEL) = 1 -15% 2 15% mA - 17 20 23 μs Leakage detected if RLKG_GSG ≤ 1 kΩ and not detected if RLKG_GSG ≥ 10 kΩ Design Info 1 - 10 kΩ Equivalent to resistance range -25 °C ≤ Tj ≤ +150 °C guaranteed by design/characterization -12% 1.8 +15% mA -40 °C ≤ Tj ≤ +150 °C -17% 1.8 +15% mA - 17 20 23 μs - -20 - -10 mA - 10 - 20 mA Design Info -1 - +1 V IOUT = 0 mA IOUT = 6.6 mA Leakage detected if RLKG_GSG ≤ 1 kΩ and not detected if RLKG_GSG ≥ 10 kΩ Design Info RLKG_GSG_TH 4a Min Leakage to BAT deglitch filter time VRCM current limitation External ground or battery shift DocID029257 Rev 1 255/277 276 Electrical characteristics L9680 Table 58. Squib Leakage Test (VRCM) No Symbol 13 RSQ_LOW_TH 14a IRSQ_LOW_TH Parameter Conditions TFLT_RLOW 16 RSQ_HIGH 17 IRSQ_HIGH 18 TFLT_RHIGH 19 Typ Max Unit 200 - 500 Equivalent to resistance range -25 °C ≤ Tj ≤ +150 °C guaranteed by design/characterization -12% 6 +12% mA -40 °C ≤ Tj ≤ +150 °C -17% 6 +12% mA - 12 15 18 μs Design Info 2 - 5 kΩ -17% 700 +17% μA 12 15 18 μs - - 2 μs Design Info Detection threshold for “resistance too low” 14b 15 Min “Resistance too low” deglitch filter time Detection Threshold for “resistance too high” Equivalent to resistance range “Resistance too high” deglitch filter time - Time needed to change Tdelay_STG_sele the VRCM STG thresholds guaranteed by design (450 μA-to-2 mA or 2 mAction to-450 μA) 16.17.3 High/low side FET test All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0(max) VIN 35 V, 6 V SSxy 35 V, 7 V SYNCBOOST 35 V. Table 59. High/low side FET test No Symbol 1 IHS_FET_TH 2 ILS_FET_TH 3 Parameter Detection threshold high side FET test Detection threshold ILS_FET_TH_HIGH low side FET test 4 EFET_TEST 5 TDRIVER_DIS 6 TTOT_FETTEST_A 7 TFETTIMEOUT CTIVE 256/277 Conditions - Min Typ Max Unit -12% 1.8 +12% mA 450 +15.5% μA -15% 2 +15% mA SYS_CTL(PD&VRCM_SEL) = 0 -15.5% SYS_CTL(PD&VRCM_SEL) = 1 Energy transferred to squib during HS/LS FET tests Design Info - - 170 μJ Driver Disable time Guarantee by design - - 1.5 μs Total FET test activation time in case of no fault condition Guarantee by design - - 4 μs HS/LS FET test timeout - 190 200 210 μs DocID029257 Rev 1 L9680 Electrical characteristics Table 59. High/low side FET test (continued) No Symbol Parameter Conditions Min Typ Max Unit Deglitch filter time during FET test on IHS_FET_TH / ILS_FET_TH current thresholds - 0.8 1 1.2 μs 8 TFLT_LKGB_FT 9 ILIM_HS_FET HS FET current in HS driver diagnostics Not tested, see item # 1 in errata sheet section 40 50 60 mA 10 SGxyOPEN Squib open ground detection GNDSUBx as ground reference 300 450 600 mV 11 TFLT_SGOPEN Squib open ground detection filter time - 46 50 54 μs 16.17.4 Deployment timer test All electrical characteristics are valid for the following conditions unless otherwise noted: -40 °C Ta +95 °C, VINGOOD0 VIN 35 V. Table 60. Deployment timer test - AC specifications No Symbol 1 tPULSE_PERIOD 2 IPULSE_HIGH Parameter Conditions Deployment timer pulse test period time Deployment timer pulse test high time Min Typ 7 8 SYSDIAGREQ(DSTEST)=PULSE - Max Unit DCR_x( Deploy_ Time)* TDEP_TIM 9 ms - μs E_RES 16.18 Remote sensor interface All electrical characteristics are valid for the following conditions unless otherwise noted: 40 °C Ta +95 °C, VINGOOD0 VIN 35 V, VSATBUCK(min) VSATBUCK, VSYNCBOOST(min) VSYNCBOOST 16.18.1 PSI-5 interface Table 61. PSI-5 satellite transceiver - DC specifications No Symbol Parameter 1 IRSU 2 VRSU_MAX Max. output voltage excluding sync. pulse 3 VRSU_SYNC_MAX Max. output voltage including sync. pulse Conditions Min Typ Max Unit -35 - -4 mA (internal regulation, VSATBUCK = VSYNCBOOST) - - 11 V (internal regulation, VSYNCBOOST = VIN) - - 16.5 V Interface quiescent current - DocID029257 Rev 1 257/277 276 Electrical characteristics L9680 Table 61. PSI-5 satellite transceiver - DC specifications (continued) No Symbol 4 RRSU Parameter Conditions Min Typ Max Unit RSU output resistance From IRSU = -4 mA to -65 mA 3 - 9.5 Static reverse current into SATBUCK or SYNCBOOST pin (VSUPPLY) VRSUx > VSUPPLY + VRSU_STB 0.0 - 10 mA 5 ISTB_TH 6 VRSU_STB Output short to battery threshold - 10.0 - 100 mV 7 IOCTH_PSI5 Over current detection threshold Interface disabled after TFLT_OCTH_PSI5 -120 - -66 mA 8 ILIM_PSI5 Output current limit IRSUx -130 - -80 mA 9 ILIM_OC_PSI5 10 - - mA 10 IBO 11 ILKGG 12 ILKGB 13 IOL 14 DACRES 15 Difference between current ABS(ILIM_RSU) - ABS(IOCTH_RSU) limitation and OC threshold Base current Default value -15% -15 +15% mA Trigger point for fault current detection To ground; detected by IB -50.4 -42 -35 mA To battery; detected by IB -3.5 - -1 ILKGB - ILKGB Output open load detection VRSUx = open threshold (min) (max) mA DAC resolution - - 10 - Bit ILSB LSB current Design Info - 93.75 - μA 16 Vt2 Sync pulse amplitude IRSU = 4 - 35 mA Referred to VRSUx voltage before sync pulse 3.8 - - V 17 VSYNCDROP Sync drop-out voltage VSYNCBOOST - VRSUx 1 - - V 18 ILIM_SYNC_LS Sync pulse current limit (LS driver) - 50 - 80 mA 19 ILIM_SYNC Static current limitation for each transceiver output RSUx During sync pulse generator VRSUx=GND -240 - -120 mA 20 C1 Capacitor on RSUx Regulator 22 nF nominal Design Info 13 - - nF 21 RE2 RSU damping resistance Design info - 2.5 - Ω 22 C2 ECU pin capacitance 5 nF nominal Design Information, not tested 4 - 6 nF 23 - Total number of sensors connected to bus Design info 1 - 3 - 258/277 DocID029257 Rev 1 L9680 Electrical characteristics Table 62. PSI-5 satellite transceiver - AC specifications No Symbol 1 TBit_125k 2 TBit_189k 3 TFLT_OCTH_PSI5 Over Current Detection deglitch Normal operation filter time TBLK_OCTH_PSI5 Over Current Detection Blanking Time 4 5 Parameter Conditions Min Typ Max Unit Bit time (125kbps At the sensor connector mode) 7.6 8 8.4 μs Bit time (189kbps At the sensor connector mode) 5 5.3 5.6 μs 500 - 600 μs At interface power on (BLKTxSEL = 0) 4.6 - 5.4 ms At interface power on (BLKTxSEL = 1) 9.4 - 10.8 ms 12 - 16 μs 6 TSTBTH Reverse Battery Blocking Enable Time - 7 t0 Reference time @0.5 V on top of V(RSUx) - 0 - - 8 t1 Start delay time From t0 to SATSYNC -3 - - μs 9 t2 Sync signal sustain start @ VRSU+3.8 V relative to t0 - - 7 μs 10 SRRISE_RSU Sync slope rising slew rate 0.43 - 1.5 V/μs 11 SRFALL_RSU Sync slope falling slew rate -1.5 - - V/μs 12 t3 Sync signal sustain time Design Info 16 - - μs 13 t4 Discharge time limit Design Info - - 35 μs 14 TBLANK Decoder blanking time (decoding Design Info disabled) - - 42 μs 15 TSYNC Time between two sync pulses Design Info 400 500 - μs 16 TFLT_PSI5_HF PSI5 Deglitch filter time F = 189 kbaud Configurable by SPI (4bits) 1 - 2 μs 17 TFLT_PSI5_LF PSI5 Deglitch filter time F = 125 kbaud Configurable by SPI (4bits) 1.5 - 2.5 μs 18 Related to t0, Sensor Side, P8P-500-3L 44 - 58.6 μs 19 Related to t0, Sensor Side, P8P-500-3H 44 - 58.6 μs Related to t0, Sensor Side, P8P-500-4H 44 - 58.6 μs Related to t0, Sensor Side, P10P-500-3L 44 - 58.6 μs 22 Related to t0, Sensor Side, P10P-500-3H 44 - 58.6 μs 23 Related to t0, Sensor Side, P10P-500-4H 44 - 58.6 μs 20 21 T_ES_1, T_LS_1 Message start time, Slot 1 DocID029257 Rev 1 259/277 276 Electrical characteristics L9680 Table 62. PSI-5 satellite transceiver - AC specifications (continued) No Conditions Min Typ Max Unit 24 Related to t0, Sensor Side, P8P-500-3L 181.3 - 210.4 μs 25 Related to t0, Sensor Side, P8P-500-3H 181.3 - 210.4 μs Related to t0, Sensor Side, P8P-500-4H 139.5 - 164.2 μs Related to t0, Sensor Side, P10P-500-3L 181.3 - 210.4 μs 28 Related to t0, Sensor Side, P10P-500-3H 181.3 - 210.4 μs 29 Related to t0, Sensor Side, P10P-500-4H 139.5 - 164.2 μs 30 Related to t0, Sensor Side, P8P-500-3L 328.9 - 373.5 μs 31 Related to t0, Sensor Side, P8P-500-3H 328.9 - 373.5 μs Related to t0, Sensor Side, P8P-500-4H 245.5 - 281.3 μs Related to t0, Sensor Side, P10P-500-3L 328.9 - 373.5 μs 34 Related to t0, Sensor Side, P10P-500-3H 328.9 - 373.5 μs 35 Related to t0, Sensor Side, P10P-500-4H 245.5 - 281.3 μs 36 Related to t0, Sensor Side, P8P-500-3L 107.2 - 127.6 μs 37 Related to t0, Sensor Side, P8P-500-3H 82 - 99.4 μs Related to t0, Sensor Side, P8P-500-4H 82 - 99.4 μs Related to t0, Sensor Side, P10P-500-3L 121 - 142.8 μs 40 Related to t0, Sensor Side, P10P-500-3H 91 - 109.4 μs 41 Related to t0, Sensor Side, P10P-500-4H 91 - 109.4 μs 42 Related to t0, Sensor Side, P8P-500-3L 151 - 174.6 μs 43 Related to t0, Sensor Side, P8P-500-3H 119.8 - 139.9 μs Related to t0, Sensor Side, P8P-500-4H 119.8 - 139.9 μs Related to t0, Sensor Side, P10P-500-3L 167.8 - 193 μs 46 Related to t0, Sensor Side, P10P-500-3H 131 - 152.5 μs 47 Related to t0, Sensor Side, P10P-500-4H 131 - 152.5 μs 48 Related to t0, Sensor Side, P8P-500-3L 231.6 - 264.9 μs 49 Related to t0, Sensor Side, P8P-500-3H 206 - 236.7 μs Related to t0, Sensor Side, P8P-500-4H 168 - 194.9 μs Related to t0, Sensor Side, P10P-500-3L 245.4 - 280.1 μs 52 Related to t0, Sensor Side, P10P-500-3H 215.5 - 246.7 μs 53 Related to t0, Sensor Side, P10P-500-4H 177.5 - 205 μs 26 27 32 33 Symbol T_ES_2, T_LS_2 T_ES_3, T_LS_3 38 T_s1_end_open 39 44 45 T_s1_end_closure 50 51 260/277 T_s2_end_open Parameter Message start time, Slot 2 Message start time, Slot 3 Slot 1 End valid window, opening time Slot 1 End valid window, closure time Slot 2 End valid window, opening time DocID029257 Rev 1 L9680 Electrical characteristics Table 62. PSI-5 satellite transceiver - AC specifications (continued) No Conditions Min Typ Max Unit 54 Related to t0, Sensor Side, P8P-500-3L 302.8 - 342.1 μs 55 Related to t0, Sensor Side, P8P-500-3H 271.6 - 308 μs Related to t0, Sensor Side, P8P-500-4H 225.4 - 256.5 μs Related to t0, Sensor Side, P10P-500-3L 319.6 - 360.5 μs 58 Related to t0, Sensor Side, P10P-500-3H 282.7 - 320 μs 59 Related to t0, Sensor Side, P10P-500-4H 236.5 - 269 μs 60 Related to t0, Sensor Side, P8P-500-3L 365.1 - 412.5 μs 61 Related to t0, Sensor Side, P8P-500-3H 339.4 - 384.3 μs Related to t0, Sensor Side, P8P-500-4H 263.9 - 300.9 μs Related to t0, Sensor Side, P10P-500-3L 378.9 - 427.7 μs 64 Related to t0, Sensor Side, P10P-500-3H 348.5 - 394.3 μs 65 Related to t0, Sensor Side, P10P-500-4H 273 - 311 μs 66 Related to t0, Sensor Side, P8P-500-3L 465.9 - 522.7 μs 67 Related to t0, Sensor Side, P8P-500-3H 434.7 - 488 μs Related to t0, Sensor Side, P8P-500-4H 342.5 - 386.1 μs Related to t0, Sensor Side, P10P-500-3L 482.7 - 541.1 μs 70 Related to t0, Sensor Side, P10P-500-3H 445.9 - 500 μs 71 Related to t0, Sensor Side, P10P-500-4H 353.7 - 398.2 μs 56 57 62 63 68 69 72 Symbol T_s2_end_closure T_s3_end_open T_s3_end_closure Parameter Slot 2 End valid window, closure time Slot 3 End valid window, opening time Slot 3 End valid window, closure time SYS_CFG(RSU_SYNCPULSE_SHIFT _CONF)=0 Related to Start of Sync Pulse on ch. N-1 - 160 ---------f osc - μs SYS_CFG(RSU_SYNCPULSE_SHIFT _CONF)=1 Related to Start of Sync Pulse on ch. N-1 - 288 ---------f osc - μs - 10 - 15 μs Leakage Deglitch Filter Time 10 - 15 μs Design Info F = 125 kbaud Calculated from transition of last sensor bit to when data is available in SPI register - - 19 μs Design Info F = 189 kbaud Calculated from transition of last sensor bit to when data is available in SPI register - - 14 μs TSYNC_DLY_SHORT Sync Pulse Start Delay 73 TSYNC_DLY_LONG 74 TFLT_OPEN_RSU 75 TFLT_LKG_RSU Open Detection Deglitch Filter Time 76 TWRITE_EN_DELAY_LF Data register write delay 77 TWRITE_EN_DELAY_HF DocID029257 Rev 1 261/277 276 Electrical characteristics 16.18.2 L9680 WSS interface Table 63. WSS sensor - DC specifications No Symbol 1 C1 2 VRSU_MAX 3 RRSU 4 IBO Parameter Conditions ITH2 Unit 6 - - nF RSUx Max output voltage (internal regulation, VSATBUCK=VSYNCBOOST) - - 11 V Output resistance From IRSU=-4mA to -35mA 4 - 12 Ω Base Current Auto Adaptive option (default value) +15% -7 -15% mA Fixed threshold option -25 °C ≤ Tj ≤ +150 °C guaranteed by design/characterization +15% -9.8 -15% mA Fixed threshold option -40 °C ≤ Tj ≤ +150 °C +20% -9.8 -20% mA 14mA / 28mA detection Fixed threshold option +15% -19.6 -15% mA -4.5 - -0.2 mA Open sensor detection RSUx OPEN -25 °C ≤ Tj ≤ +150 °C guaranteed by design/characterization RSUx OPEN -40 °C ≤ Tj ≤ +150 °C -5.5 - 0 mA Leakage to GND threshold VRSUx= GND 13.2 15 17.1 mA 7mA / 14mA detection 7a ITHOPEN Max 10nF nominal, Design Info 5b 6 Typ RSU load capacitance 5a ITH1 Min 7b 8 ITHGND 9 IOCTH_WSS Over Current Detection Threshold output disabled after TFLT_OCTH_WSS -65 - -38 mA 10 ILIMTH_WSS Output Current Limit - -65 - -40 mA 1 - - mA 10 - 100 mV 0.0 - 10 mA ILOAD = -1mA VCC0.5 - VCC V ILOAD = 1mA - - 0.4 V -10 - 10 μA 11 Difference between ΔILIM_OC_WSS Current Limitation and OC ILIM_RSU - IOC_RSU Threshold 12 VRSU_STB 13 ISTBTH 14 VOH_WS 15 VOL_WS 16 ILKG_WS 262/277 Output Short to Battery Threshold Static reverse current into SATBUCK or SYNCBOOST pin (V_supply) WSx Output Voltage WSx Output Leakage VRSUx > V_supply + VRSUxSTB Tri-state leakage DocID029257 Rev 1 L9680 Electrical characteristics Table 64. WSS sensor - AC specifications No Symbol 1 TFLT_WS 2 3 - - Parameter Conditions Min Typ Max Unit WS Deglitch filter time Configurable by SPI (4bits) 8 - 15.6 μs Latency time between receiving sensor data @ RSUx pin and reaching threshold high level of WSx pin (trigger point 80% of RSUx modulated current) - - 2+ TFLT_ μs Design Info - - 125 ns Jitter on Latency time WS 4 TFLT_OCTH_WS Over Current Detection Deglitch filter time S - 500 - 600 μs 5 TFLT_OPEN_RS Open Detection Deglitch Filter Time U - 10 - 15 μs 6 TFLT_LKG_RSU - 10 - 15 μs 7 TSTANDSTILL_T - 1.13 - - ms - 2.55 ms 8 H_L TSTANDSTILL_T H_H Leakage Deglitch Filter Time Pulse duration to assert standstill bit thresholds - DocID029257 Rev 1 263/277 276 Electrical characteristics 16.19 L9680 DC sensor interface All electrical characteristics are valid for the following conditions unless otherwise noted: 40 °C Ta +95 °C, VINGOOD0 VIN 35 V, 8.5 V SYNCBOOST 35 V. Table 65. DC Sensor interface specifications No Symbol 1 VOUT_DCSREG 2 ILIM_DCSREG 3 Parameter VDCS_ACC1 5 VDCS_RANGE2 6 VDCS_ACC2 7 IDCS_RANGE1 8 IDCS_ACC1 9 IDCS_RANGE2 10 IDCS_ACC2 11 IDCS_RANGE3 12 IDCS_ACC3 13 RDCS_RANGE Min Typ Max Unit DCS output voltage regulation mode DCS regulator enabled -10% 6.25 +10% V DCS current limitation regulation mode DCS regulator enabled 24 27 30 mA First voltage measurement (VDCS_MEAS1) to compensate external ground shift and internal offset -1 - 1.4 V VDCS = VDCS_RANGE1 DCS voltage measurement accuracy 1 Included ADC error -15 - 15 % DCS voltage measurement range 2 1.5 - 10 V VDCS = VDCS_RANGE2 DCS voltage measurement accuracy 2 Included ADC error -8 - +8 % DCS Current measurement range 1 1 - 2 mA -30 - +30 % 2 - 22 mA -12 - +12 % ILIM_D - mA DCS voltage VDCS_RANGE1 measurement range1 4 Conditions - - IDCS = IDCS_RANGE1 DCS current measurement accuracy 1 Included ADC error DCS current measurement range 2 - IDCS = IDCS_RANGE2 DCS current measurement accuracy 2 Included ADC error DCS current measurement range 3 Regulator in current limitation - CSREG VDCS = 0V DCS Current measurement accuracy 3 Included ADC error -12 - +12 % DCS resistance measurement range Design info 65 - 3000 Ω Performing voltage measurements 1 and 2 After software calculation all errors included -15 - 15 % 14 RDCS_ACC Accuracy of digital resistance measurement 15 IPD_DCS DCSx current pull down VDCS = 1.5 V 130 200 260 μA 16 RPD_DCS DCSx resistance pull down Device active, DCSx current pull down disabled 90 150 210 kΩ 264/277 DocID029257 Rev 1 L9680 Electrical characteristics Table 65. DC Sensor interface specifications No Symbol Min Typ Max Unit 17 IPD_DCS_TOT DCSx total current pull down IPD_DCS_TOT = IPD_DCS + RPD_DCS VDCS = 6.5 V 160 240 330 μA 18 CDCS Output capacitance Design Info 10 - - nF 19 IREF_DCS Internal Current Reference for DCS Current Measurement - -5% 300 +5% μA 20 Ratio_VDCS Divider ratio for DCSx voltage measurement - -3% 7.125 +3% V/V 21 VOFF_DCS DCSx internal offset during voltage measurement - 0.35 0.375 0.39 V 16.20 Parameter Conditions Safing engine All electrical characteristics are valid for the following conditions unless otherwise noted: 40 °C Ta +95 °C, VINGOOD0 VIN 35 V, VCCx(min) VCCx VCCx(max), VCC = 3.3 V or 5 V. Table 66. Arming Interface – DC specifications No Symbol 1 VTH_H_ACL 2 VTH_L_ACL 3 Parameter Conditions Min Typ Max Unit ACL input voltage thresholds - 2.33 - 2.5 V - 1.58 - 1.71 V VHYS_ACl ACL hysteresis - 0.6 0.75 0.9 V 4 RPD_ACL ACL pull down resistance VACL = 3.3V 150 210 270 kΩ 5 VOH_ARM ARMx output high voltage ILOAD = -0.5 mA internal safing selected VCC-0.60 - VCC V 6 VOL_ARM ARMx output low voltage ILOAD = 2.0 mA internal safing selected 0 - 0.4 V 7 RPD_ARM ARMx pull down resistance - 65 100 135 kΩ 8 VIH_ARM ARMx high level input voltage - 2 - - V 9 VIL_ARM ARMx low level input voltage - - - 0.8 V 10 RPD_ARMx, x=1,2,3 ARM1,2,3 pull down resistor External safing selected 60 100 140 kΩ 11 IPU_ARM4 ARM4 pull up current ARM4 = 0V external safing selected -100 -75 -50 μA 12 VOH_PSINHB PSINHB output high voltage ILOAD = -0.5 mA Internal safing selected VCC-0.60 - VCC V DocID029257 Rev 1 265/277 276 Electrical characteristics L9680 Table 66. Arming Interface – DC specifications (continued) No Symbol Parameter 13 VOL_PSINHB PSINHB output low voltage 14 RPD_PSINHB 15 Conditions Min Typ Max Unit ILOAD = 2.0 mA Internal safing selected 0 - 0.4 V PSINHB pull down resistance - 65 100 135 kΩ VIH_PSINHB PSINHB high level input voltage - 2 - - V 16 VIL_PSINHB PSINHB low level input voltage - - - 0.8 V 17 VIH_SAF_CSx SAF_CSx high level input voltage - 2 - - V 18 VIL_SAF_CSx SAF_CSx low level input voltage - - - 0.8 19 IPU_SAF_CSx SAF_CSx pull up current SAF_CSx = 0 V to VIH_SAF_CSx(min) -70 -45 -20 μA Min Typ Max Unit - 475 500 525 μs - 213 - 237 ms - 168 - 187 ms - 154 - 171 ms - 114 - 126 ms Scrap validation TACL and TON_ACL valid - 3 - - cycles Scrap invalid TACL invalid - 2 - - cycles TSCRAP_TIMEOUT Scrap timeout timer - 520 550 580 μs Scrap seed counter frequency - - ƒ osc ---------16 - MHz - - - 0 ms Table 67. Arming interface – AC specifications No Symbol 1 TARM 2 TACL_HI 3 TACL_LO 4 TON_ACL_HI 5 TON_ACL_LO 6 TVALID_ACL 7 TINVALID_ACL 8 9 fSCRAP_SEED Parameter Sensor sampling period ACL period time thresholds ACL on-time thresholds 10 11 12 TPULSE_STRECH Arming enable pulse stretch time - 30 32 34 ms 242 - 270 ms - 1934 - 2162 ms - - 1.00 μs - - 1.00 μs - - 1.00 μs - - 1.00 μs 13 14 TRISE_ARM ARMx rise time 15 TFALL_ARM ARMx fall time 16 TRISE_PSINHB PSINHB rise time 17 TFALL_PSINHB PSINHB fall time 266/277 Conditions 50 pF load, 20% to 80% internal safing selected DocID029257 Rev 1 L9680 Electrical characteristics 16.21 General purpose output drivers All electrical characteristics are valid for the following conditions unless otherwise noted: 40 °C Ta +95 °C, VINGOOD0 VIN 35V, VGPODx + 5V VERBOOST. Table 68. GPO interface DC specifications No Symbol Parameter Conditions Min Typ Max Unit 1 VSAT_GPO_L Output saturation voltage VGPOD – VGPOS ILOAD = 50 mA - - 0.5 V 2 VSAT_GPO_H Output saturation voltage VGPOD – VGPOS ILOAD = 70 mA - - 0.7 V 3 ILIM_GPO Driver current limit VGPOD – VGPOS = 1.5 V 73 110 160 mA 4 IOC_GPO Over current detection - 73 110 160 mA 5 GPO diag OFF output voltage on GPOD in low VOUT_GPOD_OL side mode in open load condition GPOxLS = 1 IOUT = 0 mA -10% 2.5 +10% V 6 GPO diag OFF output voltage on GPOS in high VOUT_GPOS_OL side mode in open load condition GPOxLS = 0 IOUT = 0 mA -10% 2.5 +10% V GPO diag OFF state short to ground detection GPOxLS = 0 / 1 threshold 15 27 40 μA 7 ISRC_TH 8 ISINK_TH_LS GPO Diag OFF state short GPOxLS = 1 to battery detection GPOS = 0 threshold low side mode 15 27 46 μA 9 ISINK_TH_HS GPO Diag OFF state short to battery detection GPOxLS = 0 threshold high side mode 170 220 270 μA -90 -70 -50 μA 50 70 90 μA -90 -70 -50 μA 320 400 480 μA 0.5 1 3 mA 10 11 12 13 14 GPOxLS = 1, GPO Driver OFF, GPOD = 0 V, GPOS = 0 V ILIM_GPOD_SRC GPO Diag OFF state low side mode current limitation on GPOD GPOxLS = 1, ILIM_GPOD_SINK GPO Driver OFF, GPOD = 18 V, GPOS = 0 V GPOxLS = 0, GPO Driver OFF, GPOD = 18 V, GPOS = 0 V ILIM_GPOS_SRC GPO Diag OFF state high side mode current limitation on GPOS GPOxLS = 0, ILIM_GPOS_SINK GPO driver OFF, GPOD = 18 V,GPOS = 18 V IOL_GPO Open load current threshold GPO driver ON DocID029257 Rev 1 267/277 276 Electrical characteristics L9680 Table 68. GPO interface DC specifications (continued) No Symbol 15 16 IDIAG_GPO Parameter Conditions Min Typ Max Unit - - 130 μA VGPOD = 18 V VGPOS = 0V Power-off or Sleep Mode -5 - +5 μA -5 - +5 μA Voltage measurement in progress through Analog MUX Diagnostic current on load Increased leakage for a short specified time (32μs) ILKG_GPOD_OFF GPOD output leakage current 17 ILKG_GPOD_ON VGPOD = 18 V VGPOS = 0 V GPO Driver OFF Active or Passive Mode with GPO un-configured 18 ILKG_GPOS_OFF VGPOD = 18 V VGPOS = 0 V Power-off or Sleep Mode -5 - +5 μA VGPOD = 18 V VGPOS = 0 V GPO Driver OFF Active or Passive Mode with GPO un-configured -5 - +5 μA VGPOS = VGPOD + 1 V GPO Driver OFF - - 1 mA - 150 175 190 °C - 5 10 15 °C Design Info 6 - - nF GPOS output leakage current 19 ILKG_GPOS_ON 20 IREV_GPO 21 TJSD_GPO 22 THYS_TSD_GPO 23 CGPO Reverse current Thermal shutdown Load capacitor Table 69. GPO driver interface – AC specifications No Symbol Parameter Conditions Min Typ Max Unit 1 SRGPOx GPOx output voltage slew rate 30% - 70%; RLOAD = 273 Ω, CLOAD = 100 nF 0.1 0.25 0.4 V/μs 2 TFLT_OC Over current detection filter time GPO Driver ON 10 12 14 μs 3 TFLT_UC Open load detection filter time GPO Driver ON 8 10 12 μs TFLT_STB Short to battery detection in OFF state deglitch filter time GPO Driver OFF 8 10 15 μs TFLT_STG Short to GND detection in OFF state deglitch filter time GPO Driver OFF 8 10 15 μs 4 5 268/277 DocID029257 Rev 1 L9680 Electrical characteristics Table 69. GPO driver interface – AC specifications (continued) No Symbol 6 TMASK_STUP_ON 7 Diagnostic mask TMASK_STUP_OFF delay after switch OFF 8 TFLT_TSD 9 FPWM 10 DCPWM 16.22 Parameter Conditions Min Typ Max Unit 136 - 200 μs 520 - 584 μs - - 10 μs GPO PWM frequency Design Info - 125 GPO PWM duty cycle Increment step = 1.6% 0 - Diagnostic mask CGPOX = 100 nF typ delay after switch ON Thermal shutdown filter time CGPOX = 100 nF typ - Hz 100 % Analog to digital converter All electrical characteristics are valid for the following conditions unless otherwise noted: 40 °C Ta +95 °C, VINGOOD0 VIN 35 V. Table 70. Analog to digital converter No 1 2 3 Symbol Parameter VADC_RANGE ADC input voltage range VADC_REF ADC_RES ADC reference voltage ADC resolution (1) Conditions Min Typ Max Unit - 0.1 - 2.5 V - -1.5% 2.5 +1.5% V Design Info - 10 - bit Separation between adjacent levels, measured bit to bit of actual and an ideal output step. No missing codes -1 - +1 LSB -3 - +3 LSB DNL Differential non linearity error (DNL) 5 INL Maximum difference between the Integral non linearity error actual analog value at the (INL) transition between 2 adjacent steps and its ideal value 6 EQUANT 7 TotErr 8 9 4 Quantization error Design Info -0.5 - 0.5 LSB Total error Includes INL, DNL, ADC Reference voltage tolerance and quantization error -15 - +15 LSB TotErr_0v1 ADC total error for 0.1 V input voltage - -5 - +5 LSB TotErr_2v4 ADC total error for 2.4 V input voltage - -15 - +15 LSB DocID029257 Rev 1 269/277 276 Electrical characteristics L9680 Table 70. Analog to digital converter (continued) No Symbol 10 RLSB_1 Parameter Reproducibility: conversion result variation for constant input signal Conditions Min Typ Max Unit 1x sampling measurements. Guaranteed by design -6 - 6 LSB 4x sampling measurements. Guaranteed by design -3 - 3 LSB 8x sampling measurements. Guaranteed by design -2.5 - 2.5 LSB 11 RLSB_4 12 RLSB_8 13 Pre-ADC Pre-ADC settling time - - 4.81 - μs 14 T_TSC Single conversion time - - 2.25 - μs 15 IQ Intra-queue settling time - - 3.5 - μs 16 Post-ADC Post- ADC settling time - - 3.44 - μs 17 - ADC conversion time voltage 4x sampling for each of the 4 conversions in the queue Design Info - 54.75 - μs ADC conversion time – current and voltage 8x sampling for DCS, temperature and squib loop resistance measurements + 4x sampling for remaining 2 conversions in the queue Design Info - 51.25 - μs 18 - 1. LSB = (2.5V / 1024) = 2.44mV 16.23 Voltage diagnostics (Analog MUX) All electrical characteristics are valid for the following conditions unless otherwise noted: 40 °C Ta +95 °C, VINGOOD0 VIN 35V. Table 71. Voltage diagnostics (Analog MUX No Symbol 1 Ratio_1 2 Ratio_4 3 Ratio_7 4 Min Typ Max Units VIN_RANGE_1 = 0.1 V to 2.5 V - 1 - V/V VINPUT_RANGE_4 = 1 V to 10 V -3% 4 +3% V/V VINPUT_RANGE_7 = 1.5V to 17.5V -3% 7 +3% V/V Ratio_10 VINPUT_RANGE_10 = 2 V to 25 V -3% 10 +3% V/V 5 Ratio_15 VINPUT_RANGE_15 = 3 V to 35 V -3% 15 +3% V/V 6 Offset High impedance -10 - 10 mV 270/277 Parameter Divider ratios Divider Offset Conditions DocID029257 Rev 1 L9680 Electrical characteristics Table 71. Voltage diagnostics (Analog MUX (continued) No Symbol 7 RRATIO_4 8 RRATIO_7 9 RRATIO_10 10 RRATIO_15 11 ILEAK_MUX_ON 16.24 Parameter Conditions Multiplexer input resistance Additional multiplexer on-state input leakage current Min Typ Max Units Multiplexer input to GNDA 80 - - kΩ Multiplexer input to GNDA 120 - - kΩ Multiplexer input to GNDA 160 - - kΩ Multiplexer input to GNDA 200 - - kΩ For all divider ratio expect ratio_1 - - 60 μA Temperature sensor All electrical characteristics are valid for the following conditions unless otherwise noted: 40 °C Ta +95 °C, VINGOOD0 VIN 35 V. Table 72. Temperature sensor specifications No Symbol Parameter 1 TMON_RANGE Monitoring temperature range 2 TMON_ACC Monitoring temperature accuracy Conditions Min Typ Max Unit - -40 - 150 °C - -15 - 15 °C DocID029257 Rev 1 271/277 276 Quality information L9680 17 Quality information 17.1 OTP memory The device contains a 128-bits One-Time Programmable memory. This OTP memory is used for the following purposes: 1. 86 bits data + 3 bits CRC for critical parameters trimming: bandgaps, oscillators, reference currents, firing currents, DC sensor and RSU interface parameters. 2. 18 bits data for other blocks trimming: ADC, ER Cap Measurement 3. 20 bits data for die and wafer traceability 4. 1 bit for debug purpose User read/write access to the OTP memory via SPI is only possible during production testing and require activation of a special test mode. During mission mode, the trimming bits are automatically read from OTP and transferred to the related circuits at each POR cycle. During this operation, actual CRC of the protected trimming data is calculated and checked against the expected CRC stored in the OTP. In case of CRC check failure the OTPCRC_ERR flag is set in the FLTSR register. 272/277 DocID029257 Rev 1 L9680 18 Errata sheet Errata sheet Table 73. Errata sheet # Component Revision Category / Function 1 L9680CC The high side driver diagnostic, described in section on page Deployment 171, doesn’t work. As consequence, the ILIM_HS_FET parameter Diagnostic is not tested in production. 2 L9680CC WSS Over current detection Issue Description The over current threshold doesn’t work. The user can use the leakage to ground flag to understand if a fault condition is present. The interface is anyway protected by means of thermal protection. DocID029257 Rev 1 273/277 276 Package information 19 L9680 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 19.1 TQFP100 (14x14x1.4 mm exp. pad down) package information Figure 72. TQFP100 (14x14x1.4 mm exp. pad down) package outline 6($7,1* 3/$1( ' & ' $ $ ' ' $ FFF & ( ( $ / N PP *$*(3/$1( *$3*36 B(B<( 274/277 F H / 3,1 ,'(17,),&$7,21 ( ( E DocID029257 Rev 1 L9680 Package information Table 74. TQFP100 (14x14x1.4 mm exp. pad down) package mechanical data Dimensions Ref Inches(1) Millimeters Min. Typ. Max. Min. Typ. Max. A - - 1.20 - - 0.0472 A1 0.05 - 0.15 0.0020 - 0.0059 A2 0.95 1.00 1.05 0.0374 0.0394 0.0413 b 0.17 0.22 0.27 0.0067 0.0087 0.0106 c 0.09 - 0.20 0.0035 - 0.0079 D 15.80 16.00 16.20 0.6220 0.6299 0.6378 D1 13.80 14.00 14.20 0.5433 0.5512 0.5591 5.40 - 8.50 0.2126 - 0.3346 D3 - 12.00 - - 0.4724 - E 15.80 16.00 16.20 0.622 0.6299 0.6378 E1 13.80 14.00 14.20 0.5433 0.5512 0.5591 5.40 - 8.50 0.2126 - 0.3346 E3 - 12.00 - - 0.4724 - e - 0.50 - - 0.0197 - L 0.45 0.60 0.75 0.0177 0.0236 0.0295 L1 - 1.00 - - 0.0394 - k - 3.50 7.00 - 0.1378 0.2756 ccc - - 0.08 - - 0.0031 (2) D2 (2)) E2 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. The size of exposed pad is variable depending of lead frame design pad size. End user should verify “D2” and “E2” dimensions for each device application. DocID029257 Rev 1 275/277 276 Revision history 20 L9680 Revision history Table 75. Document revision history 276/277 Date Revision 03-May-2016 1 Changes Initial release. DocID029257 Rev 1 L9680 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2016 STMicroelectronics – All rights reserved DocID029257 Rev 1 277/277 277