INTERSIL ISL22426

ISL22426
®
Dual Digitally Controlled Potentiometer (XDCP™)
Data Sheet
July 17, 2006
FN6180.0
Low Noise, Low Power, SPI® Bus, 128 Taps
Features
The ISL22426 integrates two digitally controlled
potentiometers (DCP) and non-volatile memory on a
monolithic CMOS integrated circuit.
• Two potentiometers in one package
The digitally controlled potentiometers are implemented with
a combination of resistor elements and CMOS switches. The
position of the wipers are controlled by the user through the
SPI serial interface. Each potentiometer has an associated
volatile Wiper Register (WR) and a non-volatile Initial Value
Register (IVR) that can be directly written to and read by the
user. The contents of the WR controls the position of the
wiper. At power-up the device recalls the contents of the
DCP’s IVR to the corresponding WR.
• SPI serial interface
The DCPs can be used as three-terminal potentiometers or
as two-terminal variable resistors in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• High reliability
- Endurance: 1,000,000 data changes per bit per register
• 128 resistor taps
• Non-volatile storage of wiper position
• Wiper resistance: 70Ω typical @ 3.3V
• Shutdown mode
• Shutdown current 5µA max
• Power supply: 2.7V to 5.5V
• 50kΩ or 10kΩ total resistance
- Register data retention: 50 years @ T <55°C
• 14 Lead TSSOP
Pinout
• Pb-free plus anneal product (RoHS compliant)
ISL22426
(14 LEAD TSSOP)
TOP VIEW
VCC
1
14
SDI
SHDN
2
13
CS
RH0
3
12
RH1
RL1
RW1
RL0
4
11
RW0
5
10
NC
6
9
GND
SCK
7
8
SDO
Ordering Information
PART NUMBER
PART MARKING
RESISTANCE OPTION
(kΩ)
TEMP. RANGE
(°C)
PACKAGE
PKG. DWG. #
ISL22426UFV14Z
(Notes 1, 2)
22426 UFVZ
50
-40 to +125
14 Ld TSSOP
(Pb-free)
M14.173
ISL22426WFV14Z
(Notes 1, 2)
22426 WFVZ
10
-40 to +125
14 Ld TSSOP
(Pb-free)
M14.173
NOTES:
1. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate
termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
2. Add “-TK” suffix for 1,000 Tape and Reel option
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2005. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
ISL22426
Block Diagram
VCC
SCK
SDI
SPI
INTERFACE
SDO
CS
POWER UP
INTERFACE,
CONTROL
AND STATUS
LOGIC
RH1
WR1
RW1
RL1
RH0
NONVOLATILE
REGISTERS
SHDN
WR0
RW0
RL0
GND
Pin Descriptions
TSSOP PIN
SYMBOL
1
VCC
2
SHDN
3
RH0
“High” terminal of DCP0
4
RL0
“Low” terminal of DCP0
5
RW0
“Wiper” terminal of DCP0
6
NC
7
SCK
SPI interface clock input
8
SDO
Open drain SPI interface Data Output
9
GND
Device ground pin
10
RW1
“Wiper” terminal of DCP1
11
RL1
“Low” terminal of DCP1
12
RH1
“High” terminal of DCP1
13
CS
Chip Select active low input
14
SDI
SPI interface Data Input
2
DESCRIPTION
Power supply pin
Shutdown active low input
FN6180.0
July 17, 2006
ISL22426
Absolute Maximum Ratings
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Voltage at any Digital Interface Pin
with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V
Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC
Lead Temperature (Soldering, 10s) . . . . . . . . . . . . . . . . . . . . . 300°C
IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA
Latchup (Note 4) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C
ESD (HBM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5kV
(CDM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV
Thermal Resistance (Typical, Note 3)
θJA (°C/W)
14 Lead TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
Recommended Operating Conditions
Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C
Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +150°C
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
4. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using
a max negative pulse of -0.8V for all pins.
Analog Specifications
SYMBOL
RTOTAL
VRH, VRL
RW
CH/CL/CW
(Note 21)
ILkgDCP
Over recommended operating conditions unless otherwise stated.
PARAMETER
RH to RL resistance
TEST CONDITIONS
MIN
TYP
(NOTE 5)
MAX
UNIT
W option
10
kΩ
U option
50
kΩ
RH to RL resistance tolerance
W and U option
End-to-End Temperature Coefficient
W option
±50
ppm/°C
(Note 21)
U option
±80
ppm/°C
(Note 21)
VRH and VRL Terminal Voltages
VRH and VRL to GND
Wiper resistance
VCC = 3.3V @ +25°C, wiper current =
VCC/RTOTAL
-20
0
70
Voltage at pin from GND to VCC
0.1
%
VCC
V
200
Ω
10/10/25
Potentiometer capacitance
Leakage on DCP pins
+20
pF
1
µA
VOLTAGE DIVIDER MODE (0V @ RLi; VCC @ RHi; measured at RWi, unloaded; i = 0 or 1)
INL
(Note 10)
Integral non-linearity
Monotonic over all tap positions
-1
1
LSB
(Note 6)
DNL
(Note 9)
Differential non-linearity
Monotonic over all tap positions
-0.5
0.5
LSB
(Note 6)
ZSerror
(Note 7)
Zero-scale error
W option
0
1
5
U option
0
0.5
2
LSB
(Note 6)
FSerror
(Note 8)
Full-scale error
W option
-5
-1
0
U option
-2
-1
0
VMATCH
(Note 11)
DCP to DCP matching
Any two DCPs at same tap position, same
voltage at all RH terminals, and same voltage
at all RL terminals
-2
TCV
(Note 12)
Ratiometric temperature coefficient
DCP register set to 40 hex
3
2
±4
LSB
(Note 6)
LSB
(Note 6)
ppm/°C
FN6180.0
July 17, 2006
ISL22426
Analog Specifications
SYMBOL
Over recommended operating conditions unless otherwise stated. (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 5)
MAX
UNIT
RESISTOR MODE (Measurements between RWi and RLi with RHi not connected, or between RWi and RHi with RLi not connected; i = 0 or 1)
RINL
(Note 16)
Integral non-linearity
DCP register set between 10h and 7Fh;
monotonic over all tap positions
-1
1
MI
(Note 13)
RDNL
(Note 15)
Differential non-linearity
DCP register set between 10h and 7Fh;
monotonic over all tap positions
-0.5
0.5
MI
(Note 13)
Roffset
(Note 14)
Offset
W option
0
1
7
MI
(Note 13)
U option
0
0.5
2
MI
(Note 13)
Any two DCPs at the same tap position with
the same terminal voltages
-2
2
MI
(Note 13)
MAX
UNIT
0.5
mA
RMATCH
(Note 17)
DCP to DCP matching
Operating Specifications Over the recommended operating conditions unless otherwise specified.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 5)
ICC1
VCC supply current (volatile
write/read)
fSCK = 5MHz; (for SPI Active, Read and
Volatile Write states only)
ICC2
VCC supply current (non-volatile
write/read)
fSCK = 5MHz; (for SPI Active, Read and Nonvolatile Write states only)
3
mA
VCC current (standby)
VCC = +5.5V @ +85°C, SPI interface in
standby state
5
µA
VCC = +5.5V @ +125°C, SPI interface in
standby state
7
µA
VCC = +3.6V @ +85°C, SPI interface in
standby state
3
µA
VCC = +3.6V @ +125°C, SPI interface in
standby state
5
µA
VCC = +5.5V @ +85°C, SPI interface in
standby state
3
µA
VCC = +5.5V @ +125°C, SPI interface in
standby state
5
µA
VCC = +3.6V @ +85°C, SPI interface in
standby state
2
µA
VCC = +3.6V @ +125°C, SPI interface in
standby state
4
µA
1
µA
ISB
ISD
ILkgDig
VCC current (shutdown)
Leakage current, at pins SHDN, SCK, Voltage at pin from GND to VCC
SDI, SDO and CS
-1
tWRT
(Note 21)
Wiper Response Time after SPI write
to WR register
1.5
µs
tShdnRec
(Note 21)
DCP recall time from shutdown mode From rising edge of SHDN signal to wiper
stored position and RH connection
1.5
µs
1.5
µs
SCK rising edge of last bit of ACR data byte
to wiper stored position and RH connection
Vpor
Power-on recall voltage
VccRamp
VCC ramp rate
tD
Power-up delay
Minimum VCC at which memory recall occurs
2.0
2.6
0.2
VCC above Vpor, to DCP Initial Value
Register recall completed, and SPI Interface
in standby state
4
V
V/ms
3
ms
FN6180.0
July 17, 2006
ISL22426
Operating Specifications Over the recommended operating conditions unless otherwise specified. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
TYP
(NOTE 5)
MAX
UNIT
EEPROM SPECIFICATION
EEPROM Endurance
EEPROM Retention
tWC
(Note 19)
Temperature T ≤ 55 °C
1,000,000
Cycles
50
Years
Non-volatile Write cycle time
12
20
ms
SERIAL INTERFACE SPECIFICATIONS
VIL
SHDN, SCK, SDI, and CS input buffer
LOW voltage
-0.3
0.3*VCC
V
VIH
SHDN, SCK, SDI, and CS input buffer
HIGH voltage
0.7*VCC
VCC+0.3
V
Hysteresis
SHDN, SCK, SDI, and CS input buffer
hysteresis
0.05*
VCC
VOL
SDO output buffer LOW voltage
IOL = 4mA
Rpu
(Note 20)
SDO pull-up resistor off-chip
Maximum is determined by tRO and tFO with
maximum bus load Cb = 30pF, fSCK = 5MHz
Cpin
(Note 21)
SHDN, SCK, SDI, SDO and CS pin
capacitance
V
0
0.4
V
2
kΩ
10
pF
fSCK
SPI frequency
tCYC
SPI clock cycle time
200
ns
tWH
SPI clock high time
100
ns
tWL
SPI clock low time
100
ns
tLEAD
Lead time
250
ns
tLAG
Lag time
250
ns
tSU
SDI, SCK and CS input setup time
50
ns
tH
SDI, SCK and CS input hold time
50
ns
tRI
SDI, SCK and CS input rise time
10
ns
tFI
SDI, SCK and CS input fall time
10
20
ns
SDO output Disable time
0
100
ns
350
ns
tDIS
5
MHz
tV
SDO output valid time
tHO
SDO output hold time
tRO
SDO output rise time
Rpu = 2k, Cb = 30pF
60
ns
tFO
SDO output fall time
Rpu = 2k, Cb = 30pF
60
ns
tCS
CS deselect time
0
2
ns
µs
NOTES:
5. Typical values are for TA = +25°C and 3.3V supply voltage.
6. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the
incremental voltage when changing from one tap to an adjacent tap.
7. ZS error = V(RW)0/LSB.
8. FS error = [V(RW)127 – VCC]/LSB.
9. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting.
10. INL = [V(RW)i – i • LSB – V(RW)]/LSB for i = 1 to 127
11. VMATCH = [V(RWx)i – V(RWy)i]/LSB, for i = 1 to 127, x = 0 or 1 and y = 0 or 1.
Max ( V ( RW ) i ) – Min ( V ( RW ) i )
10 6
12. TC = --------------------------------------------------------------------------------------------- × ----------------- for i = 16 to 112 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper
V
[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range.
5
FN6180.0
July 17, 2006
ISL22426
13. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and
00 hex respectively.
14. Roffset = RW0/MI, when measuring between RW and RL.
Roffset = RW127/MI, when measuring between RW and RH.
15. RDNL = (RWi – RWi-1)/MI, for i = 1 to 127.
16. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 127.
17. RMATCH = (RWi,x – RWi,y)/MI, for i = 1 to 127, x = 0 or 1 and y = 0 or 1.
6
for i = 16 to 112, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min ( ) is
[ Max ( Ri ) – Min ( Ri ) ]
10
TC R = ---------------------------------------------------------------- × ----------------- the minimum value of the resistance over the temperature range.
[ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 165°C
19. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle.
18.
20. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates.
21. This parameter is not 100% tested.
Timing Diagrams
Input Timing
tCS
CS
tCYC
tLEAD
tLAG
...
SCK
tSU
tH
tWL
...
MSB
SDI
tRI
tFI
tWH
LSB
HIGH IMPEDANCE
SDO
Output Timing
CS
SCK
...
tV
tDIS
...
MSB
SDO
SDI
tHO
LSB
ADDR
XDCP Timing (for All Load Instructions)
CS
SCK
...
tWRT
SDI
...
MSB
LSB
VW
SDO
HIGH IMPEDANCE
6
FN6180.0
July 17, 2006
ISL22426
Typical Performance Curves
VCC
100
1.2
80
T =125ºC
70
1
VCC
60
0.8
Isb (µA)
WIPER RESISITANCE (Ω)
1.4
Vcc = 3.3V, T = 125ºC
90
50
40
0.6
30
0.4
Vcc = 3.3V, T = -40ºC
Vcc = 3.3V, T = 20ºC
20
T =25ºC
10
0.2
0
0
0
20
40
60
80
100
120
2.7
3.2
3.7
4.2
TAP POSITION (DECIMAL)
5.2
Vcc, V
FIGURE 1. WIPER RESISTANCE vs TAP POSITION
[ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W)
FIGURE 2. STANDBY ICC vs VCC
0.2
0.2
Vcc = 2.7V
T = 25ºC
T = 25ºC
Vcc = 2.7V
0.1
INL (LSB)
0.1
DNL (LSB)
4.7
0
0
-0.1
-0.1
Vcc = 5.5V
Vcc = 5.5V
-0.2
-0.2
0
20
40
60
80
100
0
120
20
40
FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
120
10k
-0.30
0.90
Vcc = 2.7V
0.70
Vcc = 2.7V
Vcc = 5.5V
0.30
0.10
-20
0
20
40
60
80
TEMPERATURE (ºC)
FIGURE 5. ZSerror vs TEMPERATURE
7
50k
Vcc = 5.5V
-0.60
-0.90
10k
-1.20
50k
-0.10
FSerror (LSB)
ZSerror (LSB)
100
FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER
MODE FOR 10kΩ (W)
1.10
-0.30
-40
80
0.00
1.30
0.50
60
TAP POSITION (DECIMAL)
TAP POSITION (DECIMAL)
100
120
-1.50
-40
-20
0
20
40
60
80
100
120
TEMPERATURE (ºC)
FIGURE 6. FSerror vs TEMPERATURE
FN6180.0
July 17, 2006
ISL22426
Typical Performance Curves
0.4
T=25ºC
T = 25ºC
0.2
0.2
0
0
INL (LSB)
DNL (LSB)
0.4
(Continued)
-0.2
Vcc = 5.5V
-0.2
Vcc =5.5V
Vcc =2.7V
Vcc = 2.7V
-0.4
-0.4
-0.6
16
-0.6
36
56
76
96
116
16
36
TAP POSITION(DECIMAL)
FIGURE 7. DNL vs TAP POSITION IN Rheostat MODE FOR
10kΩ (W)
76
96
116
FIGURE 8. INL vs TAP POSITION IN Rheostat MODE FOR
10kΩ (W)
1.00
105
50k
Vcc = 2.7V
90
0.50
10k
75
TCv (ppm/°C)
END TO END RTOTAL CHANGE (%)
56
TAP POSITION (DECIMAL)
0.00
-0.50
Vcc = 5.5V
-1.00
-40
10k
60
45
30
50k
15
0
-20
0
20
40
60
80
100
120
16
36
56
76
96
TAP POSITION (DECIM AL)
TEMPERATURE (ºC)
FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm
FIGURE 9. END TO END RTOTAL % CHANGE vs
TEMPERATURE
INPUT
OUTPUT
300
TCr (ppm/°C)
250
10k
200
150
50k
100
Wiper at Mid Point (position 40h)
Rtotal = 9.5kΩ
50
0
16
36
56
76
96
TAP POSITION (DECIMAL)
FIGURE 11. TC FOR Rheostat MODE IN ppm
8
FIGURE 12. FREQUENCY RESPONSE (2.6MHz)
FN6180.0
July 17, 2006
ISL22426
Typical Performance Curves
(Continued)
Wiper Mid Point Movement
from 3Fh to 40h
FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h
FIGURE 14. LARGE SIGNAL SETTLING TIME
Pin Description
Bus Interface Pins
Potentiometer Pins
Serial Clock (SCK)
This is the serial clock input of the SPI serial interface.
RHi and RLi (i = 0, 1)
The high (RHi) and low (RLi) terminals of the ISL22426 are
equivalent to the fixed terminals of a mechanical
potentiometer. RHi and RLi are referenced to the relative
position of the wiper and not the voltage potential on the
terminals. With WRi set to 127 decimal, the wiper will be
closest to RHi, and with the WRi set to 0, the wiper is closest
to RLi.
Serial Data Output (SDO)
The SDO is an open drain serial data output pin. During a
read cycle, the data bits are shifted out at the falling edge of
the serial clock SCK, while the CS input is low.
SDO requires an external pull-up resistor for proper
operation.
Serial Data Input (SDI)
RWi (i = 0, 1)
RWi is the wiper terminal and is equivalent to the movable
terminal of a mechanical potentiometer. The position of the
wiper within the array is determined by the WRi register.
SHDN
The SHDN pin forces the resistor to end-to-end open circuit
condition on RHi and shorts RWi to RLi. When SHDN is
returned to logic high, the previous latch settings put RWi at
the same resistance setting prior to shutdown. This pin is
logically ORed with SHDN bit in ACR register. SPI interface
is still available in shutdown mode and all registers are
accessible. This pin must remain HIGH for normal operation.
RHi
RWi
RLi
FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE
9
The SDI is the serial data input pin for the SPI interface. It
receives device address, operation code, wiper address and
data from the SPI external host device. The data bits are
shifted in at the rising edge of the serial clock SCK, while the
CS input is low.
Chip Select (CS)
CS LOW enables the ISL22426, placing it in the active
power mode. A HIGH to LOW transition on CS is required
prior to the start of any operation after power up. When CS is
HIGH, the ISL22426 is deselected and the SDO pin is at
high impedance, and (unless an internal write cycle is
underway) the device will be in the standby state.
Principles of Operation
The ISL22426 is an integrated circuit incorporating two
DCPs with its associated registers, non-volatile memory and
the SPI serial interface providing direct communication
between host and potentiometers and memory. The resistor
array is comprised of individual resistors connected in
series. At either end of the array and between each resistor
is an electronic switch that transfers the potential at that
point to the wiper.
FN6180.0
July 17, 2006
ISL22426
The electronic switches on the device operate in a “make
before break” mode when the wiper changes tap positions.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
When the device is powered down, the last value stored in
IVRi will be maintained in the non-volatile memory. When
power is restored, the contents of the IVRi is recalled and
loaded into the corresponding WRi to set the wiper to the
initial value.
6
5
4
3
2
General Purpose
General Purpose
General Purpose
General Purpose
General Purpose
Not Available
Not Available
Not Available
Not Available
Not Available
DCP Description
1
0
IVR1
IVR0
WR1
WR0
Each DCP is implemented with a combination of resistor
elements and CMOS switches. The physical ends of each
DCP are equivalent to the fixed terminals of a mechanical
potentiometer (RH and RL pins). The RW pin of each DCP is
connected to intermediate nodes, and is equivalent to the
wiper terminal of a mechanical potentiometer. The position
of the wiper terminal within the DCP is controlled by volatile
Wiper Register (WR). Each DCP has its own WR. When the
WR of a DCP contains all zeroes (WR[6:0]= 00h), its wiper
terminal (RW) is closest to its “Low” terminal (RL). When the
WR register of a DCP contains all ones (WR[6:0]= 7Fh), its
wiper terminal (RW) is closest to its “High” terminal (RH). As
the value of the WR increases from all zeroes (0) to all ones
(127 decimal), the wiper moves monotonically from the
position closest to RL to the closest to RH. At the same time,
the resistance between RW and RL increases monotonically,
while the resistance between RH and RW decreases
monotonically.
While the ISL22426 is being powered up, all four WRs are
reset to 40h (64 decimal), which locates RW roughly at the
center between RL and RH. After the power supply voltage
becomes large enough for reliable non-volatile memory
reading, all WRs will be reload with the value stored in
corresponding non-volatile Initial Value Registers (IVRs).
The WRs can be read or written to directly using the SPI
serial interface as described in the following sections. The
SPI interface register address bits have to be set to 0000b or
0001b to access the WR of DCP0 or DCP1 respectively. The
WRi and IVRi can be read or written to directly using the SPI
serial interface as described in the following sections.
Memory Description
The ISL22426 contains seven non-volatile and three volatile
8-bit registers. The memory map of ISL22426 is on Table 1.
The two non-volatile registers (IVRi) at address 0 and 1,
contain initial wiper value and volatile registers (WRi) contain
current wiper position. In addition, five non-volatile General
Purpose registers from address 2 to address 6 are available.
The non-volatile IVRi and volatile WRi registers are
accessible with the same address.
The Access Control Register (ACR) contains information
and control bits described below in Table 2.
The VOL bit (ACR[7]) determines whether the access is to
wiper registers WR or initial value registers IVR.
TABLE 2. ACCESS CONTROL REGISTER (ACR)
BIT #
7
6
5
4
3
2
1
0
Bit Name
VOL
SHDN
WIP
0
0
0
0
0
If VOL bit is 0, the non-volatile IVR register is accessible. If
VOL bit is 1, only the volatile WR is accessible. Note, value
is written to IVR register also is written to the WR. The
default value of this bit is 0.
The SHDN bit (ACR[6]) disables or enables Shutdown
mode. This bit is logically ORed with SHDN pin. When this
bit is 0, DCP is in Shutdown mode. The default value of
SHDN bit is 1.
The WIP bit (ACR[5]) is read only bit. It indicates that nonvolatile write operation is in progress. The WIP bit can be
read repeatedly after a non-volatile write to determine if the
write has been completed. It is impossible to write to the
IVRi, WRi or ACR while WIP bit is 1.
SPI Serial Interface
The ISL22426 supports an SPI serial protocol, mode 0. The
device is accessed via the SDI input and SDO output with
data clocked in on the rising edge of SCK, and clocked out
on the falling edge of SCK. CS must be LOW during
communication with the ISL22426. SCK and CS lines are
controlled by the host or master. The ISL22426 operates
only as a slave device.
All communication over the SPI interface is conducted by
sending the MSB of each byte of data first.
TABLE 1. MEMORY MAP
ADDRESS
NON-VOLATILE
VOLATILE
8
—
ACR
7
Reserved
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ISL22426
Protocol Conventions
be written to volatile or both volatile and non-volatile
registers. Refer to “Memory Description” and Figure 16.
The first byte sent to the ISL22426 from the SPI host is the
Identification Byte. A valid Identification Byte contains 0101
as the four MSBs, with the following four bits set to 0.
Device can receive more than one byte of data by auto
incrementing the address after each received byte. Note
after reaching the address 0110b, the internal pointer “rolls
over” to address 0000b.
The internal non-volatile write cycle starts after rising edge of
CS and takes up to 20ms. Thus, non-volatile registers must
be written individually.
TABLE 3. IDENTIFICATION BYTE FORMAT
0
1
0
1
0
0
0
0
(MSB)
(LSB)
The next byte sent to the ISL22426 contains the instruction
and register pointer information. The four MSBs are the
instruction and four LSBs are register address (see Table 4).
Read Operation
A read operation to the ISL22426 is a three-byte operation. It
requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte
following by “dummy” Data Byte is sent to SDI pin. The SPI
host reads the data from SDO pin on falling edge of SCK.
The host terminates the read operation by pulling the CS pin
from LOW to HIGH (see Figure 17).
TABLE 4. IDENTIFICATION BYTE FORMAT
7
6
5
4
3
2
1
0
I3
I2
I1
I0
R3
R2
R1
R0
There are only two valid instruction sets:
The ISL22426 will provide the Data Bytes to the SDO pin as
long as SCK is provided by the host from the registers
indicated by an internal pointer. This pointer initial value is
determined by the register address in the Read operation
instruction, and increments by one during transmission of
each Data Byte. After reaching the memory location 0110b,
the pointer “rolls over” to 0000b, and the device continues to
output the data for each received SCK clock.
1011(binary) - is a Read operation
1100(binary) - is a Write operation
Write Operation
A Write operation to the ISL22426 is a three-byte operation.
It requires first, the CS transition from HIGH to LOW, then a
valid Identification Byte, then a valid instruction byte
following by Data Byte is sent to SDI pin. The host
terminates the write operation by pulling the CS pin from
LOW to HIGH. For a write to addresses 0000b or 0001b, the
MSB at address 8 (ACR[7]) determines if the Data Byte is to
In order to read back the non-volatile IVR, it is recommended
that the application reads the ACR first to verify the WIP bit
is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat
its reading sequence again.
CS
SCK
SDI
0
1
0
1
0
0
0
0
0
I3
I2
I1
I0
R3
R2
R1 R0
0
D6 D5 D4
D3
D2
D1 D0
D2
D1 D0
FIGURE 16. THREE BYTE WRITE SEQUENCE
CS
SCK
SDI
DON’T CARE
0
1
0
1
0
0
0
0
0
I3
I2
I1
I0
R3
R2
R1 R0
SDO
0
D6 D5 D4
D3
FIGURE 17. THREE BYTE READ SEQUENCE
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ISL22426
Applications Information
any non-volatile memory changes. This is done by setting
MSB bit at address 1000b to 1.
Communicating with ISL22426
The non-volatile IVRi stores the power up value of the wiper.
IVRs are accessible when MSB bit at address 1000b is set
to 0. Writing a new value to the IVRi register will set a new
power up position for the wiper. Also, writing to this register
will load the same value into the corresponding WRi as the
IVRi. Reading from the IVRi will not change the WRi, if its
contents are different.
Communication with ISL22426 proceeds using SPI interface
through the ACR (address 1000b), IVRi (addresses 0000b,
0001b) and WRi (addresses 0000b, 0001b) registers.
The wiper of the potentiometer is controlled by the WRi
register. Writes and reads can be made directly to these
registers to control and monitor the wiper position without
Examples:
A. Writing to the IVR:
This sequence will write a new value (77h) to the IVR0(non-volatile):
Set the ACR (Addr 1000b) for NV write (40h)
Send the ID byte, Instruction Byte, then the Data byte
0 1 0 1 0 0 0 0 1 1 0 0 1 0 0
0
0 1 0 0
(Sent to DI)
0
0
0
0
Set the IVR0 (Addr 0000b) to 77h
Send the ID byte, Instruction Byte, then the Data byte
0 1 0 1 0 0 0 0 1 1 0 0 0 0 0
0
0 1 1 1
(Sent to DI)
0
1
1
1
0
1 1 0 0
(Sent to DI)
0
0
0
0
x
x
x
x
B. Reading from the WR:
This sequence will read the value from the WR1 (volatile):
Write to ACR first to access the volatile WRs
Send the ID byte, Instruction Byte, then the Data byte
0 1 0 1 0 0 0 0 1 1 0 0 1 0 0
Read the data from WR1 (Addr 0001b)
Send the ID byte, Instruction Byte, then Read the Data byte
0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 1 x x x x
(Out on DO)
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FN6180.0
July 17, 2006
ISL22426
hin Shrink Small Outline Plastic Packages (TSSOP)
M14.173
N
INDEX
AREA
E
0.25(0.010) M
E1
2
SYMBOL
3
0.05(0.002)
-A-
INCHES
GAUGE
PLANE
-B1
14 LEAD THIN SHRINK SMALL OUTLINE PLASTIC
PACKAGE
B M
0.25
0.010
SEATING PLANE
L
A
D
-C-
α
e
A1
b
A2
c
0.10(0.004)
0.10(0.004) M
C A M
B S
MIN
1. These package dimensions are within allowable dimensions of
JEDEC MO-153-AC, Issue E.
MILLIMETERS
MIN
MAX
NOTES
A
-
0.047
-
1.20
-
A1
0.002
0.006
0.05
0.15
-
A2
0.031
0.041
0.80
1.05
-
b
0.0075
0.0118
0.19
0.30
9
c
0.0035
0.0079
0.09
0.20
-
D
0.195
0.199
4.95
5.05
3
E1
0.169
0.177
4.30
4.50
4
e
0.026 BSC
0.65 BSC
-
E
0.246
0.256
6.25
6.50
-
L
0.0177
0.0295
0.45
0.75
6
8o
0o
N
NOTES:
MAX
α
14
0o
14
7
8o
Rev. 2 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E1” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “b” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact. (Angles in degrees)
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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13
FN6180.0
July 17, 2006