ISL22416 ® Single Digitally Controlled Potentiometer (XDCP™) Data Sheet September 9, 2009 FN6227.2 Low Noise, Low Power, SPI® Bus, 128 Taps Features The ISL22416 integrates a single digitally controlled potentiometer (DCP) and non-volatile memory on a monolithic CMOS integrated circuit. • 128 resistor taps The digitally controlled potentiometer is implemented with a combination of resistor elements and CMOS switches. The position of the wiper is controlled by the user through the SPI serial interface. The potentiometer has an associated volatile Wiper Register (WR) and a non-volatile Initial Value Register (IVR) that can be directly written to and read by the user. The contents of the WR controls the position of the wiper. At power-up, the device recalls the contents of the DCP’s IVR to the WR. • Non-volatile storage of wiper position • SPI serial interface • Wiper resistance: 70Ω typical @ VCC = 3.3V • Shutdown mode • Shutdown current 5µA max • Power supply: 2.7V to 5.5V • 50kΩ or 10kΩ total resistance • High reliability - Endurance: 1,000,000 data changes per bit per register - Register data retention: 50 years @ T ≤ +55°C The DCP can be used as a three-terminal potentiometer or as a two-terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing. • 10 Ld MSOP and 10 Ld TDFN package • Pb-free (RoHS compliant) Pinout ISL22416 (10 LD TDFN) TOP VIEW ISL22416 (10 LD MSOP) TOP VIEW SCK 1 10 VCC SCK 1 O 10 VCC SDO 2 9 RH SDO 2 9 RH SDI 3 8 RW SDI 3 8 RW 4 7 RL CS 4 7 RL SHDN 5 6 GND CS SHDN 5 6 GND Ordering Information PART NUMBER (Note) PART MARKING RESISTANCE OPTION (kΩ) TEMP. RANGE (°C) PACKAGE (Pb-free) PKG. DWG. # ISL22416UFU10Z* 416UZ 50 -40 to +125 10 Ld MSOP M10.118 ISL22416UFRT10Z* 416U 50 -40 to +125 10 Ld 3x3 TDFN L10.3x3B ISL22416WFU10Z* 416WZ 10 -40 to +125 10 Ld MSOP M10.118 ISL22416WFRT10Z* 416W 10 -40 to +125 10 Ld 3x3 TDFN L10.3x3B *Add “-TK” suffix for tape and reel. Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) and XDCP are registered trademarks of Intersil Americas Inc. Copyright Intersil Americas Inc. 2006, 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. ISL22416 Block Diagram VCC SCK SDO SPI INTERFACE SDI CS POWER-UP INTERFACE, CONTROL AND STATUS LOGIC RH WR RL IVR NON-VOLATILE REGISTER SHDN RW GND Pin Descriptions MSOP/TDFN PIN NUMBER SYMBOL 1 SCK SPI interface clock input 2 SDO Push-pull/Open Drain Data Output of the SPI serial interface 3 SDI Data Input of the SPI serial interface 4 CS Chip Select active low input 5 SHDN 6 GND 7 RL “Low” terminal of DCP 8 RW “Wiper” terminal of DCP 9 RH “High” terminal of DCP 10 VCC Power supply pin 2 DESCRIPTION Shutdown active low input Device ground pin FN6227.2 September 9, 2009 ISL22416 Absolute Maximum Ratings Thermal Information Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Voltage at any Digital Interface Pin with Respect to GND . . . . . . . . . . . . . . . . . . . . . -0.3V to VCC+0.3 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6V Voltage at any DCP pin with Respect to GND . . . . . . . -0.3V to VCC IW (10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA Latchup (Note 1) . . . . . . . . . . . . . . . . . . Class II, Level B @ +125°C ESD Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5kV Charge Device Model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Lead MSOP (Note 2). . . . . . . . . . . . 162 N/A 10 Lead TDFN (Notes 2, 3) . . . . . . . . . 74 7 Maximum Junction Temperature (Plastic Package). . . . . . . . +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Temperature Range (Extended Industrial). . . . . . . .-40°C to +125°C Power Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5mW VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3.0mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 1. Jedec Class II pulse conditions and failure criterion used. Level B exceptions are: using a max positive pulse of 6.5V on the SHDN pin, and using a max negative pulse of -1V for all pins. 2. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 3. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Analog Specifications SYMBOL RTOTAL Over recommended operating conditions, unless otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. PARAMETER RH to RL Resistance TEST CONDITIONS MIN TYP (Note 4) MAX UNIT W option 10 kΩ U option 50 kΩ RH to RL Resistance Tolerance W and U option End-to-End Temperature Coefficient W option ±50 ppm/°C (Note 18) U option ±80 ppm/°C (Note 18) Wiper Resistance VCC = 3.3V, wiper current = VCC/RTOTAL 70 VRH, VRL VRH and VRL Terminal Voltages VRH and VRL to GND CH/CL/CW (Note 18) Potentiometer Capacitance RW ILkgDCP Leakage on DCP Pins -20 +20 0 200 VCC 10/10/25 Voltage at pin from GND to VCC 0.1 % Ω V pF 1 µA VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded) INL (Note 9) Integral Non-linearity Monotonic over all tap positions, W and U option -1 1 LSB (Note 5) DNL (Note 8) Differential Non-linearity Monotonic over all tap positions, W and U option -0.5 0.5 LSB (Note 5) ZSerror (Note 6) Zero-scale Error W option LSB (Note 5) FSerror (Note 7) Full-scale Error Ratiometric Temperature Coefficient TCV (Note 10, 18) 3 0 1 5 U option 0 0.5 2 W option -5 -1 0 U option -2 -1 0 DCP register set to 40 hex for W and U option ±4 LSB (Note 5) ppm/°C FN6227.2 September 9, 2009 ISL22416 Analog Specifications SYMBOL Over recommended operating conditions, unless otherwise stated. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) PARAMETER TEST CONDITIONS MIN TYP (Note 4) MAX UNIT RESISTOR MODE (Measurements between RW and RL with RH not connected, or between RW and RH with RL not connected) RINL (Note 14) Integral Non-linearity DCP register set between 10 hex and 7F hex; monotonic over all tap positions; W and U option -1 1 MI (Note 11) RDNL (Note 13) Differential Non-linearity W option -1 1 MI (Note 11) U option -0.5 0.5 MI (Note 11) W option 0 1 5 MI (Note 11) U option 0 0.5 2 MI (Note 11) Roffset (Note 12) Offset Operating Specifications Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 4) MAX UNIT ICC1 VCC Supply Current (Volatile Write/Read) fSCK = 5MHz; (for SPI Active, Read and Volatile Write states only) 0.5 mA ICC2 VCC Supply Current (Non-volatile Write/Read) fSCK = 5MHz; (for SPI Active, Read and Non-volatile Write states only) 3 mA VCC Current (Standby) VCC = +5.5V @ +85°C, SPI interface in standby state 5 µA VCC = +5.5V @ +125°C, SPI interface in standby state 7 µA VCC = +3.6V @ +85°C, SPI interface in standby state 3 µA VCC = +3.6V @ +125°C, SPI interface in standby state 5 µA VCC = +5.5V @ +85°C, SPI interface in standby state 3 µA VCC = +5.5V @ +125°C, SPI interface in standby state 5 µA VCC = +3.6V @ +85°C, SPI interface in standby state 2 µA VCC = +3.6V @ +125°C, SPI interface in standby state 4 µA 1 µA ISB ISD ILkgDig VCC Current (Shutdown) Leakage Current, at Pins SHDN, SCK, Voltage at pin from GND to VCC, SDI, SDO and CS SDO is inactive -1 tWRT (Note 18) Wiper Response Time Wiper Response Time after SPI write to WR register 1.5 µs tShdnRec (Note 18) DCP Recall Time from Shutdown Mode From rising edge of SHDN signal to wiper stored position and RH connection 1.5 µs SCK rising edge of last bit of ACR data byte to wiper stored position and RH connection 1.5 µs VPOR VCC Ramp Power-on Recall Voltage VCC Ramp Rate Minimum VCC at which memory recall occurs 2.0 0.2 4 2.6 V V/ms FN6227.2 September 9, 2009 ISL22416 Operating Specifications Over the recommended operating conditions, unless otherwise specified. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. (Continued) SYMBOL tD PARAMETER Power-up Delay TEST CONDITIONS MIN TYP (Note 4) VCC above VPOR, to DCP Initial Value Register recall completed, and SPI Interface in standby state MAX UNIT 3 ms EEPROM SPECIFICATION EEPROM Endurance EEPROM Retention tWC (Note 16) Temperature T ≤ +55°C 1,000,000 Cycles 50 Years Non-volatile Write Cycle Time 12 20 ms SERIAL INTERFACE SPECIFICATIONS VIL SHDN, SCK, SDI, and CS Input Buffer LOW Voltage -0.3 0.3*VCC V VIH SHDN, SCK, SDI, and CS Input Buffer HIGH Voltage 0.7*VCC VCC + 0.3 V Hysteresis SHDN, SCK, SDI, and CS Input Buffer Hysteresis 0.05* VCC SDO Output Buffer LOW Voltage IOL = 4mA 0.4 V Rpu (Note 17) SDO Pull-up Resistor Off-chip Maximum is determined by tRO and tFO with maximum bus load Cb = 30pF, fSCK = 5MHz 2 kΩ Cpin (Note 18) SHDN, SCK, SDI, SDO and CS Pin Capacitance 10 pF fSCK SPI Frequency 5 MHz tCYC SPI Clock Cycle Time 200 ns tWH SPI Clock High Time 100 ns tWL SPI Clock Low Time 100 ns tLEAD Lead Time 250 ns tLAG Lag Time 250 ns tSU SDI, SCK and CS Input Setup Time 50 ns tH SDI, SCK and CS Input Hold Time 50 ns tRI SDI, SCK and CS Input Rise Time 10 ns tFI SDI, SCK and CS Input Fall Time 10 20 ns SDO Output Disable Time 0 100 ns 350 ns VOL tDIS 0 V tV SDO Output Valid Time tHO SDO Output Hold Time tRO SDO Output Rise Time Rpu = 2k, Cbus = 30pF 60 ns tFO SDO Output Fall Time Rpu = 2k, Cbus = 30pF 60 ns tCS CS Deselect Time 0 2 ns µs NOTES: 4. Typical values are for TA = +25°C and 3.3V supply voltage. 5. LSB: [V(RW)127 – V(RW)0]/127. V(RW)127 and V(RW)0 are V(RW) for the DCP register set to 7F hex and 00 hex respectively. LSB is the incremental voltage when changing from one tap to an adjacent tap. 6. ZS error = V(RW)0/LSB. 7. FS error = [V(RW)127 – VCC]/LSB. 5 FN6227.2 September 9, 2009 ISL22416 NOTES: (Continued) 8. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 127. i is the DCP register setting. 9. INL = [V(RW)i – (i • LSB) – V(RW)0]/LSB for i = 1 to 127 Max ( V ( RW ) i ) – Min ( V ( RW ) i ) 10 6 - × --------------------- for i = 16 to 127 decimal, T = -40°C to 125°C. Max( ) is the maximum value of the wiper 10. TC V = --------------------------------------------------------------------------------------------[ Max ( V ( RW ) i ) + Min ( V ( RW ) i ) ] ⁄ 2 +165°C voltage and Min ( ) is the minimum value of the wiper voltage over the temperature range. 11. MI = |RW127 – RW0|/127. MI is a minimum increment. RW127 and RW0 are the measured resistances for the DCP register set to 7F hex and 00 hex respectively. 12. Roffset = RW0/MI, when measuring between RW and RL. Roffset = RW127/MI, when measuring between RW and RH. 13. RDNL = (RWi – RWi-1)/MI -1, for i = 1 to 127. 14. RINL = [RWi – (MI • i) – RW0]/MI, for i = 1 to 127. 6 [ Max ( Ri ) – Min ( Ri ) ] 10 15. TC = --------------------------------------------------------------- × ----------------- for i = 16 to 127, T = -40°C to 125°C. Max( ) is the maximum value of the resistance and Min ( ) is R [ Max ( Ri ) + Min ( Ri ) ] ⁄ 2 165°C the minimum value of the resistance over the temperature range. 16. tWC is the time from the end of a Write sequence of SPI serial interface, to the end of the self-timed internal non-volatile write cycle. 17. Rpu is specified for the highest data rate transfer for the device. Higher value pull-up can be used at lower data rates. 18. Limits should be considered typical and are not production tested. Timing Diagrams Input Timing tCS CS SCK tSU SDI tH tLAG tCYC tLEAD ... tWH tWL ... MSB tRI tFI LSB HIGH IMPEDANCE SDO Output Timing CS SCK ... tV SDO SDI MSB tHO tDIS ... LSB ADDR 6 FN6227.2 September 9, 2009 ISL22416 XDCP Timing (for All Load Instructions) CS tWC SCK ... tWRT ... MSB SDI LSB VW SDO HIGH IMPEDANCE Typical Performance Curves 100 1.2 80 1.0 70 60 ISB (µA) WIPER RESISITANCE (Ω) 1.4 VCC = 3.3V, T = +125°C 90 50 40 30 0.6 0.4 VCC = 3.3V, T = -40°C VCC = 3.3V, T = +20°C 20 T = +125°C 0.8 T = +25°C 0.2 10 0 2.7 0 0 20 40 60 80 100 120 3.2 3.7 TAP POSITION (DECIMAL) 4.2 4.7 5.2 VCC (V) FIGURE 1. WIPER RESISTANCE vs TAP POSITION [ I(RW) = VCC/RTOTAL ] FOR 10kΩ (W) FIGURE 2. STANDBY ICC vs VCC 0.2 0.2 T = +25°C T = +25°C VCC = 2.7V 0.1 INL (LSB) DNL (LSB) 0.1 0 -0.1 VCC = 2.7V 0 -0.1 VCC = 5.5V VCC = 5.5V -0.2 -0.2 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) FIGURE 3. DNL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) 7 0 20 40 60 80 100 120 TAP POSITION (DECIMAL) FIGURE 4. INL vs TAP POSITION IN VOLTAGE DIVIDER MODE FOR 10kΩ (W) FN6227.2 September 9, 2009 ISL22416 Typical Performance Curves (Continued) 0.0 1.3 10k 1.1 -0.3 ZSERROR (LSB) ZSERROR (LSB) 0.9 0.7 0.5 VCC = 2.7V VCC = 5.5V 0.3 0.1 -0.3 -40 -20 0 20 VCC = 5.5V 50k -0.6 -0.9 10k -1.2 50k -0.1 VCC = 2.7V 40 60 80 100 -1.5 -40 120 -20 0 TEMPERATURE (°C) 20 40 60 80 FIGURE 5. ZSERROR vs TEMPERATURE 0.4 T = +25°C T = +25°C VCC = 5.5V 0.2 DNL (LSB) 120 FIGURE 6. FSERROR vs TEMPERATURE 0.4 VCC = 5.5V 0.2 INL (LSB) 0 -0.2 -0.4 0 -0.2 -0.4 VCC = 2.7V -0.6 16 36 VCC = 2.7V 56 76 96 -0.6 16 116 36 TAP POSITION (DECIMAL) FIGURE 7. DNL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 56 76 96 TAP POSITION (DECIMAL) 116 FIGURE 8. INL vs TAP POSITION IN RHEOSTAT MODE FOR 10kΩ (W) 1.0 105 90 0.5 75 VCC = 2.7V TCv (ppm/°C) END TO END RTOTAL CHANGE (%) 100 TEMPERATURE (ºC) 50k 0.0 VCC = 5.5V 10k -0.5 60 45 50k 30 10k 15 -1.0 -40 0 -20 0 20 40 60 80 TEMPERATURE (ºC) FIGURE 9. END TO END RTOTAL % CHANGE vs TEMPERATURE 8 100 120 16 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 10. TC FOR VOLTAGE DIVIDER MODE IN ppm FN6227.2 September 9, 2009 ISL22416 Typical Performance Curves (Continued) OUTPUT INPUT 300 TCr (ppm/°C) 250 200 150 50k 10k 100 WIPER AT MID POINT (POSITION 40h) RTOTAL = 9.5kΩ 50 0 16 36 56 76 96 TAP POSITION (DECIMAL) FIGURE 11. TC FOR RHEOSTAT MODE IN ppm FIGURE 12. FREQUENCY RESPONSE (2.6MHz) SCL SIGNAL AT WIPER (WIPER UNLOADED) SIGNAL AT WIPER (WIPER UNLOADED MOVEMENT FROM 7Fh TO 00h) WIPER MID POINT MOVEMENT FROM 3Fh TO 40h FIGURE 13. MIDSCALE GLITCH, CODE 3Fh TO 40h Pin Description FIGURE 14. LARGE SIGNAL SETTLING TIME SHDN Potentiometer Pins RH AND RL The high (RH) and low (RL) terminals of the ISL22416 are equivalent to the fixed terminals of a mechanical potentiometer. RH and RL are referenced to the relative position of the wiper and not the voltage potential on the terminals. With WR set to 127 decimal, the wiper will be closest to RH, and with the WR set to 0, the wiper is closest to RL. RW The SHDN pin forces the resistor to end-to-end open circuit condition on RH and shorts RW to RL. When SHDN is returned to logic high, the previous latch settings put RW at the same resistance setting prior to shutdown. This pin is logically ANDed with SHDN bit in ACR register. SPI interface is still available in shutdown mode and all registers are accessible. This pin must remain HIGH for normal operation. RH RW RW is the wiper terminal and is equivalent to the movable terminal of a mechanical potentiometer. The position of the wiper within the array is determined by the WR register. RL FIGURE 15. DCP CONNECTION IN SHUTDOWN MODE 9 FN6227.2 September 9, 2009 ISL22416 Bus Interface Pins SERIAL CLOCK (SCK) This is the serial clock input of the SPI serial interface. SERIAL DATA OUTPUT (SDO) The SDO is an open drain serial data output pin. During a read cycle, the data bits are shifted out at the falling edge of the serial clock SCK, while the CS input is low. SDO requires an external pull-up resistor for proper operation. SERIAL DATA INPUT (SDI) The SDI is the serial data input pin for the SPI interface. It receives device address, operation code, wiper address and data from the SPI external host device. The data bits are shifted in at the rising edge of the serial clock SCK, while the CS input is low. CHIP SELECT (CS) CS LOW enables the ISL22416, placing it in the active power mode. A HIGH to LOW transition on CS is required prior to the start of any operation after power up. When CS is HIGH, the ISL22416 is deselected and the SDO pin is at high impedance, and (unless an internal write cycle is underway) the device will be in the standby state. Principles of Operation The ISL22416 is an integrated circuit incorporating one DCP with its associated registers, non-volatile memory and the SPI serial interface providing direct communication between host and potentiometer and memory. The resistor array is comprised of individual resistors connected in series. At either end of the array and between each resistor is an electronic switch that transfers the potential at that point to the wiper. The electronic switches on the device operate in a “make before break” mode when the wiper changes tap positions. When the device is powered down, the last value stored in IVR will be maintained in the non-volatile memory. When power is restored, the contents of the IVR is recalled and loaded into the WR to set the wiper to the initial value. DCP Description The DCP is implemented with a combination of resistor elements and CMOS switches. The physical ends of each DCP are equivalent to the fixed terminals of a mechanical potentiometer (RH and RL pins). The RW pin of the DCP is connected to intermediate nodes, and is equivalent to the wiper terminal of a mechanical potentiometer. The position of the wiper terminal within the DCP is controlled by a 7-bit volatile Wiper Register (WR). When the WR of a DCP contains all zeroes (WR<6:0>: 00h), its wiper terminal (RW) is closest to its “Low” terminal (RL). When the WR register of a DCP contains all ones (WR<6:0>: 7Fh), its wiper terminal 10 (RW) is closest to its “High” terminal (RH). As the value of the WR increases from all zeroes (0) to all ones (127 decimal), the wiper moves monotonically from the position closest to RL to the closest to RH. At the same time, the resistance between RW and RL increases monotonically, while the resistance between RH and RW decreases monotonically. While the ISL22416 is being powered up, the WR is reset to 40h (64 decimal), which locates RW roughly at the center between RL and RH. After the power supply voltage becomes large enough for reliable non-volatile memory reading, the WR will be reload with the value stored in a non-volatile Initial Value Register (IVR). The WR and IVR can be read or written to directly using the SPI serial interface as described in the following sections. Memory Description The ISL22416 contains one non-volatile 7-bit register, known as the Initial Value Register (IVR), volatile 7-bit Wiper Register (WR), and volatile 8-bit Access Control Register (ACR). The memory map is shown in Table 1. The non-volatile register (IVR) at address 0, contain initial wiper position and volatile registers (WR) contain current wiper position. TABLE 1. MEMORY MAP ADDRESS NON-VOLATILE VOLATILE 2 — ACR 1 Reserved 0 IVR WR The non-volatile IVR and volatile WR registers are accessible with the same address. The Access Control Register (ACR) contains information and control bits described in Table 2. The VOL bit (ACR<7>) determines whether the access is to wiper registers WR or initial value registers IVR. TABLE 2. ACCESS CONTROL REGISTER (ACR) BIT # 7 BIT NAME VOL 6 5 4 3 2 1 0 SHDN WIP 0 0 0 0 0 If VOL bit is 0, the non-volatile IVR register is accessible. If VOL bit is 1, only the volatile WR is accessible. Note, value is written to IVR register also is written to the WR. The default value of this bit is 0. The SHDN bit (ACR<6>) disables or enables Shutdown mode. This bit is logically ANDed with SHDN pin. When this bit is 0, DCP is in Shutdown mode. Default value of SHDN bit is 1. The WIP bit (ACR<5>) is read only bit. It indicates that non-volatile write operation is in progress. The WIP bit can be read repeatedly after a non-volatile write to determine if the write has been completed. It is impossible to write to the WR or ACR while WIP bit is 1. FN6227.2 September 9, 2009 ISL22416 Shutdown Mode The device can be put in Shutdown mode either by pulling the SHDN pin to GND or setting the SHDN bit in the ACR register to 0. The truth table for Shutdown mode is in Table 3. TABLE 3. SHUTDOWN MODE by Data Byte is sent to SDI pin. The host terminates the write operation by pulling the CS pin from LOW to HIGH. For a write to address 0 (WR), the byte at address 2 (ACR<7>) determines if the Data Byte is to be written to volatile or both volatile and non-volatile registers. Refer to “Memory Description” on page 10 and Figure 16. SHDN PIN SHDN BIT MODE High 1 Normal operation Low 1 Shutdown Read Operation High 0 Shutdown Low 0 Shutdown A read operation to the ISL22416 is a three byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte followed by “dummy” Data Byte is sent to SDI pin. The SPI host reads the data from SDO pin on falling edge of SCK. The host terminates the read operation by pulling the CS pin from LOW to HIGH (see Figure 17). The internal non-volatile write cycle starts after rising edge of CS and takes up to 20ms. SPI Serial Interface The ISL22416 supports an SPI serial protocol, mode 0. The device is accessed via the SDI input and SDO output with data clocked in on the rising edge of SCK, and clocked out on the falling edge of SCK. CS must be LOW during communication with the ISL22416. SCK and CS lines are controlled by the host or master. The ISL22416 operates only as a slave device. All communication over the SPI interface is conducted by sending the MSB of each byte of data first. The first byte sent to the ISL22416 from the SPI host is the Identification Byte. A valid Identification Byte contains 0101 as the four MSBs, with the following four bits set to 0. TABLE 4. IDENTIFICATION BYTE FORMAT 1 0 Applications Information Communicating with ISL22416 Protocol Conventions 0 In order to read back the non-volatile IVR, it is recommended that the application reads the ACR first to verify the WIP bit is 0. If the WIP bit (ACR[5]) is not 0, the host should repeat its reading sequence again. 1 0 0 0 (MSB) 0 (LSB) The next byte sent to the ISL22416 contains the instruction and register pointer information. The four MSBs are the instruction and two LSBs are register address (see Table 5). TABLE 5. IDENTIFICATION BYTE FORMAT 7 6 5 4 3 2 1 0 I3 I2 I1 I0 0 0 R1 R0 Communication with ISL22416 proceeds using SPI interface through the ACR (address 10b), IVR (address 00b) and WR (address 00b) registers. The wiper of the potentiometer is controlled by the WR register. Writes and reads can be made directly to this register to control and monitor the wiper position without any non-volatile memory changes. This is done by setting MSB bit at address 10b to 1. The non-volatile IVR stores the power up value of the wiper. IVR is accessible when MSB bit at address 10b is set to 0. Writing a new value to the IVR register will set a new power up position for the wiper. Also, writing to this register will load the same value into the WR as the IVR. Reading from the IVR will not change the WR, if its contents are different. There are only two valid instruction sets: 1011(binary) - is a Read operation 1100(binary) - is a Write operation There are only two registers address possible for this DCP. If the R1, R0 bits are zero, then the read or write is to either the IVR or the WR register (depends of VOL bit at ACR). If the R1 bit is 1 and R0 bit is 0, then the operation is on the ACR. Write Operation A Write operation to the ISL22416 is a three-byte operation. It requires first, the CS transition from HIGH to LOW, then a valid Identification Byte, then a valid instruction byte followed 11 FN6227.2 September 9, 2009 ISL22416 CS SCK SDI 0 1 0 0 1 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0 0 D6 D5 D4 D3 D2 D1 D0 D2 D1 D0 FIGURE 16. THREE BYTE WRITE SEQUENCE CS SCK SDI DON’T CARE 0 1 0 0 1 0 0 0 0 I3 I2 I1 I0 0 0 R1 R0 SDO 0 D6 D5 D4 D3 FIGURE 17. THREE BYTE READ SEQUENCE Examples B. Reading from the WR This sequence will read the value from the WR (volatile): A. Writing to the IVR This sequence will write a new value (77h) to the IVR (non-volatile): Set the ACR (Addr 02h) for NV write (40h) Write to ACR first to access the WR Send the ID byte, Instruction Byte, then the Data byte 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 0 0 Send the ID byte, Instruction Byte, then the Data byte (Sent to DI) 0 1 0 1 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 (Sent to DI) Read the data from WR (Addr 00h) Send the ID byte, Instruction Byte, then Read the Data byte Set the IVR (Addr 00h) to 77h 0 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 x x x x x x x x Send the ID byte, Instruction Byte, then the Data byte (Out on DO) 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 (Sent to DI) 12 FN6227.2 September 9, 2009 ISL22416 Mini Small Outline Plastic Packages (MSOP) N M10.118 (JEDEC MO-187BA) 10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE E1 E INCHES SYMBOL -B- INDEX AREA 1 2 0.20 (0.008) A B C TOP VIEW 4X θ 0.25 (0.010) R1 R GAUGE PLANE A SEATING PLANE -C- A2 A1 b -He D 0.10 (0.004) 4X θ L SEATING PLANE C -A0.20 (0.008) C C a SIDE VIEW CL E1 0.20 (0.008) C D -B- END VIEW MILLIMETERS MAX MIN MAX NOTES A 0.037 0.043 0.94 1.10 - A1 0.002 0.006 0.05 0.15 - A2 0.030 0.037 0.75 0.95 - b 0.007 0.011 0.18 0.27 9 c 0.004 0.008 0.09 0.20 - D 0.116 0.120 2.95 3.05 3 E1 0.116 0.120 2.95 3.05 4 e L1 MIN 0.020 BSC 0.50 BSC - E 0.187 0.199 4.75 5.05 - L 0.016 0.028 0.40 0.70 6 L1 0.037 REF 0.95 REF - N 10 10 7 R 0.003 - 0.07 - - R1 0.003 - 0.07 - - θ 5o 15o 5o 15o - α 0o 6o 0o 6o Rev. 0 12/02 NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-187BA. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. Dimension “D” does not include mold flash, protrusions or gate burrs and are measured at Datum Plane. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E1” does not include interlead flash or protrusions and are measured at Datum Plane. - H - Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. Formed leads shall be planar with respect to one another within 0.10mm (.004) at seating Plane. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension “b” does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of “b” dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Datums -A -H- . and - B - to be determined at Datum plane 11. Controlling dimension: MILLIMETER. Converted inch dimensions are for reference only 13 FN6227.2 September 9, 2009 ISL22416 Thin Dual Flat No-Lead Plastic Package (TDFN) L10.3x3B 2X 10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE 0.15 C A A D MILLIMETERS 2X 0.15 C B E SYMBOL MIN NOMINAL MAX NOTES A 0.70 0.75 0.80 - A1 - - 0.05 - 0.20 REF A3 6 INDEX AREA b 0.18 D2 B 2.23 A C SEATING PLANE D2 6 INDEX AREA 7 0.08 C 8 2 7, 8 - 1.49 1.64 1.74 7, 8 0.50 BSC - k 0.20 - - L 0.30 0.40 0.50 8 N 10 2 Nd 5 3 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. NX k 3. Nd refers to the number of terminals on D. 4. All dimensions are in millimeters. Angles are in degrees. E2 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. E2/2 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. NX L N N-1 NX b e (Nd-1)Xe REF. BOTTOM VIEW 5 0.10 M C A B 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. COMPLIANT TO JEDEC MO-229-WEED-3 except for dimensions E2 & D2. CL NX (b) 2.48 NOTES: (DATUM A) 8 2.38 Rev. 0 2/06 D2/2 1 E2 e A3 SIDE VIEW (DATUM B) 0.10 C 5, 8 3.00 BSC E // 0.30 3.00 BSC D TOP VIEW 0.25 - (A1) 9 L 5 e SECTION "C-C" C C TERMINAL TIP FOR ODD TERMINAL/SIDE All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 14 FN6227.2 September 9, 2009