Data Sheet

PCA8576D
Automotive 40 x 4 LCD segment driver for low multiplex rates
up to 1:4
Rev. 2 — 6 June 2013
Product data sheet
1. General description
The PCA8576D is a peripheral device which interfaces to almost any Liquid Crystal
Display (LCD) with low multiplex rates. It generates the drive signals for any static or
multiplexed LCD containing up to four backplanes and up to 40 segments. It can be easily
cascaded for larger LCD applications. The PCA8576D is compatible with most
microcontrollers and communicates via the two-line bidirectional I2C-bus. Communication
overheads are minimized by a display RAM with auto-incremented addressing, by
hardware subaddressing and by display memory switching (static and duplex drive
modes).
2. Features and benefits
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AEC-Q100 compliant for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static or 2, 3, 4 backplane multiplexing
Selectable display bias configuration: static, 1⁄2 or 1⁄3
Internal LCD bias generation with voltage-follower buffers
40 segment drives:
 Up to 20 7-segment numeric characters
 Up to 10 14-segment alphanumeric characters
 Any graphics of up to 160 elements
40  4-bit RAM for display data storage
Auto-incremented display data loading across device subaddress boundaries
Display memory bank switching in static and duplex drive modes
Versatile blinking modes
Independent supplies possible for LCD and logic voltages
Wide power supply range: from 1.8 V to 5.5 V
Wide logic LCD supply range:
 From 2.5 V for low-threshold LCDs
 Up to 6.5 V for high-threshold twisted nematic LCDs
Low power consumption
400 kHz I2C-bus interface
May be cascaded for large LCD applications (up to 2560 elements possible)
No external components required
Compatible with chip-on-glass and chip-on-board technology
Manufactured in silicon gate CMOS process
PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
3. Ordering information
Table 1.
Ordering information
Type number
Package
PCA8576DU
Name
Description
Version
bare die
59 bumps
PCA8576DU/2DA
3.1 Ordering options
Table 2.
Ordering options
Product type number
Sales item (12NC)
Orderable part number
IC
revision
Delivery form
PCA8576DU/2DA/Q2
935294883026
PCA8576DU/2DA/Q2,0
1
chips with bumps in tray
4. Marking
Table 3.
Marking codes
Product type number
Marking code
PCA8576DU/2DA/Q2
PC8576D-2
5. Block diagram
BP0
BP2
BP1
BP3
S0 to S39
40
VLCD
DISPLAY SEGMENT
OUTPUTS
BACKPLANE
OUTPUTS
LCD
VOLTAGE
SELECTOR
DISPLAY
REGISTER
OUTPUT BANK SELECT
AND BLINK CONTROL
DISPLAY
CONTROLLER
LCD BIAS
GENERATOR
VSS
CLK
SYNC
OSC
CLOCK SELECT
AND TIMING
BLINKER
TIMEBASE
OSCILLATOR
POWER-ON
RESET
INPUT
FILTERS
I2C-BUS
CONTROLLER
DISPLAY RAM
40 × 4-BIT
PCA8576D
COMMAND
DECODER
WRITE DATA
CONTROL
DATA POINTER AND
AUTO INCREMENT
VDD
SCL
SDA
SUBADDRESS
COUNTER
SA0
A0
A1
A2
013aaa467
Fig 1.
Block diagram of PCA8576D
PCA8576D
Product data sheet
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
6. Pinning information
S17
S16
S15
S14
S13
S12
S11
S10
S9
S8
S7
S6
S5
S4
35
34
33
32
31
30
29
28
27
26
25
24
23
22
6.1 Pinning
21
S3
S18
36
20
S2
S19
37
19
S1
S20
38
18
S0
S21
39
17
BP3
S22
40
16
BP1
S23
41
15
BP2
S24
42
14
BP0
S25
43
S26
44
13
VLCD
S27
45
S28
46
S29
47
12
VSS
S30
48
S31
49
11
SA0
S32
50
10
A2
S33
51
9
A1
53
54
55
56
57
58
59
1
2
3
4
5
6
7
8
S35
S36
S37
S38
S39
SDA
SDA
SDA
SCL
SCL
SYNC
CLK
VDD
OSC
A0
C1
52
S34
C2
PCA8576DU
013aaa468
Viewed from active side. C1 and C2 are alignment marks. For mechanical details, see Figure 23.
Fig 2.
PCA8576D
Product data sheet
Pinning diagram for PCA8576DU (bare die)
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
6.2 Pin description
Table 4.
Pin description
Symbol
Pin
Description
PCA8576DU
SDA
1, 58, 59
I2C-bus serial data input and output
SCL
2, 3
I2C-bus serial clock input
CLK
5
external clock input or output
VDD
6
supply voltage
SYNC
4
cascade synchronization input or output
OSC
7
internal oscillator enable input
A0 to A2
8 to 10
subaddress inputs
SA0
11
I2C-bus address input; bit 0
VSS
12[1]
ground supply voltage
VLCD
13
LCD supply voltage
BP0, BP2, BP1,
BP3
14 to 17
LCD backplane outputs
S0 to S39
18 to 57
LCD segment outputs
[1]
PCA8576D
Product data sheet
The substrate (rear side of the die) is connected to VSS and should be electrically isolated.
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
7. Functional description
The PCA8576D is a versatile peripheral device designed to interface any microcontroller
with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing
up to four backplanes and up to 40 segments.
The possible display configurations of the PCA8576D depend on the number of active
backplane outputs required. A selection of display configurations is shown in Table 5. All
of these configurations can be implemented in the typical system shown in Figure 3.
Table 5.
Selection of possible display configurations
Number of
Backplanes
Icons
7-segment
14-segment
Dot matrix/
Elements
4
160
20
10
160 (4  40)
3
120
15
7
120 (3  40)
2
80
10
5
80 (2  40)
1
40
5
2
40 (1  40)
VDD
R≤
Digits/Characters
tr
2CB
HOST
MICROPROCESSOR/
MICROCONTROLLER
VDD
VLCD
40 segment drives
SDA
LCD PANEL
SCL
PCA8576D
4 backplanes
OSC
A0
A1
A2
(up to 160
elements)
SA0 VSS
VSS
013aaa469
The resistance of the power lines must be kept to a minimum.
For chip-on-glass applications, due to the Indium Tin Oxide (ITO) track resistance, each supply line
must be routed separately between the chip and the connector.
Fig 3.
Typical system configuration
The host microprocessor or microcontroller maintains the 2-line I2C-bus communication
channel with the PCA8576D. The internal oscillator is enabled by connecting
pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms
are generated internally. The only other connections required to complete the system are
to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.
PCA8576D
Product data sheet
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
7.1 Power-on reset
At power-on the PCA8576D resets to the following starting conditions:
•
•
•
•
•
•
•
All backplane and segment outputs are set to VLCD
The selected drive mode is: 1:4 multiplex with 1⁄3 bias
Blinking is switched off
Input and output bank selectors are reset
The I2C-bus interface is initialized
The data pointer and the subaddress counter are cleared (set to logic 0)
The display is disabled (bit E = 0, see Table 11)
Data transfers on the I2C-bus must be avoided for 1 ms following power-on to allow the
reset action to complete.
7.2 LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider consisting of
three impedances connected in series between VLCD and VSS. The middle resistor can be
bypassed to provide a 1⁄2 bias voltage level for the 1:2 multiplex configuration. The LCD
voltage can be temperature compensated externally using the supply to pin VLCD.
7.3 LCD voltage selector
The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the
selected LCD drive configuration. The operation of the voltage selector is controlled by the
mode-set command (see Table 11) from the command decoder. The biasing
configurations that apply to the preferred modes of operation, together with the biasing
characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in
Table 6.
Table 6.
Discrimination ratios
LCD drive
mode
Number of:
LCD bias
Backplanes Levels configuration
V off  RMS 
------------------------V LCD
V on  RMS 
-----------------------V LCD
V on  RMS 
D = -----------------------V off  RMS 
static
1
2
static
0
1

3
1⁄
2
0.354
0.791
2.236
1:2 multiplex 2
4
1⁄
3
0.333
0.745
2.236
1:3 multiplex 3
4
1⁄
3
0.333
0.638
1.915
4
1⁄
3
0.333
0.577
1.732
1:2 multiplex 2
1:4 multiplex 4
A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD
threshold voltage (Vth), typically when the LCD exhibits approximately 10 % contrast. In
the static drive mode a suitable choice is VLCD > 3Vth.
Multiplex drive modes of 1:3 and 1:4 with 1⁄2 bias are possible but the discrimination and
hence the contrast ratios are smaller.
1
Bias is calculated by ------------- , where the values for a are
1+a
a = 1 for 1⁄2 bias
PCA8576D
Product data sheet
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
a = 2 for 1⁄3 bias
The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 1
V on  RMS  =
V LCD
a 2 + 2a + n
-----------------------------2
n  1 + a
(1)
where the values for n are
n = 1 for static mode
n = 2 for 1:2 multiplex
n = 3 for 1:3 multiplex
n = 4 for 1:4 multiplex
The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 2:
V off  RMS  =
V LCD
a 2 – 2a + n
-----------------------------2
n  1 + a
(2)
Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 3:
V on  RMS 
D = ----------------------- =
V off  RMS 
2
a + 1 + n – 1
-------------------------------------------2
a – 1 + n – 1
(3)
Using Equation 3, the discrimination for an LCD drive mode of 1:3 multiplex with
1⁄
2 bias
is
1⁄
2 bias
21
is ---------- = 1.528 .
3
3 = 1.732 and the discrimination for an LCD drive mode of 1:4 multiplex with
The advantage of these LCD drive modes is a reduction of the LCD full scale voltage VLCD
as follows:
• 1:3 multiplex (1⁄2 bias): V LCD =
6  V off  RMS  = 2.449V off  RMS 
4  3
- = 2.309V off  RMS 
• 1:4 multiplex (1⁄2 bias): V LCD = --------------------3
These compare with V LCD = 3V off  RMS  when 1⁄3 bias is used.
It should be noted that VLCD is sometimes referred as the LCD operating voltage.
7.3.1 Electro-optical performance
Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The
RMS voltage, at which a pixel will be switched on or off, determine the transmissibility of
the pixel.
PCA8576D
Product data sheet
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
For any given liquid, there are two threshold values defined. One point is at 10 % relative
transmission (at Vlow) and the other at 90 % relative transmission (at Vhigh), see Figure 4.
For a good contrast performance, the following rules should be followed:
V on  RMS   V high
(4)
V off  RMS   V low
(5)
Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection
of a, n (see Equation 1 to Equation 3) and the VLCD voltage.
Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module
manufacturer. Vth(off) is sometimes just named Vth. Vth(on) is sometimes named saturation
voltage Vsat.
It is important to match the module properties to those of the driver in order to achieve
optimum performance.
100 %
Relative Transmission
90 %
10 %
Vlow
OFF
SEGMENT
Vhigh
GREY
SEGMENT
VRMS [V]
ON
SEGMENT
001aam358
Fig 4.
PCA8576D
Product data sheet
Electro-optical characteristic: relative transmission curve of the liquid
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
7.4 LCD drive mode waveforms
7.4.1 Static drive mode
The static LCD drive mode is used when a single backplane is provided in the LCD. The
backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Figure 5.
Tfr
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
VLCD
state 2
0V
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl745
(1) Vstate1(t) = VSn(t)  VBP0(t).
(2) Von(RMS) = VLCD.
(3) Vstate2(t) = VSn+1(t)  VBP0(t).
(4) Voff(RMS) = 0 V.
Fig 5.
PCA8576D
Product data sheet
Static drive mode waveforms
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
7.4.2 1:2 Multiplex drive mode
The 1:2 multiplex drive mode is used when two backplanes are provided in the LCD. This
mode allows fractional LCD bias voltages of 1⁄2 bias or 1⁄3 bias as shown in Figure 6 and
Figure 7.
Tfr
VLCD
BP0
LCD segments
VLCD / 2
VSS
state 1
VLCD
BP1
state 2
VLCD / 2
VSS
VLCD
Sn
VSS
VLCD
Sn+1
VSS
(a) Waveforms at driver.
VLCD
VLCD / 2
state 1
0V
−VLCD / 2
−VLCD
VLCD
VLCD / 2
state 2
0V
−VLCD / 2
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl746
(1) Vstate1(t) = VSn(t)  VBP0(t).
(2) Von(RMS) = 0.791VLCD.
(3) Vstate2(t) = VSn+1(t)  VBP1(t).
(4) Voff(RMS) = 0.354VLCD.
Fig 6.
PCA8576D
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄2 bias
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
2VLCD / 3
Sn+1
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl747
(1) Vstate1(t) = VSn(t)  VBP0(t).
(2) Von(RMS) = 0.745VLCD.
(3) Vstate2(t) = VSn+1(t)  VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 7.
PCA8576D
Product data sheet
Waveforms for the 1:2 multiplex drive mode with 1⁄3 bias
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
7.4.3 1:3 Multiplex drive mode
When three backplanes are provided in the LCD, the 1:3 multiplex drive mode applies
(see Figure 8).
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+2
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl748
(1) Vstate1(t) = VSn(t)  VBP0(t).
(2) Von(RMS) = 0.638VLCD.
(3) Vstate2(t) = VSn+1(t)  VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 8.
PCA8576D
Product data sheet
Waveforms for the 1:3 multiplex drive mode with 1⁄3 bias
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
7.4.4 1:4 Multiplex drive mode
When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies (see
Figure 9).
Tfr
VLCD
BP0
LCD segments
2VLCD / 3
VLCD / 3
VSS
state 1
VLCD
BP1
state 2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP2
2VLCD / 3
VLCD / 3
VSS
VLCD
BP3
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+1
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+2
2VLCD / 3
VLCD / 3
VSS
VLCD
Sn+3
2VLCD / 3
VLCD / 3
VSS
(a) Waveforms at driver.
VLCD
2VLCD / 3
VLCD / 3
state 1
0V
−VLCD / 3
−2VLCD / 3
−VLCD
VLCD
2VLCD / 3
VLCD / 3
state 2
0V
−VLCD / 3
−2VLCD / 3
−VLCD
(b) Resultant waveforms
at LCD segment.
mgl749
(1) Vstate1(t) = VSn(t)  VBP0(t).
(2) Von(RMS) = 0.577VLCD.
(3) Vstate2(t) = VSn+1(t)  VBP1(t).
(4) Voff(RMS) = 0.333VLCD.
Fig 9.
PCA8576D
Product data sheet
Waveforms for the 1:4 multiplex drive mode with 1⁄3 bias
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
7.5 Oscillator
7.5.1 Internal clock
The internal logic of the PCA8576D and its LCD drive signals are timed either by its
internal oscillator or by an external clock. The internal oscillator is enabled by connecting
pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used
as the clock signal for several PCA8576D in the system that are connected in cascade.
7.5.2 External clock
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
The LCD frame signal frequency is determined by the clock frequency (fclk).
Remark: A clock signal must always be supplied to the device; removing the clock may
freeze the LCD in a DC state, which is not suitable for the liquid crystal.
7.6 Timing
The PCA8576D timing controls the internal data flow of the device. This includes the
transfer of display data from the display RAM to the display segment outputs. In cascaded
applications, the correct timing relationship between each PCA8576D in the system is
maintained by the synchronization signal at pin SYNC. The timing also generates the LCD
frame signal whose frequency is derived from the clock frequency. The frame signal
frequency is a fixed division of the clock frequency from either the internal or an external
f clk
clock: f fr = ------- .
24
7.7 Display register
The display register holds the display data while the corresponding multiplex signals are
generated. There is a one-to-one relationship between the data in the display register, the
LCD segment outputs, and one column of the display RAM.
7.8 Segment outputs
The LCD drive section includes 40 segment outputs S0 to S39 which should be
connected directly to the LCD. The segment output signals are generated in accordance
with the multiplexed backplane signals and with data residing in the display register. When
less than 40 segment outputs are required, the unused segment outputs should be left
open-circuit.
7.9 Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which must be
connected directly to the LCD. The backplane output signals are generated in accordance
with the selected LCD drive mode. If less than four backplane outputs are required, the
unused outputs can be left open-circuit.
In the 1:3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two
adjacent outputs can be tied together to give enhanced drive capabilities.
PCA8576D
Product data sheet
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
In the 1:2 multiplex drive mode, BP0 and BP2, BP1 and BP3 all carry the same signals
and may also be paired to increase the drive capabilities.
In the static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
7.10 Display RAM
The display RAM is a static 40  4-bit RAM which stores LCD data. A logic 1 in the RAM
bit-map indicates the on-state of the corresponding LCD element; similarly, a logic 0
indicates the off-state. There is a one-to-one correspondence between the RAM
addresses and the segment outputs, and between the individual bits of a RAM word and
the backplane outputs. The display RAM bit map Figure 10 shows the rows 0 to 3 which
correspond with the backplane outputs BP0 to BP3, and the columns 0 to 39 which
correspond with the segment outputs S0 to S39. In multiplexed LCD applications the
segment data of the first, second, third and fourth row of the display RAM are
time-multiplexed with BP0, BP1, BP2 and BP3 respectively.
display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
35
36
37
38
39
0
display RAM bits
1
(rows)/
backplane outputs
2
(BP)
3
mbe525
Display RAM bit map showing direct relationship between RAM addresses and segment outputs;
also between bits in a RAM word and the backplane outputs.
Fig 10. Display RAM bit map
When display data is transmitted to the PCA8576D, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and does not wait for an acknowledge cycle as with the commands. Depending
on the current multiplex drive mode, data is stored singularly, in pairs, triplets or
quadruplets. To illustrate the filling order, an example of a 7-segment numeric display
showing all drive modes is given in Figure 11; the RAM filling organization depicted
applies equally to other LCD types.
PCA8576D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 June 2013
© NXP B.V. 2013. All rights reserved.
15 of 45
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Sn+2
Sn+3
static
display RAM filling order
b
f
Sn+1
BP0
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
g
e
Sn+6
Sn
Sn+7
c
DP
d
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
Sn
a
b
f
g
multiplex
Sn+2
BP1
e
Sn+3
c
Sn+1
1:3
Sn+2
DP
d
a
b
Sn
multiplex
BP1
c
b
f
BP0
g
16 of 45
© NXP B.V. 2013. All rights reserved.
Sn+1
BP1
c
d
g e d DP
n
n+1
n+2
n+3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
MSB
a b
LSB
f
g e c d DP
n
rows
display RAM 0 b
rows/backplane
1 DP
outputs (BP)
2 c
3 x
n+1
n+2
a
d
g
x
f
e
x
x
MSB
LSB
b DP c a d g
f
e
DP
BP2
n
rows
display RAM 0 a
rows/backplane
1 c
BP3 outputs (BP) 2 b
3 DP
n+1
f
e
g
d
MSB
a c b DP f
LSB
e g d
001aaj646
x = data bit unchanged.
Fig 11. Relationship between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus
PCA8576D
multiplex
e
f
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
byte4
byte5
a
Sn
1:4
BP2
DP
d
c b a
columns
display RAM address/segment outputs (s)
byte1
byte2
byte3
g
e
rows
display RAM 0
rows/backplane
1
outputs (BP)
2
3
BP0
f
LSB
Automotive 40 x 4 LCD segment driver for low multiplex rates
Rev. 2 — 6 June 2013
All information provided in this document is subject to legal disclaimers.
Sn+1
MSB
columns
display RAM address/segment outputs (s)
byte1
byte2
BP0
1:2
transmitted display byte
columns
display RAM address/segment outputs (s)
byte1
a
Sn+4
Sn+5
LCD backplanes
NXP Semiconductors
PCA8576D
Product data sheet
LCD segments
drive mode
PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
The following applies to Figure 11:
• In static drive mode the eight transmitted data bits are placed in row 0 as one byte.
• In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words.
• In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted.
• In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words.
7.11 Data pointer
The addressing mechanism for the display RAM is realized using the data pointer.
This allows the loading of an individual display data byte, or a series of display data bytes,
into any location of the display RAM. The sequence commences with the initialization of
the data pointer by the load-data-pointer command (see Section 7.17).
Following this command, an arriving data byte is stored at the display RAM address
indicated by the data pointer. The filling order is shown in Figure 11.
After each byte is stored, the content of the data pointer is automatically incremented by a
value dependent on the selected LCD drive mode:
After each byte is stored, the contents of the data pointer is automatically incremented by
a value dependent on the selected LCD drive mode:
•
•
•
•
In static drive mode by eight
In 1:2 multiplex drive mode by four
In 1:3 multiplex drive mode by three
In 1:4 multiplex drive mode by two
If an I2C-bus data access is terminated early then the state of the data pointer is unknown.
The data pointer should be re-written prior to further RAM accesses.
7.12 Subaddress counter
The storage of display data is determined by the contents of the subaddress counter.
Storage is allowed to take place only when the contents of the subaddress counter match
with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is
defined by the device-select command (see Section 7.17). If the contents of the
subaddress counter and the hardware subaddress do not match then data storage is
inhibited but the data pointer is incremented as if data storage had taken place. The
subaddress counter is also incremented when the data pointer overflows.
The storage arrangements described lead to extremely efficient data loading in cascaded
applications. When a series of display bytes are sent to the display RAM, automatic
wrap-over to the next PCA8576D occurs when the last RAM address is exceeded.
PCA8576D
Product data sheet
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
Subaddressing across device boundaries is successful even if the change to the next
device in the cascade occurs within a transmitted character (such as during the 14th
display data byte transmitted in 1:3 multiplex mode).
The hardware subaddress must not be changed while the device is being accessed on the
I2C-bus interface.
7.13 Output bank selector
The output bank selector (see Table 14) selects one of the four rows per display RAM
address for transfer to the display register. The actual row selected depends on the
particular LCD drive mode in operation and on the instant in the multiplex sequence.
• In 1:4 multiplex mode, all RAM addresses of row 0 are selected, these are followed by
the contents of row 1, 2, and then 3
• In 1:3 multiplex mode, rows 0, 1, and 2 are selected sequentially
• In 1:2 multiplex mode, rows 0 and 1 are selected
• In static mode, row 0 is selected
The SYNC signal resets these sequences to the following starting points: row 3 for
1:4 multiplex, row 2 for 1:3 multiplex, row 1 for 1:2 multiplex and row 0 for static mode.
The PCA8576D includes a RAM bank switching feature in the static and 1:2 multiplex
drive modes. In the static drive mode, the bank-select command may request the contents
of row 2 to be selected for display instead of the contents of row 0. In the 1:2 mode, the
contents of rows 2 and 3 may be selected instead of rows 0 and 1. This gives the
provision for preparing display information in an alternative bank and to be able to switch
to it, once it is assembled.
7.14 Input bank selector
The input bank selector loads display data into the display RAM in accordance with the
selected LCD drive configuration. Display data can be loaded in row 2 in static drive mode
or in rows 2 and 3 in 1:2 multiplex drive mode by using the bank-select command. The
input bank selector functions independently to the output bank selector.
7.15 Blinking
The PCA8576D has a very versatile display blinking capability. The whole display can
blink at a frequency selected by the blink-select command (see Table 15). Each blink
frequency is a fraction of the clock frequency; the ratio between the clock frequency and
blink frequency depends on the blink mode selected (see Table 7).
An additional feature allows an arbitrary selection of LCD segments to blink in the static
and 1:2 drive modes. This is implemented without any communication overheads by the
output bank selector which alternates the displayed data between the data in the display
RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can
also be implemented by the blink-select command (see Table 15).
In the 1:3 and 1:4 drive modes, where no alternative RAM bank is available, groups of
LCD segments can blink selectively by changing the display RAM data at fixed time
intervals.
PCA8576D
Product data sheet
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Rev. 2 — 6 June 2013
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
The entire display can blink at a frequency other than the nominal blink frequency by
sequentially resetting and setting the display enable bit E at the required rate using the
mode-set command (see Table 11).
Table 7.
Blinking frequencies[1]
Blink mode
Normal operating mode ratio
Nominal blink frequency
off
-
blinking off
1
f clk
--------768
2 Hz
2
f clk
-----------1536
1 Hz
3
f clk
-----------3072
0.5 Hz
[1]
Blink modes 1, 2 and 3 and the nominal blink frequencies 0.5 Hz, 1 Hz and 2 Hz correspond to an oscillator
frequency (fclk) of 1536 Hz (see Section 11).
7.16 Characteristics of the I2C-bus
The I2C-bus is for bidirectional, two-line communication between different ICs or modules.
The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must
be connected to a positive supply via a pull-up resistor when connected to the output
stages of a device. Data transfer may be initiated only when the bus is not busy.
7.16.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain
stable during the HIGH period of the clock pulse as changes in the data line at this time
will be interpreted as a control signal (see Figure 12).
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mba607
Fig 12. Bit transfer
PCA8576D
Product data sheet
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
7.16.2 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy.
A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START
condition - S.
A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP
condition - P (see Figure 13).
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
mbc622
Fig 13. Definition of START and STOP conditions
7.16.3 System configuration
A device generating a message is a transmitter, a device receiving a message is the
receiver. The device that controls the message is the master and the devices which are
controlled by the master are the slaves (see Figure 14).
MASTER
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
MASTER
TRANSMITTER/
RECEIVER
SDA
SCL
mga807
Fig 14. System configuration
7.16.4 Acknowledge
The number of data bytes transferred between the START and STOP conditions from
transmitter to receiver is unlimited. Each byte of eight bits is followed by an acknowledge
cycle.
• A slave receiver which is addressed must generate an acknowledge after the
reception of each byte.
• Also a master receiver must generate an acknowledge after the reception of each
byte that has been clocked out of the slave transmitter.
• The device that acknowledges must pull-down the SDA line during the acknowledge
clock pulse, so that the SDA line is stable LOW during the HIGH period of the
acknowledge related clock pulse (set-up and hold times must be taken into
consideration).
PCA8576D
Product data sheet
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Rev. 2 — 6 June 2013
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
• A master receiver must signal an end of data to the transmitter by not generating an
acknowledge on the last byte that has been clocked out of the slave. In this event the
transmitter must leave the data line HIGH to enable the master to generate a STOP
condition.
Acknowledgement on the I2C-bus is shown in Figure 15.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 15. Acknowledgement of the I2C-bus
7.16.5 I2C-bus controller
The PCA8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCA8576D are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally
tied to VSS which defines the hardware subaddress 0. In multiple device
applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding
scheme such that no two devices with a common I2C-bus slave address have the same
hardware subaddress.
7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCA8576D.
The PCA8576D slave address is illustrated in Table 8.
Table 8.
I2C slave address byte
Slave address
Bit
7
6
5
4
3
2
1
MSB
0
PCA8576D
Product data sheet
0
LSB
1
1
1
0
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Rev. 2 — 6 June 2013
0
SA0
R/W
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
The least significant bit of the slave address that a PCA8576D will respond to is defined
by the level tied to its SA0 input. The PCA8576D is a write-only device and will not
respond to a read access. Having two reserved slave addresses allows the following on
the same I2C-bus:
• Up to 16 PCA8576D for very large LCD applications
• The use of two types of LCD multiplex drive modes.
The I2C-bus protocol is shown in Figure 16. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of two possible PCA8576D
slave addresses available. All PCA8576D whose SA0 inputs correspond to bit 0 of the
slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is
ignored by all PCA8576D whose SA0 inputs are set to the alternative level.
acknowledge
by A0, A1 and A2
selected
PCA8576D only
acknowledge by
all addressed
PCA8576D
R/W
slave address
S
S
0 1 1 1 0 0 A 0 A C
0
COMMAND
A
n ≥ 1 byte(s)
1 byte
DISPLAY DATA
A
P
n ≥ 0 byte(s)
update data pointers
and if necessary,
subaddress counter
013aaa470
Fig 16. I2C-bus protocol
After an acknowledgement, one or more command bytes follow, that define the status of
each addressed PCA8576D.
The last command byte sent is identified by resetting its most significant bit, continuation
bit C, (see Figure 17). The command bytes are also acknowledged by all addressed
PCA8576D on the bus.
MSB
C
LSB
REST OF OPCODE
msa833
Fig 17. Format of command byte
After the last command byte, one or more display data bytes may follow. Display data
bytes are stored in the display RAM at the address specified by the data pointer and the
subaddress counter. Both data pointer and subaddress counter are automatically updated
and the data directed to the intended PCA8576D device.
An acknowledgement after each byte is asserted only by the PCA8576D that are
addressed via address lines A0, A1 and A2. After the last display byte, the I2C-bus master
asserts a STOP condition (P). Alternately a START may be asserted to restart an I2C-bus
access.
PCA8576D
Product data sheet
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
7.17 Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. The
commands available to the PCA8576D are defined in Table 9.
Table 9.
Definition of PCA8576D commands
Command
Operation Code
Reference
Bit
7
6
5
4
3
2
1
mode-set
C
1
0
[1]
E
B
M[1:0]
load-data-pointer
C
0
P[5:0]
device-select
C
1
1
0
0
A[2:0]
bank-select
C
1
1
1
1
0
I
blink-select
C
1
1
1
0
AB
BF[1:0]
[1]
0
Table 11
Table 12
Table 13
O
Table 14
Table 15
Not used.
All available commands carry a continuation bit C in their most significant bit position as
shown in Figure 17. When this bit is set, it indicates that the next byte of the transfer to
arrive will also represent a command. If this bit is reset, it indicates that the command byte
is the last in the transfer. Further bytes will be regarded as display data (see Table 10).
Table 10.
C bit description
Bit
Symbol
7
C
continue bit
0
last control byte in the transfer; next byte will be regarded
as display data
1
control bytes continue; next byte will be a command too
Mode-set command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6 to 5
-
10
fixed value
4
-
-
unused
3
E
display status[1]
0[2]
disabled (blank)[3]
1
enabled
LCD bias configuration[4]
B
1 to 0
Product data sheet
Description
Table 11.
2
PCA8576D
Value
0[2]
1⁄
3
bias
1
1⁄
2
bias
M[1:0]
LCD drive mode selection
01
static; BP0
10
1:2 multiplex; BP0, BP1
11
1:3 multiplex; BP0, BP1, BP2
00[2]
1:4 multiplex; BP0, BP1, BP2, BP3
[1]
The possibility to disable the display allows implementation of blinking under external control.
[2]
Default value.
[3]
The display is disabled by setting all backplane and segment outputs to VLCD.
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
[4]
Not applicable for static drive mode.
Table 12.
Load-data-pointer command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6
-
0
fixed value
P[5:0]
000000[1]
5 to 0
100111
[1]
to 6 bit binary value, 0 to 39; transferred to the data pointer to
define one of forty display RAM addresses
Default value.
Table 13.
Device-select command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6 to 3
-
1100
fixed value
2 to 0
A[2:0]
000[1] to 111 3 bit binary value, 0 to 7; transferred to the subaddress
counter to define one of eight hardware subaddresses
[1]
Default value.
Table 14.
Bank-select command bit description
Bit
Symbol
Value
Description
Static
7
C
0, 1
see Table 10
6 to 2
-
11110
fixed value
1
I
0
PCA8576D
Product data sheet
1:2 multiplex[1]
input bank selection; storage of arriving display data
0[2]
RAM bit 0
RAM bits 0 and 1
1
RAM bit 2
RAM bits 2 and 3
O
output bank selection; retrieval of LCD display data
0[2]
RAM bit 0
RAM bits 0 and 1
1
RAM bit 2
RAM bits 2 and 3
[1]
The bank-select command has no effect in 1:3 and 1:4 multiplex drive modes.
[2]
Default value.
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
Table 15.
Blink-select command bit description
Bit
Symbol
Value
Description
7
C
0, 1
see Table 10
6 to 3
-
1110
fixed value
2
AB
1 to 0
blink mode selection
0[1]
normal blinking[2]
1
alternate RAM bank blinking[3]
BF[1:0]
blink frequency selection
00[1]
off
01
1
10
2
11
3
[1]
Default value.
[2]
Normal blinking is assumed when the LCD multiplex drive modes 1:3 or 1:4 are selected.
[3]
Alternate RAM bank blinking does not apply in 1:3 and 1:4 multiplex drive modes.
7.18 Display controller
The display controller executes the commands identified by the command decoder. It
contains the device’s status registers and coordinates their effects. The display controller
is also responsible for loading display data into the display RAM in the correct filling order.
PCA8576D
Product data sheet
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Automotive 40 x 4 LCD segment driver for low multiplex rates
8. Internal circuitry
VDD
VDD
VSS
VSS
SA0
VDD
CLK
SCL
VSS
VDD
VSS
OSC
VSS
VDD
SDA
SYNC
VSS
VSS
VDD
A0, A1 A2
VSS
VLCD
BP0, BP1,
BP2, BP3
VSS
VLCD
VLCD
S0 to S39
VSS
VSS
mdb076
Fig 18. Device protection circuits
PCA8576D
Product data sheet
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
9. Limiting values
CAUTION
Static voltages across the liquid crystal display can build up when the LCD supply voltage
(VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted
display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together.
Table 16. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
PCA8576D
Product data sheet
Conditions
Min
Max
Unit
VDD
supply voltage
0.5
+6.5
V
VLCD
LCD supply voltage
0.5
+7.5
V
VI
input voltage
on each of the pins CLK,
SDA, SCL, SYNC, SA0,
OSC, A0 to A2
0.5
+6.5
V
VO
output voltage
on each of the pins S0 to
S39, BP0 to BP3
0.5
+7.5
V
II
input current
10
+10
mA
IO
output current
10
+10
mA
IDD
supply current
50
+50
mA
IDD(LCD)
LCD supply current
50
+50
mA
ISS
ground supply current
50
+50
mA
Ptot
total power dissipation
-
400
mW
Po
output power
-
100
mW
VESD
electrostatic discharge
voltage
HBM
[1]
-
5000
V
MM
[2]
-
200
V
-
100
mA
65
+150
C
40
+85
C
Ilu
latch-up current
[3]
Tstg
storage temperature
[4]
Tamb
ambient temperature
operating device
[1]
Pass level; Human Body Model (HBM) according to Ref. 6 “JESD22-A114”.
[2]
Pass level; Machine Model (MM), according to Ref. 7 “JESD22-A115”.
[3]
Pass level; latch-up testing according to Ref. 8 “JESD78” at maximum ambient temperature (Tamb(max)).
[4]
According to the store and transport requirements (see Ref. 11 “UM10569”) the devices have to be stored
at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %.
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PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
10. Static characteristics
Table 17. Static characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Supplies
VDD
supply voltage
1.8
-
5.5
V
VLCD
LCD supply voltage
[1]
2.5
-
6.5
V
supply current
[2]
-
3.5
7
A
-
2.7
-
A
-
18
25
A
-
13
-
A
1.0
1.3
1.6
V
VSS
-
0.3VDD
V
0.7VDD
-
VDD
V
on pins CLK and SYNC
1
-
-
mA
on pin SDA
3
-
-
mA
IDD
fclk(ext) = 1536 Hz
VDD = 3.0 V;
Tamb = 25 C
IDD(LCD)
LCD supply current
fclk(ext) = 1536 Hz
[2]
VLCD = 3.0 V;
Tamb = 25 C
Logic[3]
VP(POR)
power-on reset supply voltage
VIL
LOW-level input voltage
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
VIH
HIGH-level input voltage
on pins CLK, SYNC,
OSC, A0 to A2, SA0,
SCL, SDA
IOL
LOW-level output current
output sink current;
VOL = 0.4 V; VDD = 5 V
[4][5]
IOH(CLK)
HIGH-level output current on pin CLK
output source current;
VOH = 4.6 V; VDD = 5 V
1
-
-
mA
IL
leakage current
VI = VDD or VSS;
on pins CLK, SCL, SDA,
A0 to A2 and SA0
1
-
+1
A
IL(OSC)
leakage current on pin OSC
VI = VDD
1
-
+1
A
-
-
7
pF
100
-
+100
mV
on pins BP0 to BP3
-
1.5
-
k
on pins S0 to S39
-
6.0
-
k
[6]
input capacitance
CI
LCD outputs
VO
output voltage variation
on pins BP0 to BP3 and
S0 to S39
RO
output resistance
VLCD = 5 V
[7]
[1]
VLCD > 3 V for 1⁄3 bias.
[2]
LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50 % duty factor; I2C-bus inactive.
[3]
The I2C-bus interface of PCA8576D is 5 V tolerant.
[4]
When tested, I2C pins SCL and SDA have no diode to VDD and may be driven to the VI limiting values given in Table 16.
[5]
Propagation delay of driver between clock (CLK) and LCD driving signals.
[6]
Periodically sampled, not 100 % tested.
[7]
Outputs measured one at a time.
PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
11. Dynamic characteristics
Table 18. Dynamic characteristics
VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 6.5 V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Clock
[1]
fclk(int)
internal clock frequency
1440
1850
2640
Hz
fclk(ext)
external clock frequency
960
-
2640
Hz
tclk(H)
HIGH-level clock time
60
-
-
s
tclk(L)
LOW-level clock time
60
-
-
s
-
30
-
ns
1
-
-
s
-
-
30
s
Synchronization
tPD(SYNC_N) SYNC propagation delay
tSYNC_NL
tPD(drv)
SYNC LOW time
driver propagation delay
VLCD = 5 V
[2]
I2C-bus[3]
Pin SCL
fSCL
SCL clock frequency
-
-
400
kHz
tLOW
LOW period of the SCL clock
1.3
-
-
s
tHIGH
HIGH period of the SCL clock
0.6
-
-
s
tSU;DAT
data set-up time
100
-
-
ns
tHD;DAT
data hold time
0
-
-
ns
Pin SDA
Pins SCL and SDA
tBUF
bus free time between a STOP and
START condition
1.3
-
-
s
tSU;STO
set-up time for STOP condition
0.6
-
-
s
tHD;STA
hold time (repeated) START condition
0.6
-
-
s
tSU;STA
set-up time for a repeated START
condition
0.6
-
-
s
tr
rise time of both SDA and SCL signals fSCL = 400 kHz
-
-
0.3
s
tf
fall time of both SDA and SCL signals
Cb
capacitive load for each bus line
fSCL < 125 kHz
tw(spike)
spike pulse width
on the
I2C-bus
-
-
1.0
s
-
-
0.3
s
-
-
400
pF
-
-
50
ns
[1]
Typical output duty factor: 50 % measured at the CLK output pin.
[2]
Not tested in production.
[3]
All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an
input voltage swing of VSS to VDD.
PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
1 / fCLK
tclk(L)
tclk(H)
0.7 VDD
CLK
0.3 VDD
0.7 VDD
SYNC
0.3 VDD
tPD(SYNC_N)
tSYNC_NL
0.5 V
BP0 to BP3,
and S0 to S39
(VDD = 5 V)
0.5 V
tPD(drv)
001aai163
Fig 19. Driver timing waveforms
SDA
tBUF
tLOW
tf
SCL
tHD;STA
tr
tHD;DAT
tHIGH
tSU;DAT
SDA
tSU;STA
tSU;STO
mga728
Fig 20. I2C-bus timing waveforms
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Automotive 40 x 4 LCD segment driver for low multiplex rates
12. Application information
12.1 Cascaded operation
In large display configurations, up to 16 PCA8576D can be differentiated on the same
I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the
programmable I2C-bus slave address (SA0).
Table 19.
Addressing cascaded PCA8576D
Cluster
Bit SA0
Pin A2
Pin A1
Pin A0
Device
1
0
0
0
0
0
0
0
1
1
0
1
0
2
0
1
1
3
1
0
0
4
1
0
1
5
1
1
0
6
2
1
1
1
1
7
0
0
0
8
0
0
1
9
0
1
0
10
0
1
1
11
1
0
0
12
1
0
1
13
1
1
0
14
1
1
1
15
The PCA8576D connected in cascade are synchronized to allow the backplane signals
from only one device in the cascade to be shared. This arrangement is cost-effective in
large LCD applications since the backplane outputs of only one device need to be
through-plated to the backplane electrodes of the display. The other cascaded PCA8576D
contribute additional segment outputs but their backplane outputs are left open-circuit
(see Figure 21).
All PCA8576D connected in cascade are correctly synchronized by the SYNC signal. This
synchronization is guaranteed after the power-on reset. The only time that SYNC is likely
to be needed is if synchronization is lost accidentally, for example, by noise in adverse
electrical environments, or if the LCD multiplex drive mode is changed in an application
using several cascaded PCA8576D, as the drive mode cannot be changed on all of the
cascaded devices simultaneously. SYNC can be either an input or an output signal; a
SYNC output is implemented as an open-drain driver with an internal pull-up resistor.
The PCA8576D asserts SYNC at the start of its last active backplane signal and monitors
the SYNC line at all other times. If cascade synchronization is lost, it is restored by the first
PCA8576D to assert SYNC. The timing relationship between the backplane waveforms
and the SYNC signal for each LCD drive mode is shown in Figure 22.
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Automotive 40 x 4 LCD segment driver for low multiplex rates
The contact resistance between the SYNC on each cascaded device must be controlled.
If the resistance is too high, the device is not able to synchronize properly; this is
particularly applicable to chip-on-glass applications. The maximum SYNC contact
resistance allowed for the number of devices in cascade is given in Table 20.
Table 20.
SYNC contact resistance
Number of devices
Maximum contact resistance
2
6 k
3 to 5
2.2 k
6 to 10
1.2 k
10 to 16
700 
The PCA8576D can be cascaded with the PCA8534A. This allows optimal drive selection
for a given number of pixels to display. Figure 19 and Figure 20 show the timing of the
synchronization signals.
VDD
VLCD
SDA
40 segment drives
SCL
LCD PANEL
SYNC
PCA8576D
CLK
(up to 2560
elements)
OSC
BP0 to BP3
(open-circuit)
A0
A1
A2
SA0 VSS
VLCD
VDD
R≤
HOST
MICROPROCESSOR/
MICROCONTROLLER
tr
2CB
VDD
VLCD
40 segment drives
SDA
SCL
SYNC
PCA8576D
CLK
4 backplanes
BP0 to BP3
OSC
013aaa471
VSS
A0
A1
A2
SA0 VSS
Fig 21. Cascaded PCA8576D configuration
PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
Tfr =
1
ffr
BP0
SYNC
(a) static drive mode.
BP0
(1/2 bias)
BP0
(1/3 bias)
SYNC
(b) 1:2 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(c) 1:3 multiplex drive mode.
BP0
(1/3 bias)
SYNC
(d) 1:4 multiplex drive mode.
mgl755
Fig 22. Synchronization of the cascade for the various PCA8576D drive modes
12.2 RAM writing in 1:3 multiplex drive mode
In 1:3 multiplex drive mode, the RAM is written as shown in Table 21 (see Figure 11 as
well).
Table 21. Standard RAM filling in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are not connected to any elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
3
4
5
6
7
8
9
:
0
a7
a4
a1
b7
b4
b1
c7
c4
c1
d7
:
1
a6
a3
a0
b6
b3
b0
c6
c3
c0
d6
:
2
a5
a2
-
b5
b2
-
c5
c2
-
d5
:
3
-
-
-
-
-
-
-
-
-
-
:
If the bit at position BP2/S2 would be written by a second byte transmitted, then the
mapping of the segment bits would change as illustrated in Table 22.
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Automotive 40 x 4 LCD segment driver for low multiplex rates
Table 22. Continuos RAM filling by rewriting in 1:3 multiplex drive mode
Assumption: BP2/S2, BP2/S5, BP2/S8 etc. are connected to elements on the display.
Display RAM
bits (rows)/
backplane
outputs (BPn)
Display RAM addresses (columns)/segment outputs (Sn)
0
1
2
0
a7
a4
a1/b7 b4
b1/c7 c4
1
a6
a3
a0/b6 b3
2
a5
a2
b5
b2
3
-
-
-
-
3
4
5
6
7
8
9
:
c1/d7 d4
d1/e7 e4
:
b0/c6 c3
c0/d6 d3
d0/e6 e3
:
c5
c2
d5
d2
e5
e2
:
-
-
-
-
-
-
:
In the case described in Table 22 the RAM has to be written entirely and BP2/S2, BP2/S5,
BP2/S8 etc. have to be connected to elements on the display. This can be achieved by a
combination of writing and rewriting the RAM like follows:
• In the first write to the RAM, bits a7 to a0 are written.
• In the second write, bits b7 to b0 are written, overwriting bits a1 and a0 with bits b7
and b6.
• In the third write, bits c7 to c0 are written, overwriting bits b1 and b0 with bits c7 and
c6.
Depending on the method of writing to the RAM (standard or continuous filling by
rewriting), some elements remain unused or can be used, but it has to be considered in
the module layout process as well as in the driver software design.
13. Test information
13.1 Quality information
This product has been qualified in accordance with the Automotive Electronics Council
(AEC) standard Q100 - Failure mechanism based stress test qualification for integrated
circuits, and is suitable for use in automotive applications.
PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
14. Bare die outline
Bare die; 59 bumps
PCA8576DU/2DA
D
35
(1)
22
21
Y
e
36
x
0
E
0
y
51
9
C2
52
59 1
8
C1
X
L
A
b
detail X
A2
A1
detail Y
0
0.5
1 mm
scale
Notes
1. Marking code: PC8576D-2
Outline
version
pca8576du_2da_do
References
IEC
JEDEC
JEITA
European
projection
Issue date
11-03-07
11-03-10
PCA8576DU/2DA
Fig 23. Bare die outline PCA8576DU/2DA/2 (for dimensions see Table 23)
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Automotive 40 x 4 LCD segment driver for low multiplex rates
Table 23. Dimensions of PCA8576DU
Original dimensions are in mm.
A
A1
max
-
-
-
-
-
-
-
-
nom
0.40
0.015
0.381
0.052
2.2
2.0
-
0.077
min
-
-
-
-
-
-
0.072
-
[1]
A2
b
D
E
e[1]
Unit (mm)
L
Dimension not drawn to scale.
Table 24. Bump location for PCA8576DU
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip (see Figure 2 and Figure 23).
PCA8576D
Product data sheet
Symbol
Bump
X (m)
Y (m)
Description
SDA
1
34.38
876.6
I2C-bus serial data input/output
SCL
2
109.53
876.6
I2C-bus serial clock input
SCL
3
181.53
876.6
SYNC
4
365.58
876.6
cascade synchronization input/output
CLK
5
469.08
876.6
external clock input/output
VDD
6
577.08
876.6
supply voltage
OSC
7
740.88
876.6
internal oscillator enable input
A0
8
835.83
876.6
subaddress inputs
A1
9
1005.48
630.9
A2
10
1005.48
513.9
SA0
11
1005.48
396.9
I2C-bus address input; bit 0
VSS
12
1005.48
221.4
ground supply voltage
VLCD
13
1005.48
10.71
LCD supply voltage
BP0
14
1005.48
156.51
LCD backplane outputs
BP2
15
1005.48
232.74
BP1
16
1005.48
308.97
BP3
17
1005.48
385.2
S0
18
1005.48
493.2
S1
19
1005.48
565.2
S2
20
1005.48
637.2
S3
21
1005.48
709.2
S4
22
347.22
876.6
S5
23
263.97
876.6
S6
24
180.72
876.6
S7
25
97.47
876.6
S8
26
14.22
876.6
S9
27
69.03
876.6
S10
28
152.28
876.6
S11
29
235.53
876.6
S12
30
318.78
876.6
LCD segment outputs
LCD segment outputs
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
Table 24. Bump location for PCA8576DU …continued
All x/y coordinates represent the position of the center of each bump with respect to the center
(x/y = 0) of the chip (see Figure 2 and Figure 23).
Symbol
Bump
X (m)
Y (m)
Description
S13
31
402.03
876.6
S14
32
485.28
876.6
S15
33
568.53
876.6
S16
34
651.78
876.6
S17
35
735.03
876.6
S18
36
1005.5
625.59
S19
37
1005.5
541.62
S20
38
1005.5
458.19
S21
39
1005.5
374.76
S22
40
1005.5
291.33
S23
41
1005.5
207.9
S24
42
1005.5
124.47
S25
43
1005.5
41.04
S26
44
1005.5
42.39
S27
45
1005.5
125.8
S28
46
1005.5
209.3
S29
47
1005.5
292.7
S30
48
1005.5
376.1
S31
49
1005.5
459.5
S32
50
1005.5
543
S33
51
1005.5
625.6
S34
52
735.03
876.6
S35
53
663.03
876.6
S36
54
591.03
876.6
S37
55
519.03
876.6
S38
56
447.03
876.6
S39
57
375.03
876.6
LCD segment outputs
SDA
58
196.38
876.6
I2C-bus serial data input/output
SDA
59
106.38
876.6
Table 25. Alignment marks
All x/y coordinates represent the position of the center of each alignment mark with respect to the
center (x/y = 0) of the chip (see Figure 2 and Figure 23).
PCA8576D
Product data sheet
Symbol
X (m)
Y (m)
C1
930.42
870.3
C2
829.98
870.3
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Automotive 40 x 4 LCD segment driver for low multiplex rates
15. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under
normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that
all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent
standards.
16. Packing information
16.1 Tray information
&
-
$
+
[
%
$
$
.
)
(
'
\
\
[
*
)
(
&
1
/
0
6(&7,21$$
;
'LPHQVLRQVLQPP
GHWDLO;
DDD
Fig 24. Tray details
PCA8576D
Product data sheet
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Automotive 40 x 4 LCD segment driver for low multiplex rates
Table 26. Description of tray details
Tray details are shown in Figure 24.
Tray details
Dimensions
A
B
C
D
E
F
G
H
J
K
L
M
N
Unit
3.6
3.6
2.36
2.11
50.8
45.72
39.6
5.6
5.6
39.6
3.96
2.18
2.49
mm
Number of pockets
x direction
y direction
12
12
PDUNLQJFRGH
DDD
Fig 25. Tray alignment
17. Abbreviations
Table 27.
PCA8576D
Product data sheet
Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
HBM
Human Body Model
ITO
Indium Tin Oxide
LCD
Liquid Crystal Display
LSB
Least Significant Bit
MM
Machine Model
MSB
Most Significant Bit
PCB
Printed Circuit Board
RAM
Random Access Memory
RMS
Root Mean Square
SCL
Serial CLock line
SDA
Serial DAta line
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Automotive 40 x 4 LCD segment driver for low multiplex rates
18. References
[1]
AN10170 — Design guidelines for COG modules with NXP monochrome LCD
drivers
[2]
AN10706 — Handling bare die
[3]
IEC 60134 — Rating systems for electronic tubes and valves and analogous
semiconductor devices
[4]
IEC 61340-5 — Protection of electronic devices from electrostatic phenomena
[5]
IPC/JEDEC J-STD-020D — Moisture/Reflow Sensitivity Classification for
Nonhermetic Solid State Surface Mount Devices
[6]
JESD22-A114 — Electrostatic Discharge (ESD) Sensitivity Testing Human Body
Model (HBM)
[7]
JESD22-A115 — Electrostatic Discharge (ESD) Sensitivity Testing Machine Model
(MM)
[8]
JESD78 — IC Latch-Up Test
[9]
JESD625-A — Requirements for Handling Electrostatic-Discharge-Sensitive
(ESDS) Devices
[10] UM10204 — I2C-bus specification and user manual
[11] UM10569 — Store and transport requirements
19. Revision history
Table 28.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
PCA8576D v.2
20130606
Product data sheet
-
PCA8576D v.1
Modifications:
PCA8576D v.1
PCA8576D
Product data sheet
•
•
•
Added improved IDD and IDD(LCD) values (Table 17)
Improved description of bit E
Changed tray information (Section 16.1)
20110404
Product data sheet
-
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-
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PCA8576D
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Automotive 40 x 4 LCD segment driver for low multiplex rates
20. Legal information
20.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
20.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
PCA8576D
Product data sheet
Suitability for use in automotive applications — This NXP
Semiconductors product has been qualified for use in automotive
applications. Unless otherwise agreed in writing, the product is not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer's own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 June 2013
© NXP B.V. 2013. All rights reserved.
41 of 45
PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Bare die — All die are tested on compliance with their related technical
specifications as stated in this data sheet up to the point of wafer sawing and
are handled in accordance with the NXP Semiconductors storage and
transportation conditions. If there are data sheet limits not guaranteed, these
will be separately indicated in the data sheet. There are no post-packing tests
performed on individual die or wafers.
NXP Semiconductors has no control of third party procedures in the sawing,
handling, packing or assembly of the die. Accordingly, NXP Semiconductors
assumes no liability for device functionality or performance of the die or
systems after third party sawing, handling, packing or assembly of the die. It
is the responsibility of the customer to test and qualify their application in
which the die is used.
All die sales are conditioned upon and subject to the customer entering into a
written die sale agreement with NXP Semiconductors through its legal
department.
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
PCA8576D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 June 2013
© NXP B.V. 2013. All rights reserved.
42 of 45
PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2
Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .4
Selection of possible display configurations . . . .5
Discrimination ratios . . . . . . . . . . . . . . . . . . . . . .6
Blinking frequencies[1] . . . . . . . . . . . . . . . . . . .19
I2C slave address byte . . . . . . . . . . . . . . . . . . .21
Definition of PCA8576D commands . . . . . . . .23
C bit description . . . . . . . . . . . . . . . . . . . . . . . .23
Mode-set command bit description . . . . . . . . .23
Load-data-pointer command bit description . . .24
Device-select command bit description . . . . . .24
Bank-select command bit description . . . . . . .24
Blink-select command bit description . . . . . . .25
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .27
Static characteristics . . . . . . . . . . . . . . . . . . . .28
Dynamic characteristics . . . . . . . . . . . . . . . . . .29
Addressing cascaded PCA8576D . . . . . . . . . .31
SYNC contact resistance . . . . . . . . . . . . . . . . .32
Standard RAM filling in 1:3 multiplex
drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
Continuos RAM filling by rewriting in 1:3
multiplex drive mode. . . . . . . . . . . . . . . . . . . . .34
Dimensions of PCA8576DU . . . . . . . . . . . . . . .36
Bump location for PCA8576DU . . . . . . . . . . . .36
Alignment marks . . . . . . . . . . . . . . . . . . . . . . . .37
Description of tray details . . . . . . . . . . . . . . . . .39
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .39
Revision history . . . . . . . . . . . . . . . . . . . . . . . .40
PCA8576D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 June 2013
© NXP B.V. 2013. All rights reserved.
43 of 45
PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
23. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Block diagram of PCA8576D . . . . . . . . . . . . . . . . .2
Pinning diagram for PCA8576DU (bare die) . . . . .3
Typical system configuration . . . . . . . . . . . . . . . . .5
Electro-optical characteristic: relative
transmission curve of the liquid . . . . . . . . . . . . . . .8
Static drive mode waveforms . . . . . . . . . . . . . . . . .9
Waveforms for the 1:2 multiplex drive mode
with 1⁄2 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Waveforms for the 1:2 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Waveforms for the 1:3 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Waveforms for the 1:4 multiplex drive mode
with 1⁄3 bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
Display RAM bit map . . . . . . . . . . . . . . . . . . . . . .15
Relationship between LCD layout, drive mode,
display RAM filling order and display data
transmitted over the I2C-bus . . . . . . . . . . . . . . . .16
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Definition of START and STOP conditions. . . . . .20
System configuration . . . . . . . . . . . . . . . . . . . . . .20
Acknowledgement of the I2C-bus . . . . . . . . . . . .21
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . .22
Format of command byte . . . . . . . . . . . . . . . . . . .22
Device protection circuits . . . . . . . . . . . . . . . . . . .26
Driver timing waveforms . . . . . . . . . . . . . . . . . . .30
I2C-bus timing waveforms . . . . . . . . . . . . . . . . . .30
Cascaded PCA8576D configuration . . . . . . . . . .32
Synchronization of the cascade for the various
PCA8576D drive modes . . . . . . . . . . . . . . . . . . .33
Bare die outline PCA8576DU/2DA/2 (for
dimensions see Table 23) . . . . . . . . . . . . . . . . . .35
Tray details . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Tray alignment . . . . . . . . . . . . . . . . . . . . . . . . . . .39
PCA8576D
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 6 June 2013
© NXP B.V. 2013. All rights reserved.
44 of 45
PCA8576D
NXP Semiconductors
Automotive 40 x 4 LCD segment driver for low multiplex rates
24. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
3.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2
4
Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 2
6
Pinning information . . . . . . . . . . . . . . . . . . . . . . 3
6.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7
Functional description . . . . . . . . . . . . . . . . . . . 5
7.1
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 6
7.2
LCD bias generator . . . . . . . . . . . . . . . . . . . . . 6
7.3
LCD voltage selector . . . . . . . . . . . . . . . . . . . . 6
7.3.1
Electro-optical performance . . . . . . . . . . . . . . . 7
7.4
LCD drive mode waveforms . . . . . . . . . . . . . . . 9
7.4.1
Static drive mode . . . . . . . . . . . . . . . . . . . . . . . 9
7.4.2
1:2 Multiplex drive mode. . . . . . . . . . . . . . . . . 10
7.4.3
1:3 Multiplex drive mode. . . . . . . . . . . . . . . . . 12
7.4.4
1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 13
7.5
Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.5.1
Internal clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.5.2
External clock . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.6
Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.7
Display register . . . . . . . . . . . . . . . . . . . . . . . . 14
7.8
Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 14
7.9
Backplane outputs . . . . . . . . . . . . . . . . . . . . . 14
7.10
Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.11
Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7.12
Subaddress counter . . . . . . . . . . . . . . . . . . . . 17
7.13
Output bank selector . . . . . . . . . . . . . . . . . . . 18
7.14
Input bank selector . . . . . . . . . . . . . . . . . . . . . 18
7.15
Blinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.16
Characteristics of the I2C-bus. . . . . . . . . . . . . 19
7.16.1
Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.16.2
START and STOP conditions . . . . . . . . . . . . . 20
7.16.3
System configuration . . . . . . . . . . . . . . . . . . . 20
7.16.4
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 20
7.16.5
I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 21
7.16.6
Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.16.7
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 21
7.17
Command decoder . . . . . . . . . . . . . . . . . . . . . 23
7.18
Display controller . . . . . . . . . . . . . . . . . . . . . . 25
8
Internal circuitry. . . . . . . . . . . . . . . . . . . . . . . . 26
9
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 27
10
Static characteristics. . . . . . . . . . . . . . . . . . . . 28
11
Dynamic characteristics . . . . . . . . . . . . . . . . . 29
12
12.1
12.2
13
13.1
14
15
16
16.1
17
18
19
20
20.1
20.2
20.3
20.4
21
22
23
24
Application information . . . . . . . . . . . . . . . . .
Cascaded operation. . . . . . . . . . . . . . . . . . . .
RAM writing in 1:3 multiplex drive mode . . . .
Test information . . . . . . . . . . . . . . . . . . . . . . .
Quality information . . . . . . . . . . . . . . . . . . . . .
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . .
Handling information . . . . . . . . . . . . . . . . . . .
Packing information . . . . . . . . . . . . . . . . . . . .
Tray information . . . . . . . . . . . . . . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .
References. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . .
Legal information . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
31
31
33
34
34
35
38
38
38
39
40
40
41
41
41
41
42
42
43
44
45
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2013.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 6 June 2013
Document identifier: PCA8576D