INTEGRATED CIRCUITS DATA SHEET PCF8576D Universal LCD driver for low multiplex rates Product specification Supersedes data of 2003 Apr 01 2003 Jun 23 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D CONTENTS 1 FEATURES 2 GENERAL DESCRIPTION 3 ORDERING INFORMATION 4 BLOCK DIAGRAM 5 PINNING 6 FUNCTIONAL DESCRIPTION 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 Power-on reset LCD bias generator LCD voltage selector LCD drive mode waveforms Oscillator Timing Display register Segment outputs Backplane outputs Display RAM Data pointer Subaddress counter Output bank selector Input bank selector Blinker 7 CHARACTERISTICS OF THE I2C-BUS 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 Bit transfer Start and stop conditions System configuration Acknowledge PCF8576D I2C-bus controller Input filters I2C-bus protocol Command decoder Display controller Cascaded operation 2003 Jun 23 8 LIMITING VALUES 9 HANDLING 10 DC CHARACTERISTICS 11 AC CHARACTERISTICS 12 BONDING PAD INFORMATION 13 DEVICE PROTECTION 14 TRAY INFORMATION 15 PACKAGE OUTLINE 16 SOLDERING 16.1 Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods 16.2 16.3 16.4 16.5 2 17 DATA SHEET STATUS 18 DEFINITIONS 19 DISCLAIMERS 20 PURCHASE OF PHILIPS I2C COMPONENTS Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 1 PCF8576D FEATURES • Single-chip LCD controller/driver • Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing • Selectable display bias configuration: static, 1/2 and 1/3 • Internal LCD bias generation with voltage-follower buffers • Compatible with 4, 8 or 16-bit microprocessors or microcontrollers • 40 segment drives: up to twenty 8-segment numeric characters; up to ten 15-segment alphanumeric characters; or any graphics of up to 160 elements • May be cascaded for large LCD applications (up to 2560 elements possible) • 40 × 4-bit RAM for display data storage • Compatible with chip-on-glass technology • Auto-incremented display data loading across device subaddress boundaries • Manufactured in silicon gate CMOS process. • Display memory bank switching in static and duplex drive modes 2 • No external components GENERAL DESCRIPTION The PCF8576D is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates. It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 40 segments and can easily be cascaded for larger LCD applications. The PCF8576D is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional I2C-bus. Communication overheads are minimized by a display RAM with auto-incremented addressing, by hardware subaddressing and by display memory switching (static and duplex drive modes). • Versatile blinking modes • Independent supplies possible for LCD and logic voltages • Wide power supply range: from 1.8 to 5.5 V • Wide logic LCD supply range: from 2.5 V for low-threshold LCDs and up to 6.5 V for guest-host LCDs and high-threshold (automobile) twisted nematic LCDs • Low power consumption • 400 kHz I2C-bus interface • TTL/CMOS compatible 3 ORDERING INFORMATION PACKAGE TYPE NUMBER NAME PCF8576DH TQFP64 DESCRIPTION plastic thin quad flat package, 64 leads; body; 10 × 10 × 1.0 mm VERSION SOT357-1 PCF8576DU − chips in tray − PCF8576DU/2 − chip with bumps in tray − 2003 Jun 23 3 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... 29 to 32, 34 to 47, 49 to 64, 2 to 7 28 BACKPLANE OUTPUTS DISPLAY SEGMENT OUTPUTS DISPLAY REGISTER LCD VOLTAGE SELECTOR 4 VSS CLK SYNC OSC VDD SCL SDA 20 OUTPUT BANK SELECT AND BLINK CONTROL DISPLAY CONTROLLER LCD BIAS GENERATOR PCF8576DH 13 CLOCK SELECT 12 AND TIMING BLINKER TIMEBASE 15 POWER-ON RESET OSCILLATOR Universal LCD driver for low multiplex rates 27 BLOCK DIAGRAM 21 26 Philips Semiconductors 4 2003 Jun 23 25 VLCD S0 to S39 BP0 BP2 BP1 BP3 handbook, full pagewidth DISPLAY RAM 40 × 4 BIT COMMAND DECODER WRITE DATA CONTROL DATA POINTER AND AUTO INCREMENT 14 11 10 INPUT FILTERS I2C-BUS CONTROLLER 19 SUB-ADDRESS COUNTER 1, 8, 9, 22 to 24, 33, 48 16 17 18 MDB075 n.c. A1 A2 PCF8576D Fig.1 Block diagram. A0 Product specification SA0 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 5 PCF8576D PINNING PIN PAD PCF8576DH PCF8576DU SDA 10 1, 58 and 59 SCL 11 2 and 3 I2C-bus serial clock input CLK 13 5 external clock input/output VDD 14 6 supply voltage SYNC 12 4 cascade synchronization input/output OSC 15 7 internal oscillator enable input 16 to 18 8 to 10 SA0 19 11 I2C-bus slave address input; bit 0 VSS 20 12 logic ground VLCD 21 13 LCD supply voltage 25 to 28 14 to 17 LCD backplane outputs 29 to 32, 34 to 47, 49 to 64, 2 to 7 18 to 57 LCD segment outputs 1, 8, 9, 22 to 24, 33 and 48 − SYMBOL A0 to A2 BP0, BP2, BP1, BP3 S0 to S39 n.c. 2003 Jun 23 DESCRIPTION 5 I2C-bus serial data input/output subaddress inputs not connected Philips Semiconductors Product specification 49 S18 50 S19 51 S20 52 S21 53 S22 54 S23 55 S24 56 S25 57 S26 58 S27 59 S28 60 S29 61 S30 PCF8576D 62 S31 64 S33 handbook, full pagewidth 63 S32 Universal LCD driver for low multiplex rates n.c. 1 48 n.c. S34 2 47 S17 S35 3 46 S16 S36 4 45 S15 S37 5 44 S14 S38 6 43 S13 S39 7 42 S12 n.c. 8 41 S11 PCF8576DH n.c. 9 40 S10 SDA 10 39 S9 SCL 11 38 S8 SYNC 12 37 S7 CLK 13 36 S6 VDD 14 35 S5 OSC 15 34 S4 Fig.2 Pin configuration (TQFP64). 2003 Jun 23 6 S3 32 S2 31 S1 30 S0 29 BP3 28 BP1 27 BP2 26 BP0 25 n.c. 24 n.c. 23 n.c. 22 VLCD 21 VSS 20 SA0 19 A2 18 33 n.c. A1 17 A0 16 MDB073 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6 PCF8576D FUNCTIONAL DESCRIPTION The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8576D. The internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are to the power supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application. The PCF8576D is a versatile peripheral device designed to interface any microprocessor/microcontroller with a wide variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to 40 segments. The display configurations possible with the PCF8576D depend on the number of active backplane outputs required. A selection of display configurations is shown in Table 1; all of these configurations can be implemented in the typical system shown in Fig.3. Table 1 Selection of display configurations NUMBER OF 14-SEGMENTS ALPHANUMERIC 7-SEGMENTS NUMERIC DOT MATRIX BACKPLANES SEGMENTS DIGITS INDICATOR SYMBOLS 4 160 20 20 10 20 160 dots (4 × 40) 3 120 15 15 8 8 120 dots (3 × 40) 2 80 10 10 5 10 80 dots (2 × 40) 1 40 5 5 2 12 40 dots (1 × 40) handbook, full pagewidth VDD R≤ tr 2CB HOST MICROPROCESSOR/ MICROCONTROLLER VDD VLCD 6 SDA 1, 58, 59 SCL OSC 2, 3 CHARACTERS INDICATOR SYMBOLS 13 40 segment drives PCF8576D 4 backplanes 7 8 A0 9 10 A1 A2 11 LCD PANEL (up to 160 elements) 12 SA0 VSS VSS The resistance of the power supply lines must be kept to a minimum. For chip-on-glass applications, due to Indium Tin Oxide (ITO) track resistance, each supply line must be routed separately between the chip and the connector. Fig.3 Typical system configuration. 2003 Jun 23 7 MDB079 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.1 PCF8576D Power-on reset 1 Bias is calculated by the formula ------------1+a At power-on the PCF8576D resets to the following starting conditions: For 1⁄2bias, a = 1; for 1⁄3bias, a = 2. • All backplane outputs are set to VLCD The LCD on voltage Von is calculated by the formula • All segment outputs are set to VLCD • Drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected V op • Blinking is switched off • Input and output bank selectors are reset (as defined in Table 4) 2 1 1 ---- + ( N – 1 ) ⋅ ------------- 1+a N -----------------------------------------------------------N The LCD off voltage Voff is calculated by the formula • The I2C-bus interface is initialized 2 a – ( 2a + N ) --------------------------------2 N ⋅ (1 + a) • The data pointer and the subaddress counter are cleared V op • Display is disabled. where Vop is the resultant voltage at the LCD segment; N is the LCD drive mode: 1 = static, 2 = 1 : 2, 3 = 1 : 3, 4 = 1 : 4. Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action. 6.2 Discrimination is the ratio of Von to Voff, and is determined LCD bias generator V on = by the formula --------V off Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three resistors connected in series between VLCD and VSS. The middle resistor can be bypassed to provide a 1⁄2bias voltage level for the 1 : 2 multiplex configuration. The LCD voltage can be temperature compensated externally via the supply to pin VLCD. 6.3 Using the above formula, the discrimination for an LCD drive mode of 1 : 3 with 1⁄2bias is 3 = 1.732, and the discrimination for an LCD drive mode of 1 : 4 with 1⁄2bias is 21 ---------- = 1.528. 3 LCD voltage selector The advantage of these LCD drive modes is a reduction of the LCD full-scale voltage VLCD as follows: The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting Discrimination ratios (D), are given in Table 2. 1 : 3 multiplex (1⁄2bias): VLCD = 6 × V off(rms) = 2.449 Voff(rms) 1 : 4 multiplex (1⁄2bias): VLCD = A practical value for VLCD is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VLCD > 3Vth. (4 × 3) ---------------------3 = 2.309 Voff(rms) These compare with VLCD = 3 Voff(rms) when 1⁄3bias is used. Multiplex drive modes of 1 : 3 and 1 : 4 with 1⁄2bias are possible but the discrimination and hence the contrast ratios are smaller. 2003 Jun 23 2 (a + 1) + (N – 1) -------------------------------------------2 (a – 1) + (N – 1) 8 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 2 PCF8576D Preferred LCD drive modes: summary of characteristics NUMBER OF V off(rms) --------------------V lcd V on(rms) --------------------V lcd V on(rms) D = --------------------V off(rms) BACKPLANES LEVELS LCD BIAS CONFIGURATION static 1 2 static 0 1 ∞ 1 : 2 multiplex 2 3 1⁄ 2 0.354 0.791 2.236 1 : 2 multiplex 2 4 1⁄ 3 0.333 0.745 2.236 4 1⁄ 3 0.333 0.638 1.915 4 1⁄ 3 0.333 0.577 1.732 LCD DRIVE MODE 1 : 3 multiplex 3 1 : 4 multiplex 6.4 4 LCD drive mode waveforms 6.4.1 STATIC DRIVE MODE The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment drive (Sn) waveforms for this mode are shown in Fig.4. Tframe handbook, full pagewidth LCD segments VLCD BP0 VSS state 1 (on) VLCD state 2 (off) Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD state 1 0V −VLCD VLCD state 2 V state1(t) = V S (t) – V BP0(t) n 0V −VLCD (b) Resultant waveforms at LCD segment. MGL745 V on(rms) = V LCD V state2(t) = V S n+1 (t) – V BP0(t) V off(rms) = 0 V Fig.4 Static drive mode waveforms. 2003 Jun 23 9 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4.2 PCF8576D 1 : 2 MULTIPLEX DRIVE MODE The 1 : 2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD bias voltages of 1⁄2bias or 1⁄3bias as shown in Figs 5 and 6. Tframe handbook, full pagewidth VLCD BP0 LCD segments VLCD/2 VSS state 1 VLCD BP1 state 2 VLCD/2 VSS VLCD Sn VSS VLCD Sn + 1 VSS (a) Waveforms at driver. VLCD VLCD/2 state 1 0V −VLCD/2 −VLCD VLCD VLCD/2 state 2 0V −VLCD/2 −VLCD (b) Resultant waveforms at LCD segment. MGL746 V state1(t) = V S (t) – V BP0(t) n V on(rms) = 0.791V LCD V state2(t) = V S (t) – V BP1(t) n V off(rms) = 0.354V LCD Fig.5 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2bias. 2003 Jun 23 10 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D Tframe handbook, full pagewidth BP0 BP1 Sn Sn + 1 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD 2VLCD/3 VLCD/3 state 1 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 state 2 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. MGL747 V state1(t) = V S (t) – V BP0(t) n V on(rms) = 0.745V LCD V state2(t) = V S (t) – V BP1(t) n V off(rms) = 0.333V LCD Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3bias. 2003 Jun 23 11 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4.3 PCF8576D 1 : 3 MULTIPLEX DRIVE MODE When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies (see Fig.7). Tframe handbook, full pagewidth BP0 BP1 BP2 Sn Sn + 1 Sn + 2 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD state 1 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD VLCD 2VLCD/3 VLCD/3 state 2 0V −VLCD/3 −2VLCD/3 −VLCD (b) Resultant waveforms at LCD segment. MGL748 V state1(t) = V S (t) – V BP0(t) n V on(rms) = 0.638V LCD V state2(t) = V S (t) – V BP1(t) n V off(rms) = 0.333V LCD Fig.7 Waveforms for the 1 : 3 multiplex drive mode. 2003 Jun 23 12 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.4.4 PCF8576D 1 : 4 MULTIPLEX DRIVE MODE When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies (see Fig.8). Tframe handbook, full pagewidth BP0 BP1 BP2 BP3 Sn Sn + 1 Sn + 2 Sn + 3 VLCD 2VLCD/3 LCD segments VLCD/3 VSS state 1 VLCD 2VLCD/3 state 2 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS VLCD 2VLCD/3 VLCD/3 VSS (a) Waveforms at driver. VLCD state 1 2VLCD/3 VLCD/3 0V −VLCD/3 −2VLCD/3 −VLCD V state1(t) = V S (t) – V BP0(t) n VLCD V on(rms) = 0.577V LCD 2VLCD/3 VLCD/3 state 2 V state2(t) = V S (t) – V BP1(t) n 0V −VLCD/3 −2VLCD/3 −VLCD V off(rms) = 0.333V LCD (b) Resultant waveforms at LCD segment. Fig.8 Waveforms for the 1 : 4 multiplex drive mode. 2003 Jun 23 13 MGL749 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.5 6.5.1 PCF8576D Oscillator 6.9 INTERNAL CLOCK The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane outputs are required, the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode, BP3 carries the same signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2 multiplex drive mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they can be connected in parallel for very high drive requirements. The internal logic of the PCF8576D and its LCD drive signals are timed either by its internal oscillator or by an external clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. If the internal oscillator is used, the output from pin CLK can be used as the clock signal for several PCF8576Ds in the system that are connected in cascade. After power-up, pin SDA must be HIGH to guarantee that the clock starts. 6.5.2 EXTERNAL CLOCK Pin CLK is enabled as an external clock input by connecting pin OSC to VDD. The LCD frame signal frequency is determined by the clock frequency (fCLK). 6.10 Timing The PCF8576D timing controls the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. In cascaded applications, the correct timing relationship between each PCF8576D in the system is maintained by the synchronization signal at pin SYNC. The timing also generates the LCD frame signal whose frequency is derived from the clock frequency. The frame signal frequency is a fixed division integer of the clock frequency (nominally 64 kHz) from either the internal or an external clock. f CLK Frame frequency = ---------24 6.7 When display data is transmitted to the PCF8576D, the display bytes received are stored in the display RAM in accordance with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets. For example, in the 1 : 2 mode, the RAM data is stored every second bit. To illustrate the filling order, an example of a 7-segment numeric display showing all drive modes is given in Fig.10; the RAM filling organization depicted applies equally to other LCD types. Display register The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM. 6.8 With reference to Fig.10, in the static drive mode, the eight transmitted data bits are placed in bit 0 of eight successive display RAM addresses. In the 1 : 2 mode, the eight transmitted data bits are placed in bits 0 and 1 of four successive display RAM addresses. In the 1 : 3 mode, these bits are placed in bits 0, 1 and 2 of three successive addresses, with bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted. Segment outputs The LCD drive section includes 40 segment outputs S0 to S39 which should be connected directly to the LCD. The segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the display latch. When less than 40 segment outputs are required, the unused segment outputs should be left open-circuit. 2003 Jun 23 Display RAM The display RAM is a static 40 × 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane outputs. The first RAM column corresponds to the 40 segments operated with respect to backplane BP0 (see Fig.9). In multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are time-multiplexed with BP1, BP2 and BP3 respectively. A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state. 6.6 Backplane outputs 14 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D In the 1 : 4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM addresses. 6.11 arriving data byte is stored at the display RAM address indicated by the data pointer in accordance with the filling order shown in Fig.10. After each byte is stored, the contents of the data pointer are automatically incremented by a value dependent on the selected LCD drive mode: eight (static drive mode), four (1 : 2 mode), three (1 : 3 mode) or two (1 : 4 mode). If an I2C-bus data access is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further RAM accesses. Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an display RAM addresses (rows) / segment outputs (S) 0 1 2 3 4 35 36 37 38 39 0 display RAM bits 1 (columns) / backplane outputs 2 (BP) 3 MBE525 Fig.9 6.12 Display RAM bit-map showing direct relationship between display RAM addresses and segment outputs, and between bits in a RAM word and backplane outputs. Subaddress counter 6.13 The storage of display data is determined by the contents of the subaddress counter. Storage is allowed to take place only when the contents of the subaddress counter agree with the hardware subaddress applied to A0, A1 and A2. The subaddress counter value is defined by the DEVICE SELECT command. If the contents of the subaddress counter and the hardware subaddress do not agree then data storage is inhibited but the data pointer is incremented as if data storage had taken place. The subaddress counter is also incremented when the data pointer overflows. The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual bit chosen depends on the selected LCD drive mode and on the instant in the multiplex sequence. In 1 : 4 mode, all RAM addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 mode, bits 0, 1 and 2 are selected sequentially. In 1 : 2 mode, bits 0 and 1 are selected and, in static mode, bit 0 is selected. Signal SYNC will reset these sequences to the following starting points; bit 3 for 1 : 4 mode, bit 2 for 1 : 3 mode, bit 1 for 1 : 2 mode and bit 0 for static mode. The storage arrangements described lead to extremely efficient data loading in cascaded applications. When a series of display bytes are sent to the display RAM, automatic wrap-over to the next PCF8576D occurs when the last RAM address is exceeded. Subaddressing across device boundaries is successful even if the change to the next device in the cascade occurs within a transmitted character (such as during the 14th display data byte transmitted in 1 : 3 mode). The PCF8576D includes a RAM bank switching feature in the static and 1 : 2 drive modes. In the static drive mode, the BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In 1 : 2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to be prepared in an alternative bank and then selected for display when it is assembled. The hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface. 2003 Jun 23 Output bank selector 15 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 6.14 PCF8576D Input bank selector An additional feature allows an arbitrary selection of LCD segments to be blinked in the static and 1 : 2 drive modes. This is implemented without any communication overheads by the output bank selector which alternates the displayed data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This mode can also be implemented by the BLINK command. The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration. The BANK SELECT command can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in 1 : 2 mode. The input bank selector functions are independent of the output bank selector. 6.15 Blinker In the 1 : 3 and 1 : 4 drive modes, where no alternative RAM bank is available, groups of LCD segments can be blinked by selectively changing the display RAM data at fixed time intervals. The PCF8576D has a very versatile display blinking capability. The whole display can blink at a frequency selected by the BLINK command. Each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock frequency and blink frequency depends on the blink mode selected, as shown in Table 3. Table 3 The entire display can be blinked at a frequency other than the nominal blink frequency by sequentially resetting and setting the display enable bit E at the required rate using the MODE SET command. Blinking frequencies BLINK MODE NORMAL OPERATING MODE RATIO NOMINAL BLINK FREQUENCY Off − blinking off 2 Hz f CLK ----------768 2 Hz 1 Hz f CLK ------------1536 1 Hz 0.5 Hz f CLK ------------3072 0.5 Hz Note 1. Blink modes 0.5, 1 and 2 Hz, and nominal blink frequencies 0.5, 1 and 2 Hz correspond to an oscillator frequency (fCLK) of 1536 Hz at pin CLK. The oscillator frequency range is given in Chapter 11. 2003 Jun 23 16 This text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here in _white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader.This text is here inThis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the Acrobat reader. white to force landscape pages to be ... static a 2 Sn 3 Sn 4 Sn 5 Sn 6 b f g e 1 17 Sn 2 Sn 3 1:3 Sn 1 Sn 2 Sn 7 DP BP1 e c d DP b f BP1 c 0 1 2 3 BP2 DP a b BP0 n 5 n 6 n 7 c x x x b x x x a x x x f x x x g x x x e x x x d x x x DP x x x n n 1 n 2 n 3 a b x x f g x x e c x x d DP x x n n 1 n 2 b DP c x a d g x f e x x n n 1 a c b DP f e g d LSB c b a f g e d DP e 0 1 2 3 bit/ BP BP1 c d MSB a b f LSB g e c d DP MSB LSB b DP c a d g f e BP2 g BP3 MSB a c b DP f LSB e g d Fig.10 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus. MGL751 Product specification DP PCF8576D x = data bit unchanged. n 4 Sn bit/ BP f 1 n 3 BP0 a Sn Sn 0 1 2 3 bit/ BP d multiplex n 2 b f e 1:4 n 1 BP0 a g multiplex n MSB 0 1 2 3 bit/ BP g multiplex transmitted display byte 1 Sn c Sn Sn BP0 Sn d 1:2 display RAM filling order handbook, full pagewidth Sn LCD backplanes Philips Semiconductors LCD segments Universal LCD driver for low multiplex rates 2003 Jun 23 drive mode Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 7 PCF8576D acknowledge clock pulse so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the master to generate a STOP condition (see Fig.14). CHARACTERISTICS OF THE I2C-BUS The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. In chip-on-glass applications where the track resistance from the SDA pad to the system SDA line can be significant, a potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is therefore necessary to minimize the track resistance from the SDA pad to the system SDA line to guarantee a valid LOW-level during the acknowledge cycle. 7.1 7.5 The PCF8576D acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. The only data output from the PCF8576D are the acknowledge signals of the selected devices. Device selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress. Bit transfer In single device applications, the hardware subaddress inputs A0, A1 and A2 are normally tied to VSS which defines the hardware subaddress 0. In multiple device applications A0, A1 and A2 are tied to VSS or VDD in accordance with a binary coding scheme such that no two devices with a common I2C-bus slave address have the same hardware subaddress. One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.11). 7.2 Start and stop conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P), (see Fig.12). 7.3 7.6 System configuration 7.7 I2C-bus protocol Two I2C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8576D. The least significant bit of the slave address that a PCF8576D will respond to is defined by the level tied to its SA0 input. The PCF8576D is a write-only device and will not respond to a read access. Having two reserved slave addresses allows the following on the same I2C-bus: Acknowledge The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse. An addressed slave receiver must generate an acknowledge after receiving each byte. Also a master receiver must generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The acknowledging device must pull-down the SDA line during the 2003 Jun 23 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’, (see Fig.13). 7.4 PCF8576D I2C-bus controller • Up to 16 PCF8576Ds for very large LCD applications • The use of two types of LCD multiplex drive. The I2C-bus protocol is shown in Fig.15. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of two possible PCF8576D slave addresses available. All PCF8576Ds whose SA0 inputs correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored by all PCF8576Ds whose SA0 inputs are set to the alternative level. 18 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D A1 and A2. After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to RESTART an I2C-bus access. After an acknowledgement, one or more command bytes follow that define the status of each addressed PCF8576D. The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Fig.16). The command bytes are also acknowledged by all addressed PCF8576Ds on the bus. 7.8 Command decoder The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation bit C in their most significant bit position as shown in Fig.16. When this bit is set, it indicates that the next byte of the transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the transfer. Further bytes will be regarded as display data. After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter are automatically updated and the data directed to the intended PCF8576D device. The five commands available to the PCF8576D are defined in Table 4. An acknowledgement after each byte is asserted only by the PCF8576Ds that are addressed via address lines A0, SDA SCL data line stable; data valid change of data allowed MBA607 Fig.11 Bit transfer. handbook, full pagewidth SDA SDA SCL SCL S P START condition STOP condition Fig.12 Definition of START and STOP conditions. 2003 Jun 23 19 MBC622 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates MASTER TRANSMITTER/ RECEIVER PCF8576D SLAVE TRANSMITTER/ RECEIVER SLAVE RECEIVER MASTER TRANSMITTER/ RECEIVER MASTER TRANSMITTER SDA SCL MGA807 Fig.13 System configuration. handbook, full pagewidth DATA OUTPUT BY TRANSMITTER not acknowledge DATA OUTPUT BY RECEIVER acknowledge SCL FROM MASTER 1 2 8 9 S clock pulse for acknowledgement START condition MBC602 Fig.14 Acknowledgement on the I2C-bus. k, full pagewidth R/W acknowledge by A0, A1 and A2 selected PCF8576D only acknowledge by all addressed PCF8576Ds slave address S S 0 1 1 1 0 0 A 0 A C COMMAND A DISPLAY DATA A P 0 1 byte n ≥ 1 byte(s) n ≥ 0 byte(s) update data pointers and if necessary, subaddress counter MDB078 Fig.15 I2C-bus protocol. 2003 Jun 23 20 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D MSB LSB C REST OF OPCODE MSA833 C = 0 = last command. C = 1 = commands continue. Fig.16 Format of command byte. Table 4 Definition of PCF8576D commands COMMAND MODE SET OPCODE C 1 0 (1) E OPTIONS B M1 M0 Table 5 DESCRIPTION Defines LCD drive mode. Table 6 Defines LCD bias configuration. Table 7 Defines display status; the possibility to disable the display allows implementation of blinking under external control. LOAD DATA POINTER C 0 P5 P4 P3 P2 P1 P0 Table 8 Six bits of immediate data, bits P5 to P0, are transferred to the data pointer to define one of forty display RAM addresses. DEVICE SELECT C 1 1 0 0 A2 A1 A0 Table 9 Three bits of immediate data, bits A0 to A2, are transferred to the subaddress counter to define one of eight hardware subaddresses. BANK SELECT C 1 1 1 1 0 I O Table 10 Defines input bank selection (storage of arriving display data). Table 11 Defines output bank selection (retrieval of LCD display data); the BANK SELECT command has no effect in 1 : 3 and 1 : 4 multiplex drive modes. BLINK C 1 1 1 0 A BF1 BF0 Table 12 Table 13 Note 1. Not used. 2003 Jun 23 21 Defines the blink frequency. Selects the blink mode; normal operation with frequency set by BF1, BF0 or blinking by alternating display RAM banks; alternating RAM bank blinking does not apply in 1 : 3 and 1 : 4 multiplex drive modes. Philips Semiconductors Product specification Universal LCD driver for low multiplex rates Table 5 PCF8576D Mode set option 1 Table 12 Blink option 1 LCD DRIVE MODE BITS BITS BLINK FREQUENCY DRIVE MODE BACKPLANE M1 M0 BF1 BF0 Off 0 0 Static BP0 0 1 2 Hz 0 1 1:2 BP0, BP1 1 0 1 Hz 1 0 1:3 BP0, BP1, BP2 1 1 0.5 Hz 1 1 1:4 BP0, BP1, BP2, BP3 0 0 Table 13 Blink option 2 Table 6 Mode set option 2 BLINK MODE LCD BIAS BIT B 1⁄3bias 0 1⁄2bias 1 Table 7 Normal blinking 0 Alternate RAM bank blinking 1 Note 1. Normal blinking is assumed when LCD multiplex drive modes 1 : 3 or 1 : 4 are selected. Mode set option 3 DISPLAY STATUS BIT A BIT E Disabled (blank) 0 7.9 Enabled 1 The display controller executes the commands identified by the command decoder. It contains the device’s status registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display RAM in the correct filling order. Table 8 Load data pointer option 1 DESCRIPTION BITS Display controller 6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0 7.10 Table 9 Device select option 1 DESCRIPTION In large display configurations, up to 16 PCF8576Ds can be differentiated on the same I2C-bus by using the 3-bit hardware subaddresses (A0, A1 and A2) and the programmable I2C-bus slave address (SA0). PCF8576Ds connected in cascade are synchronized to allow the backplane signals from only one device in the cascade to be shared. This arrangement is cost-effective in large LCD applications since the backplane outputs of only one device need to be through-plated to the backplane electrodes of the display. The other cascaded PCF8576Ds contribute additional segment outputs but their backplane outputs are left open-circuit (see Fig.17). BITS 3 bit binary value of 0 to 7 A2 A1 A0 Table 10 Bank select option 1 (input) MODE BIT I STATIC 1:2 RAM bit 0 RAM bits 0 and 1 0 RAM bit 2 RAM bits 2 and 3 1 Table 11 Bank select option 2 (output) MODE BIT O STATIC 1:2 RAM bit 0 RAM bits 0 and 1 0 RAM bit 2 RAM bits 2 and 3 1 2003 Jun 23 Cascaded operation 22 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D Table 14 SYNC contact resistance All PCF8576Ds connected in cascade are correctly synchronized by the SYNC signal. This synchronization is guaranteed after the Power-on reset. The only time that SYNC is likely to be needed is if synchronization is lost accidentally, for example, by noise in adverse electrical environments, or if the LCD multiplex drive mode is changed in an application using several cascaded PCF8576Ds, as the drive mode cannot be changed on all of the cascaded devices simultaneously. SYNC can be either an input or an output signal; a SYNC output is implemented as an open-drain driver with an internal pull-up resistor. A PCF8576D asserts SYNC at the start of its last active backplane signal, and monitors the SYNC line at all other times. If cascade synchronization is lost, it will be restored by the first PCF8576D to assert SYNC. The timing relationship between the backplane waveforms and the SYNC signal for each LCD drive mode is shown in Fig.18. NUMBER OF DEVICES MAXIMUM CONTACT RESISTANCE 2 6000 Ω 3 to 5 2200 Ω 6 to 10 1200 Ω 10 to 16 700 Ω The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications. The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 14. handbook, full pagewidth VDD VLCD 6 SDA 1, 58, 59 SCL 2, 3 SYNC 4 13 40 segment drives LCD PANEL PCF8576DU CLK 5 OSC 7 8 9 10 11 12 A0 A1 A2 SA0 VSS (up to 2560 elements) BP0 to BP3 (open-circuit) VLCD VDD R≤ HOST MICROPROCESSOR/ MICROCONTROLLER tr 2CB V DD V LCD 6 13 SDA 1, 58, 59 SCL 2, 3 SYNC 4 PCF8576DU CLK 5 OSC 7 40 segment drives 4 backplanes BP0 to BP3 MDB077 8 VSS A0 9 A1 10 A2 11 12 SA0 VSS Fig.17 Cascaded PCF8576D configuration. 2003 Jun 23 23 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 1 Tframe = f frame handbook, full pagewidth BP0 SYNC (a) static drive mode. BP1 (1/2 bias) BP1 (1/3 bias) SYNC (b) 1 : 2 multiplex drive mode. BP2 SYNC (c) 1 : 3 multiplex drive mode. BP3 SYNC MGL755 (d) 1 : 4 multiplex drive mode. Fig.18 Synchronization of the cascade for the various PCF8576D drive modes. 2003 Jun 23 24 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 8 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage −0.5 +6.5 V VLCD LCD supply voltage VSS − 0.5 +7.5 V Vi1 input voltage CLK, SYNC, SA0, OSC, A0 to A2 VSS − 0.5 VDD + 0.5 V Vi2 input voltage SCL and SDA VSS − 0.5 +6.5 V VO output voltage S0 to S39, BP0 to BP3 VSS − 0.5 VDD + 0.5 V II DC input current −10 +10 mA IO DC output current −10 +10 mA IDD VDD current −50 +50 mA ISS VSS current −50 +50 mA ILCD VLCD current −50 +50 mA Ptot total power dissipation − 400 mW PO power dissipation per output − 100 mW Tstg storage temperature −65 +150 °C 9 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ). 2003 Jun 23 25 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 10 DC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supplies 1.8 − 5.5 V note 1 2.5 − 6.5 V note 2; fCLK = 1536 Hz − 8 20 µA − 24 60 µA VDD supply voltage VLCD LCD supply voltage IDD supply current ILCD LCD supply current note 2; fCLK = 1536 Hz Logic VIL LOW-level input voltage CLK, SYNC, OSC, A0 to A2 and SA0 VSS − 0.3VDD V VIH HIGH-level input voltage CLK, SYNC, OSC, A0 to A2 and SA0 0.7VDD − VDD V VIL2 LOW-level input voltage SCL, SDA VSS − 0.3VDD V VIH2 HIGH-level input voltage SCL, SDA 0.7VDD − VDD V IOL1 LOW-level output current CLK, SYNC VOL = 0.4 V; VDD = 5 V 1 − − mA IOH1 HIGH-level output current CLK VOH = 4.6 V; VDD = 5 V −1 − − mA IOL2 LOW-level output current SDA VOL = 0.4 V; VDD = 5 V 3 − − mA IL1 leakage current CLK, SCL, SDA, A0 to A2 and SA0 VI = VDD or VSS −1 − +1 µA IL2 leakage current OSC VI = VDD −1 − +1 µA VPOR power-on reset voltage level 1.0 1.3 1.6 V CI input capacitance − − 7 pF note 3 note 4 LCD outputs VBP DC voltage tolerance BP0 to BP3 −100 − +100 mV VS DC voltage tolerance S0 to S39 −100 − +100 mV RBP output resistance BP0 to BP3 note 5; VLCD = 5 V − 1.5 − kΩ RS output resistance S0 to S39 note 5; VLCD = 5 V − 6.0 − kΩ Notes 1. VLCD > 3 V for 1⁄3bias. 2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive. 3. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven according to the Vi2 limiting values given in Chapter 8. Also see Fig.23. 4. Periodically sampled, not 100% tested. 5. Outputs measured one at a time. 2003 Jun 23 26 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 11 AC CHARACTERISTICS VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified. SYMBOL PARAMETER CONDITIONS note 1 MIN. TYP. MAX. UNIT fCLK oscillator frequency 397 1536 3046 Hz tCLKH input CLK HIGH time 60 − − µs tCLKL input CLK LOW time 60 − − µs tPD(SYNC) SYNC propagation delay − 30 − ns tSYNCL SYNC LOW time 1 − − µs tPD(LCD) driver delays with test loads − − 30 µs VLCD = 5 V; note 2 Timing characteristics: I2C-bus; note 3 fSCL SCL clock frequency − − 400 kHz tBUF bus free time between a STOP and START 1.3 − − µs tHD;STA START condition hold time 0.6 − − µs tSU;STA set-up time for a repeated START condition 0.6 − − µs tLOW SCL LOW time 1.3 − − µs tHIGH SCL HIGH time 0.6 − − µs tr SCL and SDA rise time − − 0.3 µs tf SCL and SDA fall time − − 0.3 µs CB capacitive bus line load − − 400 pF tSU;DAT data set-up time 100 − − ns tHD;DAT data hold time 0 − − ns tSU;STO set-up time for STOP condition 0.6 − − µs tSW tolerable spike width on bus − − 50 ns Notes 1. Typical output duty factor: 50% measured at the CLK output pin. 2. Not tested in production. 3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to VIL and VIH with an input voltage swing of VSS to VDD. handbook, full pagewidth SYNC 6.8 Ω VDD (2%) CLK 3.3 k Ω 0.5VDD (2%) BP0 to BP3, and S0 to S39 SDA, SCL (2%) VDD 1 nF VSS MCE439 Fig.19 Test loads. 2003 Jun 23 1.5 k Ω 27 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 1/fCLK handbook, full pagewidth tCLKH tCLKL 0.7VDD 0.3VDD CLK 0.7VDD SYNC 0.3VDD tPD(SYNC) tPD(SYNC) tSYNCL 0.5 V BP0 to BP3, and S0 to S39 (VDD = 5 V) 0.5 V tPD(LCD) MCE424 Fig.20 Driver timing waveforms. handbook, full pagewidth SDA t BUF tf t LOW SCL t HD;STA t HD;DAT tr t HIGH t SU;DAT SDA MGA728 t SU;STA Fig.21 I2C-bus timing waveforms. 2003 Jun 23 28 t SU;STO Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 12 BONDING PAD INFORMATION COORDINATES SYMBOL Table 15 Bonding pad locations All x/y coordinates represent the position of the centre of each pad (in µm) with respect to the centre (x/y = 0) of the chip (see Fig.22). x COORDINATES SYMBOL PAD x y SDA 1 −34.38 −876.6 SCL 2 109.53 −876.6 SCL 3 181.53 −876.6 SYNC 4 365.58 −876.6 CLK 5 469.08 −876.6 VDD 6 577.08 −876.6 OSC 7 740.88 −876.6 A0 8 835.83 −876.6 A1 9 1005.48 −630.9 A2 10 1005.48 −513.9 SA0 11 1005.48 −396.9 VSS 12 1005.48 −221.4 VLCD 13 1005.48 10.71 BP0 14 1005.48 156.51 BP2 15 1005.48 232.74 BP1 16 1005.48 308.97 BP3 17 1005.48 385.2 S0 18 1005.48 493.2 S1 19 1005.48 565.2 S2 20 1005.48 637.2 S3 21 1005.48 709.2 S4 22 347.22 876.6 S5 23 263.97 876.6 S6 24 180.72 876.6 S7 25 97.47 876.6 S8 26 14.22 876.6 S9 27 −69.03 876.6 S10 28 −152.28 876.6 876.6 S11 2003 Jun 23 29 −235.53 PAD y S12 30 −318.78 876.6 S13 31 −402.03 876.6 S14 32 −485.28 876.6 S15 33 −568.53 876.6 S16 34 −651.78 876.6 S17 35 −735.03 876.6 S18 36 −1005.5 625.59 S19 37 −1005.5 541.62 S20 38 −1005.5 458.19 S21 39 −1005.5 374.76 S22 40 −1005.5 291.33 S23 41 −1005.5 207.9 S24 42 −1005.5 124.47 S25 43 −1005.5 41.04 S26 44 −1005.5 −42.39 S27 45 −1005.5 −125.8 S28 46 −1005.5 −209.3 S29 47 −1005.5 −292.7 S30 48 −1005.5 −376.1 S31 49 −1005.5 −459.5 S32 50 −1005.5 −543 S33 51 −1005.5 −625.6 S34 52 −735.03 −876.6 S35 53 −663.03 −876.6 S36 54 −591.03 −876.6 S37 55 −519.03 −876.6 S38 56 −447.03 −876.6 S39 57 −375.03 −876.6 SDA 58 −196.38 −876.6 SDA 59 −106.38 −876.6 C1 930.42 −870.3 C2 −829.98 −870.3 Alignment marks 29 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 S3 36 20 S2 37 19 S1 S20 38 18 S0 S21 39 17 BP3 S22 40 16 BP1 41 15 BP2 S24 42 14 BP0 S25 43 13 VLCD S26 44 S27 45 S28 46 12 S29 47 VSS S30 48 S31 11 49 SA0 10 A2 9 A1 S18 S19 S23 2.01 mm S17 handbook, full pagewidth PCF8576D S32 50 S33 51 x 0 0 y PCF8576DU C1 S37 S39 SDA SDA 3 4 5 6 7 8 A0 S36 2 OSC S35 1 VDD 59 CLK 58 SYNC 57 SCL 55 56 SCL 54 SDA 53 S38 52 S34 C2 2.26 mm Chip dimensions: approximately 2.26 × 2.01 mm. Bump dimensions (except pad 1): 52 × 80 × 17.5 (height) µm. Bump dimensions (pad 1): 52 × 76 × 17.5 (height) µm. Alignment marks: diameter = 72 µm. Fig.22 Bonding pad locations. 2003 Jun 23 30 MDB074 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 13 DEVICE PROTECTION handbook, full pagewidth VDD VDD VSS VSS SA0 VDD CLK SCL VSS VDD VSS OSC VSS VDD SDA SYNC VSS VSS VDD A0, A1 A2 VSS VLCD BP0, BP1, BP2, BP3 VSS VLCD VLCD S0 to S39 VSS VSS MDB076 Fig.23 Device protection diagram. 2003 Jun 23 31 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 14 TRAY INFORMATION x handbook, full pagewidth G A C H y 1,1 2,1 x,1 D 1,2 B F x,y 1,y E MCE404 For dimensions, see Table 16. Fig.24 Tray details. Table 16 Tray dimensions (see Fig.24) SYMBOL DESCRIPTION VALUE A pocket pitch, in x direction 5.59 mm B pocket pitch, in y direction 6.35 mm C pocket width, in x direction 3.16 mm D pocket width, in y direction 3.16 mm E tray width, in x direction 50.8 mm F tray width, in y direction 50.8 mm G cut corner to pocket 1,1 centre 5.83 mm H cut corner to pocket 1,1 centre 6.35 mm x number of pockets in x direction 8 y number of pockets in y direction 7 handbook, halfpage PC8576DU MDB080 The orientation of the IC in a pocket is indicated by the position of the IC type name on the die surface with respect to the chamfer on the upper left corner of the tray. Fig.25 Tray alignment. 2003 Jun 23 32 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 15 PACKAGE OUTLINE TQFP64: plastic thin quad flat package; 64 leads; body 10 x 10 x 1.0 mm SOT357-1 c y X A 48 33 49 32 ZE e E HE A (A 3) A2 A 1 wM pin 1 index θ bp 64 Lp L 17 1 detail X 16 ZD e v M A wM bp D B HD v M B 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e mm 1.2 0.15 0.05 1.05 0.95 0.25 0.27 0.17 0.18 0.12 10.1 9.9 10.1 9.9 0.5 HD HE 12.15 12.15 11.85 11.85 L Lp v w y 1 0.75 0.45 0.2 0.08 0.1 Z D(1) Z E(1) θ 1.45 1.05 7 0o 1.45 1.05 o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT357-1 137E10 MS-026 2003 Jun 23 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 02-03-14 33 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D To overcome these problems the double-wave soldering method was specifically developed. 16 SOLDERING 16.1 Introduction to soldering surface mount packages If wave soldering is used the following conditions must be observed for optimal results: This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011). • Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. • For packages with leads on two sides and a pitch (e): There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 16.2 – larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; – smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. Reflow soldering The footprint must incorporate solder thieves at the downstream end. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. • For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material applied, SnPb or Pb-free respectively. • below 220 °C (SnPb process) or below 245 °C (Pb-free process) A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. – for all the BGA packages 16.4 – for packages with a thickness ≥ 2.5 mm Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C. – for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages. • below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 °C. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 16.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. 2003 Jun 23 Manual soldering 34 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates 16.5 PCF8576D Suitability of surface mount IC packages for wave and reflow soldering methods SOLDERING METHOD PACKAGE(1) WAVE BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable(3) DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS not PLCC(4), SO, SOJ suitable LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP REFLOW(2) suitable suitable suitable not recommended(4)(5) suitable not recommended(6) suitable Notes 1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. 2003 Jun 23 35 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D 17 DATA SHEET STATUS LEVEL DATA SHEET STATUS(1) PRODUCT STATUS(2)(3) Development DEFINITION I Objective data II Preliminary data Qualification This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. III Product data This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Production This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 18 DEFINITIONS 19 DISCLAIMERS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 2003 Jun 23 36 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D Bare die All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die. Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify their application in which the die is used. 20 PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. 2003 Jun 23 37 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D NOTES 2003 Jun 23 38 Philips Semiconductors Product specification Universal LCD driver for low multiplex rates PCF8576D NOTES 2003 Jun 23 39 Philips Semiconductors – a worldwide company Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: [email protected]. SCA75 © Koninklijke Philips Electronics N.V. 2003 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 403512/02/pp40 Date of release: 2003 Jun 23 Document order number: 9397 750 11483