PHILIPS PCF8562

INTEGRATED CIRCUITS
DATA SHEET
PCF8562
Universal LCD driver
for low multiplex rates
Preliminary Specification
November 22, 2004
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
CONTENTS
14.1
1
FEATURES
2
GENERAL DESCRIPTION
3
ORDERING INFORMATION
4
BLOCK DIAGRAM
14.2
14.3
14.4
14.5
5
PINNING
15
6
FUNCTIONAL DESCRIPTION
16
DEFINITIONS
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
6.13
6.14
6.15
Power-on reset
LCD bias generator
LCD voltage selector
LCD drive mode waveforms
Oscillator
Timing
Display register
Segment outputs
Backplane outputs
Display RAM
Data pointer
Device Select
Output bank selector
Input bank selector
Blinker
17
DISCLAIMERS
18
PURCHASE OF PHILIPS I2C COMPONENTS
7
CHARACTERISTICS OF THE I2C-BUS
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
Bit transfer
Start and stop conditions
System configuration
Acknowledge
PCF8562 I2C-bus controller
Input filters
I2C-bus protocol
Command decoder
Display controller
Multiple chip operation
8
LIMITING VALUES
9
HANDLING
10
DC CHARACTERISTICS
11
AC CHARACTERISTICS
12
DEVICE PROTECTION
13
PACKAGE OUTLINES
14
SOLDERING
November 22, 2004
2
Introduction to soldering surface mount
packages
Reflow soldering
Wave soldering
Manual soldering
Suitability of surface mount IC packages for
wave and reflow soldering methods
DATA SHEET STATUS
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
1
PCF8562
FEATURES
• Single-chip LCD controller/driver
• Selectable backplane drive configuration: static or 2/3/4 backplane multiplexing
• Selectable display bias configuration: static, 1/2 and 1/3
• Internal LCD bias generation with voltage-follower buffers
• 32 segment drives: up to sixteen 8-segment numeric characters; up to eight 15-segment alphanumeric characters; or
any graphics of up to 128 elements
• 32 × 4-bit RAM for display data storage
• Auto-incremental display data loading across device subaddress boundaries
• Display memory bank switching in static and duplex drive modes
• Versatile blinking modes
• Independent supplies possible for LCD and logic voltages
• Wide power supply range: from 1.8 to 5.5 V
• Wide logic LCD supply range: from 2.5 V for low-threshold LCDs and up to 6.5 V for guest-host LCDs and
high-threshold (automobile) twisted nematic LCDs
• Low power consumption
• 400 kHz I2C-bus interface
• TTL/CMOS compatible
• Compatible with 4, 8 or 16-bit microprocessors or microcontrollers
• No external components
• Compatible with chip-on-glass technology
• Manufactured in silicon gate CMOS process.
2
GENERAL DESCRIPTION
The PCF8562 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD) with low multiplex rates.
It generates the drive signals for any static or multiplexed LCD containing up to four backplanes and up to 32 segments.
The PCF8562 is compatible with most microprocessors/microcontrollers and communicates via a two-line bidirectional
I2C-bus. Communication overheads are minimized by a display RAM with auto-incremental addressing, by hardware
subaddressing and by display memory switching (static and duplex drive modes).
3
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
NAME
PCF8562TT
November 22, 2004
TSSOP48
DESCRIPTION
plastic, 48 leads; body
VERSION
SOT362-1
3
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Philips Semiconductors
BLOCK DIAGRAM
Universal LCD driver
for low multiplex rates
November 22, 2004
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Preliminary specification
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Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
5
PCF8562
PINNING
PIN
SYMBOL
DESCRIPTION
PCF8562TT
SDA
10
I2C-bus serial data Input / Output
SCL
11
I2C-bus serial clock input
CLK
13
external clock input / output
VDD
14
supply voltage
SYNC
12
cascade synchronisation input / output
OSC
15
internal oscillator enable input
A0 to A2
16 to 18
sub address inputs
SAO
19
I2C-bus slave address input: bit 0
VSS
20
logic ground
VLCD
21
LCD supply voltage
BP0 to BP3
22 to 25
LCD backplane outputs
S0 to S22
26 to 48
LCD segments output
S23 to S31
1 to 9
November 22, 2004
5
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
48
1
S23
S22
S24
S21
S25
S20
S26
S19
S27
S18
S28
S17
S29
S16
S30
S15
S31
S14
SDA
S13
SCL
S12
SYNC
S11
PCF8562
CLK
S10
VDD
S9
OSC
S8
A0
S7
A1
S6
A2
S5
SA0
S4
V SS
S3
VLCD
S2
BP0
S1
BP2
S0
BP1
BP3
MDB073v2
25
24
Fig.2 Pin Configuration (TSSOP48)
November 22, 2004
6
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
6
PCF8562
FUNCTIONAL DESCRIPTION
The PCF8562 is a versatile peripheral device designed to interface any microprocessor/microcontroller with a wide
variety of LCDs. It can directly drive any static or multiplexed LCD containing up to four backplanes and up to
32 segments.
The display configurations possible with the PCF8562 depend on the number of active backplane outputs required. A
selection of display configurations is shown in Table 1; all of these configurations can be implemented in the typical
system shown in Fig.4.
The host microprocessor/microcontroller maintains the 2-line I2C-bus communication channel with the PCF8562. The
internal oscillator is enabled by connecting pin OSC to pin VSS. The appropriate biasing voltages for the multiplexed LCD
waveforms are generated internally. The only other connections required to complete the system are to the power
supplies (VDD, VSS and VLCD) and the LCD panel chosen for the application.
Table 1
Selection of display configurations
NUMBER OF
14-SEGMENTS
ALPHANUMERIC
7-SEGMENTS NUMERIC
DOT MATRIX
BACKPLANE
S
SEGMENTS
DIGITS
INDICATOR
SYMBOLS
CHARACTERS
INDICATOR
SYMBOLS
4
128
16
16
8
16
128 dots (4 × 32)
3
86
12
12
6
12
96 dots (3 × 32)
2
64
8
8
4
8
64 dots (2 × 32)
1
32
4
4
2
4
32 dots (1 × 32)
VDD
R≤
tr
2CB
HOST
MICROPROCESSOR/
MICROCONTROLLER
VDD
VLCD
SDA
32 segment drives
SCL
PCF8562
OSC
4 backplanes
A0
A1
A2
SA0 VSS
VSS
The resistance of the power supply lines must be kept to a minimum.
Fig.4 Typical system configuration.
November 22, 2004
7
LCD PANEL
(up to 128
elements)
MDB079v2
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
6.1
PCF8562
Power-on reset
At power-on the PCF8562 resets to the following starting conditions:
• All backplane outputs are set to VLCD
• All segment outputs are set to VLCD
• Drive mode ‘1 : 4 multiplex with 1⁄3bias’ is selected
• Blinking is switched off
• Input and output bank selectors are reset (as defined in Table 4)
• The I2C-bus interface is initialized
• The data pointer and the subaddress counter are cleared
• Display is disabled.
Data transfers on the I2C-bus should be avoided for 1 ms following power-on to allow completion of the reset action.
6.2
LCD bias generator
Fractional LCD biasing voltages are obtained from an internal voltage divider comprising three resistors connected in
series between VLCD and VSS. The middle resistor can be bypassed to provide a 1⁄2bias voltage level for the 1 : 2
multiplex configuration. The LCD voltage can be temperature compensated externally via the supply to pin VLCD.
6.3
LCD voltage selector
The LCD voltage selector co-ordinates the multiplexing of the LCD in accordance with the selected LCD drive
configuration. The operation of the voltage selector is controlled by MODE SET commands from the command decoder.
The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as
functions of VLCD and the resulting Discrimination ratios (D), are given in Table 2.
A practical value for VLCD is determined by equating Voff(rms) with a defined LCD threshold voltage (Vth), typically when
the LCD exhibits approximately 10% contrast. In the static drive mode a suitable choice is VLCD > 3Vth.
Multiplex drive modes of 1 : 3 and 1 : 4 with 1⁄2 bias are possible but the discrimination and hence the contrast ratios are
smaller.
6.3.1
LCD BIAS FORMULAE
1
Bias is calculated by the formula ------------1+a
where for 1⁄2 bias, a = 1; for 1⁄3 bias, a = 2.
The LCD on voltage (Von) is calculated by the formula
V op
2
1
1
---- + ( N – 1 ) ⋅ ⎛⎝ -------------⎞⎠
1+a
N
-----------------------------------------------------------N
V op
a – ( 2a + N )
---------------------------------2
N ⋅ (1 + a)
2
The LCD off voltage (Voff) is calculated by the formula
where Vop is the resultant voltage at the LCD segment; N is the LCD drive mode: 1 = static, 2 = 1 : 2, 3 = 1 : 3, 4 = 1 : 4.
November 22, 2004
8
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
2
(a + 1) + (N – 1)
-------------------------------------------2
(a – 1) + (N – 1)
V on
Discrimination is the ratio of Von to Voff, and is determined by the formula --------- =
V off
Using the above formula, the discrimination for an LCD drive mode of 1 : 3 with 1⁄2bias is
3 = 1.732, and the
21
discrimination for an LCD drive mode of 1 : 4 with 1⁄2bias is ---------- = 1.528.
3
The advantage of these LCD drive modes is a reduction of the LCD full-scale voltage VLCD as follows:
• 1 : 3 multiplex (1⁄2 bias): VLCD =
6 × V off(rms) = 2.449 Voff(rms)
• 1 : 4 multiplex (1⁄2 bias): VLCD =
(4 × 3)
---------------------3
= 2.309 Voff(rms)
These compare with VLCD = 3 Voff(rms) when 1⁄3 bias is used.
Table 2
Discrimination ratios
NUMBER OF
LCD DRIVE MODE
BACKPLANES
LEVELS
LCD BIAS
CONFIGURATION
V off(rms)
--------------------V lcd
Von(rms)
-------------------V lcd
V on(rms)
D = --------------------V off(rms)
static
1
2
static
0
1
∞
1 : 2 multiplex
2
3
0.354
0.791
2.236
1 : 2 multiplex
2
4
0.333
0.745
2.236
1 : 3 multiplex
3
4
0.333
0.638
1.915
1 : 4 multiplex
4
4
1⁄
2
1⁄
3
1⁄
3
1⁄
3
0.333
0.577
1.732
November 22, 2004
9
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
6.4
PCF8562
LCD drive mode waveforms
6.4.1
STATIC DRIVE MODE
The static LCD drive mode is used when a single backplane is provided in the LCD. The backplane (BPn) and segment
drive (Sn) waveforms for this mode are shown in Fig.5.
Tframe
ull pagewidth
LCD segments
VLCD
BP0
VSS
state 1
(on)
VLCD
state 2
(off)
Sn
VSS
VLCD
Sn + 1
VSS
(a) Waveforms at driver.
VLCD
state 1
0V
−VLCD
V state1(t) = V S (t) – V BP0(t)
n
VLCD
V on(rms) = V LCD
V state2(t) = V S
state 2
0V
−VLCD
V off(rms) = 0 V
(b) Resultant waveforms
at LCD segment.
MGL745
Fig.5 Static drive mode waveforms.
November 22, 2004
10
(t) – V BP0(t)
n+1
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
6.4.2
PCF8562
1 : 2 MULTIPLEX DRIVE MODE
The 1 : 2 multiplex drive mode is used when two backplanes are provided in the LCD. This mode allows fractional LCD
bias voltages of 1⁄2bias or 1⁄3bias as shown in Figs 6 and 7.
Tframe
handbook, full pagewidth
VLCD
BP0
LCD segments
VLCD/2
VSS
state 1
VLCD
BP1
state 2
VLCD/2
VSS
VLCD
Sn
VSS
VLCD
Sn + 1
VSS
(a) Waveforms at driver.
VLCD
VLCD/2
state 1
0V
−VLCD/2
−VLCD
VLCD
VLCD/2
state 2
0V
−VLCD/2
−VLCD
(b) Resultant waveforms
at LCD segment.
MGL746
V state1(t) = V S (t) – V BP0(t)
n
V on(rms) = 0.791V LCD
V state2(t) = V S (t) – V BP1(t)
n
V off(rms) = 0.354V LCD
Fig.6 Waveforms for the 1 : 2 multiplex drive mode with 1⁄2 bias.
November 22, 2004
11
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
Tframe
handbook, full pagewidth
BP0
BP1
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
2VLCD/3
state 2
VLCD/3
VSS
VLCD
Sn
Sn + 1
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
MGL747
V state1(t) = V S (t) – V BP0(t)
n
V on(rms) = 0.745V LCD
V state2(t) = V S (t) – V BP1(t)
n
V off(rms) = 0.333V LCD
Fig.7 Waveforms for the 1 : 2 multiplex drive mode with 1⁄3 bias.
November 22, 2004
12
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
6.4.3
PCF8562
1 : 3 MULTIPLEX DRIVE MODE
When three backplanes are provided in the LCD, the 1 : 3 multiplex drive mode applies (see Fig.8).
Tframe
handbook, full pagewidth
BP0
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
BP1
BP2
Sn
Sn + 1
Sn + 2
state 2
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
state 1
2VLCD/3
VLCD/3
0V
−VLCD/3
−2VLCD/3
−VLCD
VLCD
2VLCD/3
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
(b) Resultant waveforms
at LCD segment.
MGL748
V state1(t) = V S (t) – V BP0(t)
n
V on(rms) = 0²638V LCD
V state2(t) = V S (t) – V BP1(t)
n
V off(rms) = 0.333V LCD
Fig.8 Waveforms for the 1 : 3 multiplex drive mode.
November 22, 2004
13
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
6.4.4
PCF8562
1 : 4 MULTIPLEX DRIVE MODE
When four backplanes are provided in the LCD, the 1 : 4 multiplex drive mode applies (see Fig.9).
Tframe
handbook, full pagewidth
BP0
VLCD
2VLCD/3
LCD segments
VLCD/3
VSS
state 1
VLCD
BP1
BP2
BP3
Sn
Sn + 1
Sn + 2
Sn + 3
state 2
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
VLCD
2VLCD/3
VLCD/3
VSS
(a) Waveforms at driver.
VLCD
2VLCD/3
VLCD/3
state 1
0V
−VLCD/3
−2VLCD/3
−VLCD
V state1(t) = V S (t) – V BP0(t)
VLCD
n
2VLCD/3
V on(rms) = 0²577V LCD
VLCD/3
state 2
0V
−VLCD/3
−2VLCD/3
−VLCD
V state2(t) = V S (t) – V BP1(t)
n
V off(rms) = 0.333V LCD
(b) Resultant waveforms
at LCD segment.
Fig.9 Waveforms for the 1 : 4 multiplex drive mode.
November 22, 2004
14
MGL749
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
6.5
6.5.1
PCF8562
Oscillator
INTERNAL CLOCK
The internal logic of the PCF8562 and its LCD drive signals are timed either by its internal oscillator or by an external
clock. The internal oscillator is enabled by connecting pin OSC to pin VSS. After power-up, pin SDA must be HIGH to
guarantee that the clock starts.
6.5.2
EXTERNAL CLOCK
Pin CLK is enabled as an external clock input by connecting pin OSC to VDD.
The LCD frame signal frequency is determined by the clock frequency (fCLK).
A clock signal must always be supplied to the device; removing the clock may freeze the LCD in a DC state.
6.6
Timing
The PCF8562 timing controls the internal data flow of the device. This includes the transfer of display data from the
display RAM to the display segment outputs. The timing also generates the LCD frame signal whose frequency is derived
from the clock frequency. The frame signal frequency is a fixed division integer of the clock frequency (nominally 64 kHz)
from either the internal or an external clock.
f CLK
Frame frequency = ---------24
6.7
Display register
The display latch holds the display data while the corresponding multiplex signals are generated. There is a one-to-one
relationship between the data in the display latch, the LCD segment outputs and each column of the display RAM.
6.8
Segment outputs
The LCD drive section includes 32 segment outputs S0 to S31 which should be connected directly to the LCD. The
segment output signals are generated in accordance with the multiplexed backplane signals and with data residing in the
display latch. When less than 32 segment outputs are required, the unused segment outputs should be left open-circuit.
6.9
Backplane outputs
The LCD drive section includes four backplane outputs BP0 to BP3 which should be connected directly to the LCD. The
backplane output signals are generated in accordance with the selected LCD drive mode. If less than four backplane
outputs are required, the unused outputs can be left open-circuit. In the 1 : 3 multiplex drive mode, BP3 carries the same
signal as BP1, therefore these two adjacent outputs can be tied together to give enhanced drive capabilities. In the 1 : 2
multiplex drive mode, BP0 and BP2, BP1 and BP3 respectively carry the same signals and may also be paired to
increase the drive capabilities. In the static drive mode the same signal is carried by all four backplane outputs and they
can be connected in parallel for very high drive requirements.
6.10
Display RAM
The display RAM is a static 32 × 4-bit RAM which stores LCD data. A logic 1 in the RAM bit-map indicates the on-state
of the corresponding LCD segment; similarly, a logic 0 indicates the off-state. There is a one-to-one correspondence
between the RAM addresses and the segment outputs, and between the individual bits of a RAM word and the backplane
outputs. The first RAM column corresponds to the 32 segments operated with respect to backplane BP0 (see Fig.10). In
multiplexed LCD applications the segment data of the second, third and fourth column of the display RAM are
time-multiplexed with BP1, BP2 and BP3 respectively.
When display data is transmitted to the PCF8562, the display bytes received are stored in the display RAM in accordance
with the selected LCD drive mode. The data is stored as it arrives and does not wait for an acknowledge cycle as with
the commands. Depending on the current multiplex drive mode, data is stored singularly, in pairs, triplets or quadruplets.
For example, in the 1 : 2 mode, the RAM data is stored every second bit. To illustrate the filling order, an example of a
November 22, 2004
15
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
7-segment numeric display showing all drive modes is given in Fig.10; the RAM filling organization depicted applies
equally to other LCD types.
display RAM addresses (rows) / segment outputs (S)
0
1
2
3
4
27
28
29
30
31
0
display RAM bits
1
(columns) /
backplane outputs
2
(BP)
3
MBE525v2
Fig.10 Display RAM bit-map showing direct relationship between display RAM addresses and
segment outputs also between bits in a RAM word and the backplane outputs.
With reference to Fig.10, in the static drive mode, the eight transmitted data bits are placed in bit 0 of eight successive
display RAM addresses. In the 1 : 2 mode, the eight transmitted data bits are placed in bits 0 and 1 of four successive
display RAM addresses. In the 1 : 3 mode, these bits are placed in bits 0, 1 and 2 of three successive addresses, with
bit 2 of the third address left unchanged. This last bit may, if necessary, be controlled by an additional transfer to this
address but care should be taken to avoid overriding adjacent data because full bytes are always transmitted.
In the 1 : 4 mode, the eight transmitted data bits are placed in bits 0, 1, 2 and 3 of two successive display RAM
addresses.
6.11
Data pointer
The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual
display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with
the initialization of the data pointer by the LOAD DATA POINTER command. Following this, an arriving data byte is stored
at the display RAM address indicated by the data pointer in accordance with the filling order shown in Fig.11. After each
byte is stored, the contents of the data pointer are automatically incremented by a value dependent on the selected LCD
drive mode: eight (static drive mode), four (1 : 2 mode), three (1 : 3 mode) or two (1 : 4 mode). If an I2C-bus data access
is terminated early then the state of the data pointer will be unknown. The data pointer should be re-written prior to further
RAM accesses.
6.12
Device Select
Storage is allowed to take place when the internal select register agrees with the hardware subaddress applied to A0,
A1 and A2.
The hardware subaddress should not be changed whilst the device is being accessed on the I2C-bus interface.
6.13
Output bank selector
The output bank selector selects one of the four bits per display RAM address for transfer to the display latch. The actual
bit chosen depends on the selected LCD drive mode and on the instant in the multiplex sequence. In 1 : 4 mode, all RAM
addresses of bit 0 are selected, these are followed by the contents of bit 1, bit 2 and then bit 3. Similarly in 1 : 3 mode,
bits 0, 1 and 2 are selected sequentially. In 1 : 2 mode, bits 0 and 1 are selected and, in static mode, bit 0 is selected.
Signal SYNC will reset these sequences to the following starting points; bit 3 for 1 : 4 mode, bit 2 for 1 : 3 mode, bit 1
for 1 : 2 mode and bit 0 for static mode.
November 22, 2004
16
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
The PCF8562 includes a RAM bank switching feature in the static and 1 : 2 drive modes. In the static drive mode, the
BANK SELECT command may request the contents of bit 2 to be selected for display instead of the contents of bit 0. In
1 : 2 mode, the contents of bits 2 and 3 may be selected instead of bits 0 and 1. This allows display information to be
prepared in an alternative bank and then selected for display when it is assembled.
6.14
Input bank selector
The input bank selector loads display data into the display RAM in accordance with the selected LCD drive configuration.
The BANK SELECT command can be used to load display data in bit 2 in static drive mode or in bits 2 and 3 in
1 : 2 mode. The input bank selector functions are independent of the output bank selector.
6.15
Blinker
The PCF8562 has a very versatile display blinking capability. The whole display can blink at a frequency selected by the
BLINK command. Each blink frequency is a multiple integer value of the clock frequency; the ratio between the clock
frequency and blink frequency depends on the blink mode selected, as shown in Table 3.
An additional feature allows an arbitrary selection of LCD segments to be blinked in the static and 1 : 2 drive modes.
This is implemented without any communication overheads by the output bank selector which alternates the displayed
data between the data in the display RAM bank and the data in an alternative RAM bank at the blink frequency. This
mode can also be implemented by the BLINK command.
In the 1 : 3 and 1 : 4 drive modes, where no alternative RAM bank is available, groups of LCD segments can be blinked
by selectively changing the display RAM data at fixed time intervals.
The entire display can be blinked at a frequency other than the nominal blink frequency by sequentially resetting and
setting the display enable bit E at the required rate using the MODE SET command.
Table 3
Blinking frequencies
BLINK MODE
NORMAL OPERATING MODE
RATIO
NOMINAL BLINK FREQUENCY
Off
−
blinking off
2 Hz
f CLK
----------768
2 Hz
1 Hz
f CLK
------------1536
1 Hz
0.5 Hz
f CLK
------------3072
0.5 Hz
Note
1. Blink modes 0.5, 1 and 2 Hz, and nominal blink frequencies 0.5, 1 and 2 Hz correspond to an oscillator frequency
(fCLK) of 1536 Hz at pin CLK. The oscillator frequency range is given in Chapter 11.
November 22, 2004
17
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static
a
2
Sn
3
Sn
4
Sn
5
Sn
6
b
f
g
e
1
Sn
2
Sn
3
18
Sn
1:3
Sn
Sn
7
DP
f
c
d
DP
b
f
BP1
BP2
DP
a
b
BP0
n 5
n 6
n 7
c
x
x
x
b
x
x
x
a
x
x
x
f
x
x
x
g
x
x
x
e
x
x
x
d
x
x
x
DP
x
x
x
n
n 1
n 2
n 3
a
b
x
x
f
g
x
x
e
c
x
x
d
DP
x
x
n
n 1
n 2
b
DP
c
x
a
d
g
x
f
e
x
x
n
n 1
a
c
b
DP
f
e
g
d
LSB
c b a f
g e d DP
e
0
1
2
3
bit/
BP
BP1
c
a b f
LSB
g e c d DP
MSB
LSB
b DP c a d g f
e
BP3
MSB
a c b DP f
LSB
e g d
DP
PCF8562
Fig.11 Relationships between LCD layout, drive mode, display RAM filling order and display data transmitted over the I2C-bus.
MGL751
Preliminary specification
d
MSB
BP2
g
x = data bit unchanged.
0
1
2
3
bit/
BP
f
1
n 4
Sn
c
Sn
Sn
n 3
BP0
a
d
multiplex
0
1
2
3
bit/
BP
BP1
e
e
1:4
n 2
b
g
multiplex
n 1
BP0
a
1
2
n
MSB
0
1
2
3
bit/
BP
g
multiplex
transmitted display byte
1
Sn
c
Sn
Sn
BP0
Sn
d
1:2
display RAM filling order
handbook, full pagewidth
Sn
LCD backplanes
Philips Semiconductors
LCD segments
Universal LCD driver
for low multiplex rates
November 22, 2004
drive mode
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
7
PCF8562
CHARACTERISTICS OF THE I2C-BUS
The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a serial data
line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when
connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
In chip-on-glass applications where the track resistance from the SDA pad to the system SDA line can be significant, a
potential divider is generated by the bus pull-up resistor and the Indium Tin Oxide (ITO) track resistance. It is therefore
necessary to minimize the track resistance from the SDA pad to the system SDA line to guarantee a valid LOW-level
during the acknowledge cycle.
7.1
Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period
of the clock pulse as changes in the data line at this time will be interpreted as a control signal (see Fig.12).
7.2
Start and stop conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the
clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH
is defined as the STOP condition (P), (see Fig.13).
7.3
System configuration
A device generating a message is a ‘transmitter’, a device receiving a message is the ‘receiver’. The device that controls
the message is the ‘master’ and the devices which are controlled by the master are the ‘slaves’, (see Fig.14).
7.4
Acknowledge
The number of data bytes that can be transferred from transmitter to receiver between the START and STOP conditions
is unlimited. Each byte of eight bits is followed by an acknowledge bit. The acknowledge bit is a HIGH-level signal on the
bus that is asserted by the transmitter during which time the master generates an extra acknowledge related clock pulse.
An addressed slave receiver must generate an acknowledge after receiving each byte. Also a master receiver must
generate an acknowledge after receiving each byte that has been clocked out of the slave transmitter. The
acknowledging device must pull-down the SDA line during the acknowledge clock pulse so that the SDA line is stable
LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be taken into
consideration). A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the
last byte that has been clocked out of the slave. In this event the transmitter must leave the data line HIGH to enable the
master to generate a STOP condition (see Fig.15).
7.5
PCF8562 I2C-bus controller
The PCF8562 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus
master receiver. The only data output from the PCF8562 are the acknowledge signals of the selected devices. Device
selection depends on the I2C-bus slave address, on the transferred command data and on the hardware subaddress.
7.6
Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL
lines.
7.7
I2C-bus protocol
Two I2C-bus slave addresses (01110000 and 01110010) are reserved for the PCF8562. The least significant bit of the
slave address that a PCF8562 will respond to is defined by the level tied to its SA0 input. The PCF8562 is a write-only
device and will not respond to a read access.
November 22, 2004
19
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
The I2C-bus protocol is shown in Fig.16. The sequence is initiated with a START condition (S) from the I2C-bus master
which is followed by one of two possible PCF8562 slave addresses available. All PCF8562s whose SA0 inputs
correspond to bit 0 of the slave address respond by asserting an acknowledge in parallel. This I2C-bus transfer is ignored
by all PCF8562s whose SA0 inputs are set to the alternative level.
After an acknowledgement, one or more command bytes follow which define the status of the PCF8562.
The last command byte sent is identified by resetting its most significant bit, continuation bit C, (see Fig.17). The
command bytes are also acknowledged by all addressed PCF8562s on the bus.
After the last command byte, one or more display data bytes may follow. Display data bytes are stored in the display
RAM at the address specified by the data pointer and the subaddress counter. Both data pointer and subaddress counter
are automatically updated.
An acknowledgement after each byte is asserted only by PCF8562s that are addressed via address lines A0, A1 and A2.
After the last display byte, the I2C-bus master asserts a STOP condition (P). Alternately a START may be asserted to
RESTART an I2C-bus access.
7.8
Command decoder
The command decoder identifies command bytes that arrive on the I2C-bus. All available commands carry a continuation
bit C in their most significant bit position as shown in Fig.17. When this bit is set, it indicates that the next byte of the
transfer to arrive will also represent a command. If this bit is reset, it indicates that the command byte is the last in the
transfer. Further bytes will be regarded as display data.
The five commands available to the PCF8562 are defined in Table 4.
SDA
SCL
change
of data
allowed
data line
stable;
data valid
Fig.12 Bit transfer.
November 22, 2004
20
MBA607
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
handbook, full pagewidth
SDA
SDA
SCL
SCL
S
P
START condition
STOP condition
MBC622
Fig.13 Definition of START and STOP conditions.
MASTER
TRANSMITTER/
RECEIVER
SLAVE
TRANSMITTER/
RECEIVER
SLAVE
RECEIVER
MASTER
TRANSMITTER/
RECEIVER
MASTER
TRANSMITTER
SDA
SCL
MGA807
Fig.14 System configuration.
dbook, full pagewidth
DATA OUTPUT
BY TRANSMITTER
not acknowledge
DATA OUTPUT
BY RECEIVER
acknowledge
SCL FROM
MASTER
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
MBC602
Fig.15 Acknowledgement on the I2C-bus.
November 22, 2004
21
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
handbook, full pagewidth
acknowledge
R/W
acknowledge
slave address
S
S
0 1 1 1 0 0 A 0 A C
0
COMMAND
A
n ≥ 1 byte(s)
1 byte
DISPLAY DATA
A
P
n ≥ 0 byte(s)
update data pointers
MDB078v2
Fig.16 I2C-bus protocol.
MSB
C
LSB
REST OF OPCODE
C = 0 = last command.
C = 1 = commands continue.
MSA833
Fig.17 Format of command byte.
November 22, 2004
22
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
Table 4
PCF8562
Definition of PCF8562 commands
COMMAND
MODE SET
OPCODE
C
1
0
(1)
E
OPTIONS
B
M1
M0
DESCRIPTION
Table 5
Defines LCD drive mode.
Table 6
Defines LCD bias configuration.
Table 7
Defines display status; the possibility to
disable the display allows implementation
of blinking under external control.
LOAD DATA
POINTER
C
0
P5
P4
P3
P2
P1
P0
Table 8
Six bits of immediate data, bits P5 to P0,
are transferred to the data pointer to
define one of 32 display RAM addresses.
DEVICE
SELECT
C
1
1
0
0
A2
A1
A0
Table 9
Three bits of immediate data, bits A0 to
A2, are transferred to the subaddress
counter to define one of eight hardware
subaddresses.
BANK
SELECT
C
1
1
1
1
0
I
O
Table 10
Defines input bank selection (storage of
arriving display data).
Table 11
Defines output bank selection (retrieval of
LCD display data); the BANK SELECT
command has no effect in 1 : 3 and 1 : 4
multiplex drive modes.
BLINK
C
1
1
1
0
A
BF1 BF0 Table 12
Table 13
Note
1. Not used.
November 22, 2004
23
Defines the blink frequency.
Selects the blink mode; normal operation
with frequency set by BF1, BF0 or blinking
by alternating display RAM banks;
alternating RAM bank blinking does not
apply in 1 : 3 and 1 : 4 multiplex drive
modes.
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
Table 5
PCF8562
Mode set option 1
LCD DRIVE MODE
DRIVE
MODE
BITS
BACKPLANE
M1
M0
Static
BP0
0
1
1:2
BP0, BP1
1
0
1:3
BP0, BP1, BP2
1
1
1:4
BP0, BP1, BP2, BP3
0
0
Table 6
Mode set option 2
LCD BIAS
BIT B
1⁄3bias
0
1⁄2bias
1
Table 7
Mode set option 3
DISPLAY STATUS
BIT E
Disabled (blank)
0
Enabled
1
Table 8
Load data pointer option 1
DESCRIPTION
BITS
6 bit binary value of 0 to 39 P5 P4 P3 P2 P1 P0
Table 9
Device select option 1
DESCRIPTION
BITS
3 bit binary value of 0 to 7
A2
A1
A0
Table 10 Bank select option 1 (input)
MODE
BIT I
STATIC
1:2
RAM bit 0
RAM bits 0 and 1
0
RAM bit 2
RAM bits 2 and 3
1
Table 11 Bank select option 2 (output)
MODE
BIT O
STATIC
1:2
RAM bit 0
RAM bits 0 and 1
0
RAM bit 2
RAM bits 2 and 3
1
November 22, 2004
24
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
Table 12 Blink option 1
BITS
BLINK FREQUENCY
BF1
BF0
Off
0
0
2 Hz
0
1
1 Hz
1
0
0.5 Hz
1
1
Table 13 Blink option 2
BLINK MODE
BIT A
Normal blinking
0
Alternate RAM bank blinking
1
Note
1. Normal blinking is assumed when LCD multiplex drive modes 1 : 3 or 1 : 4 are selected.
7.9
Display controller
The display controller executes the commands identified by the command decoder. It contains the device’s status
registers and co-ordinates their effects. The display controller is also responsible for loading display data into the display
RAM in the correct filling order.
7.10
Multiple chip operation
For large display configurations please refer to the PCF8576D device.
Please refer to PCF8576D if you need to drive more segments (>128 elements).
November 22, 2004
25
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
Table 14 SYNC contact resistance
MAXIMUM CONTACT
RESISTANCE
NUMBER OF DEVICES
2
6 000 Ω
3 to 5
2 200 Ω
6 to 10
1 200 Ω
10 to 16
700 Ω
The contact resistance between the SYNC input/output on each cascaded device must be controlled. If the resistance is
too high, the device will not be able to synchronize properly; this is particularly applicable to chip-on-glass applications.
The maximum SYNC contact resistance allowed for the number of devices in cascade is given in Table 14.
8 LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134).
SYMBOL
PARAMETER
MIN.
MAX.
UNIT
VDD
supply voltage
−0.5
+6.5
V
VLCD
LCD supply voltage
VSS − 0.5
+7.5
V
Vi1
input voltage CLK, SYNC, SA0, OSC, A0 to A2
VSS − 0.5
VDD + 0.5
V
Vi2
input voltage SCL and SDA
VSS − 0.5
+6.5
V
VO
output voltage S0 to S39, BP0 to BP3
VSS − 0.5
VDD + 0.5
V
II
DC input current
−10
+10
mA
IO
DC output current
−10
+10
mA
IDD
VDD current
−50
+50
mA
ISS
VSS current
−50
+50
mA
ILCD
VLCD current
−50
+50
mA
Ptot
total power dissipation
−
400
mW
PO
power dissipation per output
−
100
mW
Tstg
storage temperature
−65
+150
°C
9
HANDLING
Inputs and outputs are protected against electrostatic discharge in normal handling. However, to be totally safe, it is
desirable to take normal precautions appropriate to handling MOS devices (see “Handling MOS Devices” ).
November 22, 2004
26
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
10 DC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Supplies
VDD
supply voltage
1.8
−
5.5
V
VLCD
LCD supply voltage
note 1
2.5
−
6.5
V
IDD
supply current
note 2; fCLK = 1 536 Hz
−
8
20
µA
ILCD
LCD supply current
note 2; fCLK = 1 536 Hz
−
24
60
µA
Logic
VIL
LOW-level input voltage
CLK, SYNC, OSC, A0 to A2 and SA0
VSS
−
0.3VDD
V
VIH
HIGH-level input voltage
CLK, SYNC, OSC, A0 to A2 and SA0
0.7VDD
−
VDD
V
VIL2
LOW-level input voltage SCL, SDA
VSS
−
0.3VDD
V
VIH2
HIGH-level input voltage SCL, SDA
0.7VDD
−
VDD
V
IOL1
LOW-level output current CLK, SYNC VOL = 0.4 V; VDD = 5 V
1
−
−
mA
IOH1
HIGH-level output current CLK
VOH = 4.6 V; VDD = 5 V
−1
−
−
mA
IOL2
LOW-level output current SDA
VOL = 0.4 V; VDD = 5 V
3
−
−
mA
IL1
leakage current
CLK, SCL, SDA, A0 to A2 and SA0
VI = VDD or VSS
−1
−
+1
µA
IL2
leakage current OSC
VI = VDD
−1
−
+1
µA
VPOR
power-on reset voltage level
1.0
1.3
1.6
V
CI
input capacitance
−
−
7
pF
note 3
note 4
LCD outputs
VBP
DC voltage tolerance BP0 to BP3
−100
−
+100
mV
VS
DC voltage tolerance S0 to S31
−100
−
+100
mV
RBP
output resistance BP0 to BP3
note 5; VLCD = 5 V
−
1.5
kΩ
RS
output resistance S0 to S31
note 5; VLCD = 5 V
−
6.0
kΩ
Notes
1. VLCD > 3 V for 1⁄3bias.
2. LCD outputs are open-circuit; inputs at VSS or VDD; external clock with 50% duty factor; I2C-bus inactive.
3. When tested, I2C pins SCL and SDA have no diode to VDD and may be driven according to the Vi2 limiting values
given in Chapter 8. Also see Fig.21.
4. Periodically sampled, not 100% tested.
5. Outputs measured one at a time.
November 22, 2004
27
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
11 AC CHARACTERISTICS
VDD = 1.8 to 5.5 V; VSS = 0 V; VLCD = 2.5 to 6.5 V; Tamb = −40 to +85 °C; unless otherwise specified.
SYMBOL
PARAMETER
fCLK
oscillator frequency
tCLKH
CONDITIONS
MIN.
TYP.
MAX.
UNIT
960
1890
2640
Hz
input CLK HIGH time
60
−
−
µs
tCLKL
input CLK LOW time
60
−
−
µs
tPD(SYNC)
SYNC propagation delay
−
30
−
ns
tSYNCL
SYNC LOW time
1
−
−
µs
tPD(LCD)
driver delays with test loads
−
−
30
µs
Timing characteristics:
I2C-bus;
note 1
VLCD = 5 V; note 2
note 3
fSCL
SCL clock frequency
−
−
400
kHz
tBUF
bus free time between a STOP and START
1.3
−
−
µs
tHD;STA
START condition hold time
0.6
−
−
µs
tSU;STA
set-up time for a repeated START condition
0.6
−
−
µs
tLOW
SCL LOW time
1.3
−
−
µs
tHIGH
SCL HIGH time
0.6
−
−
µs
tr
SCL and SDA rise time
−
−
0.3
µs
tf
SCL and SDA fall time
−
−
0.3
µs
CB
capacitive bus line load
−
−
400
pF
tSU;DAT
data set-up time
100
−
−
ns
tHD;DAT
data hold time
0
−
−
ns
tSU;STO
set-up time for STOP condition
0.6
−
−
µs
tSW
tolerable spike width on bus
−
−
50
ns
Notes
1. Typical output duty factor: 50% measured at the CLK output pin.
2. Not tested in production.
3. All timing values are valid within the operating supply voltage and ambient temperature range and are referenced to
VIL and VIH with an input voltage swing of VSS to VDD.
handbook, full pagewidth
6.8 Ω
SYNC
(2%)
CLK
3.3 k Ω
(2%)
BP0to BP3, and
S0to S31
VDD
0.5VDD
SDA,
SCL
(2%)
VDD
1 nF
VSS
MCE439v2
Fig.18 Test loads.
November 22, 2004
1.5 k Ω
28
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
1/fCLK
handbook, full pagewidth
tCLKH
tCLKL
0.7VDD
0.3VDD
CLK
0.7VDD
SYNC
0.3VDD
tPD(SYNC)
tPD(SYNC)
tSYNCL
0.5 V
BP0 to BP3,
and S0 to S31
(VDD = 5 V)
0.5 V
tPD(LCD)
MCE424v2
Fig.19 Driver timing waveforms.
handbook, full pagewidth
SDA
t BUF
tf
t LOW
SCL
t HD;STA
t HD;DAT
tr
t HIGH
t SU;DAT
SDA
MGA728
t SU;STA
Fig.20 I2C-bus timing waveforms.
November 22, 2004
29
t SU;STO
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
12 DEVICE PROTECTION
handbook, full pagewidth
VDD
VDD
VSS
VSS
SA0
VDD
CLK
SCL
VSS
VDD
VSS
OSC
VSS
VDD
SDA
SYNC
VSS
VSS
VDD
A0, A1 A2
VSS
VLCD
BP0, BP1,
BP2, BP3
VSS
VLCD
VLCD
S0 to S31
VSS
VSS
MDB076
Fig.21 Device protection diagram.
November 22, 2004
30
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
13 PACKAGE OUTLINES
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
E
D
A
X
c
HE
y
v M A
Z
48
25
Q
A2
(A 3)
A1
pin 1 index
A
θ
Lp
L
1
detail X
24
w M
bp
e
2.5
0
5 mm
scale
DIMENSIONS (mm are the original dimensions).
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (2)
e
HE
L
Lp
Q
v
w
y
Z
θ
mm
1.2
0.15
0.05
1.05
0.85
0.25
0.28
0.17
0.2
0.1
12.6
12.4
6.2
6.0
0.5
8.3
7.9
1
0.8
0.4
0.50
0.35
0.25
0.08
0.1
0.8
0.4
8
0o
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
OUTLINE
VERSION
SOT362-1
November 22, 2004
REFERENCES
IEC
JEDEC
EIAJ
EUROPEAN
PROJECTION
ISSUE DATE
95-02-10
99-12-27
MO-153
31
o
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
14 SOLDERING
14.1
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our
“Data Handbook IC26; Integrated Circuit Packages” (document order number 9398 652 90011).
There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain
surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended.
14.2
Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the
printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by
legislation and environmental forces the worldwide use of lead-free solder pastes is increasing.
Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
Typical reflow peak temperatures range from 215 to 270 °C depending on solder paste material. The top-surface
temperature of the packages should preferably be kept:
• below 220 °C (SnPb process) or below 245 °C (Pb-free process)
– for all the BGA packages
– for packages with a thickness ≥Š 2.5 mm
– for packages with a thickness < 2.5 mm and a volume ≥ 350 mm3 so called thick/large packages.
• below 235 °C (SnPb process) or below 260 °C (Pb-free process) for packages with a thickness < 2.5 mm and a volume
< 350 mm3 so called small/thin packages.
Moisture sensitivity precautions, as indicated on packing, must be respected at all times.
14.3
Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with
a high component density, as solder bridging and non-wetting can present major problems.
To overcome these problems the double-wave soldering method was specifically developed.
If wave soldering is used the following conditions must be observed for optimal results:
• Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth
laminar wave.
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction
of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit
board.
The footprint must incorporate solder thieves at the downstream end.
• For packages with leads on four sides, the footprint must be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners.
During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured.
Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 °C or 265 °C, depending on solder material
applied, SnPb or Pb-free respectively.
A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.
November 22, 2004
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Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
14.4
PCF8562
Manual soldering
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron
applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 °C.
When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
14.5
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE(1)
WAVE
REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA
not suitable
suitable
DHVQFN, HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP,
HTSSOP, HVQFN, HVSON, SMS
not suitable(3)
suitable
PLCC(4), SO, SOJ
suitable
suitable
LQFP, QFP, TQFP
not recommended(4)(5)
suitable
SSOP, TSSOP, VSO, VSSOP
not recommended(6)
suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP, TSSOP, VSO and VSSOP packages with a pitch (e) equal to or larger than
0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
November 22, 2004
33
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
15 DATA SHEET STATUS
LEVEL
DATA SHEET
STATUS(1)
PRODUCT
STATUS(2)(3)
Development
DEFINITION
I
Objective data
II
Preliminary data Qualification
This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III
Product data
This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
Production
This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
16 DEFINITIONS
Short-form specification ⎯ The data in a short-form specification is extracted from a full data sheet with the same type
number and title. For detailed information see the relevant data sheet or data handbook.
Limiting values definition ⎯ Limiting values given are in accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are
stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics
sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information ⎯ Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified
use without further testing or modification.
November 22, 2004
34
Philips Semiconductors
Preliminary specification
Universal LCD driver
for low multiplex rates
PCF8562
17 DISCLAIMERS
Life support applications ⎯ These products are not designed for use in life support appliances, devices, or systems
where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors
customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify
Philips Semiconductors for any damages resulting from such application.
Right to make changes ⎯ Philips Semiconductors reserves the right to make changes in the products - including
circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance.
When the product is in full production (status ‘Production’), relevant changes will be communicated via a Customer
Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use
of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products,
and makes no representations or warranties that these products are free from patent, copyright, or mask work right
infringement, unless otherwise specified.
Bare die ⎯ All die are tested and are guaranteed to comply with all data sheet limits up to the point of wafer sawing for
a period of ninety (90) days from the date of Philips' delivery. If there are data sheet limits not guaranteed, these will be
separately indicated in the data sheet. There are no post packing tests performed on individual die or wafer. Philips
Semiconductors has no control of third party procedures in the sawing, handling, packing or assembly of the die.
Accordingly, Philips Semiconductors assumes no liability for device functionality or performance of the die or systems
after third party sawing, handling, packing or assembly of the die. It is the responsibility of the customer to test and qualify
their application in which the die is used.
18 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
November 22, 2004
35
Philips Semiconductors – a worldwide company
Contact information
For additional information please visit http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
For sales offices addresses send e-mail to: [email protected].
© Koninklijke Philips Electronics N.V. 2003
SCA75
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
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