2.5A Regulator with Integrated High-Side MOSFET for Synchronous Buck or Boost Buck Converter ISL85402 Features The ISL85402 is a synchronous buck controller with a 125mΩ high-side MOSFET and low-side driver integrated. The ISL85402 supports a wide input range of 3V to 36V in buck mode. It supports 2.5A continuous load under conditions of 5V VOUT, VIN range of 8V to 36V, 500kHz and +105°C ambient temperature with still air. For any specific application, the actual maximum output current depends upon the die temperature not exceeding +125°C with the power dissipated in the IC, which is related to input voltage, output voltage, duty cycle, switching frequency, board layout and ambient temperature, etc. Refer to “Output Current” on page 14 for more details. • Buck Mode: Input Voltage Range 3V to 36V (Refer to “Input Voltage” on page 13 for more details) The ISL85402 has a flexible selection of operation modes of forced PWM mode and PFM mode. In PFM mode, the quiescent input current is as low as 180µA (AUXVCC connected to VOUT). The load boundary between PFM and PWM can be programmed to cover wide applications. The low-side driver can be either used to drive an external low-side MOSFET for a synchronous buck, or left unused for a standard non-synchronous buck. The low-side driver can also be used to drive a boost converter as a pre-regulator followed by a buck controlled by the same IC, which greatly expands the operating input voltage range down to 2.5V or lower (Refer to “Typical Application Schematic III - Boost Buck Converter” on page 5). The ISL85402 offers the most robust current protections. It uses peak current mode control with cycle-by-cycle current limiting. It is implemented with frequency foldback under current limit condition; besides that, the hiccup overcurrent mode is also implemented to guarantee reliable operations under harsh short conditions. The ISL85402 has comprehensive protections against various faults including overvoltage and over-temperature protections, etc. • Boost Mode Expands Operating Input Voltage Lower Than 2.5V (Refer to “Input Voltage” on page 13 for more details) • Selectable Forced PWM Mode or PFM Mode • 300µA IC Quiescent Current (PFM, No Load); 180µA Input Quiescent Current (PFM, No Load, VOUT Connected to AUXVCC) • Less than 3µA Shut Down Input Current (IC Disabled) • Operational Topologies - Synchronous Buck - Non-Synchronous Buck - Two-Stage Boost Buck • Programmable Frequency from 200kHz to 2.2MHz and Frequency Synchronization Capability • ±1% Tight Voltage Regulation Accuracy • Reliable Overcurrent Protection - Temperature Compensated Current Sense - Cycle-by-Cycle Current Limiting with Frequency Foldback - Hiccup Mode for Worst Case Short Condition • 20 Ld 4x4 QFN Package • Pb-Free (RoHS Compliant) Applications • General Purpose • 24V Bus Power • Battery Power • Point of Load • Embedded Processor and I/O Supplies 100 95 VIN SYNC AUXVCC VIN BOOT ISL85402 PHASE ILIMIT LGATE SS EXT_BOOST FS SGND VOUT EFFICIENCY (%) PGOOD EN MODE VCC 6V VIN 90 85 80 36V VIN 75 24V VIN 70 65 PGND 60 FB 55 COMP 12V VIN 50 0.1m 1m 10m 100m 1.0 2.5 LOAD CURRENT (A) FIGURE 1. TYPICAL APPLICATION April 25, 2013 FN7640.1 1 FIGURE 2. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE, VOUT 5V, TA = +25°C CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL85402 Pin Configuration AUXVCC VCC SGND VIN VIN ISL85402 (20 LD QFN) TOP VIEW 20 19 18 17 16 EN 1 15 BOOT 14 PGND 13 LGATE FS 2 SS 3 FB 4 12 SYNC COMP 5 11 EXT_BOOST 7 8 9 MODE PGOOD PHASE 10 PHASE 6 ILIMIT 21Pad Thermal 21 PAD Functional Pin Descriptions PIN NAME PIN # DESCRIPTION EN 1 The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW. Range: 0V to 5.5V. FS 2 Connecting this pin to VCC, or GND, or leaving it open will force the IC to have 500kHz switching frequency. The oscillator switching frequency can also be programmed by adjusting the resistor from this pin to GND. SS 3 Connect a capacitor from this pin to ground. This capacitor, along with an internal 5µA current source, sets the soft-start interval of the converter. Also, this pin can be used to track a ramp on this pin. FB 4 This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from VOUT to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin is also monitored for overvoltage events. COMP 5 Output of the voltage feedback error amplifier. ILIMIT 6 Programmable current limit pin. With this pin connected to the VCC pin, or to GND, or left open, the current limiting threshold is set to default of 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND. MODE 7 Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and PWM can also be programmed with a resistor at this pin to ground. Check for more details in the “PFM Mode Operation” on page 13. PGOOD 8 PGOOD is an open drain output that will be pulled low immediately under the events when the output is out of regulation (OV or UV) or when the EN pin is pulled low. PGOOD is equipped with a fixed delay of 1000 cycles upon output power-up (VO > 90%). PHASE 9, 10 These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of the high-side N-channel MOSFET. 11 This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the controller will detect the voltage on this pin; if voltage on this pin is below 200mV, the controller is set in synchronous/non-synchronous buck mode and will latch in this state unless VCC is below POR falling threshold; if the voltage on this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode, the low-side driver output PWM with same duty cycle with upper-side driver to drive the boost switch. In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled. In boost mode operation, PFM is disabled when boost PWM is enabled. Check the “Boost Converter Operation” on page 14 for more details. EXT_BOOST 2 FN7640.1 April 25, 2013 ISL85402 Functional Pin Descriptions PIN NAME PIN # (Continued) DESCRIPTION SYNC 12 This pin can be used to synchronize two or more ISL85402 controllers. Multiple ISL85402s can be synchronized with their SYNC pins connected together. 180 degree phase shift is automatically generated between the master and slave ICs. The internal oscillator can also lock to an external frequency source applied on this pin with square pulse waveform (with frequency 10% higher than the IC’s local frequency, and pulse width higher than 150ns). Range: 0V to 5.5V. This pin should be left floating if not used. LGATE 13 In synchronous buck mode, this pin is used to drive the lower side MOSFET to improve efficiency. In non-synchronous buck when a diode is used as the bottom side power device, this pin should be connected to VCC before VCC startup to have low-side driver (LGATE) disabled. In boost mode, it can be used to drive the boost power MOSFET. The boost control PWM is same with the buck control PWM. PGND 14 This pin is used as the ground connection of the power flow including driver. Connect it to large ground plane. BOOT 15 This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the internal N-channel MOSFET. The boot charge circuitries are integrated inside of the IC. No external boot diode is needed. A 1µF ceramic capacitor is recommended to be used between BOOT and PHASE pin. 16, 17 Connect the input rail to these pins that are connected to the drain of the integrated high-side MOSFET as well as the source for the internal linear regulator that provides the bias of the IC. Range: 3V to 36V. With the part switching, the operating input voltage applied to the VIN pins must be under 36V. This recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to switching while not exceeding “Absolute Maximum Ratings” on page 6. VIN SGND 18 This pin provides the return path for the control and monitor portions of the IC. Connect it to a quiet ground plane. VCC 19 This pin is the output of the internal linear regulator that supplies the bias for the IC including the driver. A minimum 4.7µF decoupling ceramic capacitor is recommended between VCC to ground. 20 This pin is the input of the auxiliary internal linear regulator, which can be supplied by the regulator output after power-up. With such configuration, the power dissipation inside of the IC is reduced. The input range for this LDO is 3V to 20V. In boost mode operation, this pin works as boost output overvoltage detection pin. It detects the boost output through a resistor divider. When voltage on this pin is above 0.8V, the boost PWM is disabled; and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled. Range: 0V to 20V. 21 Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to PCB ground copper plane with area as large as possible to effectively reduce the thermal impedance. AUXVCC PAD Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL85402IRZ 85 402IRZ ISL85402EVAL1Z Evaluation Board TEMP. RANGE (°C) -40 to +105 PACKAGE (PB-Free) 20 Ld 4x4 QFN PKG. DWG. # L20.4x4C NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL85402. For more information on MSL please see techbrief TB363. 3 FN7640.1 April 25, 2013 Block Diagram AUXVCC VCC PGOOD VIN (x2) VIN CURRENT MONITOR AUXILARY LDO BIAS LDO 4 ILIMIT POWER-ON RESET SGND VCC BOOT OCP, OVP, OTP PFM LOGIC BOOST MODE CONTROL EN EXT_BOOST MODE PFM/FPWM VOLTAGE MONITOR SYNC FS SLOPE COMPENSATION LGATE OSCILLATOR + + SOFT-START LOGIC VCC 0.8V REFERENCE 5 µA EA SS BOOT REFRESH FB COMPARATOR COMP PGND ISL85402 PHASE (x2) GATE DRIVE FN7640.1 April 25, 2013 ISL85402 Typical Application Schematic I PGOOD EN MODE SYNC AUXVCC VCC PGOOD EN MODE VIN VIN SYNC AUXVCC BOOT ISL85402 VIN V OUT PHASE BOOT VCC ILIMIT VIN ISL85402 V OUT PHASE ILIMIT LGATE SS LGATE SS PGND PGND EXT_BOOST FS SGND EXT_BOOST FS SGND FB COMP FB COMP (b) NON-SYNCHRONOUS BUCK (a) SYNCHRONOUS BUCK Typical Application Schematic II - VCC Switch-Over to VOUT PGOOD EN MODE SYNC AUXVCC VCC PGOOD EN MODE VIN VIN SYNC AUXVCC BOOT ISL85402 VCC VOUT PHASE EXT_BOOST FS SGND VIN BOOT ISL85402 PHASE V OUT ILIMIT ILIMIT SS VIN LGATE LGATE SS PGND PGND EXT_BOOST FS SGND FB COMP (a) SYNCHRONOUS BUCK FB COMP (b) NON-SYNCHRONOUS BUCK Typical Application Schematic III - Boost Buck Converter Battery + + R1 R2 PGOOD EN MODE EXT_BOOST R3 LGATE AUXVCC SYNC R4 VIN VCC ISL85402 ILIMIT SS FS SGND 5 BOOT PHASE V OUT PGND COMP FB FN7640.1 April 25, 2013 ISL85402 Absolute Maximum Ratings Thermal Information VIN, PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +44V VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +6.0V AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +22V Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +50.0V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . . . . . . . . . +6.0V All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V ESD Rating Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . 2000V Machine Model (Tested per JESD22-A115C) . . . . . . . . . . . . . . . . . . 200V Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1000V Latchup Rating (Tested per JESD78B; Class II, Level A) . . . . . . . . . 100mA Thermal Resistance θJA (°C/W) θJC (°C/W) ISL85402 QFN 4x4 Package (Notes 4, 5). . . . . . 40 3.5 Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Supply Voltage on VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 36V AUXVCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +20V Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +105°C Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS VIN PIN SUPPLY VIN Pin Voltage Range Operating Supply Current IQ Shut Down Supply Current IIN_SD VIN Pin 3.05 36 V VIN Pin connected to VCC 3.05 5.5 V MODE = VCC/FLOATING (PFM), no load at the output 300 µA MODE = GND (Forced PWM), VIN = 12V, IC Operating, Not Including Driving Current 1.2 mA EN connected to GND, VIN = 12V 1.8 3 µA 4.5 4.8 V VIN = 4.2V, IVCC = 35mA 0.3 0.5 V VIN = 3V, IVCC = 25mA 0.25 0.3 V INTERNAL MAIN LINEAR REGULATOR MAIN LDO VCC Voltage VCC MAIN LDO Dropout Voltage VDROPOUT_MAIN VIN > 5V 4.2 VCC Current Limit of MAIN LDO 60 mA INTERNAL AUXILIARY LINEAR REGULATOR AUXVCC Input Voltage Range VAUXVCC AUX LDO VCC Voltage VCC LDO Dropout Voltage VDROPOUT_AUX 3 20 V 4.5 4.8 V VAUXVCC = 4.2V, IVCC = 35mA 0.3 0.5 V VAUXVCC = 3V, IVCC = 25mA 0.25 0.3 V VAUXVCC > 5V 4.2 Current Limit of AUX LDO 60 AUX LDO Switch-over Rising Threshold VAUXVCC_RISE AUXVCC voltage rise; Switch to Auxiliary LDO AUX LDO Switch-over Falling Threshold Voltage VAUXVCC_FALL AUXVCC voltage fall; Switch back to main BIAS LDO AUX LDO Switch-over Hysteresis VAUXVCC_HYS AUXVCC Switch-over Hysteresis 6 mA 3 3.1 3.2 V 2.73 2.87 2.97 V 0.2 V FN7640.1 April 25, 2013 ISL85402 Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) TYP MAX (Note 6) UNITS 2.82 2.9 3.05 V 2.8 V POWER-ON RESET Rising VCC POR Threshold VPORH_RISE Falling VCC POR Threshold VPORL_FALL 2.6 VCC POR Hysteresis VPORL_HYS 0.3 V ENABLE Required Enable On Voltage VENH Required Enable Off Voltage VENL EN Pull-up Current IEN_PULLUP 2 V 0.8 V EN Left Floating, VIN = 24V 0.8 µA EN Left Floating, VIN = 12V 0.5 µA EN Left Floating, VIN = 5V 0.25 µA OSCILLATOR PWM Frequency FOSC RFS = 665kΩ 160 200 240 kHz RFS = 51.1kΩ 1950 2200 2450 kHz FS Pin Connected to VCC or Floating or GND 450 500 550 kHz MIN ON Time tMIN_ON 130 225 ns MIN OFF Time tMIN_OFF 210 325 ns Input High Threshold VIH 2 V Input Low Threshold VIL 0.5 V SYNCHRONIZATION Input Minimum Pulse Width 25 ns Input Impedance 100 kΩ Input Minimum Frequency Divided by Free Running Frequency 1.1 Input Maximum Frequency Divided by Free Running Frequency 1.6 Output Pulse Width CSYNC = 100pF 100 ns RLOAD = 1kΩ VCC0.25 V VOL GND V VREF 0.8 V Output Pulse High VOH Output Pulse Low REFERENCE VOLTAGE Reference Voltage System Accuracy -1.0 FB Pin Source Current +1.0 5 % nA Soft-start Soft-Start Current ISS 3 5 7 µA ERROR AMPLIFIER Unity Gain-Bandwidth CLOAD = 50pF 10 MHz DC Gain CLOAD = 50pF 88 dB 3.6 V Maximum Output Voltage 7 FN7640.1 April 25, 2013 ISL85402 Electrical Specifications Refer to “Block Diagram” on page 4 and “Typical Application Schematics” on page 5. Operating Conditions Unless Otherwise Noted: VIN = 12V, or VCC = 4.5V ±10%, TA = -40°C to +105°C. Typicals are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +105°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 6) Minimum Output Voltage Slew Rate SR CLOAD = 50pF TYP MAX (Note 6) UNITS 0.5 V 5 V/µs 700 mA PFM MODE CONTROL Default PFM Current Threshold MODE = VCC or Floating INTERNAL HIGH-SIDE MOSFET Upper MOSFET rDS(ON) rDS(ON)_UP 125 180 mΩ LOW-SIDE MOSFET GATE DRIVER LGate Source Resistance 100mA Source Current 3.5 Ω LGATE Sink Resistance 100mA Sink Current 3.3 Ω BOOST CONVERTER CONTROL EXT_BOOST Boost_Off Threshold Voltage EXT_BOOST Hysteresis Sink Current IEXT_BOOST_HYS AUXVCC Boost Turn-Off Threshold Voltage AUXVCC Hysteresis Sink Current IAUXVCC_HYS 0.74 0.8 0.86 V 2.4 3.2 3.8 µA 0.74 0.8 0.86 V 2.4 3.2 3.8 µA 104 110 116 % 84 90 96 % POWER-GOOD MONITOR Overvoltage Rising Trip Point VFB/VREF Percentage of Reference Point Overvoltage Rising Hysteresis VFB/VOVTRIP Percentage Below OV Trip Point Undervoltage Falling Trip Point VFB/VREF Percentage of Reference Point Undervoltage Falling Hysteresis VFB/VUVTRIP Percentage Above UV Trip Point PGOOD Rising Delay tPGOOD_DELAY PGOOD Leakage Current PGOOD Low Voltage 3 % 3 % fOSC = 500kHz 2 ms PGOOD HIGH, VPGOOD = 4.5V 10 nA 0.10 V VPGOOD PGOOD LOW, IPGOOD = 0.2mA Default Cycle-by-Cycle Current Limit Threshold IOC_1 ILIMIT = GND or VCC or Floating Hiccup Current Limit Threshold IOC_2 Hiccup, IOC_2/IOC_1 115 % OV Latching-off Trip Point Percentage of Reference Point LG = UG = LATCH LOW 120 % OV Non-Latching-off Trip Point Percentage of Reference Point LG = UG = LOW 110 % OV Non-Latching-off Release Point Percentage of Reference Point 102.5 % Over-Temperature Trip Point 155 °C Over-Temperature Recovery Threshold 140 °C OVERCURRENT PROTECTION 3 3.6 4.2 A OVERVOLTAGE PROTECTION OVER-TEMPERATURE PROTECTION NOTE: 6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 8 FN7640.1 April 25, 2013 ISL85402 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.0 100 95 24V VIN 12V VIN 6V VIN 90 36V VIN EFFICIENCY (%) EFFICIENCY (%) Performance Curves 6V VIN 12V VIN 85 80 36V VIN 75 24V VIN 70 65 60 55 0.5 1.0 1.5 2.0 50 0.1m 2.5 1m FIGURE 3. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM MODE, 500kHz, VOUT 5V, TA = +25°C 4.970 4.968 4.968 4.966 4.966 1.0 2.5 4.964 IO = 0A 4.962 VOUT (V) VOUT (V) 4.964 IO = 2A 4.960 4.958 4.956 IO = 1A 4.962 4.952 4.952 10 15 20 25 INPUT VOLTAGE (V) 30 12V VIN 4.950 0.0 36 0.5 1.0 1.5 LOAD CURRENT (A) 2.0 2.5 FIGURE 6. LOAD REGULATION, VOUT 5V, TA = +25°C 100 95 90 12V VIN 85 24V VIN EFFICIENCY (%) 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 0.0 36V VIN 4.956 4.954 5 6V VIN 4.958 4.954 0 24V VIN 4.960 FIGURE 5. LINE REGULATION, VOUT 5V, TA = +25°C EFFICIENCY (%) 100m FIGURE 4. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE, VOUT 5V, TA = +25°C 4.970 4.950 10m LOAD CURRENT (A) LOAD CURRENT (A) 36V VIN 6V VIN 6V VIN 12V VIN 80 36V VIN 75 24V VIN 70 65 60 55 50 45 0.5 1.0 1.5 2.0 2.5 LOAD CURRENT (A) FIGURE 7. EFFICIENCY, SYNCHRONOUS BUCK, FORCED PWM MODE, 500kHz, VOUT 3.3V, TA = +25°C 9 40 0.1m 1m 10m 100m LOAD CURRENT (A) 1.0 2.5 FIGURE 8. EFFICIENCY, SYNCHRONOUS BUCK, PFM MODE, VOUT 3.3V, TA = +25°C FN7640.1 April 25, 2013 ISL85402 Performance Curves (Continued) 200 85 80 180 INPUT CURRENT (µA) 160 IC DIE TEMPERATURE (°C) VIN = 12V 140 120 VIN = 24V 100 80 60 40 20 75 70 VO = 20V 65 60 55 50 45 VO = 12V VO = 5V 40 35 30 0 -50 -25 0 25 50 75 100 125 25 0 5 10 15 AMBIENT TEMPERATURE (°C) FIGURE 9. INPUT QUIESCENT CURRENT UNDER NO LOAD, PFM MODE, VOUT = 5V 20 VIN (V) 25 30 35 40 FIGURE 10. IC DIE TEMPERATURE UNDER +25°C AMBIENT TEMPERATURE, STILL AIR, 500kHz, IO = 2A 85 IC DIE TEMPERATURE (°C) 80 VO = 20V 75 VOUT 2V/DIV 70 65 VO = 12V 60 VO = 5V 55 50 PHASE 20V/DIV 45 40 35 30 25 0 5 10 15 20 25 30 35 VIN (V) FIGURE 11. IC DIE TEMPERATURE UNDER +25°C AMBIENT TEMPERATURE, STILL AIR, 500kHz, IO = 2.5A 40 2ms/DIV FIGURE 12. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A, ENABLE ON VOUT 2V/DIV VOUT 2V/DIV PHASE 20V/DIV PHASE 20V/DIV 2ms/DIV FIGURE 13. SYNCHRONOUS BUCK MODE, VIN 36V, IO 2A, ENABLE OFF 10 2ms/DIV FIGURE 14. VIN 36V, PREBIASED START-UP FN7640.1 April 25, 2013 ISL85402 Performance Curves (Continued) VOUT 20mV/DIV (5V OFFSET) VOUT 100mV/DIV (5V OFFSET) IOUT 1A/DIV PHASE 20V/DIV PHASE 20V/DIV 5µs/DIV FIGURE 15. SYNCHRONOUS BUCK WITH FORCE PWM MODE, VIN 36V, IO 2A 1ms/DIV FIGURE 16. VIN 24V, 0 TO 2A STEP LOAD, FORCE PWM MODE VOUT 200mV/DIV (5V OFFSET) VOUT 70mV/DIV (5V OFFSET) VOUT 1V/DIV LGATE 5V/DIV LGATE 5V/DIV IOUT 1A/DIV PHASE 20V/DIV PHASE 20V/DIV 100µs/DIV 1ms/DIV FIGURE 17. VIN 24V, 80mA LOAD, PFM MODE FIGURE 18. VIN 24V, 0 TO 2A STEP LOAD, PFM MODE VOUT 10mV/DIV (5V OFFSET) VOUT 10mV/DIV (5V OFFSET) PHASE 5V/DIV PHASE 10V/DIV 20µs/DIV FIGURE 19. NON-SYNCHRONOUS BUCK, FORCE PWM MODE, VIN 12V, NO LOAD 11 5µs/DIV FIGURE 20. NON-SYNCHRONOUS BUCK, FORCE PWM MODE, VIN 12V, 2A FN7640.1 April 25, 2013 ISL85402 Performance Curves (Continued) VOUT BUCK 100mV/DIV (5V OFFSET) VOUT BUCK 100mV/DIV (5V OFFSET) VIN_BOOST_INPUT 5V/DIV VIN_BOOST_INPUT 5V/DIV PHASE_BOOST 10V/DIV PHASE_BUCK 10V/DIV PHASE_BOOST 10V/DIV PHASE_BUCK 10V/DIV 20ms/DIV FIGURE 21. BOOST BUCK MODE, BOOST INPUT STEP FROM 36V TO 3V, VOUT BUCK = 5V, IOUT_BUCK = 1A 10ms/DIV FIGURE 22. BOOST BUCK MODE, BOOST INPUT STEP FROM 3V TO 36V, VOUT BUCK = 5V, IOUT_BUCK = 1A 95 VOUT 5V/DIV 90 PHASE_BUCK 20V/DIV 30V VIN 85 EFFICIENCY (%) IL_BOOST 2A/DIV PHASE_BOOST 20V/DIV 15V VIN 80 5V VIN 75 6V VIN 70 65 60 9V VIN 55 50 0.0 0.2 10ms/DIV FIGURE 23. BOOST BUCK MODE, VO = 9V, IO = 1.8A, BOOST INPUT DROPS FROM 16V TO 9V DC 12 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 LOAD CURRENT (A) FIGURE 24. EFFICIENCY, BOOST BUCK, 500kHz, VOUT 12V, TA = +25°C FN7640.1 April 25, 2013 ISL85402 Functional Description default threshold is 700mA when there is no programming resistor at the MODE pin. Initialization Initially the ISL85402 continually monitors the voltage at the EN pin. When the voltage on the EN pin exceeds its rising ON threshold, the internal LDO will start up to build up VCC. After Power-On Reset (POR) circuits detect that VCC voltage has exceeded the POR threshold, the soft-start will be initiated. The current threshold for PWM/PFM boundary can be programmed by choosing the MODE pin resistor value calculated from Equation 2, where IPFM is the desired PWM/PFM boundary current threshold and RMODE is the programming resistor. 118500 R MODE = ---------------------------------------IPFM + 0.2 Soft-Start 500 The soft-start (SS) ramp is built up in the external capacitor on the SS pin that is charged by an internal 5µA current source. 400 C SS [ μF ] = 6.5 ⋅ t SS [ S ] (EQ. 2) The SS ramp starts from 0 to a voltage above 0.8V. Once SS reaches 0.8V, the bandgap reference takes over and IC gets into steady state operation. The SS plays a vital role in the hiccup mode of operation. The IC works as cycle-by-cycle peak current limiting at over load condition. When a harsh conditon occurs and the current in the upper side MOSFET reaches the second overcurrent threshold, the SS pin is pulled to ground and a dummy soft-start cycle is initiated. At dummy SS cycle, the current to charge soft-start cap is cut down to 1/5 of its normal value. So a dummy SS cycle takes 5x of the regular SS cycle. During the dummy SS period, the control loop is disabled and no PWM output. At the end of this cycle, it will start the normal SS. The hiccup mode persist until the second overcurrent threshold is no longer reached. The ISL85402 is capable of starting up with prebiased output. PWM Control Pulling the MODE pin to GND will set the IC in forced PWM mode. The ISL85402 employs the peak current mode PWM control for fast transient response and cycle-by-cycle current limiting. See “Block Diagram” on page 4. The PWM operation is initialized by the clock from the oscillator. The upper MOSFET is turned on by the clock at the beginning of a PWM cycle and the current in the MOSFET starts to ramp up. When the sum of the current sense signal and the slope compensation signal reaches the error amplifier output voltage level, the PWM comparator is trigger to shut down the PWM logic to turn off the high-side MOSFET. The high-side MOSFET stays off until the next clock signal comes for next cycle. The output voltage is sensed by a resistor divider from VOUT to the FB pin. The difference between the FB voltage and 0.8V reference is amplified and compensated to generate the error voltage signal at the COMP pin. Then the COMP pin signal is compared with the current ramp signal to shut down the PWM. PFM Mode Operation To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating will set the IC to have PFM (Pulse Frequency Modulation) operation in light load. In PFM mode, the switching frequency is dramatically reduced to minimize the switching loss. The ISL85402 enters PFM mode when the MOSFET peak current is lower than the PWM/PFM boundary current threshold. The 13 RMODE (kΩ) (EQ. 1) 300 200 100 0 0.0 0.2 0.4 0.6 0.8 IPFM (A) 1.0 1.2 1.4 FIGURE 25. RMODE vs IPFM Synchronous and Non-Synchronous Buck The ISL85402 supports both Synchronous and non-synchronous buck operations. For a non-synchronous buck operation when a power diode is used as the low-side power device, the LGATE driver can be disabled with LGATE connected to VCC (before IC start-up). AUXVCC Switch-Over The ISL85402 has an auxiliary LDO integrated as shown in the “Block Diagram” on page 4. It is used to replace the internal MAIN LDO function after the IC startup. “Typical Application Schematic II - VCC Switch-Over to VOUT” on page 5 shows its basic application setup with output voltage connected to AUXVCC. After IC soft-start is done and the output voltage is built up to steady state, and once the AUXVCC pin voltage is over the AUX LDO Switch-over Rising Threshold, the MAIN LDO is shut off and the AUXILIARY LDO is activated to bias VCC. Since the AUXVCC pin voltage is lower than the input voltage VIN, the internal LDO dropout voltage and the consequent power loss is reduced. This feature brings substantial efficiency improvements in light load range, especially at high input voltage applications. When the voltage at AUXVCC falls below the AUX LDO Switch-over Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO is re-activated to bias VCC. At the OV/UV fault events, the IC also switches back over from AUXILIARY LDO to MAIN LDO. The AUXVCC switchover function is offered in buck configuration. It is not offered in boost configuration when the AUXVCC pin is used to monitor the boost output voltage for OVP. Input Voltage With the part switching, the operating ISL85402 input voltage must be under 36V. This recommendation allows for short voltage ringing spikes (within a couple of ns time range) due to FN7640.1 April 25, 2013 ISL85402 part switching while not exceeding the 44V, as stated in the Absolute Maximum Ratings. The lowest IC operating input voltage (VIN pin) depends on VCC voltage and the Rising and Falling VCC POR Threshold in Electrical Specifications table on page 7. At IC startup when VCC is just over rising POR threshold, there is no switching before the soft-start starts. Therefore, the IC minimum startup voltage on the VIN pin is 3.05V (MAX of Rising VCC POR). When the soft-start is initiated, the regulator is switching and the dropout voltage across the internal LDO increases due to driving current. Thus, the IC VIN pin shutdown voltage is related to driving current and VCC POR falling threshold. The internal upper side MOSFET has typical 10nC gate drive. For a typical example of synchronous buck with 4nC lower MOSFET gate drive and 500kHz switching frequency, the driving current is 7mA total causing 70mV drop across internal LDO under 3V VIN. Then the IC shut down voltage on the VIN pin is 2.87V (2.8V+0.07V). In practical design, extra room should be taken into account with concern to voltage spikes at VIN. With boost buck configuration, the input voltage range can be expanded further down to 2.5V or lower depending on the boost stage voltage drop upon maximum duty cycle. Since the boost output voltage is connected to the VIN pin as the buck inputs, after the IC starts up, the IC will keep operating and switching as long as the boost output voltage can keep the VCC voltage higher than falling threshold. Refer to “Boost Converter Operation” on page 14 for more details. Output Voltage The ISL85402 output voltage can be programmed down to 0.8V by a resistor divider from VOUT to FB. The maximum achievable voltage is (VIN*DMAX - VDROP), where VDROP is the voltage drop in the power path including mainly the MOSFET rDS(ON) and inductor DCR. The maximum duty cycle DMAX is decided by (1 - Fs * tMIN(OFF)). Output Current With the high-side MOSFET integrated, the maximum output current, which the ISL85402 can support is decided by the package and many operating conditions. Thus, including input voltage, output voltage, duty cycle, switching frequency and temperature, etc. Note the following points. • The maximum output current is limited by the maximum OC threshold that is 4.18A (TYP). • From the thermal perspective, the die temperature shouldn’t exceed +125°C with the power loss dissipated inside of the IC. Figures 10 and 11 show the thermal performance of this part operating at different conditions. Figures 10 and 11 show 2A and 2.5A applications under +25°C still air conditions over VIN range. The temperature rise data in these figures can be used to estimate the die temperature at different ambient temperatures under various operating conditions. Note that more temperature rise is expected at higher ambient temperature due to more conduction loss caused by rDS(ON) increase. ambient conditions). For any other operating conditions, refer to the previous mentioned thermal curves to estimate the maximum output current. The output current should be derated under any conditions causing the die temperature to exceed +125°C. Basically, the die temperature is equal to the sum of ambient temperature and the temperature rise resulting from the power dissipated by the IC package with a certain junction to ambient thermal impedance θJA. The power dissipated in the IC is related to the MOSFET switching loss, conduction loss and the internal LDO loss. Besides the load, these losses are also related to input voltage, output voltage, duty cycle, switching frequency and temperature. With the exposed pad at the bottom, the heat of the IC mainly goes through the bottom pad and θJA is greatly reduced. The θJA is highly related to layout and air flow conditions. In layout, multiple vias (≥9) are strongly recommended in the IC bottom pad. The bottom pad with its vias should be placed in the ground copper plane with an area as large as possible across multiple layers. The θJA can be reduced further with air flow. Refer to Figures 8 and 9 for the thermal performance with 100 CFM air flow. Boost Converter Operation “Typical Application Schematic III - Boost Buck Converter” on page 5, shows the circuits where the boost works as a pre-stage to provide input to the following Buck stage. This is for applications when the input voltage could drop to a very low voltage in some constants (in some battery powered systems as for example), causing the output voltage to drop out of regulation. The boost converter can be enabled to boost the input voltage up to keep the output voltage in regulation. When system input voltage recovers back to normal, the boost stage is disabled while only the buck stage is switching. The EXT_BOOST pin is used to set boost mode and monitor the boost input voltage. At IC start-up before soft-start, the controller will be latched in boost mode when the voltage is at or above 200mV; it will latch in synchronous buck mode if voltage on this pin is below 200mV. In boost mode the low-side driver output PWM has the same PWM signal with the buck regulator. In boost mode, the EXT_BOOST pin is used to monitor boost input voltage to turn on and turn off the boost PWM. The AUXVCC pin is used to monitor the boost output voltage to turn on and turn off the boost PWM. Referring to Figure 26 on page 15, a resistor divider from boost input voltage to the EXT_BOOST pin is used to detect the boost input voltage. When the voltage on EXT_BOOST pin is below 0.8V, the boost PWM is enabled with a fixed 500µs soft-start and the boost duty cycle increases linearly from tMIN(ON)*Fs to ~50%. A 3µA sinking current is enabled at the EXT_BOOST pin for hysteresis purposes. When the voltage on the EXT_BOOST pin recovers to be above 0.8V, the boost PWM is disabled immediately. Use Equation 3 to calculate the upper resistor RUP (R1 in Figure 26) for a desired hysteresis VHYS at boost input voltage. VHYS R UP [ MΩ ] = ---------------------3 [ μA ] (EQ. 3) Generally, the part can output 2.5A in typical application conditions (VIN 8~30V, VO 5V, 500kHz, still air and +105°C 14 FN7640.1 April 25, 2013 ISL85402 Use Equation 4 to calculate the lower resistor RLOW (R2 in Figure 26) according to a desired boost enable threshold. R UP ⋅ 0.8 R LOW = --------------------------------------VFTH – 0.8 (EQ. 4) Where VFTH is the desired falling threshold on boost input voltage to turn on the boost, 3µA is the hysteresis current, and 0.8V is the reference voltage to be compared with. Note the boost start-up threshold has to be selected in a way that the buck is operating working well and kept in close loop regulation before boost start-up. Otherwise, large in-rush current at boost start-up could occur at boost input due to the buck open loop saturation. Similarly, a resistor divider from the boost output voltage to the AUXVCC pin is used to detect the boost output voltage. When the voltage on the AUXVCC pin is below 0.8V, the boost PWM is enabled with a fixed 500µs soft-start, and a 3µA sinking current is enabled at AUXVCC pin for hysteresis purposes. When the voltage on the AUXVCC pin recovers to be above 0.8V, the boost PWM is disabled immediately. Use Equation 3 to calculate the upper resistor RUP (R3 in Figure 26) according to a desired hysteresis VHY at boost output voltage. Use Equation 4 to calculate the lower resistor RLOW (R4 in Figure 26) according to a desired boost enable threshold at boost output. From Equations 5 and 6, Equation 7 can be derived to estimate the steady state boost output voltage as function of VBAT and VOUT: (EQ. 7) V OUTBST = V BAT + V OUT After the IC starts up, the boost buck converters can keep working when the battery voltage drops extremely low because the IC’s bias (VCC) LDO is powered by the boost output. For example, a 3.3V output application battery drops to 2V, and the VIN pin voltage is powered by the boost output voltage that is 5.2V (Equation 7), meaning that the VIN pin (buck input) still sees 5.2V to keep the IC working. Note that in the previously mentioned case, the boost input current could be high because the input voltage is very low (VIN*IIN = VOUT*IOUT/Efficiency). If the design is to achieve the low input operation with full load, the inductor and MOSFET have to be selected with enough current ratings to handle the high current appearing at boost input. The boost inductor current are the same with the boost input current, which can be estimated as Equation 8, where POUT is the output power, VBAT is the boost input voltage, and EFF is the estimated efficiency of the whole boost and buck stages. P OUT IL IN = ------------------------------------V BAT ⋅ EFF (EQ. 8) Assuming VBAT is the boost input voltage, VOUTBST is the boost output voltage and VOUT is the buck output voltage, the steady state transfer function are: Based on the same concerns of the boost input current, the IC should be disabled before the boost input voltage rises above a certain level. PFM is not available in boost mode. 1 V OUTBST = ------------------ ⋅ V BAT 1–D (EQ. 5) Oscillator and Synchronization D V OUT = D ⋅ V OUTBST = ------------------ ⋅ V BAT 1–D (EQ. 6) The oscillator has a default frequency of 500kHz with the FS pin connected to VCC, or ground, or floating. The frequency can be programmed to any frequency between 200kHz and 2.2MHz with a resistor from FS pin to GND. 145000 – 16 ⋅ FS [ kHz ] R FS [ kΩ ] = -----------------------------------------------------------------------------------FS [ kHz ] BATTERY (EQ. 9) VOUT_BST + + R1 EXT_BOOST 0.8V R2 I_HYS = 3µA R3 LOGIC LGATE AUXVCC R4 0.8V PWM LGATE DRIVE I_HYS = 3µA FIGURE 26. BOOST CONVERTER CONTROL 15 FN7640.1 April 25, 2013 ISL85402 dummy soft-start duration equaling to 5 regular soft-start periods. After this dummy soft-start cycle, the true soft-start cycle is attempted again. The IOC2 offers a robust and reliable protections against the worst case conditions. 1200 1000 The frequency foldback is implemented for the ISL85402. When overcurrent limiting, the switching frequency is reduced to be proportional to output voltage in order to keep the inductor current under limit threshold during overload condition. The low limit of frequency under frequency foldback operation is 40kHz. RFS (kΩ) 800 600 400 370 200 320 0 500 1000 1500 FS (kHz) 2000 2500 270 FIGURE 27. RFS vs FREQUENCY The SYNC pin is bi-directional and it outputs the IC’s default or programmed local clock signal when it’s free running. The IC locks to an external clock injected to the SYNC pin (external clock frequency recommended to be 10% higher than the free running frequency). The delay from the rising edge of the external clock signal to the PHASE rising edge is half of the free running switching period pulse 220ns, (0.5Tsw+220ns). The maximum external clock frequency is recommended to be 1.6 of the free running frequency. When the part enters PFM pulse skipping mode, the synchronization function is shut off and also no clock signal output in SYNC pin. With the SYNC pins simply connected together, multiple ISL85402s can be synchronized. The slave ICs automatically have 180° phase shift with respective to the master IC. Fault Protection Overcurrent Protection The overcurrent function protects against any overload condition and output short at worst case, by monitoring the current flowing through the upper MOSFET. There are 2 current limiting thresholds. The first one IOC1 is to limit the high-side MOSFET peak current cycle-by-cycle. The current limit threshold is set to default at 3.6A with ILIMIT pin connected to GND or VCC, or left open. The current limit threshold can also be programmed by a resistor RLIM at ILIMIT pin to ground. Use Equation 10 to calculate the resistor. 300000 R LIM = -----------------------------------------------------I OC [ A ] + 0.018 (EQ. 10) Note that IOC1 is higher with lower RLIM. Considering the OC programming circuit tolerances over the temperature range 40°C to 105°C, 71.5k is the lowest resistor value recommended to be used for RLIM to achieve the highest OC threshold. With 71.5k RLIM, the OC limit is 4.18A (TYP). A resistor lower than 71.5k would result in a default 3.6A OC1 threshold. The second current protection threshold IOC2 is 15% higher than IOC1 mentioned previously. Instantly after the high-side MOSFET current reaches IOC2, the PWM is shut off after 2-cycle delay and the IC enters hiccup mode. In hiccup mode, the PWM is disabled for 16 RLIM (kΩ) 0 220 170 120 70 0.0 1.0 2.0 3.0 IOC1 (A) 4.0 5.0 6.0 FIGURE 28. RLIM vs IOC1 Overvoltage Protection If the voltage detected on the FB pin is over 110% of reference, the high-side and low-side driver shuts down immediately and won’t be allowed on until FB voltage drops to 0.8V. When the FB voltage drops to 0.8V, the drivers are released to ON. If the 120% overvoltage threshold is reached, the high-side and low-side driver shuts down immediately and the IC is latched off. The IC has to be reset for restart. Thermal Protection The ISL85402 PWM will be disabled if the junction temperature reaches +155°C. A +15°C hysteresis insures that the device will not restart until the junction temperature drops below +140°C. Component Selections The ISL85402 iSim model, which is available on the internet can be used to simulate the behaviors to, which will assist with the design. Output Capacitors An output capacitor is required to filter the inductor current. Output ripple voltage and transient response are 2 critical factors when considering output capacitance choice. The current mode control loop allows for the usage of low ESR ceramic capacitors and thus smaller board layout. Electrolytic and polymer capacitors may also be used. Additional consideration applies to ceramic capacitors. While they offer excellent overall performance and reliability, the actual in-circuit capacitance must be considered. Ceramic capacitors are rated using large peak-to-peak voltage swings with no DC bias. In the DC/DC converter application, these conditions do not FN7640.1 April 25, 2013 ISL85402 reflect reality. As a result, the actual capacitance may be considerably lower than the advertised value. Consult the manufacturers data sheet to determine the actual in-application capacitance. Most manufacturers publish capacitance vs DC bias so that this effect can be easily accommodated. The effects of AC voltage are not frequently published, but an assumption of ~20% further reduction will generally suffice. The result of these considerations can easily result in an effective capacitance 50% lower than the rated value. Nonetheless, they are a very good choice in many applications due to their reliability and extremely low ESR. The following equations allow calculation of the required capacitance to meet a desired ripple voltage level. Additional capacitance may be used. For the ceramic capacitors (low ESR): ΔI V OUTripple = ----------------------------------8∗ F SW∗ C OUT (EQ. 11) where ΔI is the inductor’s peak to peak ripple current, FSW is the switching frequency and COUT is the output capacitor. If using electrolytic capacitors then: V OUTripple = ΔI*ESR (EQ. 12) Regarding transient response needs, a good starting point is to determine the allowable overshoot in VOUT if the load is suddenly removed. In this case, energy stored in the inductor will be transferred to COUT causing its voltage to rise. After calculating capacitance required for both ripple and transient needs, choose the larger of the calculated values. The following equation determines the required output capacitor value in order to achieve a desired overshoot relative to the regulated voltage. I OUT 2 * L C OUT = ------------------------------------------------------------------------------------V OUT 2 * ( V OUTMAX ⁄ V OUT ) 2 – 1 ) (EQ. 13) Increasing the value of inductance reduces the ripple current and thus ripple voltage. However, the larger inductance value may reduce the converter’s response time to a load transient. The inductor current rating should be such that it will not saturate in overcurrent conditions. Low-Side Power MOSFET In synchronous buck application, a power N MOSFET is needed as the synchronous low side MOSFET and a good one should have low Qgd, low rDS(ON) and small Rg (Rg_typ < 1.5Ω recommended). Vgth_min is recommended to be higher than 1.2V. A good example is SQS462EN. Output Voltage Feedback Resistor Divider The output voltage can be programmed down to 0.8V by a resistor divider from VOUT to FB according to Equation 15. R UP ⎞ ⎛ V OUT = 0.8 ⋅ ⎜ 1 + --------------------⎟ R ⎝ LOW⎠ In an application requiring least input quiescent current, large resistors should be used for the divider. 232k is recommended for the upper resistor. Loop Compensation Design The ISL85402 uses constant frequency peak current mode control architecture to achieve fast loop transient response. An accurate current sensing pilot device in parallel with the upper MOSFET is used for peak current control signal and overcurrent protection. The inductor is not considered as a state variable since its peak current is constant, and the system becomes single order system. It is much easier to design the compensator to stabilize the loop compared with voltage mode control. Peak current mode control has inherent input voltage feed-forward function to achieve good line regulation. Figure 29 shows the small signal model of a buck regulator. where VOUTMAX/VOUT is the relative maximum overshoot allowed during the removal of the load. Input Capacitors 1:D The inductor value determines the converter’s ripple current. Choosing an inductor current requires a somewhat arbitrary choice of ripple current, ΔI. A reasonable starting point is 30% to 40% of total load current. The inductor value can then be calculated using Equation 14: LP RLP ^ vo Vin d^ RT Rc Ro Co T i(S) d^ Fm + Buck Output Inductor V IN – V OUT V OUT L = ---------------------------- × ------------Fs × ΔI V IN ILd^ ^ iL + GAIN (VLOOP (S(fi)) Ceramic capacitors must be used at VIN pin of the IC and multiple capacitors including 1µF and 0.1µF are recommended. Place these capacitors as closely as possible to the IC. ^ Vin + ^ i in Depending on the system input power rail conditions, the aluminum electrolytic type capacitor is normally needed to provide the stable input voltage. Thus, restrict the switching frequency pulse current in a small area over the input traces for better EMC performance. The input capacitor should be able to handle the RMS current from the switching power devices. (EQ. 15) Tv (S) He(S) v^comp -Av(S) FIGURE 29. SMALL SIGNAL MODEL OF BUCK REGULATOR (EQ. 14) 17 FN7640.1 April 25, 2013 ISL85402 PWM Comparator Gain Fm: If Ti(S)>>1, then Equation 23 can be simplified as Equation 24: The PWM comparator gain Fm for peak current mode control is given by Equation 16: S 1 + -----------R o + R LP ω esr A v ( S ) 1 L v ( S ) = ----------------------- ---------------------- --------------- , ω p ≈ ------------Rt Ro C o S He ( S ) -----1+ ωp 1 dˆ - = -----------------------------F m = --------------( S e + S n )T s vˆ comp (EQ. 16) Where, Se is the slew rate of the slope compensation and Sn is given by Equation 17: V in – V o S n = R t -------------------L (EQ. 17) P (EQ. 24) Equation 24 shows that the system is a single order system. Therefore, a simple type II compensator can be easily used to stabilize the system. A type III compensator is needed to expand the bandwidth for current mode control in some cases. where, Rt is the gain of the current amplifier. C1 R2 R3 C3 CURRENT SAMPLING TRANSFER FUNCTION HE(S): In current loop, the current signal is sampled every switching cycle. It has the following transfer function in Equation 18: 2 VO VCOMP R1 VREF RBIAS (EQ. 18) S S H e ( S ) = ------- + -------------- + 1 2 ω Q n n ωn where, Qn and ωn are given by 2 Q n = – ---, ω n = πf s π FIGURE 30. TYPE III COMPENSATOR Power Stage Transfer Functions Transfer function F1(S) from control to output voltage is: S 1 + -----------ω esr vˆ o - = V in -------------------------------------F 1 ( S ) = ----2 dˆ S S ------- + -------------- + 1 2 ω Q o p ωo (EQ. 19) C LP LP Co Transfer function F2(S) from control to inductor current is given by Equation 20: S 1 + -----ˆI V ω o in z F 2 ( S ) = ---ˆ- = ----------------------- -------------------------------------R o + R LP 2 d S S ------- + -------------- + 1 2 ω Q o p ωo S ⎞⎛ S ⎛ 1 + -----------1 + ------------⎞ ⎝ ω cz1⎠ ⎝ ω cz2⎠ vˆ comp 1 - = ------------------ --------------------------------------------------------A v ( S ) = --------------SR 1 C S ⎞ vˆ O ⎛ 1 + --------1 ⎝ ω ⎠ (EQ. 25) cp 1 1 Where, ω esr = ------------- ,Q p ≈ R o -----o- ,ω o = ----------------Rc Co A type III compensator with 2 zeros and 1 pole is recommended for this part, as shown in Figure 30. Its transfer function is expressed as Equation 25: (EQ. 20) where, 1 1 1 ω cz1 = -------------- , ω cz2 = --------------------------------, ω cp = -------------( R 1 + R 3 )C 3 R2 C1 R3 C3 Compensator design goal: ⎛1 1⎞ - f Loop bandwidth fc: ⎝ --4- to -----10⎠ s Gain margin: >10dB 1 where ω z = ------------Ro Co . Phase margin: 45° Current loop gain Ti(S) is expressed as Equation 21: T i ( S ) = R t F m F 2 ( S )H e ( S ) (EQ. 21) The voltage loop gain with open current loop is expressed in Equation 22: T v ( S ) = KF m F 1 ( S )A v ( S ) (EQ. 22) The Voltage loop gain with current loop closed is given by Equation 23: Tv ( S ) L v ( S ) = ----------------------1 + Ti ( S ) (EQ. 23) The compensator design procedure is as follows: 1. Position ωCZ2 and ωCP to derive R3 and C3. Put the compensator zero ωCZ2 at (1 to 3)/(RoCo) (EQ. 26) 3 ω cz2 = ------------Ro Co Put the compensator pole ωCP at ESR zero or 0.35 to 0.5 times of switching frequency, whichever is lower. In all-ceramic-cap design, the ESR zero is normally higher than half of the switching frequency. R3 and C3 can be derived as following: 1 Case A: ESR zero --------------------- less than (0.35 to 0.5)fs 2πR c C o 18 FN7640.1 April 25, 2013 ISL85402 R o C o – 3R c C o C 3 = ------------------------------------3R 1 (EQ. 27) 3R c R 1 R 3 = ----------------------R o – 3R c (EQ. 28) Loop Gain 80 60 1 Case B: ESR zero --------------------- larger than (0.35 to 0.5)fs 40 2πR c C o (EQ. 29) R1 R 3 = ---------------------------------------0.73R o C o f s – 1 (EQ. 30) dB 20 0.33R o C o f s – 0.46 C 3 = ------------------------------------------------fs R 0 1 -20 -40 2. Derive R2 and C1. -60 100 The loop gain Lv(S) at cross over frequency of fc has unity gain. Therefore, C1 is determined by Equation 31. ( R 1 + R 3 )C 3 C 1 = --------------------------------2πf c R t R 1 C 1,000 10,000 100,000 1,000,000 Frequency (EQ. 31) Phase Margin 180 The compensator zero ωCZ1 can boost the phase margin and bandwidth. To put ωCZ1 at 2 times of cross cover frequency fc is a good start point. It can be adjusted according to specific design. R1 can be derived from Equation 32. (EQ. 32) 1 R 2 = ------------------4πf c C 1 160 140 120 100 D Degree o 80 60 Example: Vin = 12V, Vo = 5V, Io = 2A, fs = 500kHz, Co = 60µF/3mΩ, L = 10µH, Rt = 0.20V/A, fc = 50kHz, R1=105k, RBIAS = 20kΩ. Select the crossover frequency to be 35kHz. Since the output capacitors are all ceramic, use Equation 29 and 30 to derive R3 to be 20k and C3 to be 470pF. Then use Equation 31 and 32 to calculate C1 to be 180pF and R2 to be 12.7k. Select 150pF for C1 and 15k for R2. There is approximately 30pF parasitic capacitance between COMP to FB pins that contributes to a high frequency pole. Figure 31 shows the simulated bode plot of the loop. It is shown that it has 26kHz loop bandwidth with 70° phase margin and -28 dB gain margin. Note in applications where the PFM mode is desired especially when type III compensation network is used, the value of the capacitor between the COMP pin and the FB pin (not the capacitor in series with the resistor between COMP and FB) should be minimal to reduce the noise coupling for proper PFM operation. No external capacitor between COMP and FB is recommended at PFM applications. 19 40 20 0 100 1,000 10,000 100,000 1,000,000 Frequency FIGURE 31. SIMULATED LOOP BODE PLOT Boost Inductor Besides the need to sustain the current ripple to be within a certain range (30% to 50%), the boost inductor current at its soft-start is a more important perspective to be considered in selection of the boost inductor. Each time the boost starts up, there is a fixed 500µs soft-start time when the duty cycle increases linearly from tMIN(ON)*Fs to ~50%. Before and after boost start-up, the boost output voltage will jump from VIN_BOOST to voltage (VIN_BOOST + VOUT_BUCK). The design target in boost soft-start is to ensure the boost input current is sustained to minimum but capable to charge the boost output voltage to have a voltage step equaling to VOUT_BUCK. A big inductor will block the inductor current to increase and not high enough to be able to charge the output capacitor to the final steady state value (VIN_BOOST + VOUT_BUCK) within 500µs. A 6.8µH inductor is a good starting point for its selection in design. The boost inductor current at start-up must be checked by oscilloscope to ensure it is under acceptable range. It is suggested to run the iSim model, which is available on the internet to assist in designing the proper inductor value. FN7640.1 April 25, 2013 ISL85402 Boost Output Capacitor Based on the same theory in boost start-up previously described in the boost inductor selection, a large capacitor at boost output will cause high in-rush current at boost PWM start-up. 22µF is a good choice for applications with a buck output voltage less than 10V. Also some minimum amount of capacitance has to be used in boost output to keep the system stable. It is suggested to run the iSim model, which is available on the internet to assist in designing the proper capacitor value. Layout Suggestions 1. Place the input ceramic capacitors as closely as possible to the IC VIN pin and power ground connecting to the power MOSFET or Diode. Keep this loop (input ceramic capacitor, IC VIN pin and MOSFET/Diode) as tiny as possible to achieve the least voltage spikes induced by the trace parasitic inductance. as possible in multiple layers to effectively reduce the thermal impedance. 6. Place the 4.7µF ceramic decoupling capacitor at the VCC pin (the closest place to the IC). Put multiple vias (≥3) close to the ground pad of this capacitor. 7. Keep the bootstrap capacitor close to the IC. 8. Keep the LGATE drive trace as short as possible and try to avoid using via in the LGATE drive path to achieve the lowest impedance. 9. Place the positive voltage sense trace close to the place to be strictly regulated. 10. Place all the peripheral control components close to the IC. 2. Place the input aluminum capacitors closely as possible to the IC VIN pin. 3. Keep the phase node copper area small but large enough to handle the load current. 4. Place the output ceramic and aluminum capacitors close to the power stage components as well. FIGURE 32. PCB VIA PATTERN 5. Place vias (≥9) in the bottom pad of the IC. The bottom pad should be placed in ground copper plane with an area as large 20 FN7640.1 April 25, 2013 ISL85402 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE April 25, 2012 FN7640.1 1. Expanded the maximum temperature from 85°C to 105°C for the electrical characteristics and Ordering Information. 2. Added application design guide for selection of inductor and capacitor and loop compensation. 3. Added typical electrical specification of EN pull-up current, synchronization. 4. Added boost-buck efficiency curve and AUVVCC switchover description. 5. Under "Output Voltage" description, corrected "(1/Fs tMINOFF)" To " (1 - Fs * tMIN(OFF))". 6. Under "Boost Converter Operation", corrected "(VIN*IIN = VOUT*IOUT*Efficiency)" to "(VIN*IIN = VOUT*IOUT/Efficiency)". 7. Added recommendation of the maximum programmable OC threshold to be 4.18A(TYP) with 71.5k RLIM. 8. Corrected sentence in first paragraph on page 1 from: “ The ISL85402 supports a wide input range of 3V to 40V in buck mode.“ to “ The ISL85402 supports a wide input range of 3V to 36V in buck mode.“ 9. Removed following sentence from last paragraph of “Power Stage Transfer Functions” on page 19: “Deleted following sentence from last paragraph of “Power Stage Transfer Functions” on page 19: “A capacitor (<1nF) at the FB pin to ground also helps proper PFM mode operation". September 29, 2011 FN7640.0 Initial Release About Intersil Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal computing and high-end consumer markets. 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For information regarding Intersil Corporation and its products, see www.intersil.com 21 FN7640.1 April 25, 2013 ISL85402 Package Outline Drawing L20.4x4C 20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 0, 11/06 4X 4.00 2.0 16X 0.50 A B 16 6 PIN #1 INDEX AREA 20 6 PIN 1 INDEX AREA 1 4.00 15 2 .70 ± 0 . 15 11 (4X) 5 0.15 6 10 0.10 M C A B 4 20X 0.25 +0.05 / -0.07 20X 0.4 ± 0.10 TOP VIEW BOTTOM VIEW SEE DETAIL "X" 0.10 C 0 . 90 ± 0 . 1 C BASE PLANE ( 3. 8 TYP ) ( SEATING PLANE 0.08 C 2. 70 ) ( 20X 0 . 5 ) SIDE VIEW ( 20X 0 . 25 ) C 0 . 2 REF 5 ( 20X 0 . 6) 0 . 00 MIN. 0 . 05 MAX. DETAIL "X" TYPICAL RECOMMENDED LAND PATTERN NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance: Decimal ± 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 22 FN7640.1 April 25, 2013