40V Precision Single-Supply, Rail-to-Rail Output, Low-Power Operational Amplifiers ISL28118, ISL28218 Features The ISL28118 and ISL28218 are single and dual, low-power precision amplifiers optimized for single-supply applications. These devices feature a common mode input voltage range extending to 0.5V below the V- rail, a rail-rail differential input voltage range for use as a comparator, and rail-to-rail output voltage swing, which makes them ideal for single-supply applications where input operation at ground is important. • Rail-to-Rail Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mV These op amps feature low power, low offset voltage, and low temperature drift, making them the ideal choice for applications requiring both high DC accuracy and AC performance. These amplifiers are designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The combination of precision and small footprint provides the user with outstanding value and flexibility relative to similar competitive parts. Applications for these amplifiers include precision instrumentation, data acquisition, precision power supply controls, and industrial controls. • Below-Ground (V-) Input Capability to -0.5V • Rail-to-Rail Input Differential Voltage Range for Comparator Applications • Single-Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 40V • Low Current Consumption . . . . . . . . . . . . . . . . . . . . . . . 850µA • Low Noise Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6nV/√Hz • Low Noise Current . . . . . . . . . . . . . . . . . . . . . . . . . . 355fA/√Hz • Low Input Offset Voltage - ISL28118 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150µV Max. - ISL28218 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230µV Max. • Superb Offset Voltage Temperature Drift - ISL28118 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2µV/°C, Max. - ISL28218 . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4µV/°C, Max. • Operating Temperature Range. . . . . . . . . . .-40°C to +125°C Both parts are offered in 8 Ld TDFN, 8 Ld SOIC and 8 Ld MSOP packages. All devices are offered in standard pin configurations and operate over the extended temperature range of -40°C to +125°C. • No Phase Reversal Applications • Precision Instruments • Medical Instrumentation Related Literature • Data Acquisition • AN1595: ISL28218SOICEVAL1Z Evaluation Board User’s Guide • Power Supply Control • Industrial Process Control RF IN- 10kΩ RIN+ IN+ 10kΩ V+ ISL28118 V- +3V to 40V 300 200 VOUT -40°C 100 VOS (µV) RINRSENSE 400 100kΩ LOAD + GAIN = 10 RREF+ +25°C +125°C 0 -100 -200 100kΩ -300 VREF -400 -16 -15 -14 -13 13 14 15 16 INPUT COMMON MODE VOLTAGE (V) FIGURE 1. TYPICAL APPLICATION: SINGLE-SUPPLY, LOW-SIDE CURRENT SENSE AMPLIFIER September 21, 2011 FN7532.3 1 FIGURE 2. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2010, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL28118, ISL28218 Pin Configurations ISL28118 (8 LD SOIC, 8 LD MSOP) TOP VIEW ISL28118 (8 LD TDFN) TOP VIEW NC 1 -IN 2 - + +IN 3 V- 4 NC 1 7 V+ -IN 2 6 VOUT +IN 3 V- 4 8 NC PD 5 NC -IN_A 2 +IN_A 3 V- 4 VOUT_A 1 7 VOUT_B -IN_A 2 6 -IN_B +IN_A 3 5 +IN_B V- 4 8 V+ - + + - PD NC 7 V+ 6 VOUT 5 NC ISL28218 (8 LD SOIC, 8 LD MSOP) TOP VIEW ISL28218 (8 LD TDFN) TOP VIEW VOUT_A 1 - + 8 - + + - 8 V+ 7 VOUT_B 6 -IN_B 5 +IN_B Pin Descriptions ISL28118 (8 LD TDFN) ISL28118 (8 LD SOIC, MSOP) ISL28218 (8 LD TDFN) ISL28218 (8 LD SOIC, MSOP) PIN NAME EQUIVALENT CIRCUIT 3 3 3 3 +IN_A 1 Amplifier A non-inverting input 2 2 2 2 -IN_A 1 Amplifier A inverting input 6 6 1 1 VOUT_A 2 Amplifier A output 4 4 4 4 V- 3 Negative power supply 5 5 +IN_B 1 Amplifier B non-inverting input 6 6 -IN_B 1 Amplifier B inverting input 7 7 VOUT_B 2 Amplifier B output DESCRIPTION 7 7 8 8 V+ 3 Positive power supply 1, 5, 8 1, 5, 8 - - NC - No Connect PAD PAD IN- PAD V+ V+ IN+ OUT V- VCIRCUIT 1 CIRCUIT 2 2 Thermal Pad is electrically isolated from active circuitry. Pad can float, connect to Ground, or connect to a potential source that is free from signals or noise sources. V+ CAPACITIVELY TRIGGERED ESD CLAMP VCIRCUIT 3 FN7532.3 September 21, 2011 ISL28118, ISL28218 Ordering Information PART NUMBER (Notes 2, 3) PART MARKING TEMPERATURE RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # ISL28118FBZ (Note 1) 28118 FBZ -40 to +125 8 Ld SOIC M8.15E Coming Soon ISL28118FRTZ (Note 1) 118Z -40 to +125 8 Ld TDFN L8.3x3A ISL28118FUZ (Note 1) 8118Z -40 to +125 8 Ld MSOP M8.118 ISL28218FBZ (Note 1) 28218 FBZ -40 to +125 8 Ld SOIC M8.15E Coming Soon ISL28218FRTZ 218Z -40 to +125 8 Ld TDFN L8.3x3A Coming Soon ISL28218FUZ 8218Z -40 to +125 8 Ld MSOP M8.118 ISL28218SOICEVAL1Z Evaluation Board NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information pages for ISL28118, ISL28218. For more information on MSL, please see Technical Brief TB363. 3 FN7532.3 September 21, 2011 ISL28118, ISL28218 Absolute Maximum Ratings Thermal Information Maximum Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42V Maximum Differential Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Maximum Differential Input Voltage . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V Min/Max Input Voltage . . . . . . . . . . . . . . . . . . . . 42V or V- - 0.5V to V+ + 0.5V Max/Min Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA Output Short-Circuit Duration (1 output at a time) . . . . . . . . . . . . . . Indefinite ESD Tolerance Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 3kV Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 300V Charged Device Model (Tested per CDM-22CI0ID) . . . . . . . . . . . . . . . 2kV Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) ISL28118 8 Ld TDFN Package (Notes 5, 6). . . . . . . . . . 50 9 8 Ld SOIC Package (Notes 4, 7) . . . . . . . . . . 120 60 8 Ld MSOP Package (Notes 4, 7) . . . . . . . . . 165 57 ISL28218 8 Ld TDFN Package (Notes 5, 6). . . . . . . . . . 48 5.5 8 Ld SOIC Package (Notes 4, 7) . . . . . . . . . . 120 55 8 Ld MSOP Package (Notes 4, 7) . . . . . . . . . 150 45 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Operating Conditions Ambient Operating Temperature Range . . . . . . . . . . . . . .-40°C to +125°C Maximum Operating Junction Temperature . . . . . . . . . . . . . . . . . .+150°C Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3V (+1.8V/-1.2V) to 40V (±20V) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 6. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 7. For θJC, the “case temp” location is taken at the package top center. Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. MIN PARAMETER VOS DESCRIPTION Input Offset Voltage CONDITIONS ISL28118 (Note 8) TYP MAX (Note 8) UNIT -150 25 150 µV 270 µV 230 µV 290 µV -270 ISL28218 -230 40 -290 TCVOS ΔVOS IB Input Offset Voltage Temperature Coefficient ISL28118 -1.2 0.2 1.2 µV/°C ISL28218 -1.4 0.3 1.4 µV/°C Input Offset Voltage Match (ISL28218 only) -280 44 280 µV 365 µV Input Bias Current -575 -365 -230 nA -800 TCIB Input Bias Current Temperature Coefficient IOS Input Offset Current -0.8 -50 -75 4 nA 4 nA/°C 50 nA 75 nA FN7532.3 September 21, 2011 ISL28118, ISL28218 Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) MIN PARAMETER CMRR VCMIR PSRR DESCRIPTION Common-Mode Rejection Ratio CONDITIONS (Note 8) VCM = V- - 0.5V to V+ - 1.8V VCM = V- to V+ -1.8V ISL28118 SOIC 102 VCM = V- to V+ -1.8V ISL28118 MSOP 102 VCM = V- to V+ -1.8V ISL28218 103 Common Mode Input Voltage Range Guaranteed by CMRR test Power Supply Rejection Ratio VS = 3V to 40V, VCMIR = Valid Input Voltage TYP MAX (Note 8) 118 dB 118 dB 98 dB 118 dB 97 dB 118 dB 99 dB V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V 109 124 dB 105 AVOL Open-Loop Gain VO = -13V to +13V, RL = 10kΩ to ground, ISL28118 SOIC VO = -13V to +13V, RL = 10kΩ to ground, ISL28218 VO = -13V to +13V, RL = 10kΩ to ground, ISL28118 MSOP VOL VOH IS Output Voltage Low, VOUT to V- , See Figure 32 UNIT 125 dB 136 dB 120 125 dB 136 dB 122 120 dB 136 dB 116 dB ISL28118 RL = 10kΩ 70 mV 85 mV ISL28218 RL = 10kΩ 70 mV 73 mV Output Voltage High, V+ to VOUT See Figure 32 ISL28118 ISL28218 RL = 10kΩ 110 mV 120 mV Supply Current/Amplifier ISL28118 RL = Open 0.85 1.2 mA 1.6 mA ISL28218 RL = Open 0.85 1.1 mA 1.4 mA ISC+ Output Short Circuit Source Current RL = 10Ω to V- 16 mA ISC- Output Short Circuit Sink Current RL = 10Ω to V+ 28 mA VSUPPLY Supply Voltage Range Guaranteed by PSRR 3 40 V AC SPECIFICATIONS GBWP Gain Bandwidth Product ACL = 101, VOUT = 100mVP-P; RL = 2k 4 MHz enp-p Voltage Noise 0.1Hz to 10Hz, VS = ±18V 300 nVP-P en Voltage Noise Density f = 10Hz, VS = ±18V 8.5 nV/√Hz en Voltage Noise Density f = 100Hz, VS = ±18V 5.8 nV/√Hz en Voltage Noise Density f = 1kHz, VS = ±18V 5.6 nV/√Hz en Voltage Noise Density f = 10kHz, VS = ±18V 5.6 nV/√Hz 5 FN7532.3 September 21, 2011 ISL28118, ISL28218 Electrical Specifications VS ±15V, VCM = 0, VO = 0V, RL = Open, TA= +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) MIN PARAMETER DESCRIPTION CONDITIONS in Current Noise Density THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 3.5VRMS, RL = 10kΩ (Note 8) f = 1kHz, VS = ±18V TYP MAX (Note 8) UNIT 355 fA/√Hz 0.0003 % TRANSIENT RESPONSE SR Slew Rate AV = 1, RL = 2kΩ, VO = 10VP-P ±1.2 V/µs tr, tf, Small Signal Rise Time 10% to 90% of VOUT AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 100 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 100mVP-P, Rf = 0Ω, RL = 2kΩ to VCM 100 ns Settling Time to 0.01% 10V Step; 10% to VOUT AV = 1, VOUT = 10VP-P, Rf = 0Ω RL = 2kΩ to VCM 8.5 µs ts Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. MIN PARAMETER VOS DESCRIPTION Input Offset Voltage CONDITIONS ISL28118 (Note 8) TYP MAX (Note 8) UNIT -150 25 150 µV 270 µV 230 µV 290 µV -270 ISL28218 -230 40 -290 TCVOS ΔVOS IB Input Offset Voltage Temperature Coefficient ISL28118 -1.2 0.2 1.2 µV/°C ISL28218 -1.4 0.3 1.4 µV/°C Input Offset Voltage Match (ISL28218 only) -280 44 280 µV 365 µV Input Bias Current -575 -365 -230 nA -800 TCIB Input Bias Current Temperature Coefficient IOS Input Offset Current nA -0.8 -50 4 -75 CMRR VCMIR Common-Mode Rejection Ratio Common Mode Input Voltage Range 6 VCM = V- - 0.5V to V+ - 1.8V VCM = V- to V+ -1.8V ISL28118 SOIC 101 VCM = V- to V+ -1.8V ISL28118 MSOP 101 VCM = V- to V+ -1.8V ISL28218 101 Guaranteed by CMRR test nA/°C 50 nA 75 nA 119 dB 117 dB 97 dB 117 dB 96 dB 117 dB 97 dB V- - 0.5 V+ - 1.8 V V- V+ - 1.8 V FN7532.3 September 21, 2011 ISL28118, ISL28218 Electrical Specifications VS ±5V, VCM = 0, VO = 0V, TA = +25°C, unless otherwise noted. Boldface limits apply over the operating temperature range, -40°C to +125°C. Temperature data established by characterization. (Continued) MIN PARAMETER PSRR CONDITIONS (Note 8) TYP VS = 3V to 10V, VCMIR = Valid Input Voltage, ISL28118 SOIC ISL28218 SOIC 109 124 ISL28118 MSOP 108 VO = -3V to +3V, RL = 10kΩ to ground, ISL28118 SOIC ISL28218 SOIC 122 ISL28118 MSOP 120 DESCRIPTION Power Supply Rejection Ratio MAX (Note 8) dB 105 dB 124 dB 132 dB 103 AVOL Open-Loop Gain dB 117 dB 132 dB 115 VOL Output Voltage Low, VOUT to V- , See Figure 32 RL = 10kΩ VOH Output Voltage High, V+ to VOUT See Figure 31 RL = 10kΩ IS Supply Current/Amplifier RL = Open UNIT dB 0.85 38 mV 45 mV 65 mV 70 mV 1.1 mA 1.4 mA ISC+ Output Short Circuit Source Current RL = 10Ω to V- 13 mA ISC- Output Short Circuit Sink Current RL = 10Ω to V+ 20 mA AC SPECIFICATIONS GBWP Gain Bandwidth Product ACL = 101, VOUT = 100mVP-P; RL = 2k 3.2 MHz enp-p Voltage Noise 0.1Hz to 10Hz 320 nVP-P en Voltage Noise Density f = 10Hz 9 nV/√Hz en Voltage Noise Density f = 100Hz 5.7 nV/√Hz en Voltage Noise Density f = 1kHz 5.5 nV/√Hz en Voltage Noise Density f = 10kHz 5.5 nV/√Hz in Current Noise Density f = 1kHz 380 fA/√Hz THD + N Total Harmonic Distortion + Noise 1kHz, G = 1, VO = 1.25VRMS, RL = 10kΩ 0.0003 % TRANSIENT RESPONSE SR Slew Rate AV = 1, RL = 2kΩ, VO = 4VP-P ±1 V/µs tr, tf, Small Signal Rise Time 10% to 90% of VOUT AV = 1, VOUT = 100mVP-P , Rf = 0Ω, RL = 2kΩ to VCM 100 ns Fall Time 90% to 10% of VOUT AV = 1, VOUT = 100mVP-P , Rf = 0Ω, RL = 2kΩ to VCM 100 ns Settling Time to 0.01% 4V Step; 10% to VOUT AV = 1, VOUT = 4VP-P, Rf = 0Ω RL = 2kΩ to VCM 4 µs ts NOTE: 8. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7 FN7532.3 September 21, 2011 ISL28118, ISL28218 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. 200 200 VOS (µV) FIGURE 3. ISL28118 INPUT OFFSET VOLTAGE DISTRIBUTION 18 NUMBER OF AMPLIFIERS 16 14 12 10 8 6 4 2 TCVOS (µV/C) FIGURE 7. ISL28118 TCVOS vs NUMBER OF AMPLIFIERS ±15V 8 120 100 80 60 40 20 -20 -40 0 175 200 150 125 100 75 50 25 0 -25 -50 -75 -100 VOS (µV) FIGURE 6. ISL28218 INPUT OFFSET VOLTAGE DISTRIBUTION VS = ±15V -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 NUMBER OF AMPLIFIERS 50 VOS (µV) FIGURE 5. ISL28218 INPUT OFFSET VOLTAGE DISTRIBUTION 0 100 0 200 150 175 125 75 100 50 25 0 -25 -50 -75 -100 50 150 VS = ±5V 14 12 10 8 6 4 2 0 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 100 200 -125 NUMBER OF AMPLIFIERS 150 -125 NUMBER OF AMPLIFIERS VS = ±5V 200 16 -60 250 VS = ±15V 18 VOS (µV) FIGURE 4. ISL28118 INPUT OFFSET VOLTAGE DISTRIBUTION 250 0 -80 50 0 120 80 100 60 40 0 20 -20 -40 -60 -80 0 -100 50 100 -100 100 150 -120 NUMBER OF AMPLIFIERS VS = ±5V 150 -120 NUMBER OF AMPLIFIERS VS = ±15V TCVOS (µV/C) FIGURE 8. ISL28118 TCVOS vs NUMBER OF AMPLIFIERS ±5V FN7532.3 September 21, 2011 ISL28118, ISL28218 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 35 30 NUMBER OF AMPLIFIERS 25 20 15 10 5 0 VS = ±5V 30 25 20 15 10 5 0 -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 NUMBER OF AMPLIFIERS VS = ±15V -1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 Typical Performance Curves TCVOS (µV/C) TCVOS (µV/C) FIGURE 9. ISL28218 TCVOS vs NUMBER OF AMPLIFIERS ±15V FIGURE 10. ISL28218 TCVOS vs NUMBER OF AMPLIFIERS ±5V 100 400 90 300 80 200 70 VOS (µV) VOS (µV) 60 VS = ±15V 50 40 30 +25°C +125°C 0 -100 -200 20 VS = ±5V 10 0 -40 -40°C 100 -20 0 20 -300 40 60 80 100 -400 -16 120 -15 TEMPERATURE (°C) FIGURE 11. VOS vs TEMPERATURE -14 -13 13 14 15 16 INPUT COMMON MODE VOLTAGE (V) FIGURE 12. INPUT OFFSET VOLTAGE vs INPUT COMMON MODE VOLTAGE, VS = ±15V -150 0 -50 VS = ±20V -200 -100 VS = ± 15V IBIAS (nA) IBIAS (nA) -150 -200 -250 -300 -250 -300 VS = +2V/-1V -350 -350 -400 VS = ±2.25V -450 -500 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 VS (V) FIGURE 13. IBIAS vs VS 9 -400 -40 -20 0 20 40 VS = ±5V 60 80 100 120 TEMPERATURE (°C) FIGURE 14. IBIAS vs TEMPERATURE vs SUPPLY FN7532.3 September 21, 2011 ISL28118, ISL28218 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 124 124 122 122 120 120 CMRR (dB) CMRR (dB) Typical Performance Curves 118 116 118 116 114 114 112 112 110 -40 -20 0 20 40 60 80 100 110 -40 120 -20 0 TEMPERATURE (°C) 132 132 130 130 128 128 126 126 124 124 CHANNEL-A 120 118 CHANNEL-B 116 118 112 20 40 60 80 100 110 -40 120 -20 0 FIGURE 17. ISL28218 CMRR vs TEMPERATURE, VS = ±15V 20 40 60 80 100 120 FIGURE 18. ISL28218 CMRR vs TEMPERATURE, VS = ±5V 140 135 ISL28118 130 PSRR (dB) CMRR (dB) 120 TEMPERATURE (°C) TEMPERATURE (°C) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 100 CHANNEL-A 116 114 0 80 120 112 -20 60 CHANNEL-B 122 114 110 -40 40 FIGURE 16. ISL28118 CMRR vs TEMPERATURE, V S = ±5V CMRR (dB) CMRR (dB) FIGURE 15. ISL28118 CMRR vs TEMPERATURE, VS = ±15V 122 20 TEMPERATURE (°C) 125 ISL28218 120 115 110 105 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) FIGURE 19. CMRR vs FREQUENCY, VS = ±15V 10 100 -40 -20 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 20. PSRR vs TEMPERATURE, VS = ±15V FN7532.3 September 21, 2011 ISL28118, ISL28218 140 130 120 110 100 90 80 70 60 50 40 VS = ±15V 30 AV = 1 20 CL = 4pF 10 RL = 10k 0 VCM = 1VP-P -10 10 100 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) PSRR+ PSRR (dB) PSRR (dB) Typical Performance Curves PSRR- 1k 10k 100k FREQUENCY (Hz) 1M 10M 140 130 120 110 100 90 80 70 60 50 40 VS = ±5V 30 AV = 1 20 CL = 4pF 10 RL = 10k 0 VCM = 1VP-P -10 10 100 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 PSRR- 1k 10k 100k FREQUENCY (Hz) 70 60 PHASE GAIN RF = 10kΩ, RG = 100Ω 40 30 20 ACL = 10 RF = 10kΩ, RG = 1kΩ ACL = 1 0 -10 100 10 100 1k 10k 100k 1M 10M100M 1G VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 10 RF = 0, RG = ∞ 1k 10k FREQUENCY (Hz) 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 0 -2 -3 -6 RL = OPEN, 100k, 10k RL = 1k RL = 499 RL = 100 VS = ±15V CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 1k RL = 49.9 10k 100k 1M FREQUENCY (Hz) FIGURE 25. GAIN vs FREQUENCY vs RL, VS = ±15V 11 1M 10M FIGURE 24. FREQUENCY RESPONSE vs CLOSED LOOP GAIN 1 -5 100k FREQUENCY (Hz) FIGURE 23. OPEN-LOOP GAIN, PHASE vs FREQUENCY, VS = ±15V -4 10M RF = 10kΩ, RG = 10Ω ACL = 1000 50 1 1M FIGURE 22. PSRR vs FREQUENCY, VS = ±5V GAIN (dB) GAIN (dB) FIGURE 21. PSRR vs FREQUENCY, VS = ±15V PSRR+ 10M -2 -3 -4 RL = OPEN, 100k, 10k RL = 1k RL = 499 RL = 100 -5 -6 VS = ±5V CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 1k RL = 49.9 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 26. GAIN vs FREQUENCY vs RL, VS = ±5V FN7532.3 September 21, 2011 ISL28118, ISL28218 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 -2 -3 -4 VOUT = 10mVP-P -5 VS = ±5V VOUT = 50mVP-P CL = 4pF -7 A = +1 V -8 RL = INF VOUT = 100mVP-P -6 -9100 VOUT = 500mVP-P -2 -3 10k 100k 1M VS = ±5V -5 -9 100 10M 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) FIGURE 27. GAIN vs FREQUENCY vs OUTPUT VOLTAGE 90 60 50 20 40 60 34 32 30 28 26 24 VOL 0 VOH 36 VOH AND VOL (mV) VOH AND VOL (mV) VS = ±5V 38 RL = 10k 70 VOL 22 80 100 20 -40 120 -20 TEMPERATURE (°C) 0 20 40 60 1 VOL - V- (V) V+ - VOH (V) +125°C +25°C -40°C 0.01 0.01 0.1 1 LOAD CURRENT (mA) 10 FIGURE 31. OUTPUT OVERHEAD VOLTAGE HIGH vs LOAD CURRENT, VS = ±5V and ±15V 12 120 VS = ±5V and ±15V +125°C 0.001 0.001 100 FIGURE 30. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE, VS = ±5V, RL = 10k VS = ±5V and ±15V 0.1 80 TEMPERATURE (°C) FIGURE 29. OUTPUT OVERHEAD VOLTAGE vs TEMPERATURE, VS = ±15V, RL = 10k 1 10M FIGURE 28. GAIN vs FREQUENCY vs SUPPLY VOLTAGE VOH 80 -20 1M 40 VS = ±15V RL = 10k 40 -40 VS = ±15V -6 CL = 4pF R = 10k -7 L AV = +1 -8 VOUT = 100mVP-P VOUT = 1VP-P 1k VS = ±1.5V -4 +25°C 0.1 -40°C 0.01 0.001 0.001 0.01 0.1 1 LOAD CURRENT (mA) 10 FIGURE 32. OUTPUT OVERHEAD VOLTAGE LOW vs LOAD CURRENT, VS = ±5V and ±15V FN7532.3 September 21, 2011 ISL28118, ISL28218 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 5 14 VS = ±15V 13 AV = 2 RF = RG = 100k 12 VIN = ±7.5V-DC 11 +125°C -40°C 10 -10 -11 +75°C 0°C -12 -13 +75°C 0°C +25°C -3 0 2 4 6 8 10 12 14 16 18 -5 20 0 2 4 6 I-FORCE (mA) 10 12 14 16 18 20 FIGURE 34. OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±5V 1400 1400 1200 1200 CURRENT (µA) VS = ±21V 1000 VS = ±15V 800 VS = ±2.25V 600 400 -40 8 I-FORCE (mA) FIGURE 33. OUTPUT VOLTAGE SWING vs LOAD CURRENT VS = ±15V CURRENT (µA) +125°C -4 -14 -15 4 VS = ±5V AV = 2 3 RF = RG = 100k VIN = ±2.5V-DC 2 -40°C 1 -1 -2 +25°C VOL VOL VOH VOH 15 -20 0 20 40 60 80 VS = ±21V 1000 VS = ±15V 800 VS = ±2.25V 600 100 400 -40 120 -20 TEMPERATURE (°C) 0 20 40 60 80 100 120 TEMPERATURE (°C) FIGURE 35. ISL28118 SUPPLY CURRENT vs TEMPERATURE vs SUPPLY VOLTAGE FIGURE 36. ISL28218 SUPPLY CURRENT vs TEMPERATURE vs SUPPLY VOLTAGE 1100 ISUPPLY PER AMPLIFIER (µA) 1000 900 800 700 ISL28218 ISL28118 600 500 400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 VSUPPLY (V) FIGURE 37. SUPPLY CURRENT vs SUPPLY VOLTAGE 13 FN7532.3 September 21, 2011 ISL28118, ISL28218 Typical Performance Curves VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 10 10 INPUT NOISE CURRENT 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 1 0.1 100k FIGURE 38. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±18V VS = ±5V INPUT NOISE VOLTAGE (nV/√Hz) INPUT NOISE VOLTAGE INPUT NOISE VOLTAGE INPUT NOISE CURRENT 1 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 500 VS = ±18V AV = 10k 400 300 200 100 0 -100 -200 -300 -400 VS = ±5V AV = 10k 400 300 200 100 0 -100 -200 -300 -400 -500 0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 TIME (s) 0.1 5 6 7 8 9 10 FIGURE 41. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±5V 0.1 VS = ±15V CL = 4pF RL = 2k VOUT = 10VP-P 4 TIME (s) FIGURE 40. INPUT NOISE VOLTAGE 0.1Hz TO 10Hz, VS = ±18V -40°C AV = 10 +125°C +25°C 0.01 C-WEIGHTED 22Hz TO 500kHz THD + N (%) THD + N (%) 0.1 100k 10k FIGURE 39. INPUT NOISE VOLTAGE (en) AND CURRENT (in) vs FREQUENCY, VS = ±5V INPUT NOISE VOLTAGE (nV) INPUT NOISE VOLTAGE (nV) 10 10 500 -500 100 100 INPUT NOISE CURRENT (fA/√Hz) 100 VS = ±18V INPUT NOISE CURRENT (fA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 0.001 VS = ±15V CL = 4pF RL = 10k VOUT = 10VP-P -40°C +125°C 0.01 C-WEIGHTED 22Hz TO 500kHz +25°C AV = 10 0.001 AV = 1 -40°C 0.0001 10 +25°C AV = 1 +125°C 100 1k FREQUENCY (Hz) 10k 100k FIGURE 42. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10, RL = 2k 14 -40°C 0.0001 10 +25°C 100 +125°C 1k 10k 100k FREQUENCY (Hz) FIGURE 43. THD+N vs FREQUENCY vs TEMPERATURE, AV = 1, 10, RL = 10k FN7532.3 September 21, 2011 ISL28118, ISL28218 Typical Performance Curves 1 1 C-WEIGHTED 22Hz TO 22kHz VS = ±15V CL = 4pF RL = 10k 0.1 f = 1kHz +125°C -40°C THD + N (%) THD + N (%) VS = ±15V CL = 4pF RL = 2k 0.1 f = 1kHz VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) +25°C 0.01 AV = 10 AV = 1 0.001 0.0001 0 5 15 +25°C 0.01 AV = 10 AV = 1 -40°C 20 25 30 0.0001 0 +25°C 10 5 VOUT (VP-P) FIGURE 44. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE, AV = 1, 10, RL = 2k 1.2 0.8 VOUT (V) VOUT (V) 1.6 30 0.4 0 -0.4 -2 -0.8 -4 -1.2 -1.6 -6 -2.0 -2.4 20 30 40 50 60 TIME (µs) 70 80 90 100 40 20 0 -20 -40 -60 -80 20 30 40 50 60 TIME (µs) 70 80 90 100 VS = ±5V VIN = ±5.9V 5 INPUT AND OUTPUT (V) 60 10 FIGURE 47. LARGE SIGNAL 4V STEP RESPONSE, VS = ±5V 6 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 0 100 FIGURE 46. LARGE SIGNAL 10V STEP RESPONSE, VS = ±15V VOUT (V) 25 VS = ±5V AV = 1 RL = 2k CL = 4pF 2.0 0 -100 20 2.4 VS = ±15V AV = 1 4 RL = 2k CL = 4pF 2 10 -40°C +125°C 15 VOUT (VP-P) FIGURE 45. THD+N vs OUTPUT VOLTAGE (VOUT) vs TEMPERATURE, AV = 1, 10, RL = 10k 6 0 +125°C -40°C 0.001 +125°C +25°C 10 C-WEIGHTED 22Hz TO 22kHz 4 INPUT 3 2 1 OUTPUT 0 -1 -2 -3 -4 -5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 TIME (µs) FIGURE 48. SMALL SIGNAL TRANSIENT RESPONSE, VS = ±5V, ±15V 15 1.8 2 -6 0 1 2 TIME (ms) 3 4 FIGURE 49. NO PHASE REVERSAL FN7532.3 September 21, 2011 ISL28118, ISL28218 12 -40 -4 -80 -8 -120 80 8 40 4 -160 0 40 -200 0 4 8 12 16 20 24 TIME (µs) 28 32 36 6 VS = ±5V AV = 100 5 RL = 10k VIN = 50mVP-P OVERDRIVE = 1V 4 INPUT 40 OUTPUT 1 -50 0 40 -60 0 20 24 28 32 36 0 -30 -3 OUTPUT -40 INPUT 0 4 8 12 TIME (µs) 16 20 24 -4 VS = ±5V AV = 100 RL = 10k -5 VIN = 50mVP-P OVERDRIVE = 1V -6 28 32 36 40 TIME (µs) FIGURE 52. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V FIGURE 53. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±5V 100 100 VS = ±5V VS = ±15V AV = 10 10 AV = 10 10 AV = 100 ZOUT (Ω) AV = 100 ZOUT (Ω) 24 -2 10 16 20 -20 2 12 16 -1 20 8 12 -10 3 4 8 0 30 0 4 FIGURE 51. NEGATIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V OUTPUT (V) 50 0 -12 VS = ±15V AV = 100 -16 RL = 10k VIN = 100mVP-P OVERDRIVE = 1V -20 28 32 36 40 TIME (µs) FIGURE 50. POSITIVE OUTPUT OVERLOAD RESPONSE TIME, VS = ±15V 60 OUTPUT 1 1 0.10 0.10 AV = 1 AV = 1 0.01 OUTPUT (V) 0 INPUT (mV) INPUT (mV) OUTPUT 120 INPUT INPUT (mV) INPUT (mV) 160 0 0 20 VS = ±15V AV = 100 RL = 10k 16 VIN = 100mVP-P OVERDRIVE = 1V INPUT OUTPUT (V) 200 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) OUTPUT (V) Typical Performance Curves 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 54. OUTPUT IMPEDANCE vs FREQUENCY, VS = ±15V 16 0.01 1 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 55. OUTPUT IMPEDANCE vs FREQUENCY, V S = ±5V FN7532.3 September 21, 2011 ISL28118, ISL28218 Typical Performance Curves OVERSHOOT (%) 50 60 VS = ±15V VOUT = 100mVP-P 50 AV = 1 OVERSHOOT (%) 60 VS = ±15V, VCM = 0V, RL = Open, unless otherwise specified. (Continued) 40 AV = 10 AV = -1 30 20 VS = ±5V VOUT = 100mVP-P AV = 1 40 20 10 10 0 0.001 0.010 0.100 1 10 0 0.001 100 0.01 LOAD CAPACITANCE (nF) 30 26 26 VS = ±15V 28 R = 10k L 22 ISC (mA) ISC (mA) 100 20 18 ISC-SOURCE 22 20 18 16 14 14 12 12 0 20 40 60 80 100 10 -40 120 ISC-SOURCE -20 0 20 40 60 80 100 120 TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 58. ISL28118 SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±15V FIGURE 59. ISL28218 SHORT CIRCUIT CURRENT vs TEMPERATURE, VS = ±15V CROSSTALK (dB) VS = ±15V AV = 1 10k 100k FREQUENCY (Hz) FIGURE 60. MAX OUTPUT VOLTAGE vs FREQUENCY 17 ISC-SINK 24 ISC-SINK 16 VOUT (VP-P) 10 VS = ±15V 28 R = 10k L 24 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 1k 1 FIGURE 57. OVERSHOOT vs CAPACITIVE LOAD, VS = ±5V 30 -20 0.1 LOAD CAPACITANCE (nF) FIGURE 56. OVERSHOOT vs CAPACITIVE LOAD, VS = ±15V 10 -40 AV = 10 AV = -1 30 1M 150 140 130 120 110 100 90 80 70 60 50 RL_TRANSMIT = ∞ 40 30 RL_RECEIVE = 10k RL_TRANSMIT = 2k 20 10 RL_RECEIVE = 10k 0 10 100 1k 10k 100k FREQUENCY (Hz) VS = ±15V CL = 4pF VCM = 1VP-P 1M 10M FIGURE 61. CHANNEL SEPARATION vs FREQUENCY, RL = inf, VS = ±15V FN7532.3 September 21, 2011 ISL28118, ISL28218 Applications Information Functional Description The ISL28118 and ISL28218 are single and dual, 3.2MHz, single-supply, rail-to-rail output amplifiers with a common mode input voltage range extending to a range of 0.5V below the V- rail. Their input stages are optimized for precision sensing of ground-referenced signals in single-supply applications. The input stage is able to handle large input differential voltages without phase inversion, making these amplifiers suitable for high-voltage comparator applications. Their bipolar design features high open loop gain and excellent DC input and output temperature stability. These op amps feature very low quiescent current of 850µV, and low temperature drift. Both devices are fabricated in a new precision 40V complementary bipolar DI process and are immune from latch-up. Operating Voltage Range The op amp is designed to operate over a single supply range of 3V to 40V or a split supply voltage range of +1.8V/-1.2V to ±20V. The device is fully characterized at 10V (±5V) and 30V (±15V). Both DC and AC performance remain virtually unchanged over the complete operating voltage range. Parameter variation with operating voltage is shown in the “Typical Performance Curves” beginning on page 8. The input common mode voltage to the V+ rail (V+ -1.8V over the full temperature range) may limit amplifier operation when operating from split V+ and V- supplies. Figure 12 shows the common mode input voltage range variation over temperature. Input Stage Performance The ISL28118 and ISL28218 PNP input stage has a common mode input range extending up to 0.5V below ground at +25°C (Figure 12). Full amplifier performance is guaranteed down for input voltage down to ground (V-) over the -40°C to +125°C temperature range. For common mode voltages down to -0.5V below ground (V-), the amplifiers are fully functional, but performance degrades slightly over the full temperature range. This feature provides excellent CMRR, AC performance, and DC accuracy when amplifying low-level, ground-referenced signals. The input stage has a maximum input differential voltage equal to a diode drop greater than the supply voltage (max 42V) and does not contain the back-to-back input protection diodes found on many similar amplifiers. This feature enables the device to function as a precision comparator by maintaining very high input impedance for high-voltage differential input comparator voltages. The high differential input impedance also enables the device to operate reliably in large signal pulse applications, without the need for anti-parallel clamp diodes required on MOSFET and most bipolar input stage op amps. Thus, input signal distortion caused by nonlinear clamps under high slew rate conditions is avoided. In applications where one or both amplifier input terminals are at risk of exposure to voltages beyond the supply rails, current-limiting resistors may be needed at each input terminal (see Figure 62, RIN+, RIN-) to limit current through the power-supply ESD diodes to 20mA. V+ VINVIN+ RIN- - RIN+ + RF RL RG V- FIGURE 62. INPUT ESD DIODE CURRENT LIMITING Output Drive Capability The bipolar rail-to-rail output stage features low saturation levels that enable an output voltage swing to less than 15mV when the total output load (including feedback resistance) is held below 50µA (Figures 31 and 32). With ±15V supplies, this can be achieved by using feedback resistor values >300kΩ. The output stage is internally current limited. Output current limit over temperature is shown in Figures 33 and 34. The amplifiers can withstand a short circuit to either rail as long as the power dissipation limits are not exceeded. This applies to only one amplifier at a time for the dual op amp. Continuous operation under these conditions may degrade long-term reliability. The amplifiers perform well when driving capacitive loads (Figures 56 and 57). The unity gain, voltage follower (buffer) configuration provides the highest bandwidth but is also the most sensitive to ringing produced by load capacitance found in BNC cables. Unity gain overshoot is limited to 35% at capacitance values to 0.33nF. At gains of 10 and higher, the device is capable of driving more than 10nF without significant overshoot. Output Phase Reversal Output phase reversal is a change of polarity in the amplifier transfer function when the input voltage exceeds the supply voltage. The ISL28118 and ISL28218 are immune to output phase reversal out to 0.5V beyond the rail (VABS MAX) limit (Figure 49). Single Channel Usage The ISL28218 is a dual op amp. If the application requires only one channel, the user must configure the unused channel to prevent it from oscillating. The unused channel oscillates if the input and output pins are floating. This results in higher-than-expected supply currents and possible noise injection into the channel being used. The proper way to prevent oscillation is to short the output to the inverting input, and ground the positive input (Figure 63). + FIGURE 63. PREVENTING OSCILLATIONS IN UNUSED CHANNELS 18 FN7532.3 September 21, 2011 ISL28118, ISL28218 Power Dissipation ISL28118 and ISL28218 SPICE Model It is possible to exceed the +150°C maximum junction temperatures under certain load and power supply conditions. It is therefore important to calculate the maximum junction temperature (TJMAX) for all applications to determine if power supply voltages, load conditions, or package type need to be modified to remain in the safe operating area. These parameters are related using Equation 1: Figure 64 shows the SPICE model schematic and Figure 65 shows the net list for the SPICE model. The model is a simplified version of the actual device and simulates important AC and DC parameters. AC parameters incorporated into the model are: 1/f and flatband noise voltage, slew rate, CMRR, and gain and phase. The DC parameters are IOS, total supply current, and output voltage swing. The model uses typical parameters given in the “Electrical Specifications” table beginning on page 4. The AVOL is adjusted for 136dB with the dominant pole at 0.6Hz. The CMRR is set at 120dB, f = 50kHz. The input stage models the actual device to present an accurate AC representation. The model is configured for an ambient temperature of +25°C. T JMAX = T MAX + θ JA xPD MAXTOTAL (EQ. 1) where • PDMAXTOTAL is the sum of the maximum power dissipation of each amplifier in the package (PDMAX) • TMAX = Maximum ambient temperature • ΘJA = Thermal resistance of the package PDMAX for each amplifier can be calculated using Equation 2: V OUTMAX PD MAX = V S × I qMAX + ( V S - V OUTMAX ) × -----------------------R (EQ. 2) L where • PDMAX = Maximum power dissipation of 1 amplifier • VS = Total supply voltage • IqMAX = Maximum quiescent supply current of one amplifier • VOUTMAX = Maximum output voltage swing of the application • RL = Load resistance Figures 66 through 80 show the characterization vs simulation results for the noise voltage, open loop gain phase, closed loop gain vs frequency, gain vs frequency vs RL, CMRR, large signal 10V step response, small signal 0.1V step, and output voltage swing ±15V supplies. LICENSE STATEMENT The information in the SPICE model is protected under United States copyright laws. Intersil Corporation hereby grants users of this macro-model, hereto referred to as “Licensee”, a nonexclusive, nontransferable licence to use this model, as long as the Licensee abides by the terms of this agreement. Before using this macro-model, the Licensee should read this license. If the Licensee does not accept these terms, permission to use the model is not granted. The Licensee may not sell, loan, rent, or license the macro-model, in whole, in part, or in modified form, to anyone outside the Licensee’s company. The Licensee may modify the macro-model to suit his/her specific applications, and the Licensee may make copies of this macro-model for use within their company only. This macro-model is provided “AS IS, WHERE IS, AND WITH NO WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUY NOT LIMITED TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.” In no event will Intersil be liable for special, collateral, incidental, or consequential damages in connection with or arising out of the use of this macro-model. Intersil reserves the right to make changes to the product and the macro-model without prior notice. 19 FN7532.3 September 21, 2011 DX I1 80e-6 I2 54E-6 R2 5e11 3 0 750 R1 5e11 8 IOS 4e-9 Vcm En R18 DX V3 -0.91 18 +R9 GAIN = 1 1e-3 19 Vg R6 G2 1 GAIN = 0.65897 D4 Input Stage 1st Gain Stage V++ V++ V++ R13 795.7981 G9 + GAIN = 1.2566e-3 D7 DX C3 10e-12 L3 3.18319E-09 21 R11 1e-3 Vc D10 D11 V5 24 -0.4 23 26 R15 80 G13 GAIN = 12.5e-3 Vout VOUT 27 Vmid ISY D8 DX 22 G8 L4 L2 3.18319E-09 3.18319E-09 GAIN = 1 GAIN = 1 GAIN = 1.2566e-3 R14 795.7981 V-FN7532.3 September 21, 2011 Mid Supply ref V D9 G11 G12 D12 + + GAIN = 12.5e-3 GAIN = 12.5e-3 V-V- 2nd Gain Stage -0.4 C4 10e-12 DY 20 G10 DY + - D6 R12 1e-3 G6 + - GAIN = 1.69138e-3 R10 1e-3 + - 17 G4 + -+ GAIN = 0.5 C2 6.6667E-11 3.7304227e9 + - -0.96 V6 25 DX V4 Common Mode Gain Stage with Zero E3 + -+ GAIN = 1 V-- 0 FIGURE 64. SPICE SCHEMATIC Output Stage Correction Current Sources + - 2.5E-3 G14 GAIN = 12.5e-3 R16 80 ISL28118, ISL28218 C1 R7 6.6667E-11 3.7304227e9 G5 + GAIN = 1 15 DX 16 V2 -0.96 V-- GAIN = 1 L1 3.18319E-09 GAIN = 1 DX + GAIN = 1.69138e-3 D5 12 V-- V+ E2 + -+ - 14 EOS +- + - PNP_LATERAL R4 1k 6 Cin2 4.02e-12 Cin1 4.02e-12 0 10 11 R3 1k Vin+ GAIN = 0.3 Q6 Q7 PNP_input Q9 Q8 PNP_input D2DBREAK CinDif 1.33E-12 5 D14 7 DX R17 2 + - +- 750 DN 20 0 PNP_LATERAL V8 4 D13 DN V7 -0.91 +- 1 1 GAIN = 0.65897 V1 D1DBREAK 0.1 R5 13 - 0.1 G1 + - I3 54E-6 9 Vin- D3 ISL28118, ISL28218 *ISL28118_218 Macromodel - covers following *products *ISL28118 *ISL28218 * *Revision History: * Revision A, LaFontaine February 8th 2011 * Model for Noise, supply currents, CMRR *120dB f = 40kHz, AVOL 136dB f = 0.5Hz * SR = 1.2V/us, GBWP 4MHz. *Copyright 2011 by Intersil Corporation *Refer to data sheet “LICENSE STATEMENT” *Use of this model indicates your acceptance *with the terms and provisions in the License *Statement. * *Intended use: *This Pspice Macromodel is intended to give *typical DC and AC performance characteristics *under a wide range of external circuit *configurations using compatible simulation *platforms – such as iSim PE. * *Device performance features supported by this *model: *Typical, room temp., nominal power supply *voltages used to produce the following *characteristics: *Open and closed loop I/O impedances, *Open loop gain and phase, *Closed loop bandwidth and frequency *response, *Loading effects on closed loop frequency *response, *Input noise terms including 1/f effects, *Slew rate, *Input and Output Headroom limits to I/O *voltage swing, *Supply current at nominal specified supply *voltages, * *Device performance features NOT supported *by this model: *Harmonic distortion effects, *Output current limiting (current will limit at *40mA), *Disable operation (if any), *Thermal effects and/or over temperature *parameter variation, *Limited performance variation vs. supply *voltage is modeled, *Part to part performance variation due to *normal process parameter spread, *Any performance difference arising from *different packaging, *Load current reflected into the power supply *current. * source ISL28118_218 SPICEmodel * * Connections: +input * | -input * | | +Vsupply * | | | -Vsupply * | | | | output .subckt ISL28118_218 Vin+ Vin-V+ V- VOUT * source ISL28118_218_presubckt_0 * *Voltage Noise E_En VIN+ 6 2 0 0.3 D_D13 1 2 DN D_D14 1 2 DN V_V7 1 0 0.1 V_V8 4 0 0.1 R_R17 2 0 750 *R_R18 3 0 750 * *Input Stage Q_Q6 11 10 9 PNP_input Q_Q7 8 7 9 PNP_input Q_Q8 V-- VIN- 7 PNP_LATERAL Q_Q9 V-- 12 10 PNP_LATERAL I_I1 V++ 9 DC 80e-6 I_I2 V++ 7 DC 54E-6 I_I3 V++ 10 DC 54E-6 I_IOS 6 VIN- DC 4e-9 *D_D1 7 10 DBREAK *D_D2 10 7 DBREAK R_R1 5 6 5e11 R_R2 VIN- 5 5e11 R_R3 V-- 8 1000 R_R4 V-- 11 1000 C_Cin1 V-- VIN- 4.02e-12 C_Cin2 V-- 6 4.02e-12 C_CinDif 6 VIN- 1.33E-12 * *1st Gain Stage G_G1 V++ 14 8 11 0.65897 G_G2 V-- 14 8 11 0.65897 V_V1 13 14 -0.91 V_V2 14 15 -0.96 D_D3 13 V++ DX D_D4 V-- 15 DX R_R5 14 V++ 1 R_R6 V-- 14 1 * *2nd Gain Stage G_G3 V++ VG 14 VMID 1.69138e-3 G_G4 V-- VG 14 VMID 1.69138e-3 V_V3 16 VG -0.91 V_V4 VG 17 -0.96 D_D5 16 V++ DX D_D6 V-- 17 DX R_R7 VG V++ 3.7304227e9 R_R8 V-- VG 3.7304227e9 C_C1 VG V++ 6.6667E-11 C_C2 V-- VG 6.6667E-11 * *Mid supply Ref E_E2 V++ 0 V+ 0 1 E_E3 V-- 0 V- 0 1 E_E4 VMID V-- V++ V-- 0.5 I_ISY V+ V- DC 0.85E-3 * *Common Mode Gain Stage with Zero G_G5 V++ 19 5 VMID 1 G_G6 V-- 19 5 VMID 1 G_G7 V++ VC 19 VMID 1 G_G8 V-- VC 19 VMID 1 E_EOS 12 6 VC VMID 1 L_L1 18 V++ 3.18319E-09 L_L2 20 V-- 3.18319E-09 L_L3 21 V++ 3.18319E-09 L_L4 22 V-- 3.18319E-09 R_R9 19 18 1e-3 R_R10 20 19 1e-3 R_R11 VC 21 1e-3 R_R12 22 VC 1e-3 * *Pole Stage G_G9 V++ 23 VG VMID 1.2566e-3 G_G10 V-- 23 VG VMID 1.2566e-3 R_R13 23 V++ 795.7981 R_R14 V-- 23 795.7981 C_C3 23 V++ 10e-12 C_C4 V-- 23 10e-12 * *Output Stage with Correction Current Sources G_G11 26 V-- VOUT 23 12.5e-3 G_G12 27 V-- 23 VOUT 12.5e-3 G_G13 VOUT V++ V++ 23 12.5e-3 G_G14 V-- VOUT 23 V-- 12.5e-3 D_D7 23 24 DX D_D8 25 23 DX D_D9 V-- 26 DY D_D10 V++ 26 DX D_D11 V++ 27 DX D_D12 V-- 27 DY V_V5 24 VOUT -0.4 V_V6 VOUT 25 -0.4 R_R15 VOUT V++ 80 R_R16 V-- VOUT 80 .model PNP_LATERAL pnp(is=1e-016 bf=250 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model PNP_input pnp(is=1e-016 bf=100 va=80 + ik=0.138 rb=0.01 re=0.101 rc=180 kf=0 af=1) .model DBREAK D(bv=43 rs=1) .model DN D(KF=6.69e-9 AF=1) .MODEL DX D(IS=1E-12 Rs=0.1) .MODEL DY D(IS=1E-15 BV=50 Rs=1) .ends ISL28118_218 FIGURE 65. SPICE NET LIST 21 FN7532.3 September 21, 2011 ISL28118, ISL28218 Characterization vs Simulation Results INPUT NOISE VOLTAGE 10 10 INPUT NOISE CURRENT 1 0.1 0.1 1 10 100 1k FREQUENCY (Hz) 10k 1 0.1 100k 100 INPUT NOISE VOLTAGE (nV/√Hz) 100 VS = ±18V INPUT NOISE CURRENT (fA/√Hz) INPUT NOISE VOLTAGE (nV/√Hz) 100 10 1 0.1 0.1 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 PHASE GAIN 1 10 10 100 1k 10k 100k 1M 10M100M 1G 200 180 160 140 120 100 80 60 40 20 0 -20 -40 -60 VS = ±15V -80 RL = 1MΩ -100 1m 0.01 0.1 FREQUENCY (Hz) GAIN (dB) 40 VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 30 20 60 RF = 10kΩ, RG = 100Ω 50 ACL = 10 10 0 -10 100 RF = 10kΩ, RG = 1kΩ 100k 1M 10M FREQUENCY (Hz) FIGURE 70. CHARACTERIZED CLOSED-LOOP GAIN vs FREQUENCY 22 1 10 100 1k 10k 100k 1M 10M100M 1G RF = 10kΩ, RG = 10Ω RF = 10kΩ, RG = 100Ω 50 40 VS = ±5V & ±15V CL = 4pF RL = 2k VOUT = 100mVP-P ACL = 100 30 20 ACL = 10 0 RF = 0, RG = ∞ 10k GAIN ACL = 1000 10 ACL = 1 1k PHASE 70 GAIN (dB) 60 100k FIGURE 69. SIMULATED OPEN-LOOP GAIN, PHASE vs FREQUENCY RF = 10kΩ, RG = 10Ω ACL = 1000 10k FREQUENCY (Hz) FIGURE 68. CHARACTERIZED OPEN-LOOP GAIN, PHASE vs FREQUENCY 70 100 1k FREQUENCY (Hz) FIGURE 67. SIMULATED INPUT NOISE VOLTAGE GAIN (dB) GAIN (dB) FIGURE 66. CHARACTERIZED INPUT NOISE VOLTAGE 1 -10 100 RF = 10kΩ, RG = 1kΩ ACL = 1 RF = 0, RG = ∞ 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 71. SIMULATED CLOSED-LOOP GAIN vs FREQUENCY FN7532.3 September 21, 2011 ISL28118, ISL28218 Characterization vs Simulation Results 1 0 0 -1 -1 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 1 (Continued) -2 -3 -4 RL = OPEN, 100k, 10k -5 RL = 1k RL = 499k RL = 100k VS = ±15V -6 CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 1k RL = 49.9k 10k 100k 1M -2 -3 -4 RL = OPEN, 100k, 10k -5 CL = 4pF -7 A = +1 V -8 VOUT = 100mVp-p -9 100 10M 1k CMRR (dB) CMRR (dB) 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 6 2 0 0 -2 -2 -4 -4 -6 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 76. CHARACTERIZED LARGE-SIGNAL 10V STEP RESPONSE 23 10 100 1k 10k 100k 1M 10M 100M 1G FREQUENCY (Hz) VS = ±15V AV = 1 RL = 2k CL = 4pF 4 VOUT (V) VOUT (V) VS = ±15V AV = 1 4 RL = 2k CL = 4pF 2 20 10M FIGURE 75. SIMULATED CMRR vs FREQUENCY 6 10 1M FIGURE 73. SIMULATED GAIN vs FREQUENCY vs RL FIGURE 74. CHARACTERIZED CMRR vs FREQUENCY 0 100k FREQUENCY (Hz) FIGURE 72. CHARACTERIZED GAIN vs FREQUENCY vs RL -6 RL = 49.9k 10k FREQUENCY (Hz) 140 130 120 110 100 90 80 70 60 50 40 30 VS = ±15V 20 SIMULATION 10 0 1m 0.01 0.1 1 RL = 1k RL = 499k RL = 100k VS = ±15V -6 0 10 20 30 40 50 60 TIME (µs) 70 80 90 100 FIGURE 77. SIMULATED LARGE-SIGNAL 10V STEP RESPONSE FN7532.3 September 21, 2011 ISL28118, ISL28218 Characterization vs Simulation Results 100 40 20 60 40 0 -20 20 0 -20 -40 -40 -60 -60 -80 -80 -100 -100 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 VOUT (V) 60 VOUT (V) 100 VS = ±15V AND VS = ±5V AV = 1 RL = 2k CL = 4pF 80 (Continued) 2.0 0 0.2 0.4 0.6 TIME (µs) 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TIME (µs) FIGURE 78. CHARACTERIZED SMALL-SIGNAL TRANSIENT RESPONSE FIGURE 79. SIMULATED SMALL-SIGNAL TRANSIENT RESPONSE OUTPUT VOLTAGE SWING (V) 20V VOH = 14.88V 10V 0V -10V VS = ±15V RL = 10kΩ VOL = -14.93V -20V 0 0.5 1.0 TIME (ms) 1.5 2.0 FIGURE 80. SIMULATED OUTPUT VOLTAGE SWING 24 FN7532.3 September 21, 2011 ISL28118, ISL28218 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE 8/31/2011 FN7532.3 Page 7: Electrical Spec Table for Supply Current/Amplifier Change from: 1.4µA Full Temp Max Change to: 1.4mA Full Temp Max Page 28: Updated POD M8.118 to current revision. Corrected lead width dimension in side view 1 from "0.25 0.036" to "0.25 - 0.36". 5/9/2011 FN7532.2 Page 2: Added NC pin to Pin Descriptions table. Page 3: Added ISL28218EVAL1Z evaluation board to the Ordering Information table. Page 12: Added new Output Overhead Voltage plots (Figs. 31,32) Pages 19 through 24: Added SPICE model schematic, netlist, description and Figs. 66 through 80. 11/12/10 FN7532.1 On page 1: Features Section, added Low input offset voltage and superb offset voltage temperature drift for ISL28118. Updated Intersil trademark statement (bottom of page) On page 3: Removed “coming soon” from ISL28118FBZ. Updated tape & reel note. On page 4: Change ISL28118 Theta JA value from 158 to 165. Added ISL28118 min/max specs to VOS (input offset voltage), TCVOS and min specs to CMRR. On page 5: Added AVOL MIN spec for ISL28118 in dB. Changed existing AVOL spec from V/mV to dB. Added VOL max spec for ISL28118, IS Typ and Max spec for ISL28118. Changed TS from 18µs to 8.5µs. On page 6: Added Min Max VOS spec, TCVOS spec for ISL28118. Changed AVOL specs from V/mV to dB. On page 7: Changed Slew Rate TYP from ±1.2V/µs to ±1V/µs. Added for TS TYP spec = 4µs. Changed min/max note 8 to “Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.” Added Figs 3 & 4 for ISL28118. Figures 5 & 6 moved to page 8. On page 8: Added Figures 7 & 8 On page 10: Added Figures 15 & 16 for ISL28118 On page 10, in Figure 19, changed VS from ±5V to ±15V On page 12 and page 13: Added Figures 27, 28, 31 & 34 for ISL28118 On page 13: Added Figure 35 for ISL28118 On page 14: Figure 41 changed VS from ±18V to ±5V, Figure 42 added RL = 2k, Figure 43 added RL = 10k and corrected "HD+N" to "THD+N" On page 15, Figure 44 added RL = 2k, Figure 45 RL = 10k. On page 17: Added Figure 58 for ISL28118 On page 17, Figure 58 and 59, graph upper left corner changed VS = ±5V to VS = ±15V On page 17, Figure 61, deleted VS = ±5V 9/16/10 FN7532.0 Initial Release Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. *For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL28118, ISL28218. To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 25 FN7532.3 September 21, 2011 ISL28118, ISL28218 Package Outline Drawing L8.3x3A 8 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE Rev 4, 2/10 ( 2.30) 3.00 ( 1.95) A B 3.00 ( 8X 0.50) 6 PIN 1 INDEX AREA (4X) (1.50) ( 2.90 ) 0.15 PIN 1 TOP VIEW (6x 0.65) ( 8 X 0.30) TYPICAL RECOMMENDED LAND PATTERN SEE DETAIL "X" 2X 1.950 PIN #1 INDEX AREA 0.10 C 0.75 ±0.05 6X 0.65 C 0.08 C 1 SIDE VIEW 6 1.50 ±0.10 8 8X 0.30 ±0.05 8X 0.30 ± 0.10 2.30 ±0.10 C 4 0.10 M C A B 0 . 2 REF 5 0 . 02 NOM. 0 . 05 MAX. DETAIL "X" BOTTOM VIEW NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to ASME Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension applies to the metallized terminal and is measured between 0.15mm and 0.20mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be 7. Compliant to JEDEC MO-229 WEEC-2 except for the foot length. either a mold or mark feature. 26 FN7532.3 September 21, 2011 ISL28118, ISL28218 Package Outline Drawing M8.15E 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE Rev 0, 08/09 4 4.90 ± 0.10 A DETAIL "A" 0.22 ± 0.03 B 6.0 ± 0.20 3.90 ± 0.10 4 PIN NO.1 ID MARK 5 (0.35) x 45° 4° ± 4° 0.43 ± 0.076 1.27 0.25 M C A B SIDE VIEW “B” TOP VIEW 1.75 MAX 1.45 ± 0.1 0.25 GAUGE PLANE C SEATING PLANE 0.10 C 0.175 ± 0.075 SIDE VIEW “A 0.63 ±0.23 DETAIL "A" (0.60) (1.27) NOTES: (1.50) (5.40) 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Dimension does not include interlead flash or protrusions. Interlead flash or protrusions shall not exceed 0.25mm per side. 5. The pin #1 identifier may be either a mold or mark feature. 6. Reference to JEDEC MS-012. TYPICAL RECOMMENDED LAND PATTERN 27 FN7532.3 September 21, 2011 ISL28118, ISL28218 Package Outline Drawing M8.118 8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE Rev 4, 7/11 5 3.0±0.05 A DETAIL "X" D 8 1.10 MAX SIDE VIEW 2 0.09 - 0.20 4.9±0.15 3.0±0.05 5 0.95 REF PIN# 1 ID 1 2 B 0.65 BSC GAUGE PLANE TOP VIEW 0.55 ± 0.15 0.25 3°±3° 0.85±010 H DETAIL "X" C SEATING PLANE 0.25 - 0.36 0.08 M C A-B D 0.10 ± 0.05 0.10 C SIDE VIEW 1 (5.80) NOTES: (4.40) (3.00) 1. Dimensions are in millimeters. (0.65) (0.40) (1.40) TYPICAL RECOMMENDED LAND PATTERN 28 2. Dimensioning and tolerancing conform to JEDEC MO-187-AA and AMSEY14.5m-1994. 3. Plastic or metal protrusions of 0.15mm max per side are not included. 4. Plastic interlead protrusions of 0.15mm max per side are not included. 5. Dimensions are measured at Datum Plane "H". 6. Dimensions in ( ) are for reference only. FN7532.3 September 21, 2011