Data Sheet

Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08SC4
Rev. 4, 6/2010
MC9S08SC4 8-Bit
Microcontroller Data Sheet
MC9S08SC4
948F-01
8-Bit HCS08 Central Processor Unit (CPU)
•
•
Up to 40 MHz HCS08 CPU (central processor unit); up
to 20 MHz bus frequency
HC08 instruction set with added BGND instruction
•
Peripherals
• SCI — Serial Communication Interface
—
—
—
—
On-Chip Memory
•
•
4 KB of FLASH with read/program/erase over full
operating voltage and temperature
256 bytes of Random-access memory (RAM)
Power-Saving Modes
•
•
•
Two very low power stop modes
Reduced power wait mode
Clock Source Options
•
•
Oscillator (XOSC) — Loop-control Pierce oscillator;
Crystal or ceramic resonator range of 32 kHz to 38.4 kHz
or 1 MHz to 16 MHz
Internal Clock Source (ICS) — Internal clock source
module containing a frequency-locked loop (FLL)
controlled by internal or external reference; precision
trimming of internal reference allows 0.2 % resolution
and 2.0 % deviation over temperature and voltage;
supports bus frequencies from 2 MHz to 20 MHz.
System Protection
•
•
•
•
•
•
Watchdog computer operating properly (COP) reset with
option to run from dedicated 1 kHz internal clock source
or bus clock
Low-voltage detection with reset or interrupt; selectable
trip points
Illegal opcode detection with reset
Illegal address detection with reset
FLASH block protect
Reset on loss of clock
Development Support
•
Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
•
Full-duplex non-return to zero (NRZ)
LIN master extended break generation
LIN slave extended break detection
Wake-up on active edge
TPMx — Two 2-channel Timer/PWM modules (TPM1
and TPM2)
— 16-bit modulus or up/down counters
— Input capture, output compare, buffered
edge-aligned or center-aligned PWM
ADC — Analog to Digital Converter
— 8-channel, 10-bit resolution
— 2.5 μs conversion time
— Automatic compare function
— Temperature sensor
— Internal bandgap reference channel
Input/Output
•
•
•
12 general purpose I/O pins (GPIOs)
8 interrupt pins with selectable polarity
Hysteresis and configurable pull-up device on all input
pins; Configurable slew rate and drive strength on all
output pins.
Package Options
•
16-TSSOP
Operating Parameters
•
•
4.5-5.5 V operation
C,V, M temperature ranges available, covering -40 125 °C operation
Single-wire background debug interface
Freescale reserves the right to change the detail specifications as may be required to permit
improvements in the design of its products.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Table of Contents
Chapter 1
Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Chapter 2
Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chapter 3
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . . .7
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . .7
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .8
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . . .9
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .13
3.8 External Oscillator (XOSC) Characteristics . . . . . . . . .16
3.9 Internal Clock Source (ICS) Characteristics . . . . . . . .
3.10 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .
3.11.2 TPM Module Timing . . . . . . . . . . . . . . . . . . . . .
3.12 Flash Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . .
Chapter 4
Ordering Information and Mechanical Drawings . . . . . . . . . .
4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .
4.1.1 Device Numbering Scheme . . . . . . . . . . . . . . .
4.2 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 5
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18
19
21
21
22
23
24
24
25
25
25
25
25
29
MC9S08SC4 MCU Series Data Sheet, Rev. 4
2
Freescale Semiconductor
Chapter 1
Device Overview
The MC9S08SC4 is a member of the low-cost, high-performance HCS08 Family of 8-bit microcontroller units (MCUs). The
MC9S08SC4 uses the enhanced HCS08 core.
1.1
MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08SC4 MCU.
PTA3/PIA3/ADP3
PORT A
HCS08 CORE
BKGD/MS
CPU
BDC
HCS08 SYSTEM CONTROL
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
COP
LVD
USER FLASH
(MC9S08SC4 = 4096 BYTES)
PTA1/PIA1/TPM2CH0/ADP1
PTA0/PIA0/TPM1CH0/TCLK/ADP0
TCLK
TPM1CH0
16-BIT TIMER/PWM
MODULE (TPM1)
TPM1CH1
PTB7/EXTAL
PTB6/XTAL
TCLK
TPM2CH0
16-BIT TIMER/PWM
MODULE (TPM2)
TPM2CH1
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI)
RxD
TxD
PORT B
RESET
PTA2/PIA2/ADP2
PTB5/TPM1CH1
PTB4/TPM2CH1
PTB3/PIB3/ADP7
PTB2/PIB2/ADP6
PTB1/PIB1/TxD/ADP5
PTB0/PIB0/RxD/ADP4
USER RAM
(MC9S08SC4 = 256 BYTES)
SEE NOTE 1
VDD
40-MHz INTERNAL CLOCK
SOURCE (ICS)
LOW-POWER OSCILLATOR
32 kHz to 38.4 kHz
1 MHz to 16 MHz
VOLTAGE
REGULATOR
VSS
EXTAL
VDDA
VSSA
XTAL
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
ADP7-ADP0
VREFH
VREFL
NOTES
1:
VDDA/VREFH and VSSA/VREFL, are derived from VDD and VSS respectively.
Figure 1-1. MC9S08SC4 Block Diagram
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
3
Chapter 1 Device Overview
MC9S08SC4 MCU Series Data Sheet, Rev. 4
4
Freescale Semiconductor
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended system connections, and
detailed discussions of signals.
2.1
Device Pin Assignment
The following figure shows the pin assignments for the MC9S08SC4 device.
1
2
3
4
5
6
7
8
RESET
BKGD/MS
VDD
VSS
PTB7/EXTAL
PTB6/XTAL
PTB5/TPM1CH1
PTB4/TPM2CH1
16
15
14
13
12
11
10
9
PTA0/PIA0/TPM1CH0/TCLK/ADP0
PTA1/PIA1/TPM2CH0/ADP1
PTA2/PIA2/ADP2
PTA3/PIA3/ADP3
PTB0/PIB0/RxD/ADP4
PTB1/PIB1/TxD/ADP5
PTB2/PIB2/ADP6
PTB3/PIB3/ADP7
Table 2-1. Pin Function Priority
Pin
Number
16-pin
Priority
Lowest
Port Pin
Highest
Alt 1
Alt 2
Alt 3
1
Alt 4
RESET
2
BKGD
MS
3
VDD
4
VSS
5
PTB7
EXTAL
6
PTB6
7
PTB5
TPM1CH1
XTAL
8
PTB4
TPM2CH1
9
PTB3
PIB3
10
PTB2
PIB2
11
PTB1
PIB1
ADP7
ADP6
TxD
ADP5
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
5
Chapter 2 Pins and Connections
Table 2-1. Pin Function Priority (continued)
Pin
Number
16-pin
Priority
Lowest
Port Pin
Highest
Alt 1
Alt 2
Alt 3
RxD
Alt 4
12
PTB0
PIB0
ADP4
13
PTA3
PIA3
ADP3
14
PTA2
PIA2
ADP2
15
PTA1
PIA1
TPM2CH0
16
PTA0
PIA0
TPM1CH0
ADP1
TCLK
ADP0
MC9S08SC4 MCU Series Data Sheet, Rev. 4
6
Freescale Semiconductor
Chapter 3
Electrical Characteristics
3.1
Introduction
This section contains electrical and timing specifications for the MC9S08SC4 Series of microcontrollers available at the time
of publication.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3-1. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD) or the programmable pull-up resistor associated with the pin is enabled.
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
7
Chapter 3 Electrical Characteristics
Table 3-2. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Supply voltage
VDD
–0.3 to +5.8
V
Maximum current into VDD
IDD
120
mA
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
± 25
mA
Tstg
–55 to 150
°C
Storage temperature range
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
All functional non-supply pins are internally clamped to VSS and VDD.
3
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low (which would reduce overall power
consumption).
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and
it is user-determined rather than being controlled by the MCU design. To take PI/O into account in power calculations, determine
the difference between actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of
unusually high pin current (heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 3-3. Thermal Characteristics
Num
C
Rating
Symbol
1
—
Operating temperature range (packaged)
C
D
Unit
TL to TH
TA
–40 to 85
V
–40 to 105
M
–40 to 125
Maximum junction temperature
2
Value
°C
—
C
TJM
95
V
115
M
135
°C
1,2
Thermal resistance
Single-layer board
3
D
16-pin TSSOP
θJA
130
°C/W
16-pin TSSOP
θJA
87
°C/W
resistance1,2
Thermal
Four-layer board
4
D
MC9S08SC4 MCU Series Data Sheet, Rev. 4
8
Freescale Semiconductor
Chapter 3 Electrical Characteristics
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board,
and board thermal resistance.
2
Junction to Ambient Natural Convection
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 3-1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
PD = K ÷ (TJ + 273°C)
Eqn. 3-2
Solving Equation 3-1 and Equation 3-2 for K gives:
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3-3
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 3-1 and Equation 3-2
iteratively for any value of TA
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits. During
the device qualification ESD stresses were performed for the human body model (HBM) and the charge device model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 3-4. ESD and Latch-up Test Conditions
Model
Human
Body
Latch-up
Description
Symbol
Value
Unit
Series resistance
R1
1500
Ω
Storage capacitance
C
100
pF
Number of pulses per pin
—
3
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
9
Chapter 3 Electrical Characteristics
Table 3-5. ESD and Latch-Up Protection Characteristics
Rating1
No.
1
3.6
Symbol
Min
Max
Unit
1
Human body model (HBM)
VHBM
± 2000
—
V
2
Charge device model (CDM)
VCDM
± 500
—
V
3
Latch-up current at TA = 125°C
ILAT
± 100
—
mA
Parameter is achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted.
DC Characteristics
This section includes information about power supply requirements and I/O pin characteristics.
Table 3-6. DC Characteristics
Num C
4
Typ1
Max
Unit
VDD
—
4.5
—
5.5
V
5 V, ILoad = –4 mA
VDD – 1.5
—
—
5 V, ILoad = –2 mA
VDD – 0.8
—
—
All I/O pins,
5 V, ILoad = –20 mA
VDD – 1.5
—
—
high-drive strength
5 V, ILoad = –10 mA
VDD – 0.8
—
—
VOUT < VDD
0
—
–100
5 V, ILoad = 4 mA
—
—
1.5
5 V, ILoad = 2 mA
—
—
0.8
All I/O pins
5 V, ILoad = 20 mA
—
—
1.5
high-drive strength
5 V, ILoad = 10 mA
—
—
0.8
VOUT > VSS
0
—
100
low-drive strength
C voltage
C
Max total IOH for
all ports
Output high
current
C
7
Min
All I/O pins,
P Output high
P
6
Condition
— Operating voltage
C
5
Symbol
Characteristic
low-drive strength
C voltage
P
C
IOHT
All I/O pins
P Output low
8
VOH
Output low
current
Max total IOL for all ports
VOL
IOLT
V
mA
V
mA
9
P Input high voltage; all digital inputs
VIH
5V
0.65 x VDD
—
—
V
10
P Input low voltage; all digital inputs
VIL
5V
—
—
0.35 x VDD
V
11
C Input hysteresis
Vhys
0.06 x VDD
—
—
V
12
P Input leakage current (per pin)
|IIn|
—
VIn = VDD or VSS
—
0.1
1
μA
|IOZ|
VIn = VDD or VSS,
—
0.1
1
μA
VIn = VDD or VSS
—
0.2
2
μA
—
17
37
52
kΩ
17
37
52
kΩ
P
13
Hi-Z (off-state) leakage current (per pin)
input/output port pins
PTB6/XTAL,RESET
2
Pull-up or Pull-down resistors; when
enabled
14
P
C
I/O pins RPU,RPD
RESET
3
RPU
MC9S08SC4 MCU Series Data Sheet, Rev. 4
10
Freescale Semiconductor
Chapter 3 Electrical Characteristics
Table 3-6. DC Characteristics (continued)
Num C
Characteristic
D DC injection current
Symbol
Min
Typ1
Max
Unit
VIN > VDD
0
—
2
mA
4, 5, 6, 7
Single pin limit
VIN < VSS,
0
—
–0.2
mA
Total MCU limit, includes
VIN > VDD
0
—
25
mA
sum of all stressed pins
VIN < VSS,
0
—
–5
mA
CIn
—
—
—
8
pF
IIC
15
16
Condition
D Input Capacitance, all pins
17
D RAM retention voltage
VRAM
—
—
0.6
1.0
V
18
D POR re-arm voltage8
VPOR
—
0.9
1.4
2.0
V
tPOR
—
10
—
—
μs
3.85
3.95
4.0
4.1
4.15
4.25
V
4.45
4.55
4.6
4.7
4.75
4.85
V
4.15
4.25
4.3
4.4
4.45
4.55
V
9
19
D POR re-arm time
20
P Low-voltage detection threshold —
high range
VDD falling
VDD rising
21
Low-voltage warning threshold —
P high range 1
VDD falling
VDD rising
22
Low-voltage warning threshold —
P high range 0
VDD falling
VDD rising
23
T Low-voltage inhibit reset/recover
hysteresis
Vhys
24
10
P Bandgap Voltage Reference
VBG
—
VLVD1
—
VLVW3
—
VLVW2
—
—
100
—
mV
—
1.17
1.20
1.22
V
1
Typical values are measured at 25°C. Characterized, not tested.
When a pin interrupt is configured to detect rising edges, pull-down resistors are used in place of pull-up resistors.
3 The specified resistor value is the actual value internal to the device. The pull-up value may measure higher when measured
externally on the pin.
4 Power supply must maintain regulation within operating V
DD range during instantaneous and operating maximum current
conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current may flow out of VDD and could result
in external power supply going out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if no system clock is present, or if
clock rate is very low (which would reduce overall power consumption).
5 All functional non-supply pins are internally clamped to V
SS and VDD.
6 Input must be current limited to the value specified. To determine the value of the required current-limiting resistor, calculate
resistance values for positive and negative clamp voltages, then use the larger of the two values.
7 The RESET pin does not have a clamp diode to V . Do not drive this pin above V .
DD
DD
8
Maximum is highest voltage that POR will occur.
9 Simulated, not tested
10 Factory trimmed at V
DD = 5.0 V, Temp = 25°C
2
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
11
Chapter 3 Electrical Characteristics
2
125°C
25°C
–40°C
Max 1.5V@20mA
VOL (V)
1.5
1
0.5
0
0
5
10
15
IOL (mA)
a) VDD = 5V, High Drive
20
25
Figure 3-1. Typical VOL vs IOL, High Drive Strength
2
125°C
25°C
–40°C
Max 1.5V@4mA
VOL (V)
1.5
1
0.5
0
0
1
2
3
IOL (mA)
a) VDD = 5V, Low Drive
4
5
Figure 3-2. Typical VOL vs IOL, Low Drive Strength
MC9S08SC4 MCU Series Data Sheet, Rev. 4
12
Freescale Semiconductor
Chapter 3 Electrical Characteristics
2
125°C
25°C
–40°C
Max 1.5V@ –20mA
VDD – VOH (V)
1.5
1
0.5
0
0
–5
–10
–15
–20
IOH (mA)
a) VDD = 5V, High Drive
–25
Figure 3-3. Typical VDD – VOH vs IOH, High Drive Strength
2
125°C
25°C
–40°C
Max 1.5V@ –4mA
VDD – VOH (V)
1.5
1
0.5
0
0
–1
–2
–3
IOH (mA)
a) VDD = 5V, Low Drive
–4
–5
Figure 3-4. Typical VDD – VOH vs IOH, Low Drive Strength
3.7
Supply Current Characteristics
This section includes information about power supply current in various operating modes.
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
13
Chapter 3 Electrical Characteristics
Table 3-7. Supply Current Characteristics
Symbol
VDD
(V)
Typ1
Max2
Run supply current3 measured at
(CPU clock = 4 MHz, fBus = 2 MHz)
RIDD
5
1.9
2.4
P
Run supply current3 measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
RIDD
5
4.6
5.6
C
Run supply current4 measured at
(CPU clock = 32 MHz, fBus = 16 MHz)
RIDD
5
7.8
8.9
–40 °C (C & M suffix)
0.71
—
0.93
—
4
11
Num
C
1
C
2
3
Parameter
C
4
5
6
7
1
2
3
4
5
6
P
Stop3 mode
25 °C (All parts)
C5
supply current
85 °C (C suffix only)
S3IDD
5
C5
105 °C (V suffix only)
9
30
P5
125 °C (M suffix only)
28
60
C
–40 °C (C & M suffix)
0.70
—
0.89
—
3
8
P
Stop2 mode
25 °C (All parts)
C5
supply current
85 °C (C suffix only)
S2IDD
5
C5
105 °C (V suffix only)
6
22
P5
125 °C (M suffix only)
17
41
C
C
LVD adder to stop3 (LVDE = LVDSE = 1)
Adder to stop3 for oscillator
(EREFSTEN =1)
enabled6
Unit
mA
mA
mA
μA
μA
S3IDDLVD
5
110
165
μA
S3IDDOSC
5
5
8
μA
Typical values are based on characterization data at 25 °C. See Figure 3-5 through Figure 3-7 for typical curves
across voltage/temperature.
Max values in this column apply for the full operating temperature range of the device unless otherwise noted.
All modules except ADC active, ICS configured for FBE, and does not include any dc loads on port pins.
All modules except ADC active, ICS configured for FEI, and does not include any dc loads on port pins.
Stop currents are tested in production for 25 °C on all parts. Tests at other temperatures depend upon the part
number suffix and maturity of the product. Freescale may eliminate a test insertion at a particular temperature
from the production test flow once sufficient data has been collected and is approved.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768 kHz crystal and low
power mode (HGO = 0).
MC9S08SC4 MCU Series Data Sheet, Rev. 4
14
Freescale Semiconductor
Chapter 3 Electrical Characteristics
10
FEI
FBELP
Run IDD (mA)
8
6
4
2
0
0 1 2
4
8
20
16
fbus (MHz)
Figure 3-5. Typical Run IDD vs. Bus Frequency (VDD = 5V)
5
Run IDD (mA)
4
3
2
1
0
–40
0
25
Temperature (°C)
85
105
125
Note: ICS is configured to FEI.
Figure 3-6. Typical Run IDD vs. Temperature (VDD = 5V; fbus = 8MHz)
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
15
Chapter 3 Electrical Characteristics
50
STOP2
STOP3
STOP IDD (µA)
40
30
20
10
0
–40
0
25
Temperature (°C)
85
105
125
Figure 3-7. Typical Stop IDD vs. Temperature (VDD = 5V)
3.8
External Oscillator (XOSC) Characteristics
NOTE
The MC9S08SC4 series supports a narrower low frequency external reference range than
the standard ICS specification. All references to range "31.25 kHz to 39.0625 kHz" in this
section should be limited to " 32.0 kHz to 38.4 kHz".
MC9S08SC4 MCU Series Data Sheet, Rev. 4
16
Freescale Semiconductor
Chapter 3 Electrical Characteristics
Table 3-8. Oscillator Electrical Specifications (Temperature Range = –40 to 125°C Ambient)
Num
Symbol
Min
Typ1
Max
Unit
flo
32
—
38.4
kHz
fhi
1
—
5
MHz
High range (RANGE = 1, HGO = 1) FBELP mode
fhi-hgo
1
—
16
MHz
High range (RANGE = 1, HGO = 0) FBELP mode
fhi-lp
1
—
8
MHz
C
Rating
Oscillator crystal or resonator (EREFS = 1, ERCLKEN = 1)
Low range (RANGE = 0)
1
2
C
—
High range (RANGE = 1) FEE or FBE mode
2
Load capacitors
C1, C2
See crystal or resonator
manufacturer’s recommendation
Feedback resistor
3
—
RF
Low range (32 kHz to 100 kHz)
—
10
—
—
1
—
Low range, low gain (RANGE = 0, HGO = 0)
—
0
—
Low range, high gain (RANGE = 0, HGO = 1)
—
100
—
High range, low gain (RANGE = 1, HGO = 0)
—
0
—
—
0
0
High range (1 MHz to 16 MHz)
MΩ
Series resistor
4
—
RS
High range, high gain (RANGE = 1, HGO = 1)
≥ 8 MHz
kΩ
4 MHz
—
0
10
1 MHz
—
0
20
t
CSTL-LP
—
200
—
CSTL-HGO
—
400
—
t
CSTH-LP
—
5
—
t
CSTH-HGO
—
15
—
fextal
0.03125
—
5
MHz
0
—
40
MHz
Crystal start-up time 3
Low range, low gain (RANGE = 0, HGO = 0)
5
T
Low range, high gain (RANGE = 0, HGO = 1)
High range, low gain (RANGE = 1, HGO =
0)4
High range, high gain (RANGE = 1, HGO =
1)4
t
ms
Square wave input clock frequency (EREFS = 0, ERCLKEN = 1)
6
T
FEE or FBE mode 2
FBELP mode
1
Typical data was characterized at 5.0 V, 25°C or is recommended value.
The input clock source must be divided using RDIV to within the range of 31.25 kHz to 39.0625 kHz.
3 This parameter is characterized and not tested on each device. Proper PC board layout procedures must be followed to achieve
specifications. This data will vary based upon the crystal manufacturer and board design. The crystal should be characterized
by the crystal manufacturer.
4 4 MHz crystal.
2
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
17
Chapter 3 Electrical Characteristics
MCU
EXTAL
XTAL
RS
RF
C1
3.9
Crystal or Resonator
C2
Internal Clock Source (ICS) Characteristics
Table 3-9. ICS Frequency Specifications (Temperature Range = –40 to 125°C Ambient)
Num C
Rating
Internal reference frequency - factory trimmed
at VDD = 5 V and temperature = 25°C
Symbol
Min
Typical
Max
Unit
fint_ft
—
31.25
—
kHz
1
P
2
T Internal reference frequency - untrimmed1
fint_ut
25
36
41.66
kHz
3
P Internal reference frequency - user trimmed
fint_t
31.25
—
39.0625
kHz
4
T Internal reference startup time
tirefst
—
—
6
μs
fdco_ut
25.6
36.86
42.66
MHz
fdco_t
32
—
40
MHz
1
5
DCO output frequency range - untrimmed
— value provided for reference assumes:
fdco_ut = 1024 x fint_ut
6
D DCO output frequency range - trimmed
7
D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (using FTRIM)
Δfdco_res_t
—
± 0.1
± 0.2
%fdco
8
D
Resolution of trimmed DCO output frequency at fixed
voltage and temperature (not using FTRIM)
Δfdco_res_t
—
± 0.2
± 0.4
%fdco
9
D
Total deviation from actual trimmed DCO output
frequency over voltage and temperature
Δfdco_t
—
+ 0.5
– 1.0
± 2.0
%fdco
10
D
Total deviation of trimmed DCO output frequency over
fixed voltage and temperature range of 0°C to 70 °C
Δfdco_t
—
± 0.5
±1
%fdco
11
D FLL acquisition time 2
tacquire
—
—
1
ms
12
D DCO output clock long term jitter (over 2mS interval) 3
CJitter
—
0.02
0.2
%fdco
1
TRIM register at default value (0x80) and FTRIM control bit at default value (0x0).
This specification applies to any time the FLL reference source or reference divider is changed, trim value changed or changing
from FLL disabled (FBELP, FBILP) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is being used as the reference,
this specification assumes it is already running.
3 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f
BUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise injected
into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter percentage for a given
interval.
2
MC9S08SC4 MCU Series Data Sheet, Rev. 4
18
Freescale Semiconductor
Chapter 3 Electrical Characteristics
3.10
ADC Characteristics
Table 3-10. ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ1
Max
Supply voltage
Absolute
VDDA2
2.7
—
5.5
—
VREFH
Comment
V
—
V
—
Input Voltage
—
VADIN
VREFL2
Input
Capacitance
—
CADIN
—
4.5
5.5
pF
—
Input
Resistance
—
RADIN
—
3
5
kΩ
—
—
—
—
—
5
10
kΩ
—
—
10
0.4
—
8.0
0.4
—
4.0
Analog Source
Resistance
10 bit mode
fADCK > 4MHz
fADCK < 4MHz
RAS
8 bit mode (all valid fADCK)
ADC
Conversion
Clock
Frequency
2
Unit
High Speed (ADLPC=0)
fADCK
Low Power (ADLPC=1)
External to MCU
MHz
—
1
Typical values assume VDDA = 5.0 V, Temp = 25°C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2
VDDA/VREFH and VSSA/VREFL, are derived from VDD and VSS respectively.
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
Pad
leakage
due to
input
protection
ZAS
RAS
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
INPUT PIN
RADIN
RADIN
INPUT PIN
CADIN
Figure 3-8. ADC Input Impedance Equivalency Diagram
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
19
Chapter 3 Electrical Characteristics
Table 3-11. ADC Characteristics
Characteristic
Conditions
C
Symb
Min
Typ1
Max
Unit
Comment
Supply Current
ADLPC=1
ADLSMP=1
ADCO=1
—
T
IDDA
—
133
—
μA
—
Supply Current
ADLPC=1
ADLSMP=0
ADCO=1
—
T
IDDA
—
218
—
μA
—
Supply Current
ADLPC=0
ADLSMP=1
ADCO=1
—
T
IDDA
—
327
—
μA
—
Supply Current
ADLPC=0
ADLSMP=0
ADCO=1
—
T
IDDA
—
0.582
1
mA
—
P
fADACK
2
3.3
5
MHz
1.25
2
3.3
tADACK =
1/fADACK
—
20
—
ADCK
cycles
—
40
—
—
3.5
—
See ADC
chapter in
MC9S08SC4
Reference
Manual for
conversion
time
variances
—
23.5
—
—
±1.5
±3.5
—
±0.7
±1.5
—
±0.5
±1.0
—
±0.3
±0.5
ADC
Asynchronous
Clock Source
High Speed (ADLPC=0)
Low Power (ADLPC=1)
Conversion
Time
(Including
sample time)
Short Sample
(ADLSMP=0)
Sample Time
Short Sample
(ADLSMP=0)
P
tADC
Long Sample
(ADLSMP=1)
P
tADS
Long Sample
(ADLSMP=1)
Total
Unadjusted
Error
10 bit mode
Differential
Non-Linearity
10 bit mode
P
ETUE
8 bit mode
P
DNL
8 bit mode
ADCK
cycles
LSB
Includes
quantization
LSB
Monotonicity and No-Missing-Codes guaranteed
Integral
Non-Linearity
10 bit mode
Zero-Scale
Error
10 bit mode
Full-Scale
Error
C
INL
8 bit mode
P
EZS
8 bit mode
10 bit mode
8 bit mode
P
EFS
—
±0.5
±1.0
—
±0.3
±0.5
—
±1.5
±2.5
—
±0.5
±0.7
—
±1
±1.5
—
±0.5
±0.5
LSB
LSB
VADIN = VSSA
LSB
VADIN = VDDA
MC9S08SC4 MCU Series Data Sheet, Rev. 4
20
Freescale Semiconductor
Chapter 3 Electrical Characteristics
Table 3-11. ADC Characteristics
Characteristic
Conditions
Quantization
Error
10 bit mode
Input Leakage
Error
10 bit mode
Temp Sensor
Slope
−40°C– 25°C
C
Symb
Min
Typ1
Max
Unit
Comment
D
EQ
—
—
±0.5
LSB
—
—
—
±0.5
—
±0.2
±2.5
LSB
—
±0.1
±1
Pad leakage2
* RAS
—
3.266
—
mV/°C
—
V
—
8 bit mode
D
EIL
8 bit mode
D
m
25°C– 125°C
—
—
3.638
Temp Sensor
Voltage
25°C
D
VTEMP2
—
1.396
—
5
1
Typical values assume VDDA = 5.0V, Temp = 25C, fADCK=1.0MHz unless otherwise stated. Typical values are for reference only
and are not tested in production.
2 Based on input pad leakage current. Refer to pad electricals.
3.11
AC Characteristics
This section describes AC timing characteristics for each peripheral system.
3.11.1
Control Timing
Table 3-12. Control Timing
Symbol
Min
Typ1
Max
Unit
Bus frequency (tcyc = 1/fBus)
fBus
dc
—
20
MHz
P
Internal low power oscillator period
tLPO
700
975
1500
μs
3
D
External reset pulse width2
textrst
100
—
—
ns
4
D
Reset low drive3
trstdrv
66 x tcyc
—
—
ns
5
D
Pin interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH, tIHIL
100
1.5 x tcyc
—
—
ns
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
40
75
—
—
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)6
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
—
—
11
35
—
—
Num
C
1
D
2
6
1
Rating
ns
C
ns
Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
21
Chapter 3 Electrical Characteristics
2
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources. Refer to Figure 3-9.
3
When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of tcyc. After POR reset the bus clock
frequency changes to the untrimmed DCO frequency (freset = (fdco_ut)/4) because TRIM is reset to 0x80 and FTRIM is reset
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
4
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.
textrst
RESET PIN
Figure 3-9. Reset Timing
3.11.2
TPM Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 3-13. TPM Input Timing
Num
C
1
—
2
Rating
Symbol
Min
Max
Unit
External clock frequency
fTEXT
dc
1/4 fop
MHz
—
External clock period
tTEXT
4
—
tCYC
3
—
External clock high time
tTCLKH
1.5
—
tCYC
4
—
External clock low time
tTCLKL
1.5
—
tCYC
5
—
Input capture pulse width
fICPW
1.5
—
tCYC
MC9S08SC4 MCU Series Data Sheet, Rev. 4
22
Freescale Semiconductor
Chapter 3 Electrical Characteristics
tCYC
ipg_clk
tTEXT
EXTERNAL
CLOCK
tTCLKL
tTCLKH
tICPW
INPUT
CAPTURE
3.12
Flash Specifications
This section provides details about program/erase times and program-erase endurance for the FLASH memory.
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory section.
Table 3-14. FLASH Characteristics
Num
C
1
—
2
—
Characteristic
Symbol
Min
Typical
Max
Unit
Supply voltage for program/erase
Vprog/erase
4.5
—
5.5
V
Supply voltage for read operation
VRead
4.5
—
5.5
V
fFCLK
150
—
200
kHz
tFcyc
5
—
6.67
μs
frequency1
3
—
Internal FCLK
4
—
Internal FCLK period (1/fFCLK)
5
6
7
8
—
—
—
—
Byte program time (random
location)2
tprog
9
tFcyc
2
tBurst
4
tFcyc
tPage
4000
tFcyc
tMass
20,000
tFcyc
Byte program time (burst mode)
Page erase
time2
Mass erase
time2
3
9
C
Program/erase endurance
TL to TH = –40°C to +125°C
T = 25°C
nFLPE
10,000
—
—
100,000
—
—
cycles
10
C
Data retention4
tD_ret
15
100
—
years
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3 Typical endurance for FLASH is based on the intrinsic bit cell performance. For additional information on how Freescale
defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical Endurance for Nonvolatile Memory.
4 Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated
to 25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer
to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
2
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
23
Chapter 3 Electrical Characteristics
3.13
EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.13.1
Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East).
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 3-15. Radiated Emissions, Electric Field
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
VRE_TEM
VDD = 5 V
TA = +25oC
package type
16-TSSOP
0.15 – 50 MHz
4 MHz crystal
8 MHz bus
Radiated emissions,
electric field
1
50 – 150 MHz
Level1
(Max)
Unit
–7
dBμV
–11
150 – 500 MHz
–11
500 – 1000 MHz
–10
IEC Level
N
—
SAE Level
1
—
Data based on qualification test results.
MC9S08SC4 MCU Series Data Sheet, Rev. 4
24
Freescale Semiconductor
Chapter 4 Ordering Information and Mechanical Drawings
Chapter 4
Ordering Information and Mechanical Drawings
4.1
Ordering Information
This section contains ordering information for MC9S08SC4 device.
Table 4-1. Device Numbering System
Memory
FLASH
RAM
Available
Packages2
4K
256
16 TSSOP
Device Number1
S9S08SC4E0MTG
1
See MC9S08SC4 Reference Manual for a complete description of modules.
included on each device.
2 See Table 4-2 for package information.
4.1.1
Device Numbering Scheme
S
9
S08
SC 4
E0
M
TG
R
Status
- S = Auto Qualified
Tape and Reel Suffix (optional)
Package Designator
Two letter descriptor
(refer to Table 4-2).
Main Memory Type
- 9 = Flash-based
Temperature Option
- C = –40 to 85 °C
- V = –40 to 105 °C
- M = –40 to 125 °C
Core
S Family
4.2
Memory Size
Mask Set Identifier
- 4 Kbytes
- Identifies mask.
Package Information
Table 4-2. Package Information
4.3
Pin Count
Type
Designator
Case Number
Document No.
16
TSSOP
TG
948F-01
98ASH70247A
Mechanical Drawings
The following pages are mechanical drawings for the package described in Table 4-2.
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
25
Chapter 4 Ordering Information and Mechanical Drawings
MC9S08SC4 MCU Series Data Sheet, Rev. 4
26
Freescale Semiconductor
Chapter 4 Ordering Information and Mechanical Drawings
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
27
Chapter 4 Ordering Information and Mechanical Drawings
MC9S08SC4 MCU Series Data Sheet, Rev. 4
28
Freescale Semiconductor
Chapter 5 Revision History
Chapter 5
Revision History
To provide the most up-to-date information, the version of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
1
9/2008
• Initial Release.
2
7/2009
•
•
•
•
Description of Changes
•
•
•
•
Incorporated editing updates.
Added C and V temperature ranges at page 1.
Updated Section 3.10, “ADC Characteristics”.
Updated Table 3-3, Table 3-6, Table 3-7, Table 3-9, Table 3-12, Table 3-15 and Section
4.1.1, “Device Numbering Scheme”.
Added actual package mechanical drawings.
Updated Figure 3-5, Figure 3-6.
Removed Transient Susceptibilty Section.
Updated disclaimer page.
3
3/2010
• Updated TSSOP-16 package diagram, clarified ICS deviation, SCI LIN features at page
1.
• Updated Table 3-6, Table 3-7, Table 3-9, Table 3-12, Table 4-1.
• Updated Figure 3-5 and Figure 3-7.
4
6/2010
• Document changed from Advance Information to Technical Data
• Updated footnotes in Table 3-7
• Updated Figure 3-5
MC9S08SC4 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
29
Chapter 5 Revision History
MC9S08SC4 MCU Series Data Sheet, Rev. 4
30
Freescale Semiconductor
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© Freescale Semiconductor, Inc. 2010. All rights reserved.
MC9S08SC4
Rev.4
6/2010