AK8157A

[AK8157A]
= Preliminary =
AK8157A
Multiclock Generator for Premium Audio Device
1. 概
要
AK8157A は高 C/N 特性かつ低消費電力を特長とするマルチクロックジェネレータです。AKM で培われ
た技術により、AK8157A 内蔵 PLL は低消費電力かつ低ジッターを実現し、Premium DAC である AK4490
のリファレンスクロックとして最適です。The AK8157A は外部クロック入力から Master Clock, Bit Clock,
L/R Clock を生成します。またレジスタ設定により 4 種類のサンプリング周波数の組み合わせに対応す
ることができます。AK8157A は 16-pin WLCSP package を採用しています。
アプリケーション： Smart Cellular Phones, USB DACs, USB Headphones, Bluetooth Headphones
2. 特
長
 External Clock Input Frequency: 9.6MHz
 Three Frequency Selectable Clock Outputs
 Selectable Clock Output Frequencies:
- MCLK: 16.384, 22.5792, 24.576MHz
- BCLK: 2.048MHz  24.576MHz
- LRCK: 32kHz  384kHz
 Selectable Clock Output Enable / Disable Control
 Low Jitter Performance
- RMS Jitter: 45ps (10Hz  5MHz)
 Low Current Consumption: 8mA (VDD1-4 = 1.8V)
 Output Load: 80pF
 Power Supply: VDD1-4 = 1.7  2.0V
 Digital Input Level: CMOS
 Package: 16-pin WLCSP
Rev 0.1
2016/04
-1-
[AK8157A]
3. Table of Contents
1.
2.
3.
4.
5.
General Description ............................................................................................................................ 1
Features .............................................................................................................................................. 1
Table of Contents ................................................................................................................................ 2
Block Diagram ..................................................................................................................................... 3
Pin Configurations and Functions ....................................................................................................... 4
■ Pin Layout .......................................................................................................................................... 4
■ Pin Functions...................................................................................................................................... 4
■ Handling of Unused Pin ..................................................................................................................... 5
6. Absolute Maximum Ratings ................................................................................................................ 6
7. Recommended Operating Conditions................................................................................................. 6
8. Electrical Characteristics..................................................................................................................... 7
■ AC Characteristics ............................................................................................................................. 7
■ Power Supply Current ........................................................................................................................ 8
■ DC Characteristics ............................................................................................................................. 8
■ Switching Characteristics ................................................................................................................... 9
■ Timing Diagram ................................................................................................................................ 10
9. Functional Descriptions ..................................................................................................................... 11
■ System Clock Timing ....................................................................................................................... 11
■ System Reset ................................................................................................................................... 11
■ Power-up Timing .............................................................................................................................. 12
■ Glitch-free Function .......................................................................................................................... 13
■ Frequency Configuration Change Sequence .................................................................................. 13
■ Power-down and Power-up Sequence by Internal Registers .......................................................... 14
■ Register Control Interface ................................................................................................................ 16
■ Register Map .................................................................................................................................... 20
■ Register Definitions .......................................................................................................................... 20
10.
Recommended External Circuits................................................................................................... 22
11.
Package ......................................................................................................................................... 24
■ Outline Dimensions .......................................................................................................................... 24
■ Material & Lead finish....................................................................................................................... 24
■ Marking............................................................................................................................................. 25
12.
Ordering Guide .............................................................................................................................. 25
■ Ordering Guide ................................................................................................................................. 25
13.
Revision History............................................................................................................................. 25
IMPORTANT NOTICE.............................................................................................................................. 26
Rev 0.1
2016/04
-2-
[AK8157A]
4. Block Diagram
VDD
PLL1
CLKIN
9.6MHz
SDA
SCL
RSTN
CAD1
CAD0
2
IC
I/F
PLL2
ODIV1
MCLK
ODIV2
BCLK
ODIV3
LRCK
Control
Register
VSS
Figure 1. Block Diagram
Rev 0.1
2016/04
-3-
[AK8157A]
5. Pin Configurations and Functions
■ Pin Layout
4
3
2
1
CAD1
VDD2
VSS1
CLKIN
VDD3
SDA
SCL
CAD0
VSS2
RSTN
LRCK
VDD1
BCLK
VDD4
VSS3
MCLK
D
C
B
A
Top view
Figure 2. AK8157A Package: 16-pin WLCSP (Top View)
■ Pin Functions
No.
Pin Name
I/O
Function
A1
A2
MCLK
VSS3
O
-
Master Clock Output Pin (Internal pull-down pin: 160k)
Ground Pin
A3
A4
B1
B2
VDD4
BCLK
VDD1
LRCK
O
O
Power Supply Pin, 1.7  2.0V
Audio Serial Data Clock Output Pin (Internal pull-down pin: 160k)
Power Supply Pin, 1.7  2.0V
L/R Clock Output Pin (Internal pull-down pin: 160k)
B3
RSTN
I
Register Reset Control Pin
When at “L”, the register of the AK8157A is held in reset.
The AK8157A must always be reset upon power-up.
B4
VSS2
Ground Pin
C1
CAD0
I
Chip Address 0 Pin
C2
SCL
I
Control Data Clock Input Pin
C3
SDA
I/O Control Data Input / Output Pin
C4
VDD3
Power Supply Pin, 1.7  2.0V
D1
CLKIN
I
9.6MHz External Clock Input Pin
D2
VSS1
Ground Pin
D3
VDD2
Power Supply Pin, 1.7  2.0V
D4
CAD1
I
Chip Address 1 Pin
Note: All input pins must not be allowed to float.
Rev 0.1
2016/04
-4-
[AK8157A]
■ Handling of Unused Pin
Unused I/O pins must be connected appropriately.
Classification
Pin Name
Digital
MCLK, BCLK, LRCK
Pull-down pin List
pull-down pin
Setting
These pins must be connected to VSS1-3 or open.
When these pins are in disable setting, they output “L”
with internal pull-down resistor.
A1, A4, B2
Rev 0.1
2016/04
-5-
[AK8157A]
6. Absolute Maximum Ratings
(VSS1-3 = 0V; Note 1)
Parameter
Power Supplies
VDD1-4
Symbol
Min.
Max.
Unit
VDD
0.3
VSS0.3
40
65
4.6
10
VDD+0.3
85
150
V
Input Current, Any Pin Except Supplies
IIN
mA
Digital Input Voltage
VIND
V
Ambient Temperature (Power applied)
Ta
C
Storage Temperature
Tstg
C
Note 1. All voltages with respect to ground.
Note 2. Connect at least 0.1F or more decoupling capacitors between VDD1-4 and VSS1-3 to suppress
affections by a static electricity noise or an over voltage (includes over shooting) that exceeds
absolute maximum ratings.
WARNING: Operation at or beyond these limits may result in permanent damage to the device.
Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS1-3 = 0V; Note 1)
Parameter
Symbol
Min.
Typ.
Max.
Unit
Power Supplies (Note 3)
VDD1-4
VDD
1.7
1.8
2.0
V
Note 1. All voltages with respect to ground.
Note 3. VDD1-4 should be supplied from a single source. A decoupling capacitor of 0.1μF for power
supply line should be connected close to each VDD pin. The power-up sequence between
VDD1-4 are not critical.
* AKM assumes no responsibility for the usage beyond the conditions in this data sheet.
Rev 0.1
2016/04
-6-
[AK8157A]
8. Electrical Characteristics
■ AC Characteristics
(Ta=25C; VDD1-4 = 1.7  2.0V; unless otherwise specified.)
Parameter
Pin
Min.
Typ.
Max.
Unit
Input Clock Frequency
Input Capacitance
CLKIN
CLKIN
-
9.6
3
-
MHz
pF
Output Clock Frequency
MCLK
BCLK
LRCK
16.384
2.048
32
-
24.576
24.576
384
MHz
MHz
kHz
MCLK
BCLK
LRCK
-
6
12
ns
MCLK
-
25
-
ps
Output Clock Rise / Fall Time
(Note 4)
RMS Jitter (10Hz  5MHz)
Output Clock Duty Cycle
(Note 5)
MCLK
BCLK
LRCK
45
50
55
%
Output High / Low Pulse Width
(Note 6)
MCLK
BCLK
LRCK
10
-
-
ns
Output Lock Time
(Note 7)
MCLK
BCLK
LRCK
-
-
1
ms
BICK “” to LRCK Edge (tBLR) (Note 8)
(BCLK = 2.048MHz  12.288MHz)
(BCLK = 16.384MHz  24.576MHz)
BCLK
LRCK
20
10
-
-
ns
ns
LRCK Edge to BICK “” (tLRB) (Note 8)
(BCLK = 2.048MHz  12.288MHz)
(BCLK = 16.384MHz  24.576MHz)
BCLK
LRCK
20
10
-
-
ns
ns
Note 4. Rise Time = 20%VDD to 80%VDD, Fall Time = 80%VDD to 20%VDD Measured with Load
Capacitance of CL = 80pF.
Note 5. Measured with Load Capacitance of CL = 80pF.
Note 6. High Pulse Width is measured at 80%VDD Level, Low Pulse Width is measured at 20%VDD
Level, Measured with Load Capacitance of CL = 80pF.
Note 7. The time until the output settles to ±0.1% of the specified frequency from the point that the power
supply reaches VDD.
Note 8. BCLK rising edge must not occur at the same time as LRCK edge.
Rev 0.1
2016/04
-7-
[AK8157A]
■ Power Supply Current
(Ta=25C; VDD1-4 = 1.7  2.0V; unless otherwise specified.)
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current:
Normal operation
(Note 9)
(VREF_PD bit = PLL_PD bit = PLL1_PD bit = “L”)
VDD1-4
-
8
13
mA
Power down
(Note 10)
(VREF_PD bit = PLL_PD bit = PLL1_PD bit = “H”)
VDD1-4
-
0
10
A
Note 9. CLKIN = 9.6MHz, MCLK = 24.576MHz, BCLK = 24.576MHz, LRCK = 384kHz. No Output Load
Capacitance. MDSEL1-0 bits = MCKSEL1-0 bits = “11”.
Note 10. In the power down mode. VREF_PD bit = PLL_PD bit = PLL1_PD bit = “H”, and all other digital
input pins including CLKIN pin are held VSS1-3.
■ DC Characteristics
(Ta=25C; VDD1-4 = 1.7  2.0V; unless otherwise specified.)
Parameter
Symbol
Min.
High-Level Input Voltage
VIH
80%VDD
Low-Level Input Voltage
VIL
High-Level Output Voltage
(Iout = 4mA)
VOH
80%VDD
Low-Level Output Voltage
(MCLK, BCLK, LRCK pins: Iout = 4mA)
VOL
(SDA pin:
Iout = 3mA)
VOL
Input Leakage Current
Iin
Output Hi-z Leakage Current
Iout
10
Rev 0.1
Typ.
-
Max.
20%VDD
-
Unit
V
V
V
+11
20%VDD
20%VDD
10
+80
V
V
A
A
2016/04
-8-
[AK8157A]
■ Switching Characteristics
(Ta=25C; VDD1-4 = 1.7  2.0V; unless otherwise specified.)
Parameter
Symbol
Control Interface Timing (I2C Bus mode):
SCL Clock Frequency
fSCL
Bus Free Time Between Transmissions
tBUF
Start Condition Hold Time (prior to first clock pulse)
tHD:STA
Clock Low Time
tLOW
Clock High Time
tHIGH
Setup Time for Repeated Start Condition
tSU:STA
SDA Hold Time from SCL Falling
(Note 11)
tHD:DAT
SDA Setup Time from SCL Rising
tSU:DAT
Rise Time of Both SDA and SCL Lines
tR
Fall Time of Both SDA and SCL Lines
tF
Setup Time for Stop Condition
tSU:STO
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
Capacitive load on bus
Cb
Reset Timing
RSTN Pulse Width
(Note 12)
Min.
Typ.
1.3
0.6
1.3
0.6
0.6
0
0.1
0.6
0
-
tRST
150
Note 11. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 12. The register of the AK8157A can be reset by bringing the RSTN pin to “L”.
Rev 0.1
Max.
Unit
400
0.3
0.3
50
400
kHz
s
s
s
s
s
s
s
s
s
s
ns
pF
ns
2016/04
-9-
[AK8157A]
■ Timing Diagram
VIH
LRCK
VIL
tBLR
tLRB
VIH
BCLK
VIL
Figure 3. Audio Interface Timing
VIH
SDA
VIL
tBUF
tLOW
tR
tHIGH
tF
tSP
VIH
SCL
VIL
tHD:STA
Stop
Start
tHD:DAT
tSU:DAT
tSU:STA
Start
Figure 4. I2C Bus Mode Timing
tSU:STO
Stop
tRST
RSTN
VIL
Figure 5. Reset Timing
Rev 0.1
2016/04
- 10 -
[AK8157A]
9. Functional Descriptions
■ System Clock Timing
The AK8157A can generate MCLK, BCLK and LRCK simultaneously from 9.6MHz external input clock. It
requires operating the AK8157A with an audio device such as the AK4490, the AK4495 and so on. MCLK,
BCLK and LRCK phases are synchronized on a falling edge. (Figure 6).
CLKIN
9.6MHz
PLL1
PLL2
ODIV1
MCLK
ODIV2
BCLK
ODIV3
LRCK
Figure 6. System Clock Timing
The MCLK, BCLK and LRCK frequencies corresponding to each sampling speed can be selected by
MDSEL1-0 bits and MCKSEL1-0 bits (Table 1). Normal speed, double speed, quad speed and oct speed
modes are available with the AK8157A.
MDSEL1-0 bits
00
01
10
11
Table 1. Output Clock Configuration
BCLK (MHz)
MCKSEL1-0 bits
MCLK (MHz)
64fs
16.384
2.048
00
LRCK (kHz)
fs
32
Sampling
Speed
2.8224
44.1
Normal
01
22.5792
10 / 11
24.576
3.072
48
00
16.384
4.096
64
01
22.5792
5.6448
88.2
10 / 11
24.576
6.144
96
00
16.384
8.192
128
01
22.5792
11.2896
176.4
10 / 11
24.576
12.288
192
00
16.384
16.384
256
01
22.5792
22.5792
352.8
10 / 11
24.576
24.576
384
512fs
256fs
128fs
64fs
Double
Quad
Oct
■ System Reset
The AK8157A should be reset once by bringing the RSTN pin = “L” upon power-up. It initializes register
settings of the device.
Rev 0.1
2016/04
- 11 -
[AK8157A]
■ Power-up Timing
Registers of the AK8157A are initialized by bringing the RSTN pin to “L”. The MCLK, BCLK and LRCK
outputs are floating (Hi-Z) and connected to 160k pull-down internally. PLL1, PLL2 and VREF circuits
are power-up.
Registers of the AK8157A are able to write when RSTN pin is change to “H”.
Power
VDD1
VDD2
VDD3
VDD4
RSTN
SCL/SDA
1.7V
(1)
Register Initialization
Register Setting Available
Frequency Setting
CLKIN
Output Clock Enable Setting
Don’t care
(2)
PLL State
MCLK
BCLK
LRCK
Unlocked
Locked
Disable state (Hi-Z & Pull-down)
(3)
Clock is enabled without a glitch
(1) VDD1-4 power supply should be powered up at the same time by bringing the RSTN pin to “L”.
Registers of the AK8157A are initialized by bringing the RSTN pin to “L”.
After VDD1-3 reach 1.7V, the RSTN pin should be changed from “L” to “H” with an interval of
200s or more.
(2) When the RSTN pin is “H”, the output clock frequency configuration can be selected by internal
register setting (MDSEL1-0 bits and MCKSEL1-0 bits). After setting the output clock frequency
configuration, MCK_DIS bit, BCK_DIS bit and LR_DIS bit are recommended to change from “1” to
“0” with an interval of 1ms or more to output MCLK, BCLK and LRCK clocks without a glitch.
(3) The MCLK, BCLK and LRCK outputs are floating (Hi-Z) and connected to 160k pull-down
internally.
Figure 7. Power-up Timing Example
Rev 0.1
2016/04
- 12 -
[AK8157A]
■ Glitch-free Function
The AK8157A has a Glitch-free function. MCLK, BCLK and LRCK output clocks can be switched
enable and disable without a glitch.
■ Frequency Configuration Change Sequence
When outputs frequency of the MCLK, BCLK and LRCK are changed by internal register setting
(MDSEL1-0 bits and MCKSEL1-0 bits), it is recommended to disable output clocks to not output
unstable frequency clock.
CLKIN
Output State
Enable
Disable
(1)
”Disable” setting
SCL/SDA
(3)
Frequency Setting
Configuration1
(2)
PLL State
MCLK
BCLK
LRCK
Enable
”Enable” setting
Locked
Configuration2
Frequency changing
Unlock
Locked
Disable state (Hi-Z & Pull-down)
Clock is disabled without a glitch
Clock is enabled without a glitch
(1) MCK_DIS bit, BCK_DIS bit and LR_DIS bit are changed from “0” to “1”.
(2) The output clock frequency configuration can be changed by internal register setting (MDSEL1-0
bits and MCKSEL1-0 bits).
(3) After changing the output clock frequency Configuration2, it is recommended to change
MCK_DIS bit, BCK_DIS bit and LR_DIS bit to “0” from “1” with an interval of 1ms or more. Then
MCLK, BCLK and LRCK can be output without a glitch.
Figure 8. Frequency Configuration Change Sequence Example
Rev 0.1
2016/04
- 13 -
[AK8157A]
■ Power-down and Power-up Sequence by Internal Registers
Internal circuits of the AK8157A can be powered down and up by setting registers (PLL1_PD bit,
PLL2_PD bit and VREF_PD bit). It is recommended to disable output clocks to not output unstable
frequency clocks when internal circuits of the AK8157A are powered down and up.
(1) Power-down by changing MCK_DIS bit, BCK_DIS bit and LR_DIS bit from “0” to “1”
Don’t care
CLKIN
Output State
Enable
Disable
(1)
”Disable” setting
SCL/SDA
Power-down Setting
Power up
Power down
“Power down” setting
(2)
PLL State
Locked
MCLK
BCLK
LRCK
Power down
Disable state (Hi-Z & Pull-down)
Clock is disabled without a glitch
(1) MCK_DIS bit, BCK_DIS bit and LR_DIS bit are changed from “0” to “1”.
(2) Internal circuits of the AK8157A are powered down by setting internal registers (PLL1_PD bit,
PLL2_PD bit and VREF_PD bit).
Figure 9. Power-down Sequence Example
Rev 0.1
2016/04
- 14 -
[AK8157A]
(2) Power-up by changing MCK_DIS bit, BCK_DIS bit and LR_DIS bit from “1” to “0”
Don’t care
CLKIN
Output State
Disable
Disable
Enable
”Enable” setting
SCL/SDA
(2)
Power-up Setting
Power down
(1)
PLL State
MCLK
BCLK
LRCK
Power down
Power up
Power up
“Power on” setting
Unlocked
Locked
Disable state (Hi-Z & Pull-down)
Clock is enabled without a glitch
(1) Internal circuits of the AK8157A are switched to power-up state by setting internal registers
(PLL1_PD bit, PLL2_PD bit and VREF_PD bit).
(2) After PLL1_PD bit, PLL2_PD bit and VREF_PD bit are changed, it is recommended to change
MCK_DIS bit, BCK_DIS bit and LR_DIS bit to “0” from “1” with an interval of 1ms or more for
glitch-free outputs of MCLK, BICK and LRCK.
Figure 10. Power-up Sequence Example
Rev 0.1
2016/04
- 15 -
[AK8157A]
■ Register Control Interface
I2C-bus Control Mode
The AK8157A supports the fast-mode I2C-bus (max: 400kHz, Ver 1.0).
1. WRITE Operations
Figure 11 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 17). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant five bits of the slave
address are fixed as “00100”. The next bits are CAD1 and CAD0 (device address bits). This bit identifies
the specific device on the bus. The hard-wired input pin (CAD1pins, CAD0 pin) sets these device address
bits (Figure 12). If the slave address matches that of the AK8157A, the AK8157A generates an
acknowledgement and the operation is executed. The master must generate the acknowledgement
-related clock pulse and release the SDA line (HIGH) during the acknowledgement clock pulse (Figure
18). A R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates that the
write operation is to be executed.
The second byte consists of the control register address of the AK8157A and the format is MSB first.
(Figure 13). The data after the second byte contains control data. The format is MSB first, 8bits (Figure
14). The AK8157A generates an acknowledgement after each byte is received. Data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line
while SCL is HIGH defines a STOP condition (Figure 17).
The AK8157A can perform more than one byte write operation per sequence. After receipt of the third
byte the AK8157A generates an acknowledgement and awaits the next data. The master can transmit
more than one byte instead of terminating the write cycle after the first data byte is transferred. After
receiving each data packet the internal address counter is incremented by one, and the next data is
automatically taken into the next address. If the address exceeds “01H” prior to generating a stop
condition, the address counter will “roll over” to “00H” and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 19) except for the
START and STOP conditions.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
Data(n)
Data(n+1)
A
C
K
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 11. Data Transfer Sequence at I2C Bus Mode
0
0
1
0
0
CAD1
CAD0
R/W
(CAD1-0 is set by the pin)
Figure 12. The First Byte
0
0
0
A4
A3
A2
A1
A0
D1
D0
Figure 13. The Second Byte
D7
D6
D5
D4
D3
D2
Figure 14. The Third Byte and After The Third Byte
Rev 0.1
2016/04
- 16 -
[AK8157A]
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK8157A. After transmission of data, the master can
read the next address’s data by generating an acknowledgement instead of terminating the write cycle
after the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. If the address
exceeds “01H” prior to generating stop condition, the address counter will “roll over” to “00H” and the data
of “00H” will be read out.
The AK8157A supports two basic read operations: Current Address Read and Random Address Read.
2-1. Current Address Read
The AK8157A has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK8157A generates an acknowledgement, transmits 1-byte of data to the address
set by the internal address counter and increments the internal address counter by 1. If the master does
not generate an acknowledgement but generates a stop condition instead, the AK8157A ceases the
transmission.
S
T
A
R
T
SDA
S
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+2)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 15. Current Address Read
2-2. Random Address Read
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK8157A then generates an acknowledgement, 1 byte of data and
increments the internal address counter by 1. If the master does not generate an acknowledgement but
generates a stop condition instead, the AK8157A ceases the transmission.
S
T
A
R
T
SDA
S
S
T
A
R
T
R/W= “0”
Slave
Address
Sub
Address(n)
A
C
K
S
A
C
K
S
T
O
P
R/W= “1”
Slave
Address
Data(n)
A
C
K
Data(n+1)
A
C
K
Data(n+x)
A
C
K
A
C
K
P
A
C
K
Figure 16. Random Address Read
Rev 0.1
2016/04
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[AK8157A]
SDA
SCL
S
P
start condition
stop condition
Figure 17. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
no acknowledgement
DATA
OUTPUT BY
RECEIVER
acknowledgement
SCL FROM
MASTER
2
1
8
9
S
clock pulse for
the acknowledgement
START
CONDITION
Figure 18. Acknowledgement (I2C Bus)
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 19. Bit Transfer (I2C Bus)
Rev 0.1
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[AK8157A]
Function List
Function
Power Management
Table 2. Function List
Default
Power-up
Output Clock Control
Disable Clock Output
00H
The Output Clock Frequency
Selection
of the MCLK pin
The Output Clock Mode Selection
of the Sampling Speed
MCLK = 16.384MHz
01H
Bit
PLL1_PD
PLL2_PD
VREF_PD
MCK_DIS
BCK_DIS
LR_DIS
MCKSEL1-0
LRCK = 32kHz
BCLK = 2.048MHz
01H
MDSEL1-0
Rev 0.1
Address
00H
2016/04
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[AK8157A]
■ Register Map
Addr
Register
Name
D7
D6
D5
D4
D3
00H
Control 1
LR_DIS
BCK_DIS
MCK_DIS
reserved
reserved
01H
Control 2
reserved
reserved
MDSEL1
MDSEL0
reserved
D2
D1
VREF_PD PLL2_PD
reserved
D0
PLL1_PD
MCKSEL1 MCKSEL0
Notes:
The AK8157A supports read command in I2C-bus control mode.
Data must not be written into addresses from 02H to 1FH.
The reserved bits defined as “0” must contain a “0” value.
When the RSTN pin goes to “L”, the registers are initialized to their default values.
■ Register Definitions
Addr
Register
Name
D7
D6
D5
D4
D3
00H
Control 1
LR_DIS
BCK_DIS
MCK_DIS
reserved
reserved
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
Default
1
1
1
0
0
0
0
0
D2
D1
VREF_PD PLL2_PD
D0
PLL1_PD
PLL1_PD: PLL1 Power Management
0: Power up (default)
1: Power down
PLL2_PD: PLL2 Power Management
0: Power up (default)
1: Power down
VREF_PD: Internal VREF Power Management
0: Power up (default)
1: Power down
MCK_DIS: MCLK pin Output Clock Control
0: Enable: Clock Output
1: Disable: “L” Output by 160k (typ.) pull-down resistor (default)
BCK_DIS: MCLK pin Output Clock Control
0: Enable: 64fs Clock Output
1: Disable: “L” Output by 160k (typ.) pull-down resistor (default)
LR_DIS: LRCK pin Output Clock Control
0: Enable: fs Clock Output
1: Disable: “L” Output by 160k (typ.) pull-down resistor (default)
Rev 0.1
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[AK8157A]
Addr
Register
Name
D7
D6
D5
D4
D3
D2
01H
Control 2
reserved
reserved
MDSEL1
MDSEL0
reserved
reserved
R/W
R
R
R/W
R/W
R
R
R/W
R/W
Default
0
0
0
0
0
0
0
0
D1
D0
MCKSEL1 MCKSEL0
MCKSEL1-0: The Output Clock Frequency Selection of the MCLK pin
Initial value is “00” (MCLK pin = 16.384MHz).
MCKSEL1
0
0
1
1
Table 3. MCLK pin Output Clock Frequency
MCKSEL0
MCLK Output Clock (MHz)
0
16.384
1
22.5792
0
24.576
1
24.576
(default)
MDSEL1-0: The Output Clock Mode Selection of the Sampling Speed
Initial value is “00” (Sampling Speed = Normal Speed Mode).
MDSEL1
0
0
1
1
Table 4. Output Clock Sampling Speed Mode
MDSEL0
Sampling Speed Mode
0
Normal Speed
1
Double Speed
0
Quad Speed
1
Oct Speed
Rev 0.1
(default)
2016/04
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[AK8157A]
10. Recommended External Circuits
PM-IC
C1 : 0.1F
VDD = 1.8V
Control
C1
C1
CAD1
CAD1
VDD2
VSS1
CLK
IN
D
VDD3
SDA
SCL
CAD0
C
VDD1
B
CLKIN Input
9.6MHz
CAD0
SCL
SDA
AK8157A
C1
VSS2
RSTN
LRCK
LRCK Output
BCLK Output
(Top view)
RSTN
BCLK
VDD4
VSS3
MCLK
4
3
2
1
A
MCLK Output
C1
Figure 20. Recommended External Circuits
PCB Layout Consideration
The AK8157A is a high-accuracy and low-jitter clock generator. For proper performances specified in this
datasheet, careful PCB layout should be taken. The followings are layout guidelines based on the typical
connection diagram shown in Figure 20.
Power supply line & Ground pin connection
The AK8157A has four power supply pins (VDD1, VDD2, VDD3 and VDD4) which deliver power to internal
circuitry segments, and it has three ground pins (VSS1-3). These pins require connecting to ground plane
which will eliminate any common impedance with other critical switching signal return.
0.1F decoupling capacitors placed at VDD1, VDD2, VDD3 and VDD4 should be grounded at close to the
VSS1, the VSS2 and VSS3, respectively.
Rev 0.1
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[AK8157A]
The AK8157A is recommended to use with a premium DAC, the AK4490. Circuits for a high quality
premium audio solution are shown as below.
In this circuit, a 9.6MHz external clock is input to the AK8157A. MCLK, BCLK and LRCK are generated by
the AK8157A. SDATA for the AK4490 is output from the external DSP in synchronization with BCLK and
LRCK.
Digital
1.8V
VDD1.8V ground
6 LRCK
VCML 37
VREFLL 38
SMUTE
9
SCL
VDDR 28
10 SDA
VDDR 27
11 DIF0
AOUTRN 26
12 DIF1
AOUTRP 25
VSSR 30
0.1u 10u
VSSR 29
+
Rch
LPF
24 VCMR
N
23 VREFLR
13 CAD0
8
Controller
0.1u 10u
+
VSSL 31
WCK
22 VREFLR
0.1u
Micro-
Lch
LPF
VSSL 32
7
17 DEM1
4
VREFLL 39
SDATA
19 NC
BCLK
VDDL 33
5
18 CAD1
VSS2
0.1u
VDDL 34
BICK
16 DEM0
VDD3
VDD4
PDN
4
15 I2C
CAD1
3
RSTN
AOUTLP 36
3
14 PSN
SDA
10u
AOUTLN 35
AK4490EN
VDD2
AK8157A
2
VREFHL 40
1 NC
2 NC
21 VREFHR
VSS3
NC 42
LRCK
VREFHL 41
SCL
0.1u
20 VREFHR
VSS1
1
AVSS 44
MCLK
AVDD 43
A
VDD1
DVSS 46
B
CAD0
10u
0.1u
MCLK 45
C
CLKIN
10u
0.1u
TVDD 48
D
10u 10u
0.1u 0.1u
DVDD 47
9.6MHz
0.1u
Analog 5.0V
Analog 3.3V
0.1u
DSP
Digital
3.3V
0.1u
10u
Digital
1.8V
Digital
ground
Digital
1.8V
Digital
Ground
10u
Analog ground
Analog
Ground
+
Electrolytic Capacitor
Ceramic Capacitor
Figure 21. High Quality Premium Audio Solution of the AK4490 with the AK8157A
Rev 0.1
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[AK8157A]
11. Package
■ Outline Dimensions
0.4mm pitch 1.55mm x 1.55mm 16-pin WLCSP (Unit: mm)
φ0.015Ⓜ Ｃ A B
φ0.05Ⓜ Ｃ
14-φ0.265±0.03
B
A
0.4
3
2
0
1
0.175
1
A
1.55±0.03
4
(0.022)
D
0.175
C
B
A
0.4
0.58±0.034
0.382±0.02
1.55±0.03
0.03
C
0.198±0.03
C
■ Material & Lead finish
Package molding compound:
Epoxy, Halogen (bromine and chlorine) free
Solder ball material: SnAgCu
Rev 0.1
2016/04
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[AK8157A]
■ Marking
4
3
2
1
D
C
8157A
B
ＸＸＸＸ
A
1) Pin #A1 indication
2) Date Code: XXXX(4 digits)
3) Marking Code: 8157A
12. Ordering Guide
■ Ordering Guide
AK8157A
AKD8157A
40  +85C
16-pin WLCSP (0.4mm pitch)
Evaluation Board for the AK8157A
13. Revision History
Date (Y/M/D)
15/03/16
Revision
00
Reason
First Edition
Page
Contents
Rev 0.1
2016/04
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[AK8157A]
IMPORTANT NOTICE
0. Asahi Kasei Microdevices Corporation (“AKM”) reserves the right to make changes to the
information contained in this document without notice. When you consider any use or application
of AKM product stipulated in this document (“Product”), please make inquiries the sales office of
AKM or authorized distributors as to current status of the Products.
1. All information included in this document are provided only to illustrate the operation and
application examples of AKM Products. AKM neither makes warranties or representations with
respect to the accuracy or completeness of the information contained in this document nor grants
any license to any intellectual property rights or any other rights of AKM or any third party with
respect to the information in this document. You are fully responsible for use of such information
contained in this document in your product design or applications. AKM ASSUMES NO
LIABILITY FOR ANY LOSSES INCURRED BY YOU OR THIRD PARTIES ARISING FROM THE
USE OF SUCH INFORMATION IN YOUR PRODUCT DESIGN OR APPLICATIONS.
2. The Product is neither intended nor warranted for use in equipment or systems that require
extraordinarily high levels of quality and/or reliability and/or a malfunction or failure of which may
cause loss of human life, bodily injury, serious property damage or serious public impact,
including but not limited to, equipment used in nuclear facilities, equipment used in the aerospace
industry, medical equipment, equipment used for automobiles, trains, ships and other
transportation, traffic signaling equipment, equipment used to control combustions or explosions,
safety devices, elevators and escalators, devices related to electric power, and equipment used
in finance-related fields. Do not use Product for the above use unless specifically agreed by AKM
in writing.
3. Though AKM works continually to improve the Product’s quality and reliability, you are
responsible for complying with safety standards and for providing adequate designs and
safeguards for your hardware, software and systems which minimize risk and avoid situations in
which a malfunction or failure of the Product could cause loss of human life, bodily injury or
damage to property, including data loss or corruption.
4. Do not use or otherwise make available the Product or related technology or any information
contained in this document for any military purposes, including without limitation, for the design,
development, use, stockpiling or manufacturing of nuclear, chemical, or biological weapons or
missile technology products (mass destruction weapons). When exporting the Products or related
technology or any information contained in this document, you should comply with the applicable
export control laws and regulations and follow the procedures required by such laws and
regulations. The Products and related technology may not be used for or incorporated into any
products or systems whose manufacture, use, or sale is prohibited under any applicable domestic
or foreign laws or regulations.
5. Please contact AKM sales representative for details as to environmental matters such as the
RoHS compatibility of the Product. Please use the Product in compliance with all applicable laws
and regulations that regulate the inclusion or use of controlled substances, including without
limitation, the EU RoHS Directive. AKM assumes no liability for damages or losses occurring as a
result of noncompliance with applicable laws and regulations.
6. Resale of the Product with provisions different from the statement and/or technical features set
forth in this document shall immediately void any warranty granted by AKM for the Product and
shall not create or extend in any manner whatsoever, any liability of AKM.
7. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior
written consent of AKM.
Rev 0.1
2016/04
- 26 -