Data Sheet

MC33HB2001
10 A H-Bridge, SPI programmable brushed DC motor driver
Rev. 6.0 — 3 May 2016
1
Data sheet: Advance information
General description
The 33HB2001 is a SMARTMOS monolithic H-Bridge Power IC, enhanced with SPI
configurability and diagnostic capabilities. It is designed primarily for DC motor or servo
motor control applications within the specified current and voltage limits.
The 33HB2001 is able to control inductive loads with peak currents greater than 10 A.
The nominal continuous average load current is 3.0 A. A current mirror output provides
an analog feedback signal proportional to the load current.
This part is designed to specifically address the ISO 26262 safety requirements.
2
Simplified application diagram
Figure 1. Simplified application diagram
3
Features and benefits
• Advanced diagnostic reporting via a serial peripheral interface (SPI): charge pump
undervoltage, overvoltage, and undervoltage on VPWR, short to ground and short
to VPWR for each output, open load, temperature warning and overtemperature
shutdown
• Thermal management: Excellent thermal resistance of <1.0 °C/W between junction and
case (exposed pad)
• Eight selectable slew rates via the SPI: 0.25 V/μs to more than 16 V/μs for EMI and
thermal performance optimization
MC33HB2001
NXP Semiconductors
10 A H-Bridge, SPI programmable brushed DC motor driver
• Four selectable current limits via the SPI: 5.4/7.0/8.8/10.7 A covering a wide range of
applications
• Can be operated without SPI with default slew rate of 2.0 V/μs and a 7.0 A current limit
threshold
• Highly accurate real-time current feedback through a current mirror output signal with
less than 5.0 % error
• Drives inductive loads in a full H-Bridge or Half-bridge configuration
• Overvoltage protection places the load in high-side recirculation (braking) mode with
notification in H-Bridge mode
• Wide operating range: 5.0 V to 28 V operation
• Low RDS(on) integrated MOSFETs: Maximum of 125 mΩ (TJ = 150 °C) for each
MOSFET
• Internal protection for overtemperature, undervoltage, and short-circuit by signaling the
error condition and disabling the outputs
• I/O pins can withstand up to 36 V
4
Applications
•
•
•
•
5
Electronic throttle control
Exhaust gas recirculation control (EGR)
Turbo flap control
Electric pumps, motor control and auxiliaries
Ordering information
This section describes the part numbers available to be purchased along with their
differences.
Table 1. Orderable parts
Part number
Notes
MC33HB2001EK
[1]
MC33HB2001FK
[1]
Operating temperature
Package
TA = –40 °C to 125 °C
TJ = –40 °C to 150 °C
32-pin SOICW exposed pad
32-pin PQFN exposed pad
To order parts in Tape & Reel, add the R2 suffix to the part number.
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to http://www.nxp.com and perform a part number search.
MC33HB2001
Data sheet: Advance information
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10 A H-Bridge, SPI programmable brushed DC motor driver
6
Internal block diagram
Figure 2. Internal block diagram
MC33HB2001
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10 A H-Bridge, SPI programmable brushed DC motor driver
7
Pinning information
7.1 Pinning
Figure 3. Pin configuration for 32-pin SOICW
Figure 4. Pin configuration for 32-pin PQFN
7.2 Pin description
For functional description of each pin see Section 7.3 "Functional pin description".
Table 2. Pin description
Symbol
AGND
32-pin SOICW
1, 19
MC33HB2001
Data sheet: Advance information
32-pin PQFN
6, 24
Pin
function
GND
Definition
[1]
Ground for analog
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10 A H-Bridge, SPI programmable brushed DC motor driver
Symbol
32-pin SOICW
32-pin PQFN
Pin
function
Definition
ENBL
2
7
D_In
When ENBL is logic HIGH, the H-Bridge is operational.
When ENBL is logic LOW, the H-Bridge outputs are tristated and placed in Sleep mode.
DIS
3
8
D_In
When DIS is logic HIGH, both OUT1 and OUT2 are tristated
IN2
4
9
D_In
Logic input control of OUT2
IN1
5
10
D_In
Logic input control of OUT1
CFB
6
11
A_Out
The load current feedback output provides ground
referenced 0.25 % of the high-side output current.
FS_B
7
18
D_Out
Open drain active LOW status flag output
VPWR
8, 9, 24, 25
12, 13, 29, 30
Supply
These pins must be connected together physically as
close as possible and directly soldered down to a wide,
thick, low resistance supply plane on the PCB.
OUT1
10, 11
14, 15
A_Out
Source of HS1 and drain of LS1
—
12, 13, 14, 20,
21
16, 17, 19, 25,
26
NC
No connection to die or substrate
PGND
15, 16, 17, 18
20, 21, 22, 23
GND
Power ground for OUT1 and OUT2
OUT2
22, 23
27, 28
A_Out
Source of HS2 and drain of LS2
CCP
26
31
A_Out
External reservoir capacitor connection for the internal
charge pump; connected to VPWR
CS_B
27
32
D_In
SPI control chip select bar input pin
VDDQ
28
1
Supply
Logic level bias
MISO
29
2
D_Out
Provides digital data from HB2001 to the MCU
SCLK
30
3
D_In
SPI control clock input pin
MOSI
31
4
D_In
SPI control data input pin from MCU
DGND
32
5
GND
Ground for logic
EP
EP
EP
GND
Thermal exposed pad – connected to substrate
[1]
[1]
[1]
[1]
All PGND, AGND, DGND and EP pins must be connected together with very low-impedance on the PCB.
7.3 Functional pin description
7.3.1 Logic bias input (VDDQ)
VDDQ supplies a level shifted bias voltage for the logic level outputs designed to be
read by the microprocessor/microcontroller. This pin applies the logic supply voltage to
MISO making the output logic levels compliant to logic systems from 3.3 V to 5.0 V. See
Section 10.3 "VDDQ digital output supply voltage" for more details.
7.3.2 Supply voltage (VPWR)
VPWR is the power supply input for the H-Bridge. The input voltage range with full
performance is from 8.0 V to 28 V. In either case, the maximum allowable transient
MC33HB2001
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10 A H-Bridge, SPI programmable brushed DC motor driver
voltage during the event such as load dump is 40 V. Exceeding this limit could result in
an avalanche breakdown, as discussed in Section 11.3 "Output avalanche protection". A
Zener clamp and/or an appropriately valued capacitor are common methods of limiting
the transient. This pin must be externally protected against application of a reverse
voltage through an external inverted N-channel MOSFET, diode or switched relay.
7.3.3 Outputs (OUT1 and OUT2)
The OUT1 and OUT2 outputs drive the bi-directional DC motor. Each output has two
internal N-channel MOSFETs connected in a Half-bridge configuration between VPWR
and ground. Only one internal MOSFET is ON at one time for each output. The turn ON/
OFF slew times are determined by the selected SPI slew time register contents.
7.3.4 Inputs (IN1 and IN2)
The IN1 and IN2 inputs determine the direction of current flow in the H-Bridge by
directing the PWM input to one of the low-side MOSFETs (see Table 21). When a
change in the current direction is commanded via the microprocessor/microcontroller, the
PWM switches from one low-side MOSFET to the other without shoot-through current
in the H-Bridge. Both MOSFETs cannot be turned ON simultaneously in the same Halfbridge.
7.3.5 Enable inputs (ENBL)
The ENBL pin at logic [0] disables all four of the output drivers (outputs tri-stated) and the
part goes into Sleep mode. The ENBL pin at logic [1] enables the part functionality.
7.3.6 Disable inputs (DIS)
The DIS pin at logic [1] disables all four of the output drivers (outputs tri-stated) and the
part goes into Standby mode. However, it does not put the part in Sleep mode. The DIS
pin is at logic [0] does not inhibit the output.
7.3.7 Current recopy (CFB)
High-side FETs have a current recopy feature through an internal current-mirror which
supplies 1/400th of the load current. The current recopy has better than 5.0 % accuracy
for load currents between 2.0 A and 10 A. An external resistor may be connected to the
CFB pin (RCFB), which sets current to voltage gain. The circuit operates properly in the
presence of high-frequency noise. An external capacitor is used to provide filtering. Tie to
GND through a resistor if not used.
7.3.8 Charge pump capacitor (CCP)
This pin is the charge pump output pin for connecting the external charge pump reservoir
capacitor. A typical value is 100 nF. The capacitor must be connected from the CCP
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10 A H-Bridge, SPI programmable brushed DC motor driver
pin to the VPWR pin. The part does not operate properly without the external reservoir
capacitor.
7.3.9 Serial peripheral interface (SPI)
The 33HB2001 has a serial peripheral interface consisting of Chip Select (CS_B), Serial
Clock (SCLK), Master IN Slave Out (MISO), and Master Out Slave In (MOSI). This
device is configured as a SPI slave and is daisy-chainable (single CS_B for multiple SPI
slaves). See Section 9.6 "16-bit SPI interface" for detailed information on the SPI.
7.3.9.1 Serial clock (SCLK)
The SCLK input is the clock signal input for synchronization of serial data transfer. This
pin has TTL/CMOS level compatible input voltages, which allows proper operation with
microprocessors using a 3.3 V to 5.0 V supply. When CS_B is asserted low, the MOSI
data reads on the SCLK falling edge and the MISO data is updated on the SCLK rising
edge.
7.3.9.2 Serial data output (MISO)
The MISO is the SPI data out pin. When CS_B is asserted (low), the MSB is the first bit
of the word transmitted on MISO and the LSB is the last bit of the word transmitted on
MISO. After all 16 bits of the fault register are transmitted, the MISO output sequentially
transmits the digital data received on the MOSI pin. This allows the microprocessor to
distinguish a shorted MOSI pin condition. The MISO output continues to transmit the
input data from the MOSI input until CS_B eventually transitions from a logic [0] to a logic
[1]. The MISO output pin is in a high-impedance condition unless CS_B is low. When
active, the output is “rail to rail”, depending on the voltage at the VDDQ pin.
7.3.9.3 Serial data input (MOSI)
The MOSI input takes data from the microprocessor while CS_B is asserted (low). The
MSB is the first bit of each word received on MOSI and the LSB is the last bit of each
word received on MOSI. The 33HB2001 serially wraps around the MOSI input bits to the
MISO output after the MISO output transmits its fault flag bits. This pin has TTL/CMOS
level compatible input voltages, allowing proper operation with microprocessors using a
3.3 V to 5.0 V supply.
7.3.9.4 Chip select (CS_B)
The CS_B input selects this device for serial transfers. The SPI applies the contents of
the I/O register when CS_B rises. When CS_B falls, the I/O register is loaded with the
contents of the previously addressed register. This pin has TTL/CMOS level compatible
input voltages, which allows proper operation with microprocessors using a 3.3 V to 5.0 V
supply.
7.3.10 Status fault (FS_B)
This pin is the device fault status output which signals the MCU of any fault. The fault
status pin goes low to report system status according to the bits selected in the Fault
Status Mask register as explained in Table 15. This output is active LOW open drain
MC33HB2001
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10 A H-Bridge, SPI programmable brushed DC motor driver
structure, which requires a pull-up resistor to VDD. For more details on this pin, see
Table 21.
8
General product characteristics
8.1 Maximum ratings
Table 3. Maximum ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Symbol
Description (Rating)
Min.
Max.
Unit
SUPPLY
VPWR
Supply voltage (VPWR)
−0.3
40
V
VDDQ
Logic bias input (VDDQ)
−0.3
36
V
VAGND
Analog ground (AGND)
−0.3
0.3
V
VDGND
Digital ground (DGND)
−0.3
0.3
V
VPGND
Power ground (PGND)
−0.3
0.3
V
CHARGE PUMP
VCCP
Charge pump (CCP) voltage
−0.3
VPWR + 12 V
VIN1
Input 1 (IN1) voltage
−0.3
36
V
VIN2
Input 2 (IN2) voltage
−0.3
36
V
VDIS
Disable (DIS) voltage
−0.3
36
V
VENBL
Enable (ENBL) voltage
−0.3
36
V
VFS_B
Status flag (FS_B) voltage
−0.3
36
V
VMISO
Serial data output (MISO) voltage
–0.3
VMOSI
Serial data input (MOSI) voltage
–0.3
36
V
VCSB
Chip select (CS_B) voltage
–0.3
36
V
VSCLK
Serial clock (SCLK)
–0.3
36
V
VOUTX
OUT1 and OUT2 voltage
−0.3
VCFB
Current recopy (CFB)
−0.3
30
V
—
16
A
−3.0
3.0
mA
DIGITAL I/O
SPI
VDDQ + 0.3 V
OUTPUTS
VPWR + 2.0 V
CURRENTS
IPOUTX
OUTx peak current
Transient current (< 5.0 ms) TJ ≤ 150 °C
ICLAMP
Digital pin current in clamping mode
ENBL, DIS, MOSI, CS_B, SCLK, IN1, IN2
ESD PROTECTION
MC33HB2001
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10 A H-Bridge, SPI programmable brushed DC motor driver
Symbol
Description (Rating)
Min.
Max.
—
—
±2000
±4000
Unit
[1] [2]
VESD_A1
VESD_G1
ESD Voltage
Human Body Model (HBM)
Local pins, all pins except VPWR, OUT1, OUT2
Global pins: VPWR, OUT1, OUT2
VESD_A2
VESD_C2
Charge Device Model (CDM)
All pins
Corners pins
—
—
±500
±750
Machine Model
All pins
—
±200
Min.
Max.
−40
−40
150
195
°C
−40
125
°C
−65
150
°C
—
—
°C
VESD_C2
[1]
[2]
V
Human body model: AEC-Q100
Charged Device model and Machine model: AEC-Q100 Rev H
8.2 Thermal characteristics
Table 4. Thermal ratings
Symbol
Description (Rating)
Unit
THERMAL RATINGS
TJ
Operational junction temperature
Continuous
Transient
TA
Operational ambient temperature
TSTG
Storage temperature
TPPRT
[1]
Peak package reflow temperature during reflow
[2] [3]
MC33HB2001EK THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
RΘJA
Junction to Ambient Natural Convection – Single Layer
board (1s)
[4] [5]
—
75.1
°C/W
RΘJA
Junction to Ambient Natural Convection – Four Layer
board (2s2p)
[4] [5]
—
23.4
°C/W
RΘJB
Junction to Board
[6]
—
6.6
°C/W
RΘJCBOTTOM Junction to Case (bottom)
[7]
—
0.48
°C/W
ΨJT
[8]
—
2.56
°C/W
Junction to Package Top – Natural Convection
MC33HB2001FK THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS
RΘJA
Junction to Ambient Natural Convection – Single Layer
board (1s)
[4] [5]
—
63.13
°C/W
RΘJA
Junction to Ambient Natural Convection – Four Layer
board (2s2p)
[4] [5]
—
21.31
°C/W
RΘJB
Junction to Board
[6]
—
6.18
°C/W
RΘJCBOTTOM Junction to Case (bottom)
[7]
—
0.45
°C/W
ΨJT
[8]
—
2.38
°C/W
[1]
Junction to Package Top – Natural Convection
The circuit specification describes IC operation within the parametric operating range defined in the electrical characteristic table.
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10 A H-Bridge, SPI programmable brushed DC motor driver
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction
or permanent damage to the device.
NXP's Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture
Sensitivity Levels (MSL), Go to nxp.com, search by part number. Remove prefixes/suffixes and enter the core ID to view all orderable parts (for
MC33xxxD enter 33xxx), and review parametrics.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for 1s or 2s2p board, respectively.
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the board
near the package.
Thermal resistance between the die and the solder pad on the bottom of the package. Interface resistance is ignored.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-2.
When Greek letters (Ψ) are not available, the thermal characterization parameter is written as Psi-JT.
8.3 Operating conditions
This section describes the operating conditions of the device. Conditions apply to the
following data, unless otherwise noted.
Table 5. Nominal operation
Within the range of functionality, all functionalities have to be guaranteed. All voltages refer to GND. Currents are positive
into and negative out of the specified pin. TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Description (Rating)
Min.
Max.
Unit
Functional operating supply voltage range—VPWR
5.0
28
V
SPI frequency range
0.5
10
MHz
Min.
Max.
[1]
—
20
mA
[2]
—
50
μA
—
−60
100
—
μA
SUPPLY VOLTAGE
VPWR
SPI
fSPI
Table 6. Supply current consumption
VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Description (Rating)
Unit
VPWR SUPPLY CURRENT CONSUMPTIONS
IVPWR
Operating mode—VPWR
IVPWR(SLEEP) Sleep mode, measured at VPWR = 12 V
LEAKAGE CURRENTS FOR THE FUNCTIONS CONNECTED TO VPWR
IOUTLEAK
[1]
[2]
Output leakage current, outputs off, VPWR = 28 V
VOUTx = VPWR
VOUTx = GND
ENBL = Logic [1], IOUT = 0 A
ENBL = Logic[0], DIS = Logic[1] and IOUT = 0 A
8.3.1 Reverse battery
To protect against a reverse battery condition, a dedicated device to block reverse
current must be populated in the application, as shown in Figure 21 (with a diode).
Some applications require operation at very low battery voltages (start-stop applications),
and many systems have multiple H-Bridges in parallel, which require high current reverse
battery protection with very low voltage drops during the operation. In such applications,
an external, reverse-polarity, FET may be used instead of the reverse protection diode, to
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10 A H-Bridge, SPI programmable brushed DC motor driver
lower the voltage drop from battery to VPWR pins. The CCP pin can be used to bias the
gate of an N-channel FET, provided the bias current requirement is less than 20 μA. In
Figure 22, the NPN transistor is used for fast response of the N-Channel FET during turnoff.
8.3.2 Digital I/Os characteristics
Table 7. Digital I/Os characteristics
VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Parameter
Min.
Max.
Unit
DIGITAL INPUTS
VIH_X
Input high-voltage
2.0
—
V
VIL_X
Input low-voltage
—
0.8
V
VHYS_X
Input voltage threshold hysteresis
100
—
mV
RPD_X
Input pull-down resistance—MOSI, SCLK, ENBL, IN1, IN2
40
175
kΩ
RPU_X
DIS, CS_B Input pull-up resistance to 5.0 V
40
175
kΩ
CIN
Input capacitance
—
12
pF
0.8 × VDDQ
—
V
—
0.4
V
DIGITAL OUTPUTS
VOH_X
MISO output high-voltage, with −1.0 mA
VOL_X
MISO output low-voltage, with 1.0 mA
IMISO_LK
MISO tri-state leakage current
−10
10
μA
VOL_FS_B
FS_B low-voltage, with 1.0 mA
—
0.4
V
RPU_FS_B
FS_B output pull-up resistance to 5.0 V
100
500
kΩ
9
General IC functional description and application information
9.1 Introduction
The 33HB2001 is a programmable H-Bridge, power integrated circuit (IC) designed to
drive DC motors or bi-directional solenoid controlled actuators, such as throttle control or
exhaust gas recirculation actuators. It is particularly well suited for the harsh environment
found in automotive power train systems. The 33HB2001 is designed to specifically
address the ISO 26262 safety standard requirements. The key characteristic of this
versatile driver is configurability. The selectable slew rate permits the customer to choose
the slew rate needed for performance and noise suppression. The Serial Peripheral
Interface (SPI) allows the system microprocessor to clear the fault register, select a
programmable current limit, and select the slew rate.
The 33HB2001 is designed to drive a bi-directional DC motor using pulse-width
modulation (PWM) for speed and torque control. A current mirror output provides an
analog feedback signal proportional to the load current. SPI diagnostic reporting includes,
open load, short-to-battery, short-to-ground, die temperature range, overvoltage, and
undervoltage.
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10 A H-Bridge, SPI programmable brushed DC motor driver
9.2 Features
• Advanced diagnostic reporting via the serial peripheral interface (SPI)
– Charge pump undervoltage
– Overvoltage and undervoltage on VPWR
– Short to ground as well as short to VPWR for each output
– Open load
– Temperature warning
– Overtemperature shutdown
• Excellent thermal resistance of <1.0 °C/W between junction and case (exposed pad)
• Eight selectable slew rates via the SPI from 0.25 V/μs to more than 16 V/μs, giving the
user flexibility to perform trade-offs between low EMI and better thermal performance
• Active current limiting with four selectable current limits via the SPI: 5.4/7.0/8.8/10.7 A
covering a wide range of applications
• Can be operated without SPI with default slew rate of 2.0 V/μs and a 7.0 A current limit
threshold. See Figure 21 for operation without SPI
• Efficient thermal management scheme by reducing the switching losses to ensure
continuous operation and availability of the part under harsh operating conditions
• Accurate real-time current feedback through a current mirror output signal with less
than 5.0 % error
• Configurable for full H-Bridge or Half-bridge operation through the SPI
• Overvoltage protection places the load in high-side recirculation (braking) mode and
signal the error condition in H-Bridge mode
• Wide operating range: 5.0 V to 28 V operation
• Low RDS(on) integrated MOSFETs: Maximum 125 mΩ (TJ = 150 °C) for each MOSFET
• Internal protection for short-circuit, overtemperature, and undervoltage by signaling the
error condition and disabling the outputs
• I/O pins can withstand up to 36 V
9.3 Functional block diagram
Figure 5. Functional block diagram
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10 A H-Bridge, SPI programmable brushed DC motor driver
9.4 Functional description
9.4.1 H-Bridge output drivers (OUT1 and OUT2)
The 33HB2001 Power IC provides the means to efficiently drive a DC motor in both
forward and reverse shaft rotation via a monolithic H-Bridge comprising low RDS(on) Nchannel MOSFETs and integrated control circuitry. The switching action of the H-Bridge
can be pulse-width modulated to obtain both torque and speed control, with slew rates
selectable from 0.25 V/μs to 16 V/μs in eight steps, giving the user flexibility to perform
trade offs between meeting the EMI requirements and minimize switching losses. The
outputs comprise four Power MOSFETs configured as a standard H-Bridge, controlled by
the IN1 and IN2 inputs.
9.4.2 Analog control, protection, and diagnostics
The 33HB2001 has integrated voltage regulators supplying the logic and protection
functions internally. This reduces the requirements for external supplies and insures
the device is safely controlled at all times when battery voltage is applied. An integrated
charge pump provides the required bias levels to insure the output MOSFETs turn fully
ON when commanded. Each MOSFET provides feedback to the protection circuitry by
way of a current sensor. Each sense signal is compared with programmable overcurrent
levels and produces an immediate shutdown in case of a high current short-circuit. The
high-side current sense is also used for producing a current limiting PWM to reduce
overload conditions as determined by the programmable limits. The high-side current
sense is available to the MCU as an analog current proportional to the load current.
Each MOSFET has overtemperature protection circuitry disabling the device. A thermal
warning sets a flag in the SPI register when the device is approaching a protection limit.
A thermal management scheme decreases the current limiting PWM frequency, while
keeping the average current at the selected limit.
The 33HB2001 consists of advanced diagnostics and protection features such as open
load detection, overvoltage sense and protection, undervoltage protection, or charge
pump undervoltage detection.
9.4.3 MCU interface and output control
The SPI and control logic signals are compatible with both 5.0 V and 3.3 V logic systems.
The SPI provides an easy to configure interface for the MCU through programmable
control of output slew rates, current limits, enabling/disabling of outputs, SPI equivalent
of inputs (VIN1 and VIN2), and mode of operation (H-Bridge/half-bridge). The status
register makes detailed diagnostics available for protective and warning functions. The
output drivers are controlled by the input signals ENBL, DIS, IN1, and IN2 using the
parallel inputs and VIN1, VIN2, as well as EN using the SPI control.
9.5 Modes of operation
9.5.1 Description
The operating modes are:
• Sleep mode
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10 A H-Bridge, SPI programmable brushed DC motor driver
All 33HB2001 functions are disabled. The current consumption does not exceed the
sleep-state current specification.
• Standby mode
All 33HB2001 logic are fully operational with the outputs in a high-impedance state.
• Normal mode
All 33HB2001 functions are fully operational. Any detected faults transition the device
to Fault mode.
• Fault mode
Certain of functions are forced off and FS_B signal is latched to logic [0] indicating a
fault.
Figure 6. Operating mode state diagram
The 33HB2001 wakes up by EN going to a logic high state. If a valid wake-up event
occurs while the VPWR voltage level is above the specified threshold, the regulators
power-up sequence is initiated as illustrated in Figure 7.
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10 A H-Bridge, SPI programmable brushed DC motor driver
Figure 7. Regulators power-up and power-down sequences
On Power-up, Fault Status (FS_B) activates after the internal supplies reach their
operating threshold. All regulators acquire their steady-state by the turn-on delay time
(tTURN-ON). On power-up, FS_B is active for at least tPO, and then deactivates after VCP
is greater than the undervoltage threshold (VCP_UV) and all faults are clear. When ENBL
transitions to logic LOW, the outputs turn off (high-impedance state) and FS_B goes
low. Power-down starts tPD_DLY after ENBL goes low. DIS must also be low for FS_B to
deactivate. On Power-down, FS_B is activated until the internal supplies are disabled.
9.5.2 Electrical characteristics
Table 8. Electrical characteristics
VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
—
—
1.0
ms
Wake-up
[1]
tTURN-ON
Turn-on delay time. Time from ENBL going high to FS_B
returning high
tPO
Turn-on Status time. Minimum pulse width on FS_B
during power up
1.0
—
2.0
μs
tPD_DLY
Turn-off delay time. ENBL going low until FS_B is
allowed to go high
8.0
—
11
μs
[1]
ENBL is a digital input and has the characteristics defined in Table 7.
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9.6 16-bit SPI interface
9.6.1 Description
The Serial Peripheral Interface (SPI) has the following features:
•
•
•
•
•
Full duplex, 4-wire synchronous communication
Slave mode operation only
Fixed SCLK polarity and phase requirements
Fixed 16-bit command word
SCLK operation up to 10 MHz
The SPI communication works as follows:
Figure 8. SPI dynamic diagram
SPI communication is “MSB first” and is composed of 16 SCLK cycles. The MOSI data
is read on SCLK falling edge and the MISO data is updated on SCLK rising edge. The
daisy-chain feature passes data in excess of 16 bits to the next device in line. If the
number of clock pulses within CS_B low is not more than 0 and an integer multiple of 16,
the current SPI communication is ignored and a framing error is recorded in the status
register. Both the serial input and the serial output data are valid on the SCLK falling
edge, and transitions on the rising edge of SCLK.
The content reported by the 33HB2001 is the previous selected register address at the
time CS_B goes low. On the first SPI communication after enable goes high, the first
register sent on the MISO line is the status register. When addressing a READ register,
the content bits are ignored. See Table 9 for detail on timing parameters.
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10 A H-Bridge, SPI programmable brushed DC motor driver
9.6.2 Electrical characteristics
Table 9. Electrical characteristics
VDDQ = 3.13 V to 5.25 V, TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
SPI INTERFACE TIMING
fSPI
Recommended frequency of SPI operation, tSPI = 1/fSPI
0.5
—
10
MHz
tLEAD
Falling edge of CS_B to rising edge of SCLK (required setup
time)
30
—
—
ns
tLAG
Falling edge of SCLK to rising edge of CS_B (required setup
time)
30
—
—
ns
tXFER_DELAY
No data time between SPI commands
300
—
—
ns
tWH
High time of SCLK
45
tSPI/2
—
ns
tWL
Low time of SCLK
45
tSPI/2
—
ns
tSU
SCLK rising edge to MOSI (required setup time)
15
—
—
ns
tSO(EN)
Time from falling edge of CS_B to MISO low-impedance
—
—
30
ns
tSO(DIS)
Time from rising edge of CS_B to MISO high-impedance
—
—
30
ns
tVALID
Time from falling edge of SCLK to MISO data valid, VDDQ =
5.0 V, 1.0 V ≤ MISO ≤ 4.0 V, CL = 50 pF
—
—
30
ns
tVALID
Time from falling edge of SCLK to MISO data valid, VDDQ =
3.3 V, 0.66 V ≤ MISO ≤ 2.64 V, CL = 50 pF
—
—
45
ns
tH
Data hold time
30
—
—
ns
9.6.3 SPI fault reporting
The 33HB2001 has an advanced SPI fault reporting and error detection feature. The fault
status register latches a fault at the time a fault is detected.
9.6.3.1 Clearing the fault status
The fault status is cleared when the fault is no longer present and one of three events
occurs, this is referred to as “clr_flt” throughout this document.
Table 10. Timing parameters for clearing fault status
Symbol
Characteristic
Min.
Typ.
Max.
Unit
tDIS_MIN
The falling edge of a logic signal on DIS clears nonactive faults. Minimum pulse width to ensure the faults
are cleared.
—
—
1.0
μs
tENBL_MIN
The rising edge of a logic signal on ENBL clears nonactive faults. Minimum pulse width to ensure the faults
are cleared.
—
—
1.0
μs
A write to the status register selectively clears fault
status with a ‘1’ in this bit location.
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9.6.3.2 SPI framing error detection
A SPI Framing error is recorded if either of the following two conditions are met:
• The number of clock pulses within CS_B low is not more than 0 and an integer multiple
of 16
• Register 00 is addressed for a Write operation
9.6.4 SPI mapping
Bit 15 is 1 for a Write operation and 0 for a Read operation. A write to the status register
selectively clears the fault status with a ‘1’ in this bit location, unless the fault is still
present.
Table 11. SPI register selection
14
13
Register
0
0
Device Identification (Reserved)
0
1
Status
1
0
Fault Status Mask
1
1
Configuration and Control
Table 12. Device identification (Reserved)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
0
0
RV3
RV2
RV1
RV0
RV0-RV3 reserved bits. Bit 4 is the device identifier.
Table 13. Status
Bit
Name
Read
[1]
Write
[1]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
—
—
FRM
CP_U
UV
OV
SCP2
SCP1
SCG2
SCG1
OL
OC
TW
OT
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
X
X
X
X
X
X
X
X
X
X
X
X
The default value for all bits (bit 0 to bit 11) in status register is 0 if no fault is detected in the device.
Table 14. Status bits description
Bit
Bit name
15
—
—
14
—
—
13
—
—
12
—
—
11
FRM
SPI framing error
10
CP_U
Charge pump undervoltage
9
UV
VPWR undervoltage
8
OV
VPWR overvoltage
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Bit
Bit name
Description
7
SCP2
Short-circuit to power output 2
6
SCP1
Short-circuit to power output 1
5
SCG2
Short-circuit to ground output 2
4
SCG1
Short-circuit to ground output 1
3
OL
Open load
2
OC
Overcurrent - current limit has been activated
1
TW
Thermal warning
0
OT
Overtemperature shutdown
Table 15. Fault status mask
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
—
—
—
DOV
FRM
CP_U
UV
OV
SCP2
SCP1
SCG2
SCG1
OL
OC
TW
OT
0
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
0
0
X
X
X
X
X
X
X
X
X
X
X
X
Read
[1]
Write
[1]
The SPI bits in “Read” section show the default values.
The mask bits are in the same order as the Status bits. A '1' causes the FS_B to become
active when this fault is active.
Bit 12 (DOV - Disable overvoltage) configures the response to an overvoltage condition:
• 1 = Disable overvoltage protection (OV bit is warning only)
• 0 = Enable overvoltage protection in Full Bridge mode
Table 16. Configuration and control
Bit
Name
Read
[1]
Write
[1]
15
14
13
12
11
10
9
8
7
6
5
4
3
2
—
—
—
CL
TM
AL
ILM1
ILM0
SR2
SR1
SR0
EN
0
1
1
0
1
1
0
1
1
0
0
1
1
0
1
1
1
X
X
X
X
X
X
X
X
X
X
X
MODE INPUT
1
0
VIN2
VIN1
0
0
X
X
The SPI bits in “Read” section show the default values.
Table 17. Configuration and control bits description
Bit
Bit name
15
—
—
14
—
—
13
—
—
12
CL
Check for open load (in Full Bridge Standby mode)
• 1 = Enabled on transition from Standby to Normal mode. Execute test in Standby on
transition to 1
• 0 = Disable test
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[1]
Bit
Bit name
Description
11
TM
Thermal Management mode
• 1 = Enable change of current limit frequency by control of tB when OTw state
• 0 = Disable change of current limit frequency by OTw, tB shall be set to the slowest
setting
10
AL
Active Current Limit mode
• 1 = Enable active current limit when overcurrent ILIM threshold has been exceeded
• 0 = Disable active current limit. Exceeding overcurrent ILIM threshold set OC flag but
does not control outputs
9
ILIM1
ILIM Bit 1
8
ILIM0
ILIM Bit 0
7
SR2
Slew Rate Bit 2
6
SR1
Slew Rate Bit 1
5
SR0
Slew Rate Bit 0
4
EN
Disable Outputs
• 1 = ENABLE output control when ENBL pin is high and DIS pin is low
• 0 = DISABLE output control and tri-state outputs
3
MODE
Input Control mode
• 1 = H-Bridge Control mode
• 0 = Half-Bridge Control mode
2
INPUT
Active INPUT Control mode
• 1 = SPI control of outputs by way of VIN1 and VIN2, IN1 pin and IN2 pin are disabled
• 0 = Parallel control of outputs by way of IN1 pin and IN2 pin, VIN1 and VIN2 are
disabled
1
VIN2
Virtual Input 2 (SPI equivalent of IN2)
• 1 = ON equivalent to IN2 pin at logic high in parallel mode
• 0 = OFF equivalent to IN2 pin at logic low in parallel mode
0
VIN1
Virtual Input 1 (SPI equivalent of IN1)
• 1 = ON equivalent to IN1 pin at logic high in parallel mode
• 0 = OFF equivalent to IN1 pin at logic low in parallel mode
[1]
When MODE=0 (Half-bridge mode): Active Current Limit mode is disabled, OV is a warning only, SC acts independent on each output, open load is
disabled.
9.7 Protection and supervision
The 33HB2001 includes supervision features which enable advanced diagnostics by
monitoring the VPWR undervoltage, VPWR overvoltage and die temperature.
9.7.1 VPWR undervoltage detection
9.7.1.1 Description
When VPWR is less than VPWR_FUV longer than tVPWR all output transistors turn off and
remain off until VPWR increases above the VPWR_FUV threshold by VPWR_UVHYS. While
ramping up the voltage on VPWR, when VPWR increases to a voltage greater than
VPWR_FUV + VPWR_UVHYS for at least tVPWR, the 33HB2001 starts unrestricted operation.
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9.7.1.2 Electrical characteristics
Table 18. VPWR_UV electrical characterization
TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
VPWR UNDERVOLTAGE
VPWR_FUV
Undervoltage threshold to disable outputs (falling edge)
3.55
—
4.0
V
VPWR_UVHYS
Undervoltage hysteresis
250
—
450
mV
tVPWR
Undervoltage detection filter time
—
—
10
μs
VPWR_POR
Power On Reset with VPWR falling
2.3
—
3.1
V
9.7.2 VPWR overvoltage detection
If VPWR voltage is higher than OV_HSD threshold longer than tOV_HSD, the OV status bit
is set and the device is in an overvoltage condition. When the device is in an overvoltage
condition and is also in H-Bridge mode (MODE bit =1), both OUT1 and OUT2 low-side
switches controlling the load is turned off and both OUT1 and OUT2 high-side switches
are turned on to drain the energy in the load.
When VPWR voltage drops by more than OV_HYS below the OV_HSD threshold, the
outputs are restored to operation without an overvoltage condition. The OV status bit is
not reset until clr_flt conditions are satisfied.
9.7.2.1 Electrical characteristics
Table 19. VPWR_OV electrical characterization
TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
33
35
37
V
2.3
2.45
2.5
V
—
—
3.0
μs
OVERVOLTAGE DETECTION
VPWR_OV_HSD
Overvoltage detection threshold
VPWR_OV_HYS
Overvoltage detection hysteresis
tOV_HSD
[1]
[1]
Overvoltage detection filter time
Measured in H-Bridge mode, 1.0 A resistive load, SR = 000, measured from FS_B low to both VOUT ≥ 10 % VPWR
9.7.3 Die temperature
9.7.3.1 Description
The 33HB2001 has temperature sensors near the center of each power device.
The threshold of the overtemperature warning (OTW) is approximately 150 °C on any
power device. Temperature warning condition is defined as exceeding OTw. When a
temperature warning occurs, outputs are not shutdown. However, the SPI status bit
shows the actual status at accessing time. This is a non-latching condition and the
status clears when the temperature falls below the hysteresis threshold. Further action is
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10 A H-Bridge, SPI programmable brushed DC motor driver
taken on temperature warning as described in Section 9.6.4 "SPI mapping" and Section
10.4.1.4 "Active current limit regulation".
When the temperature is above the overtemperature threshold (OT) for the defined filter
time (tOT), the driver latches off, the SPI OT fault bit is set. This is a latching fault and
requires performing clr_flt, as described in Section 9.6.3.1 "Clearing the fault status",
after the temperature reduces THYS below the threshold.
9.7.3.2 Electrical characteristics
Table 20. OT electrical characterization
VPWR = 5.0 V to 28 V, unless otherwise specified.
Symbol
Characteristic
Min.
Typ.
Max.
Unit
OVERTEMPERATURE/TEMPERATURE WARNING
Overtemperature warning detection threshold
[1]
140
150
165
°C
Overtemperature shutdown threshold
[1]
165
175
190
°C
THYS
Overtemperature hysteresis
[1]
—
12
—
°C
tOT
Temperature warning detection filter time
—
—
11
μs
OTW
OT
[1]
Guaranteed by characterization.
9.7.4 Truth table
The following truth table summarizes the output response to input states. The tri-state
conditions and the status flag are reset using DIS, ENBL, or SPI. The truth table uses the
following notations: L = LOW, H = HIGH, X = HIGH or LOW, Xb is inverse of X, and Z =
High-impedance.
Table 21. Truth table
Status
Input conditions
Device state
ENBL
[1]
DIS
IN1
[2]
IN2
[2]
FS_B
[3]
Outputs
OUT1
OUT2
HALF-BRIDGE CONTROL MODE
Forward
H
L
H
L
H
H
L
Reverse
H
L
L
H
H
L
H
Freewheeling Low
H
L
L
L
H
L
L
Freewheeling High
H
L
H
H
H
H
H
IN1 Disconnected
H
L
Z
X
H
L
X
IN2 Disconnected
H
L
X
Z
H
X
L
Forward
H
L
H
H
H
H
L
Reverse
H
L
L
H
H
L
H
Freewheel High
H
L
X
L
H
H
H
IN1 Disconnected – Reverse
H
L
Z
X
H
Xb
H
H-BRIDGE CONTROL MODE
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10 A H-Bridge, SPI programmable brushed DC motor driver
Status
Input conditions
Device state
ENBL
[1]
[2]
DIS
IN1
H
L
X
Z
Disable (DIS)
H
H
X
DIS Disconnected
H
Z
H
[2]
FS_B
[3]
OUT1
OUT2
H
H
H
X
L
Z
Z
X
X
L
Z
Z
X
X
X
L
Z
Z
H
X
X
X
L
H
H
H
X
X
X
L
Z
Z
H
X
X
X
L
Z
Z
Sleep mode ENBL
L
X
X
X
H
Z
Z
ENBL Disconnected
Z
X
X
X
H
Z
Z
IN2 Disconnected – Freewheel High
IN2
Outputs
PROTECTION
[4]
Undervoltage Lockout
[5]
Overvoltage
Overtemperature
Short-circuit
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[6]
[7]
SPI bit EN=1 AND DIS=L for table entry DIS=L
When the SPI bit INPUT = 1, the SPI bit VIN1 behaves the same as IN1 and SPI bit VIN2 behaves the same as IN2.
Default response for FS_B, SPI programming may change the default behavior.
In the event of an undervoltage condition, the outputs tri-state and status flag is SET logic LOW. Upon undervoltage recovery the outputs are restored to
their original operating condition, FS_B remains low until clr_flt clears the status register.
In the event of an overvoltage condition, the outputs go to freewheeling high configuration, independent of the input signals, and the status flag is latched
to a logic LOW. Upon overvoltage recovery, the outputs are restored to following the input signals but FS_B remains low until clr_flt clears the status
register. In Half-bridge mode an overvoltage event does not change the output state.
When a short-circuit or overtemperature condition is detected, the power outputs are tri-state latched-OFF, independent of the input signals, and the
status flag is latched to a logic LOW. To reset from this condition requires the toggling of either DIS, ENBL, or VPWR or flt_clr from the SPI.
When in H-Bridge control mode, short-circuit controls both OUT1 and OUT2. However, in Half-bridge mode, short-circuit only controls the output which
detects the short-circuit.
Figure 9. Output operating configurations
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10 A H-Bridge, SPI programmable brushed DC motor driver
Figure 10. H-Bridge operation with ENBL = 1 and DIS = 0
Figure 11. Half-bridge operation with ENBL = 1 and DIS = 0
9.8 Error handling
Table 22. Error handling
Type of error
Detection condition
Action
Clear SPI flag
Restart condition
SUPERVISION
Overtemperature
Shutdown
Normal mode
See Table 21
Write Clear Fault SPI
bit OT
Latching fault requires
clr_flt
Die temperature
warning
All except Sleep mode
SPI flag only (TW)
Non-latching auto
clears when condition
clears
Non-latching fault
clears when condition
clears
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Type of error
Detection condition
Action
Clear SPI flag
Restart condition
Overcurrent
Normal Mode
SPI flag only (OC)
Write Clear Fault SPI
bit OC
Latching fault requires
clr_flt
Open load
Transition to Normal
mode or request from
MCU
SPI flag only (OL)
Write Clear Fault SPI
bit OL
Information only, no
restart required
Short-circuit to Ground Normal mode
Output 1
See Table 21
Write Clear Fault SPI
bit SCG1
Latching fault requires
clr_flt
Short-circuit to Ground Normal mode
Output 2
See Table 21
Write Clear Fault SPI
bit SCG2
Latching fault requires
clr_flt
Short-circuit to VPWR
Output 1
Normal mode
See Table 21
Write Clear Fault SPI
bit SCP1
Latching fault requires
clr_flt
Short-circuit to VPWR
Output 2
Normal mode
See Table 21
Write Clear Fault SPI
bit SCP2
Latching fault requires
clr_flt
VPWR Overvoltage
All except Sleep mode
See Table 21
Write Clear Fault SPI
bit OV
Non-latching fault
clears when condition
clears
VPWR Undervoltage
All except Sleep mode
See Table 21
Write Clear Fault SPI
bit UV
Non-latching fault
clears when condition
clears
CP Undervoltage
All except Sleep mode
SPI flag only (CP_UV). Non-latching fault
No action, except
clears when condition
if micro requests a
clears
shutdown
Non-latching fault
clears when condition
clears
SPI failure
All except Sleep mode
SPI flag only (FRM)
A valid SPI
communication
Write Clear Fault SPI
bit FRM
10 Functional block description
10.1 Oscillator
A single clock module is used for all systems and filter timing.
10.1.1 Frequency modulation
The clock is frequency modulated to spread the oscillator’s energy over a wide frequency
band. This spreading decreases the peak electromagnetic radiation level and improves
electromagnetic compatibility (EMC) performance.
Table 23. Frequency electrical characteristics
VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
8.277
9.3
10.323
Unit
Oscillator
fOSC
Oscillator frequency
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10 A H-Bridge, SPI programmable brushed DC motor driver
10.2 Charge pump
10.2.1 Description
The charge pump generates a voltage of 9.5 V nominal/12 V maximum above the VPWR
supply. The maximum external load which can be connected to the CCP pin is 20 μA.
The charge pump requires an external 20 V capacitor for energy storage and to cover
transients. A SPI flag error is reported when VCP ≤ VCP_UV. The charge pump frequency
is modulated by means of the spread spectrum modulation of the main clock.
Table 24. Charge pump electrical characteristics
VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
Charge pump
Charge pump external capacitor
[1]
—
100
—
nF
Charge pump voltage referenced to VPWR
[2]
VCP_UV
9.5
12
V
VCP
Charge pump voltage referenced to VPWR
[3]
6.0
—
(2 × VPWR)
− 1.0
V
ICP
Charge pump current capability
1.0
—
VCP_UV
Charge pump undervoltage threshold
7.45
8.0
8.7
V
tCP_UV_F
Charge pump undervoltage detection filter time
—
18.0
—
μs
fCP
Charge pump frequency
—
9.3
—
MHz
CCP
VCP
[1]
[2]
[3]
mA
A 20 V X7R capacitor with at least ≤ ±20 % tolerance is recommended.
With 1.0 mA loading on the charge pump and 8.0 V ≤ VPWR < 28.0 V
With 1.0 mA loading on the charge pump and 5.0 V ≤ VPWR < 8.0 V
10.3 VDDQ digital output supply voltage
10.3.1 Description
The VDDQ pin supplies the digital output buffer (MISO) of the 33HB2001, either at 5.0 V
or 3.3 V, by connecting externally to the system MCU supply:
Figure 12. Digital output buffer supply
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10 A H-Bridge, SPI programmable brushed DC motor driver
This pin has a pull-down resistor to ensure the input is low in the event it is left open. If
this pin is shorted to ground or left open, the SPI MISO reports 0000h.
Table 25. VDDQ electrical characterizations
VDDQ = 3.13 V to 5.25 V, TJ = –40 °C to 150 °C, unless otherwise specified.
Symbol
RDOWN_VDDQ
Characteristic
VDDQ pull-down resistor
Min.
Typ.
Max.
55
100
260
Unit
kΩ
10.4 H-Bridge and Half-bridge operation
10.4.1 Description
The H-Bridge output control is defined by the SPI bit.
Half-bridge control
• In parallel mode, the physical inputs IN1 and IN2 control the OUT1 and OUT2
respectively
• In SPI mode, VIN1 and VIN2 control the Half-bridge outputs similar to physical inputs
H-Bridge control
• In parallel mode, the physical input IN1 controls direction and IN2 controls PWM
• In SPI mode, VIN1 and VIN2 control the H-Bridge outputs similar to physical inputs
This device provides active recirculation through the opposing FET of each Half-bridge.
Embedded protections avoid cross conduction. In Half-bridge mode, active current limit,
overvoltage protection, and open load detection features are disabled. For overvoltage,
there is OV warning only. Moreover, unlike H-Bridge control mode, the short-circuit
protection acts independently on each output.
A more detailed explanation of output characteristic with respect to inputs in H-Bridge as
well as Half-bridge mode is explained in Section 9.7.4 "Truth table". The differences in
fault priorities between the two modes is described in section Section 10.4.1.1 "H-Bridge
and Half-bridge fault priority".
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10.4.1.1 H-Bridge and Half-bridge fault priority
The following tables specify which fault control dominates output control if two or more
are present at one time. Note that for these tables ENBL and DIS are defined as the
signal condition which disables the output. EN is the SPI control bit setting which disables
the outputs.
Table 26. H-Bridge mode fault priority
OT
OC
SCG1
SCG2
SCP1
SCP2
OV
UV
ENBL
OC
OT
SCG1
SC
SC
SCG2
SC
SC
SC
SCP1
OT
SC
SC
SC
SCP2
OT
SC
SC
SC
SC
OV
OT
OV
SC
SC
OV
OV
UV
UV
UV
UV
UV
UV
UV
UV
ENBL
ENBL
ENBL
ENBL
ENBL
ENBL
ENBL
ENBL
ENBL
DIS
DIS
DIS
DIS
DIS
DIS
DIS
OV
DIS
ENBL
EN
EN
EN
EN
EN
EN
EN
OV
UV
ENBL
SCP2
UV
DIS
DIS
Table 27. Half-bridge mode fault priority
OT
SCG1
SCG2
SCP1
ENBL
SCG1
OT
SCG2
OT
SC1 AND 2
SCP1
OT
SC1
SCP2
OT
SC1 AND 2 SC2
SC1 AND 2
UV
UV
UV
UV
UV
UV
ENBL
ENBL
ENBL
ENBL
ENBL
ENBL
ENBL
DIS
DIS
DIS
DIS
DIS
DIS
DIS
ENBL
EN
EN
EN
EN
EN
EN
UV
ENBL
DIS
SC1 AND 2
DIS
Table 28. Fault priority description
Name
Description
OT
Overtemperature
OC
Overcurrent
SC
Short-circuit
SCGx
Short to ground
SCPx
Short to power (VPWR)
OV
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10 A H-Bridge, SPI programmable brushed DC motor driver
Name
Description
UV
Undervoltage
10.4.1.2 Current recopy
High-side FETs have current recopy feature. Current recopy has less than 5 % error
referred to the load, for currents between 2.0 A and 10 A. Current recopy is a ratio of
1/400 of the current through the FET. This recopy current is made available on the CFB
pin.
10.4.1.3 Slew rate selection
The slew rate is selectable by SPI bits from 0.25 V/μs to 16 V/μs. There is a bypass
setting which switches the outputs as fast as possible.
10.4.1.4 Active current limit regulation
The following figure presents the simplified current regulation loop.
Figure 13. Simplified current regulated loop for ILIM
The active current limit threshold is selectable by the SPI in four steps from 5.0 A to 10 A.
The active current limit is initiated, and the OC SPI fault status bit is set when the current
exceeds the threshold set by the current limit comparator.
A blanking time (tB, 32 μs) is set from the time the current limit is exceeded. If a shortcircuit shutdown is not triggered before the blanking time has expired, the H-Bridge
switches to high-side recirculation mode for 2*tA. tA is determined by the time it takes
for the current to decay below the current limit threshold after switching to recirculation
mode.
After 2*tA, the control of the gates releases, restoring the output to the configuration
set by the inputs. If the average output FET temperature exceeds the die temperature
warning threshold (OTw), the blanking time (tB) increases by a factor of 8 (256 μs),
effectively decreasing the current limit PWM frequency. The temperature dependent
blanking time does not change during the blanking interval. Input control does not cause
the output to switch ON while current is greater than ILIM. Input control commanding the
output to switch OFF immediately switches OFF the output and resets the ILIM circuit.
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10 A H-Bridge, SPI programmable brushed DC motor driver
Figure 14. ILIM timing and thermal response
10.4.1.5 Open load detection in standby mode
This diagnostic only operates when the device is in Standby mode (both outputs in
a high-impedance state) and is configured for full H-Bridge mode. It is designed for
applications having less than 50 nF from OUT1 and OUT2 to GND, a load inductance
less than 15 mH, and an equivalent resistance of 600 Ω (typical) as a target for open load
detection.
The diagnostic can activate in one of two ways:
1. The device is transitioning from STBY mode to Normal mode and the CL bit is high.
2. The device is in STBY mode and receives a command changing the CL bit setting
from low to high.
When the open load check is performed, if there is current in an inductive load at the start
of the test, the results may not be valid.
The diagnostic is activated in two stages:
1. The circuit turns on both low-side output FETs, to discharge any residual charge
on the output capacitance. During this stage, the short-circuit detection for OUT1 or
OUT2 is functional and provides normal short-circuit protection and diagnostics.
2. In second stage, the circuit turns off the OUT1 low-side FET and applies an internal
pull-up of 1.0 mA on OUT1 while maintaining the OUT2 low-side driver on. If the
voltage on OUT1 is greater than the open load threshold after the defined filter time,
an open load fault is recorded. See Figure 15 for more details. The OUT1 and OUT2
are restored to the commanded configuration after the test results are latched into the
fault buffer.
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10 A H-Bridge, SPI programmable brushed DC motor driver
Figure 15. Open load detection circuit
10.4.1.6 Open load detection in active mode
Open load detection in Active mode is active when the output is configured for full HBridge mode and an output is being switched. Open load in Active mode is detected
when the OUT1 and OUT2 voltages do not exhibit overshoot greater than the VOLATH
(threshold) over VPWR between the time the low-side is commanded OFF and the lowside FET is turned back on during an output PWM cycle, as shown in Figure 16 and
Figure 17. On the other hand, an open load is not detected if the energy stored in the
inductor is high enough to cause an overshoot greater than the VOLATH (threshold) over
VPWR caused by the fly-back current flowing through the body diode, as shown in antishoot through phase of Figure 16.
Figure 16. Open load detection circuit for active mode
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10 A H-Bridge, SPI programmable brushed DC motor driver
Figure 17. Open load circuit operation
During normal operation, the result of the open load detection window is held until the
end of the next detection window. Open load detected in the active mode is a dynamic
status which is only cleared by detecting the load is not open or leaving Normal mode.
10.4.1.7 Short-circuit detection
The short-circuit detection circuit monitors both high-side and low-side FETs
continuously. When the current is above the short-circuit threshold (SC) for the defined
filter time (tSC), the driver is switched off, and the SPI fault bit is set. The driver can
be restored to normal operation by clearing the fault status by performing clr_flt, as
described in Section 9.6.3.1 "Clearing the fault status".
10.4.2 Electrical characteristics
Table 29. H-Bridge electrical characterization
VPWR = 5.0 V to 28 V, TJ = −40 °C to 150 °C, unless otherwise specified.
Symbol
Parameter
Min.
Typ.
Max.
Unit
OUTPUT
RDS(ON_LSD) LSDx on-state resistance, ILDS = 3.0 A, TJ = 150 °C
[1]
—
—
125
mΩ
RDS(ON_LSD) LSDx on-state resistance, ILDS = 3.0 A, TJ = −40 °C
[1] [2]
—
—
80
mΩ
RDS(ON_HSD) HSDx on-state resistance, ILDS = 3.0 A, TJ = 150 °C
[1]
—
—
125
mΩ
RDS(ON_HSD) HSDx on-state resistance, ILDS = 3.0 A, TJ = −40 °C
[1] [2]
—
—
80
mΩ
—
—
2.0
V
VF
Output MOSFET body diode forward voltage drop with
ILDS = 3.0 A
tDON
tDOFF
OUTx turn-on and turn-off delay times
Digital signal to 10 % or 90 % ILOAD = 1.0 A,
VPWR = 14 V, SR = “000”, resistive load
—
—
3.0
μs
tDDISABLE
OUTx disable delay time
—
—
3.0
μs
tRDISABLE_1
OUTx disable recovery delay time
Open load detection disabled, DIS recovery after 1.0 μs
high or ENBL recovery after 5.0 μs low, SR = “000”,
resistive load < 400 Ω
—
—
8.0
μs
OUTx disable recovery delay time
Open load detection enabled, DIS recovery after 1.0 μs
high or ENBL recovery after 5.0 μs low, SR = “000”,
resistive load < 400 Ω
—
—
128
μs
tRDISABLE_2
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10 A H-Bridge, SPI programmable brushed DC motor driver
Symbol
SR
Parameter
OUTx rising and falling slew rate, from 10 % to 90 % of
VPWR, measured with 1.0 A resistive load at VPWR = 14 V
SPI SR = 000
SPI SR = 001
SPI SR = 010
SPI SR = 011
SPI SR = 100 (default)
SPI SR = 101
SPI SR = 110
SPI SR = 111
Min.
Typ.
Max.
Unit
—
11.2
5.6
2.8
1.4
0.7
0.35
0.15
bypass
16
8.0
4.0
2.0
1.0
0.5
0.25
—
20.8
10.4
5.2
2.6
1.3
0.65
0.35
V/μs
—
—
2.5
2.5
—
—
mA
−0.100
—
0.100
A
CURRENT SENSE
IRATIO
Current recopy ratio
ILOAD < 2.0 A
2.0 A ≤ ILOAD < 10 A
IERROR
Load current error, ILOAD < 2.0 A
IERROR
Load current error, 2.0 A ≤ ILOAD < 10 A
−5.0
—
5.0
%
dI/dt
Load current slew rate
0.5
—
—
A/μs
Current limit threshold current
SPI ILIM = 00
SPI ILIM = 01 (default)
SPI ILIM = 10
SPI ILIM = 11
4.0
6.0
7.3
9.0
5.4
7.0
8.8
10.7
6.8
8.0
10.3
12.5
A
Blanking time
TJ < OTW
TJ ≥ OTW
—
—
32
256
—
—
μs
FAULT DETECTION AND CURRENT LIMIT REGULATION
ILIM
tB
SHORT-CIRCUIT SHUTDOWN
ISC_LS
Low-side short-circuit detection threshold current
ILIM + 3.0
—
ILIM + 8.0 A
ISC_HS
High-side short-circuit detection threshold current
ILIM + 4.0
—
ILIM + 9.0 A
tSC
Short-circuit detection filter time
5.0
—
10
μs
OPEN LOAD DETECTION
VOP
Open load detection voltage threshold
0.6
—
0.8
V
IOL
Out1 pull-up current
0.8
—
1.3
mA
tOP_LSD
Open load detection filter time
93
—
118
μs
VOLATH
Open load active mode threshold VOLA = VOUTx − VPWR
160
—
360
mV
[1]
[2]
In an application, RDS(on) depends on charge pump loading and timing limitations, including slew rate and duty cycle. These factors determine the
enhancement level of the device’s integrated high-side FETs during switching.
Guaranteed by characterization
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10 A H-Bridge, SPI programmable brushed DC motor driver
VDIS,ENBL
ENBL
1.5V
1.5V
DIS
tDDISABLE
VOUT1,2
IO = 100 mA
tRDISABLE
90%
10%
TIME
VIN1,IN2 (V)
Figure 18. Disable delay timing
1.5V
1.5V
VOUT1,2 (V)
tDOFF
tDON
90%
10%
TIME
Figure 19. Output delay timing
tR
VOUT1,2 (V)
tF
VPWR
90%
SR =
80% VPWR
tF
90%
10%
10%
SR =
80% VPWR
tR
TIME
Figure 20. Slew rate
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11 Applications
11.1 Introduction
The 33HB2001 is a programmable and configurable H-Bridge, power integrated circuit
(IC) designed to drive DC motors or bi-directional solenoid controlled actuators, such as
throttle control or exhaust gas recirculation actuators, with continuous average current of
3.0 A and peaks over 10.0 A. Figure 21 shows a typical simplified minimum application
schematic without SPI interface to MCU and reverse battery protection through a diode.
Figure 22 shows a typical simplified application diagram with reverse battery protection
using an external N-channel FET driven by the CCP pin. This is useful for low battery
voltage applications where diode drops could be significant. See Section 8.3.1 "Reverse
battery" for details on reverse battery protection.
The value of C1 is determined based on the maximum current in the load, and the
maximum system voltage. C1 should be able to absorb this energy without exceeding
40 V, otherwise a clamp is required, as explained in Section 11.3 "Output avalanche
protection". If ENBL is high and the part is in H-Bridge mode, the OV protection protects
against this condition.
11.2 Application diagram
Figure 21. Simplified minimum application schematic (Reverse battery protection using a diode and operation
without SPI)
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10 A H-Bridge, SPI programmable brushed DC motor driver
Figure 22. Simplified typical application schematic (Reverse battery protection with an external inverted N-channel
MOSFET and operation with SPI)
11.3 Output avalanche protection
The 33HB2001 has in-built overvoltage protection, preventing output avalanche
breakdown when configured for operation in H-Bridge mode (default operation mode) by
setting the bit MODE (bit number 3) to 1 in the Configuration and Control SPI register. As
long as the part is enabled, the entire energy in the inductor is dissipated in the high-side
recirculation loop, as explained in Section 9.7.2 "VPWR overvoltage detection". However,
when the DOV bit (bit number 12) is set to 1, which disables the overvoltage protection
and only gives an overvoltage warning, or while operating the part in Half-Bridge mode
by setting the bit MODE (bit number 3) to 0 in the Configuration and Control SPI register,
it is important to implement output avalanche protection, as shown in Figure 23. If VPWR
were to become an open circuit, the outputs would likely tri-state simultaneously due to
the disable logic. This could result in an unclamped inductive discharge.
The VPWR input to the 33HB2001 should not exceed 40 V during this transient condition,
to prevent electrical overstress of the output drivers. This can be accomplished with a
zener clamp or MOV, and/or an appropriately valued input capacitor with sufficiently low
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ESR as shown in Figure 23. If ENBL is at logic [1] and the part is in H-Bridge mode, this
problem is mitigated by internal overvoltage protection.
Figure 23. Output avalanche protection
12 Packaging
12.1 Package mechanical dimensions
Package dimensions are provided in package drawings. To find the most current
package outline drawing, go to www.nxp.com and perform a keyword search for the
drawing’s document number.
Table 30. Package outline
Package
Suffix
32-pin SOICW-EP
EK
98ARL10543D
32-pin PQFN
FK
98ARL10579D
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13 Revision history
Revision
Date
Description of changes
1.0
7/2014
• Initial release
2.0
10/2014
•
•
•
•
•
3.0
7/2015
• Changed the priority of fault based on safety requirement
• Added VDDQ decoupling capacitor in application diagram
• Modified the VPWR UV Falling lower limit and removed rising specification as it is
redundant to the falling spec with hysteresis
• Added open load detection feature in active/normal operation mode as per new
silicon
• Changed the I/O max. rating to 36V as per the new silicon
• Added feature of disabling the OV protection feature based on new silicon
• Added VPWR_POR specification
• Corrected the disable delay time specification
• Modified the oscillator frequency, tolerance and charge pump UV specification as per
the design requirement
4.0
11/2015
• Updated the ILIM and Short circuit thresholds
5.0
2/2016
• Added thermal resistance data
• Added the specification for forward voltage drop for the output FET body diode
• Updated document format and style
6.0
5/2016
•
•
•
•
Current limit thresholds modified as per changes in the design
Selectable slew rates modified as per changes in design
Updated Section 10.4.1.5 "Open load detection in standby mode"
Added fault priorities for H-Bridge and Half-Bridge mode
Updated the values for slew rate, current limit thresholds, pull-up and pulldown resistors, detection thresholds of diagnostics based on initial qualification
characterization
• Updated application diagrams
Updated oscillator frequency in Table 23
Updated open load detection filter time in Table 29
Updated charge pump frequency in Table 24
Updated max. value for 33HB2001EK Junction to Package Top - Natural Convection
ΨJT in Table 4
• Updated document format and style
14 Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
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15 Legal information
15.1 Data sheet status
Document status
1
Product status
2
Definition
Data sheet: Product preview
Development
This document contains certain information on a product under development.
NXP reserves the right to change or discontinue this product without notice.
Data sheet: Advance information
Qualification
This document contains information on a new product. Specifications and
information herein are subject to change without notice.
Data sheet: Technical data
Production
NXP Semiconductors reserves the right to change the detail specifications as
may be required to permit improvements in the design of its products.
[1]
[2]
Please consult the most recently issued document before initiating or completing a design.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple
devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences
of use of such information.
15.4 Trademarks
15.3 Disclaimers
Information in this document is provided solely to enable system and
software implementers to use NXP products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any
integrated circuits based on the information in this document. NXP reserves
the right to make changes without further notice to any products herein.
NXP makes no warranty, representation, or guarantee regarding the
suitability of its products for any particular purpose, nor does NXP assume
any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability, including without limitation
MC33HB2001
Data sheet: Advance information
consequential or incidental damages. “Typical” parameters that may be
provided in NXP data sheets and/ or specifications can and do vary in
different applications, and actual performance may vary over time. All
operating parameters, including “typicals,” must be validated for each
customer application by customer's technical experts. NXP does not
convey any license under its patent rights nor the rights of others. NXP sells
products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/salestermsandconditions.
Notice: All referenced brands, product names, service names and
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the NXP logo — is a trademark of NXP B.V.
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the Freescale logo — is a trademark of NXP B.V.
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the SafeAssure logo — is a trademark of NXP B.V.
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All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 3 May 2016
© NXP B.V. 2016. All rights reserved
45 / 48
MC33HB2001
NXP Semiconductors
10 A H-Bridge, SPI programmable brushed DC motor driver
Tables
Tab. 1.
Tab. 2.
Tab. 3.
Tab. 4.
Tab. 5.
Tab. 6.
Tab. 7.
Tab. 8.
Tab. 9.
Tab. 10.
Tab. 11.
Tab. 12.
Tab. 13.
Tab. 14.
Tab. 15.
Orderable parts ................................................. 2
Pin description ...................................................4
Maximum ratings ...............................................8
Thermal ratings ................................................. 9
Nominal operation ........................................... 10
Supply current consumption ............................10
Digital I/Os characteristics ...............................11
Electrical characteristics ..................................15
Electrical characteristics ..................................17
Timing parameters for clearing fault status ......17
SPI register selection ...................................... 18
Device identification (Reserved) ......................18
Status .............................................................. 18
Status bits description ..................................... 18
Fault status mask ............................................19
MC33HB2001
Data sheet: Advance information
Tab. 16.
Tab. 17.
Tab. 18.
Tab. 19.
Tab. 20.
Tab. 21.
Tab. 22.
Tab. 23.
Tab. 24.
Tab. 25.
Tab. 26.
Tab. 27.
Tab. 28.
Tab. 29.
Tab. 30.
Configuration and control ................................ 19
Configuration and control bits description ....... 19
VPWR_UV electrical characterization ............. 21
VPWR_OV electrical characterization ............. 21
OT electrical characterization ..........................22
Truth table ....................................................... 22
Error handling ..................................................24
Frequency electrical characteristics ................ 25
Charge pump electrical characteristics ............26
VDDQ electrical characterizations ...................27
H-Bridge mode fault priority ............................ 28
Half-bridge mode fault priority ......................... 28
Fault priority description .................................. 28
H-Bridge electrical characterization .................32
Package outline ...............................................37
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 3 May 2016
© NXP B.V. 2016. All rights reserved
46 / 48
MC33HB2001
NXP Semiconductors
10 A H-Bridge, SPI programmable brushed DC motor driver
Figures
Fig. 1.
Fig. 2.
Fig. 3.
Fig. 4.
Fig. 5.
Fig. 6.
Fig. 7.
Fig. 8.
Fig. 9.
Fig. 10.
Fig. 11.
Fig. 12.
Fig. 13.
Simplified application diagram ...........................1
Internal block diagram .......................................3
Pin configuration for 32-pin SOICW .................. 4
Pin configuration for 32-pin PQFN .................... 4
Functional block diagram ................................ 12
Operating mode state diagram ........................14
Regulators power-up and power-down
sequences ....................................................... 15
SPI dynamic diagram ...................................... 16
Output operating configurations ...................... 23
H-Bridge operation with ENBL = 1 and DIS
= 0 ................................................................... 24
Half-bridge operation with ENBL = 1 and DIS
= 0 ................................................................... 24
Digital output buffer supply ............................. 26
Simplified current regulated loop for ILIM ........29
MC33HB2001
Data sheet: Advance information
Fig. 14.
Fig. 15.
Fig. 16.
Fig. 17.
Fig. 18.
Fig. 19.
Fig. 20.
Fig. 21.
Fig. 22.
Fig. 23.
ILIM timing and thermal response ................... 30
Open load detection circuit ............................. 31
Open load detection circuit for active mode .....31
Open load circuit operation ............................. 32
Disable delay timing ........................................ 34
Output delay timing ......................................... 34
Slew rate ......................................................... 34
Simplified minimum application schematic
(Reverse battery protection using a diode
and operation without SPI) ..............................35
Simplified typical application schematic
(Reverse battery protection with an external
inverted N-channel MOSFET and operation
with SPI) ..........................................................36
Output avalanche protection ........................... 37
All information provided in this document is subject to legal disclaimers.
Rev. 6.0 — 3 May 2016
© NXP B.V. 2016. All rights reserved
47 / 48
MC33HB2001
NXP Semiconductors
10 A H-Bridge, SPI programmable brushed DC motor driver
Contents
1
2
3
4
5
6
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.9.1
7.3.9.2
7.3.9.3
7.3.9.4
7.3.10
8
8.1
8.2
8.3
8.3.1
8.3.2
9
9.1
9.2
9.3
9.4
9.4.1
9.4.2
9.4.3
9.5
9.5.1
9.5.2
9.6
9.6.1
9.6.2
9.6.3
9.6.3.1
9.6.3.2
9.6.4
9.7
9.7.1
9.7.1.1
9.7.1.2
9.7.2
9.7.2.1
9.7.3
General description ............................................ 1
Simplified application diagram .......................... 1
Features and benefits .........................................1
Applications .........................................................2
Ordering information .......................................... 2
Internal block diagram ........................................3
Pinning information ............................................ 4
Pinning ............................................................... 4
Pin description ................................................... 4
Functional pin description ..................................5
Logic bias input (VDDQ) ....................................5
Supply voltage (VPWR) .....................................5
Outputs (OUT1 and OUT2) ............................... 6
Inputs (IN1 and IN2) ..........................................6
Enable inputs (ENBL) ........................................ 6
Disable inputs (DIS) .......................................... 6
Current recopy (CFB) ........................................ 6
Charge pump capacitor (CCP) .......................... 6
Serial peripheral interface (SPI) ........................ 7
Serial clock (SCLK) ........................................... 7
Serial data output (MISO) ..................................7
Serial data input (MOSI) ....................................7
Chip select (CS_B) ............................................7
Status fault (FS_B) ............................................ 7
General product characteristics ........................ 8
Maximum ratings ............................................... 8
Thermal characteristics ......................................9
Operating conditions ........................................10
Reverse battery ............................................... 10
Digital I/Os characteristics ............................... 11
General IC functional description and
application information .................................... 11
Introduction ...................................................... 11
Features ...........................................................12
Functional block diagram .................................12
Functional description ......................................13
H-Bridge output drivers (OUT1 and OUT2) ......13
Analog control, protection, and diagnostics ..... 13
MCU interface and output control .................... 13
Modes of operation ..........................................13
Description ....................................................... 13
Electrical characteristics .................................. 15
16-bit SPI interface .......................................... 16
Description ....................................................... 16
Electrical characteristics .................................. 17
SPI fault reporting ............................................17
Clearing the fault status ...................................17
SPI framing error detection ..............................18
SPI mapping .................................................... 18
Protection and supervision .............................. 20
VPWR undervoltage detection .........................20
Description ....................................................... 20
Electrical characteristics .................................. 21
VPWR overvoltage detection ...........................21
Electrical characteristics .................................. 21
Die temperature ............................................... 21
9.7.3.1
Description ....................................................... 21
9.7.3.2
Electrical characteristics .................................. 22
9.7.4
Truth table ....................................................... 22
9.8
Error handling .................................................. 24
10
Functional block description ........................... 25
10.1
Oscillator .......................................................... 25
10.1.1
Frequency modulation ..................................... 25
10.2
Charge pump ...................................................26
10.2.1
Description ....................................................... 26
10.3
VDDQ digital output supply voltage ................. 26
10.3.1
Description ....................................................... 26
10.4
H-Bridge and Half-bridge operation ................. 27
10.4.1
Description ....................................................... 27
10.4.1.1 H-Bridge and Half-bridge fault priority ............. 28
10.4.1.2 Current recopy .................................................29
10.4.1.3 Slew rate selection .......................................... 29
10.4.1.4 Active current limit regulation .......................... 29
10.4.1.5 Open load detection in standby mode ............. 30
10.4.1.6 Open load detection in active mode ................ 31
10.4.1.7 Short-circuit detection ...................................... 32
10.4.2
Electrical characteristics .................................. 32
11
Applications .......................................................35
11.1
Introduction ...................................................... 35
11.2
Application diagram ......................................... 35
11.3
Output avalanche protection ............................36
12
Packaging .......................................................... 37
12.1
Package mechanical dimensions .................... 37
13
Revision history ................................................ 44
14
Contact information .......................................... 44
15
Legal information .............................................. 45
© NXP B.V. 2016. All rights reserved
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Released on 3 May 2016