ICL7129 ® UCT NT ROD ACEME at P E r T L P E t en e RE OL OBS END ED upport C om/tsc lS MM sil.c ECO echnica w.inter R O w T N w ur IL or act o cont -INTERS 8 1-88 July 2000 Features • • • • • • • • • • 41/2 Digit LCD, Single-Chip A/D Converter Description The Intersil ICL7129 is a very high performance 41/2-digit, analog-to-digital converter that directly drives a multiplexed liquid crystal display. This single chip CMOS integrated circuit requires only a few passive components and a reference to operate. It is ideal for high resolution hand-held digital multimeter applications. ±19,999 Count A/ D Converter Accurate to ±4 Count 10µV Resolution on 200mV Scale 110dB CMRR Direct LCD Display Drive True Differential Input and Reference Low Power Consumption Decimal Point Drive Outputs Overrange and Underrange Outputs Low Battery Detection and Indication 10:1 Range Change Input The performance of the ICL7129 has not been equaled before in a single chip A/D converter. The successive integration technique used in the ICL7129 results in accuracy better than 0.005% of full scale and resolution down to 10µV/count. Ordering Information PART NUMBER TEMP. RANGE ( oC) ICL7129CPL 0 to 70 PACKAGE The ICL7129, drawing only 1mA from a 9V battery, is well suited for battery powered instruments. Provision has been made for the detection and indication of a “LOW/BATTERY” condition. Autoranging instruments can be made with the ICL7129 which provides overrange and underrange outputs and 10:1 range changing input. The ICL7129 instantly checks for continuity, giving both a visual indication and a logic level output which can enable an external audible transducer. These features and the high performance of the ICL7129 make it an extremely versatile and accurate instrument-on-a-chip. PKG. NO. 40 Ld PDIP E40.6 ICL7129RCPL 0 to 70 40 Ld PDIP E40.6 ICL7129CM44 0 to 70 44 Ld MQFP Q44.10x10 NOTE: “R” indicates device with reversed leads. Pinouts 32 IN LO B3 , C3 , MINUS 10 31 BUFF A3 , G3 , D 3 11 30 CREF- F3 , E3 , DP3 12 29 CREF+ B4 , C4 , BC 5 13 28 COMMON 27 CONTINUITY 26 INT OUT BP3 16 25 INT IN BP2 17 24 V+ BP1 18 23 V- INT IN INT OUT CONTINUITY CREF+ COMMON BUFF CREF- IN LO DP2 3 31 NC DP1 4 30 OSC 2 5 29 OSC 1 6 28 NC LATCH/ HOLD DP3 /UR OSC 3 7 27 DP4 /OR NC 8 26 VDISP NC ANNUNCE DRIVE B1 , C1 , CONT 9 25 BP1 24 10 23 11 12 13 14 15 16 17 18 19 20 21 22 BP2 RANGE 1 V- BP3 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 1 F4 , E4 , DP4 A4 , D4 , G4 B4 , C4 , BC5 A3 , G3 , D3 21 DP3 / UR F3 , E3 , DP3 22 LATCH/HOLD B3 , C3 , MINUS DP4 /OR 20 V+ DGND 34 REF HI F2 , E2 , DP2 9 VDISP 19 44 43 42 41 40 39 38 37 36 35 34 33 2 32 35 REF LO 33 IN HI F4 , E4 , DP4 15 IN HI 36 DGND A2 , G2 , D 2 8 A4 , D4 , G4 14 REF LO 37 RANGE F2 , E2 , DP2 B2 , C2 , LO BAT 7 38 DP2 A2 , G2 , D2 DISPLAY OUTPUT LINES F1 , E1 , DP1 6 39 DP1 B2 , C2 , LO BAT A1 , G1 , D 1 5 40 OSC2 A1 , G1 , D1 OSC3 2 ANNUNCIATOR 3 DRIVE B1 , C 1 , CONT 4 F1 , E1 , DP1 OSC1 1 ICL7129 (MQFP) TOP VIEW REF HI ICL7129 (PDIP) TOP VIEW File Number 3085.2 ICL7129 Functional Block Diagram LOW BATTERY CONTINUITY BACKPLANE DRIVES SEGMENT DRIVES ANNUNCIATOR DRIVE LATCH, DECODE DISPLAY MULTIPLEXER VDISP OSC1 OSC2 UP/DOWN RESULTS COUNTER OSC3 SEQUENCE COUNTER/DECODER CONTROL LOGIC ANALOG SECTION RANGE L/H CONT V+ V- DGND OR DP3 UR DP3 DP2 DP1 Typical Application Schematic LOW BATTERY CONTINUITY V+ 5pF (MICA) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 120kHz ICL7129 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 270K 560pF 10pF (MICA) 1.2kΩ 0.1µF + 20K 1.0µF 0.1µF 150kΩ + 10kΩ 9V - 6.8µF 100kΩ - VIN 2 + ICL8069 V+ ICL7129 Absolute Maximum Ratings Thermal Information Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15V Reference Voltage (REF HI or REF LO) . . . . . . . . . . . . . . . V+ to VInput Voltage (Note 1), IN HI or IN LO . . . . . . . . . . . . . . . . . V+ to VVDISP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .DGND -0.3V to V+ Digital Input Pins 1, 2, 19, 20, 21, 22, 27, 37, 38, 39, 40 . . . . . . . . . . . . . DGND to V+ Thermal Resistance (Typical, Note 2) θJA (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 MQFP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC (MQFP - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Input voltages may exceed the supply voltages provided that input current is limited to 1400mA. Currents above this value may result in valid display readings but will not destroy the device if limited to ±1mA. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V- to V+ = 9V, V REF = 1.00V, TA = 25oC, fCLK = 120kHz, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Zero Input Reading VIN = 0V, 200mV Scale -0000 0000 +0000 Counts Zero Reading Drift VIN = 0V, 0oC To 70oC - ±0.5 - µV/oC Ratiometric Reading VIN = VREF = 1000mV, RANGE = 2V 9996 9999 10000 Counts Range Change Accuracy VIN = 0.10000V on Low, Range ≈ VIN = 1.0000V on High Range 0.9999 1.0000 1.0001 Ratio Rollover Error -VIN = +VIN = 199mV - 1.5 3.0 Counts Linearity Error 200mV Scale - 1.0 - Counts Input Common-Mode Rejection Ratio VCM = 1V,VIN = 0V, 200mV Scale - 110 - dB Input Common-Mode Voltage Range VIN = 0V, 200mV Scale - (V-) +1.5 (V+) -1.0 - V Noise (Peak-To-Peak Value not Exceeded 95% of Time) VIN = 0V 200mV Scale - 14 - µV Input Leakage Current VIN = 0V, Pin 32, 33 - 1 10 pA Scale Factor Tempco VIN = 199mV 0oC To 70oC External VREF = 0ppm/oC - 2 7 ppm/oC COMMON Voltage V+ to Pin 28 2.8 3.2 3.5 V COMMON Sink Current ∆Common = + 0.1V - 0.6 - mA COMMON Source Current ∆Common = -0.1V DGND VoItage V+ to Pin 36, V+ to V- = 9V DGND Sink Current - 10 - µA 4.5 5.3 5.8 V ∆DGND = +0.5V - 1.2 - mA Supply Voltage Range V+ to V- (Note 3) 6 9 12 V Supply Current Excluding COMMON Current V+ to V- = 9V - 1.0 1.5 mA Clock Frequency (Note 3) - 120 360 kHz VDISP Resistance VDISP to V+ - 50 - kΩ Low Battery Flag Activation Voltage V+ to V- 6.3 7.2 7.7 V CONTINUITY Comparator Threshold Voltages VOUT Pin 27 = HI 100 200 - mV VOUT Pin 27 = LO - 200 400 mV Pull-Down Current Pins 37, 38, 39 - 2 10 µA “Weak Output” Current Sink/Source Pins 20, 21 Sink/Source - 3/3 - µA Pin 27 Sink/Source - 3/9 - µA Pin 22 Source Current - 40 - µA Pin 22 Sink Current - 3 - µA 3 ICL7129 Electrical Specifications V- to V+ = 9V, V REF = 1.00V, TA = 25oC, fCLK = 120kHz, Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS NOTE: 3. Device functionality is guaranteed at the stated Min/Max limits. However, accuracy can degrade under these conditions. Pin Descriptions PIN SYMBOL 1 OSC1 Input to first clock inverter. 2 OSC3 Output of second clock inverter. 3 ANNUNCIATOR DRIVE 4 B1 , C1 , CONT Output to display segments. 5 A1 , G1 , D 1 Output to display segments. 6 F1 , E1 , DP1 Output to display segments. 7 DESCRIPTION DESCRIPTION 22 LATCH/HOLD INPUT: When floating, A/D converter operates in the free-run mode. When pulled HI, the last displayed reading is held. When pulled LO, the result counter contents are shown incrementing during the de-integrate phase of cycle. OUTPUT: Negative going edge occurs when the data latches are updated. Can be used for converter status signal. B 2 , C 2 , LO BATT Output to display segments. A2 , G2 , D 2 Output to display segments. 9 F2 , E2 , DP2 Output to display segments. 10 B3 , C3 , MINUS Output to display segments. 11 A3 , G3 , D 3 Output to display segments. 12 F3 , E3 , DP3 Output to display segments. 13 B 4 , C 4 , BC5 Output to display segments. 14 A4 , D4 , G4 Output to display segments. 15 F4 , E4 , DP4 Output to display segments. 16 BP 3 Backplane #3 output to display. 17 BP 2 Backplane #2 output to display. 18 BP 1 Backplane #1 output to display. 19 VDlSP Negative rail for display drivers. 20 DP4 /OR 23 V- Negative power supply terminal. 24 V+ Positive power supply terminal, and positive rail for display drivers. 25 INT IN 26 INT OUT 27 CONTINUITY Input to integrator amplifier. Output of integrator amplifier. INPUT: When LO, continuity flag on the display is off. When HI, continuity flag is on. OUTPUT: HI when voltage between inputs is less than +200mV. LO when voltage between inputs is more than +200mV. INPUT: When HI, turns on most significant decimal point. OUTPUT: Pulled HI when result count exceeds ±19,999. DP3 /UR SYMBOL Backplane squarewave output for driving annunciators. 8 21 PIN INPUT: Second most significant decimal point on when HI. OUTPUT: Pulled HI when result count is less than ±1,000. 4 28 COMMON Sets common-mode voltage of 3.2V below V+ for DE, 10X, etc., Can be used as pre-regulator for external reference. 29 CREF+ Positive side of external reference capacitor. 30 C REF- Negative side of external reference capacitor. 31 BUFFER 32 IN LO Negative input voltage terminal. 33 IN HI Positive input voltage terminal. 34 REF HI Positive reference voltage input terminal. 35 REF LO Negative reference voltage input terminal. 36 DGND Ground reference for digital section. Output of buffer amplifier. ICL7129 PIN SYMBOL DESCRIPTION PIN SYMBOL DESCRIPTION 37 RANGE 3µA pull-down for 200mV scale. Pulled HIGH externally for 2V scale. 39 DP1 Internal 3µA pull-down. When HI, decimal point 1 will be on. 38 DP2 Internal 3µA pull-down. When HI, decimal point 2 will be on. 40 OSC2 Output of first clock inverter. Input of second clock inverter. CREF REF HI DE RINT REF LO CINT BUFFER INT , IN INT OUT DE X10 INT1 DE- DE+ DE+ DE- INT1 , INT2 INT IN LO + Detailed Description 100 BUFFER INTEGRATOR Z1, X10 COMMON COMPARATOR 1 + + IN HI 10 - - + - TO DIGITAL SECTION COMPARATOR 2 REST, INT2 FIGURE 1. ANALOG BLOCK DIAGRAM ZERO-INTEGRATE AND LATCH INT1 INTEGRATE DE1 DE-INTEGRATE REST X10 1000 CLOCKS 2000 CLOCKS X10 DE3 ZERO-INTEGRATE INTEGRATOR RESIDUE VOLTAGE NOTE: Shaded area greatly expanded in time and amplitude. 10,000 CLOCKS DE2 REST 1000 CLOCKS FIGURE 2. INTEGRATOR WAVEFORM FOR NEGATIVE INPUT VOLTAGE SHOWING SUCCESSIVE INTEGRATION PHASES AND RESIDUE VOLTAGE capability of the DGND pin. If more supply current is required, the buffer in Figure 5 can be used to keep the loading on DGND to a minimum. COMMON can source approxi- COMMON, DGND, and “Low Battery” The COMMON and DGND (Digital GrouND) outputs of the ICL7129 are generated from internal zener diodes (Figure 3). COMMON is included primarily to set the common-mode voltage for battery operation or for any system where the input signals float with respect to the power supplies. It also functions as a pre-regulator for an external precision reference voltage source. The voltage between DGND and V+ is the supply voltage for the logic section of the ICL7129 including the display multiplexer and drivers. Both COMMON and DGND are capable of sinking current from external loads, but caution should be taken to ensure that these outputs are not overloaded. Figure 4 shows the connection of external logic circuitry to the ICL7129. This connection will work providing that the supply current requirements of the logic do not exceed the current sink 5 ICL7129 not desired in an application it can easily be overridden by connecting the pin to V+ (HI) or DGND (LO). This connection will not damage the device because the output impedance of these pins is quite high. A simplified schematic of these input/output pins is shown in Figure 6. Since there is approximately 500kΩ in series with the output driver, the pin (when used as an output) can only drive very light loads such as 4000 series, 74CXX type CMOS logic, or other high input impedance devices. The output drive capability of these four pins is limited to 3µA, nominally, and the input switching threshold is typically DGND + 2V. mately 12mA while DGND has no source capability. 24 V+ 3.2V - N + 5V LOGIC SECTION “LOW BATTERY” 28 COMMON 36 P DGND N 23 ≈500kΩ V- DP4/OR PIN 20 DP3/UR PIN 21 LATCH/HOLD PIN 22 CONTINUITY PIN 27 FIGURE 3. BIASING STRUCTURE FOR COMMON AND DGND V+ FIGURE 6. “WEAK OUTPUT” 24 LATCH/HOLD, Overrange, and Underrange Timing EXTERNAL LOGIC 36 The LATCH/HOLD output (pin 22) will be pulled low during the last 100 clock cycles of each full conversion cycle. During this time the final data from the ICL7129 counter is latched and transferred to the display decoder and multiplexer. The conversion cycle and LATCH/HOLD timing are directly related to the clock frequency. A full conversion cycle takes 30,000 clock cycles which is equivalent to 60,000 oscillator cycles. OverRange (OR pin 20) and UnderRange (UR pin 21) outputs are latched on the falling edge of LATCH/HOLD and remain in that state until the end of the next conversion cycle. In addition, digits 1 through 4 are blanked during overrange. All three of these pins are “weak outputs” and can be overridden with external drivers or pullup resistors to enable their input functions as described in the Pin Description table. ICL7129 DGND ILOGIC 23 V- FIGURE 4. DGND SINK CURRENT V+ 24 EXTERNAL LOGIC EXTERNAL LOGIC CURRENT ICL7129 - + 36 ICL7129 Instant Continuity DGND A comparator with a built-in 200mV offset is connected directly between INPUT HI and INPUT LO of the ICL7129 (Figure 7). The CONTINUITY output (pin 27) will be pulled high whenever the voltage between the analog inputs is less than 200mV. This will also turn on the “CONTINUITY” annunciator on the display. The CONTINUITY output may be used to enable an external alarm or buzzer, thereby giv- 23 V- FIGURE 5. BUFFERED DGND The “LOW BATTERY” annunciator of the display is turned on when the voltage between V+ and V- drops below 7.2V typically. The exact point at which this occurs is determined by the 6.3V zener diode and the threshold voltage of the N-Channel transistor connected to the V- rail in Figure 3. As the supply voltage decreases, the N-Channel transistor connected to the V-rail eventually turns off and the “LOW BATTERY” input to the logic section is pulled HIGH, turning on the “LOW BATTERY” annunciator. I/O Ports Four pins of the ICL7129 can be used as either inputs or outputs. The specific pin numbers and functions are described in the Pin Description table. If the output function of the pin is 6 ICL7129 display. This type of display has three backplanes and is driven in a multiplexed format similar to the ICM7231 display driver family. The specific display format is shown in Figure 8. Notice that the polarity sign, decimal points, “LOW BATTERY”, and “CONTINUITY” annunciators are directly driven by the ICL7129. The individual segments and annunciators are addressed in a manner similar to row-column addressing. Each backplane (row) is connected to one-third of the total number of segments. BP1 has all F, A, and B segments of the four least significant digits. BP2 has all of the C, E, and G segments. BP3 has all D segments, decimal points, and annunciators. The segment lines (columns) are connected in groups of three bringing all segments of the display out on just 12 lines. ing the ICL7129 an audible continuity checking capability. - + IN HI BUFFER COMMON IN LO 200mV - V + Annunciator Drive 500kΩ - + A special display driver output is provided on the ICL7129 which is intended to drive various kinds of annunciators on custom multiplexed liquid crystal displays. The ANNUNClATOR DRIVE output (pin 3) is a squarewave signal running at the backplane frequency, approximately 100Hz. This signal swings from VDISP to V+ and is in sync with the three backplane outputs BP1, BP2, and BP3. Figure 9 shows these four outputs on the same time and voltage scales. TO DISPLAY DRIVER (NOT LATCHED) CONTINUITY FIGURE 7. “INSTANT CONTINUITY” COMPARATOR AND OUTPUT STRUCTURE Since the CONTINUITY output is one of the four “weak outputs” of the ICL7129, the “continuity” annunciator on the display can be driven by an external source if desired. The continuity function can be overridden with a pull-down resistor connected between CONTINUITY pin and DGND (pin 36). Any annunciator associated with any of the three backplanes can be turned on simply by connecting it to the ANNUNClATOR DRIVE pin. To turn an annunciator off connect if to its backplane. An example of a display and annunciator drive scheme is shown in Figure 10. Display Configuration The ICL7129 is designed to drive a triplexed liquid crystal LOW BATTERY CONTINUITY f a f a b f g c e e a b f g c e d a b f g c e d b g c e d c BP1 BP2 BACKPLANE CONNECTIONS d BP3 LOW BATTERY CONTINUITY f a f a b f g c e e f g c d a b e a b f g c e d c d F4, E4, DP4 b g e c d B1, C1, CONTINUITY A4, G4, D4 A1, G1, D1 B4, C4, BC5 F1, E1, DP1 F3, E3, DP3 B2, C2, LOW BATTERY A3, G3, D3 A2, G2, D2 B3, C3, MINUS F2, E2, DP2 FIGURE 8. TRIPLEXED LIQUID CRYSTAL DISPLAY LAYOUT FOR ICL7129 7 ICL7129 compensation will depend upon the type of liquid crystal used. Display manufacturers can supply the temperature compensation requirements for their displays. Figure 11 shows two circuits that can be adjusted to give a temperature compensation of ≈ +10mV/ oC between V+ and VDISP . The diode between DGND and VDISP should have a low turn-on voltage to assure that no forward current is injected into the chip if VDISP is more negative than DGND. BP1 BP2 Component Selection BP3 There are only three passive components around the ICL7129 that need special consideration in selection. They are the reference capacitor, integrator resistor, and integrator capacitor. There is no auto-zero capacitor like that found in earlier integrating A/D converter designs. ON SEG. The integrating resistor is selected to be high enough to assure good current Iinearity from the buffer amplifier and integrator and low enough that PC board leakage is not a problem. A value of 150kΩ should be optimum for most applications. The integrator capacitor is selected to give an optimum integrator swing at full-scale. A large integrator swing will reduce the effect of noise sources in the comparator but will affect rollover error if the swing gets too close to the positive rail (≈0.7V). This gives an optimum swing of ≈2.5V at fullscale. For a 150kΩ integrating resistor and 2 conversions per second the value is 0.1µF. For different conversion rates, the value will change in inverse proportion. A second requirement for good linearity is that the capacitor have low dielectric absorption. Polypropylene caps give good performance at a reasonable price. Finally the foil side of the cap should be connected to the integrator output to shield against pickup. FIGURE 9. TYPICAL BACKPLANE AND ANNUNCIATOR DRIVE WAVEFORM ANNUNCIATOR µ m K M LOW BATTERY CONTINUITY BACKPLANE ANNUNCIATOR AMPS VOLTS Ω BACKPLANE FIGURE 10. MULTIMETER EXAMPLE SHOWING USE OF ANNUNCIATOR DRIVE OUTPUT The only requirement for the reference cap is that it be low leakage. In order to reduce the effects of stray capacitance, a 1µF value is recommended. Display Temperature Compensation Clock Oscillator For most applications an adequate display can be obtained by connecting VDlSP (pin 19) to DGND (pin 36). In applications where a wide temperature range is encountered, the voltage drive levels for some triplexed liquid crystal displays may need to vary with temperature in order to maintain good display contrast and viewing angle. The amount of temperature The ICL7129 achieves its digital range changing by integrating the input signal for 1000 clock pulses (2,000 oscillator cycles) on the 2V scale and 10,000 clock pulses on the 200mV scale. To achieve complete rejection of 60Hz on both scales, an oscillator frequency of 120kHz is required, giving two conversions per second. V+ V+ 1N4148 39K 39K 24 200K - 5K ICL7611 2N2222 20K 19 + 36 75K 24 19 VDISP ICL7129 36 DGND VDISP ICL7129 DGND 18K 23 23 V- V- FIGURE 11. TWO METHODS FOR TEMPERATURE COMPENSATING THE LIQUID CRYSTAL DISPLAY 8 ICL7129 It is important to notice that in Figure 13, digital ground of the ICL7129 (DGND pin 36) is not directly connected to power supply ground. DGND is set internally to approximately 5V less than the V+ terminal and is not intended to be used as a power input pin. It may be used as the ground reference for external logic, as shown in Figure 4 and 5. In Figure 4, DGND is used as the negative supply rail for external logic provided that the supply current for the external logic does not cause excessive loading on DGND. The DGND output can be buffered as shown in Figure 5. Here, the logic supply current is shunted away from the ICL7129 keeping the load on DGND low. This treatment of the DGND output is necessary to insure compatibility when the external logic is used to interface directly with the logic inputs and outputs of the ICL7129. In low resolution applications, where the converter uses only 31/2 digits and 100µV resolution, an R-C type oscillator is adequate. In this application a C of 51pF is recommended and the resistor value selected from fOSC = 0.45/RC. However, when the converter is used to its full potential (41/2 digits and 10µV resolution) a crystal oscillator is recommended to prevent the noise from increasing as the input signal is increased due to frequency jitter of the R-C oscillator. Both R-C and crystal oscillator circuits are shown in Figure 12. ICL7129 1 40 2 75kΩ When a battery voltage between 3.8V and 6V is desired for operation, a voltage doubling circuit should be used to bring the voltage on the ICL7129 up to a level within the power supply voltage range. This operating mode is shown in Figure 14. 51pF ICL7129 1 40 2 27kΩ 5pF 10pF 120kHz V- V+ 24 CRYSTAL MODE: PARALLEL RS < 50kΩ CL < 12pF CO < 5pF V+ REF HI REF LO + 3.8V TO 6V FIGURE 12. RC AND CRYSTAL OSCILLATOR CIRCUITS - Powering the ICL7129 36 8 IN HI 2 The ICL7129 may be operated as a battery powered hand-held instrument or integrated into larger systems that have more sophisticated power supplies. Figures 13, 14, and 15 show various powering modes that may be used with the ICL7129. 3 + 4 ICL7660 10µF 5 IN LO V- 24 0.1µF 36 COM DGND IN HI 0.1µF IN LO + VIN 32 - 10µF +5V V+ REF LO ICL7129 33 Again measurements are made with respect to COMMON since the entire system is floating. Voltage doubling is accomplished by using an ICL7660 CMOS voltage converter and two inexpensive electrolytic capacitors. The same principle applies in Figure 15 where the ICL7129 is being used in a system with only a single +5V power supply. Here measurements are made with respect to power supply ground. +5V 0.1µF 28 FIGURE 14. POWERING THE ICL7129 FROM A 3.8V TO 6V BAT- The power connection for systems with +5V and -5V supplies available is shown in Figure 13. Notice that measurements are with respect to ground. COMMON is also tied to INLO to remove any common-mode voltage swing on the integrator amplifier inputs. REF HI 35 23 + The standard supply connection using a 9V battery is shown in the Typical Application Schematic. ICL7129 DGND COM 34 24 34 V+ ICL8089 34 35 ICL8089 0.1µF 35 28 0.1µF 33 32 36 ICL7129 8 33 2 VIN + 3 V- ICL7660 4 10µF 5 23 28 32 V23 + 10µF -5V FIGURE 15. POWERING THE ICL7129 FROM A SINGLE POLARITY POWER SUPPLY FIGURE 13. POWERING THE ICL7129 FROM +5V AND -5V 9 + VIN - ICL7129 A single polarity power supply can be used to power the ICL7129 in applications where battery operation is not appropriate or convenient only if the power supply is isolated from system ground. Measurements must be made with respect to COMMON or some other voltage within its input common-mode range. Integrate Resistor RINT = VINFS/IINT RINT (Typ) = 150kΩ Integrate Capacitor (t )(I ) INT INT C INT = ---------------------------------V INT Voltage References Integrator Output Voltage Swing The COMMON output of the ICL7129 has a temperature coefficient of ±80ppm/ oC typically. This voltage is only suitable as a reference voltage for applications where ambient temperature variations are expected to be minimal. When the ICL7129 is used in most environments, other voltage references should be considered. The diagram in the Typical Application Schematic and Figure 15 show the ICL8069 1.2V band-gap voltage source used as the reference for the ICL7129, and the COMMON output as its pre-regulator. The reference voltage for the ICL7129 is set to 1.000V for both 2V and 200mV full-scale operation. V INT ( tINT ) ( I INT ) = ---------------------------------C INT VINT Maximum Swing: (V- + 0.5V) < VINT < (V+ - 0.7V) Display Count V IN COUNT = 10, 000 × ----------------- ( Range = 1 ) V REF (2V Range) V × 10 IN COUNT = 10, 000 × ----------------------- ( Range = 0 ) V REF (200mV Range) Multiple Integration A/D Converter Equations Minimum VREF: 500mV Oscillator Frequency Common Mode Input Voltage (V- + 1V) < VIN < (V+ - 0.5V) fOSC = 0.45/RC COSC > 50pF; ROSC > 50kΩ fOSC (Typ) = 120kHz or fOSC = 120kHz Crystal (Recommended) Auto Zero Capacitor: CAZ not used Reference Capacitor: 0.1µF < C REF < 1µF VCOM Oscillator Period Biased Between V+ and V-. VCOM ≅ V+ -2.9V Regulation lost when V+ to V- < ≅ 6.4V. If VCOM is externally pulled down to (V+ to V-)/2, the VCOM circuit will turn off. tOSC = 1/ fOSC Integration Clock Period tCLOCK = 2*tOSC Power Supply: Single 9V Integration Period tINT(2V) = 1000*tCLOCK tINT(200mV) = 10,000*tCLOCK V+ - V- = 9V Digital supply is generated internally VGND ≅ V+ - 4.5V (Range = 1) (Range = 0) 60/50Hz Rejection Criterion Display: Triplexed LCD tINT / t60Hz or tINT /t50Hz = Integer Continuity Output On if VINHI to VINLO < 200mV Optimum Integration Current IINT = 13µA Conversion Cycle (In Both Ranges) Full Scale Analog Input Voltage tCYC = tCLOCK x 30,000 VINFS (Typ) = 200mV or 2V ZERO-INTEGRATE AND LATCH INT1 INTEGRATE DE1 DE-INTEGRATE REST X10 1000 CLOCKS 2000 CLOCKS X10 INTEGRATOR RESIDUE VOLTAGE NOTE: Shaded area greatly expanded in time and amplitude. 10,000 CLOCKS DE2 REST 1000 CLOCKS 10 DE3 ZERO-INTEGRATE