ICM7231, ICM7232 TM Numeric/Alphanumeric Triplexed LCD Display Drivers August 1997 Features Description • ICM7231 Drives 8 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Parallel Format • ICM7232 Drives 10 Digits of 7 Segments with Two Independent Annunciators Per Digit Address and Data Input in Serial Format • All Signals Required to Drive Rows and Columns of Triplexed LCD Display are Provided • Display Voltage Independent of Power Supply • On-Chip Oscillator Provides All Display Timing • Total Power Consumption Typically 200µW, Maximum 500µW at 5V • Low-Power Shutdown Mode Retains Data With 5µW Typical Power Consumption at 5V, 1µW at 2V • Direct Interface to High-Speed Microprocessors The ICM7231 and ICM7232 family of integrated circuits are designed to generate the voltage levels and switching waveforms required to drive triplexed liquid-crystal displays. These chips also include input buffer and digit address decoding circuitry allowing six bits of input data to be decoded into 64 independent combinations of the output segments of the selected digit. The family is designed to interface to modern highperformance microprocessors and microcomputers and ease system requirements for ROM space and CPU time needed to service a display. Ordering Information PART NUMBER TEMP. RANGE ( oC) PACKAGE NUMBER OF DIGITS INPUT FORMAT PKG. NO. ICM7231BFIJL -25 to 85 40 Ld CERDIP 8 Digit Parallel F40.6 ICM7231BFIPL -25 to 85 40 Ld PDIP 8 Digit Parallel E40.6 ICM7232BFIPL -25 to 85 40 Ld PDIP 10 Digit Serial E40.6 ICM7232CRIPL -25 to 85 40 Ld PDIP 10 Digit Serial E40.6 NOTE: All versions intended for triplexed LCD displays. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved 19 FN3161.1 ICM7231, ICM7232 Pinouts ICM7232AF, BF (PDIP, CERDIP) TOP VIEW ICM7231BF (PDIP, CERDIP) TOP VIEW CS 1 40 VDD VDISP 2 39 A2 DATA CLOCK INPUT VDISP BP1 3 38 A1 BP2 4 BP3 5 b1, c1, an11 1 40 VDD 2 39 WRITE INPUT BP1 3 37 A0 BP2 4 36 VSS BP3 5 38 DATA INPUT 37 DATA ACCEPTED OUTPUT 36 VSS 6 35 BD3 b1, c1, an11 6 35 f10, e10, an210 a1, g1, d1 7 34 BD2 a1, g1, d1 7 34 a10, g10, d10 f1, e1, an21 8 33 BD1 f1, e1, an21 8 33 b10, c10, an110 b2, c2, an12 9 32 BD0 b2, c2, an12 9 32 f9, e9, an29 a2, g2, d2 10 31 AN2 a2, g2, d2 10 f2, e2, an22 11 30 AN1 f2, e2, an22 11 30 b9, c9, an19 b3, c3, an13 12 29 f8, a8, an28 b3, c3, an13 12 29 f8, a8, an28 a3, g3, d3 13 28 a8, g8, d8 a3, g3, d3 13 31 a9, g9, d9 28 a8, g8, d8 f3, e3, an23 14 27 b8, c8, an18 f3, e3, an23 14 27 b8, c8, an18 b4, c4, an14 15 26 f7, e7, an27 b4, c4, an14 15 26 f7, e7, an27 a4, g4, d4 16 25 a7, g7, d7 f4, e4, an24 17 24 b7, c7, an17 f4, e4, an24 17 24 b7, c7, an17 b5, c5, an15 18 23 f6, e6, an26 b5, c5, an15 18 23 f6, e6, an26 a5, g5, d5 19 22 a6, g6, d6 f5, e5, an25 20 21 b6, c6, an16 a4, g4, d4 16 a5, g5, d5 19 f5, e5, an25 20 ICM7232CR (PDIP) TOP VIEW DATA CLOCK INPUT VDISP 1 40 VDD 2 39 WRITE INPUT BP1 3 BP2 4 BP3 5 38 DATA INPUT 37 DATA ACCEPTED OUTPUT 36 VSS b1, c1, an11 6 35 b6, c6, an16 a1, g1, d1 7 34 a6, g6, d6 f1, e1, an21 8 33 f6, e6, an26 b2, c2, an12 9 32 b7, c7, an17 a2, g2, d2 10 31 a7, g7, d7 f2, e2, an22 11 30 f7, e7, an27 b3, c3, an13 12 29 b8, c8, an18 a3, g3, d3 13 28 a8, g8, d8 f3, e3, an23 14 27 f8, a8, an28 b4, c4, an14 15 26 b9, c9, an19 a4, g4, d4 16 25 a9, g9, d9 f4, e4, an24 17 24 f9, e9, an29 b5, c5, an15 18 23 b10, c10, an110 a5, g5, d5 19 22 a10, g10, d10 f5, e5, an25 20 21 f10, e10, an210 20 25 a7, g7, d7 22 a6, g6, d6 21 b6, c6, an16 ICM7231, ICM7232 Functional Block Diagrams D7 D6 D5 D4 D3 D2 D1 f1, e1, an21 a1, g1, d1 b1, c1, an11 D8 f2, e2, an22 a2, g2, d2 b2, c2, an12 ICM7231 VDD SEGMENT LINE DRIVERS 3 WIDE ON CHIP DISPLAY VOLTAGE LEVEL GENERATOR VH OUTPUT LATCHES 9 WIDE VL VDISP PIN 2 (INPUT) 9 9 9 9 9 9 9 BP1 9 DIGIT ADDRESS DECODER DATA DECODER AN1 BD1 BD0 EN ADDRESS INPUT LATCHES EN BD3 BD2 DATA INPUTS A0 A1 CS A2 ADDRESS INPUTS NOTE: See Figure 13 for display segment connections. 21 BP2 BP3 ONE SHOT DATA INPUT EN LATCHES AN2 COMMON LINE DRIVERS DISPLAY TIMING GENERATOR ICM7231, ICM7232 Functional Block Diagrams (Continued) D8 D7 D6 D5 D4 D3 D2 D1 f1, e1, an21 a1, g1, d1 b1, c1, an11 D9 D10 f2, e2, an22 a2, g2, d2 b2, c2, an12 ICM7232 VDD SEGMENT LINE DRIVERS 3 WIDE ON CHIP VH DISPLAY VOLTAGE LEVEL V GENERATOR OUTPUT LATCHES 9 WIDE L VDISP 9 9 9 9 9 9 9 9 9 9 PIN 2 (INPUT) BP1 DIGIT ADDRESS DECODER 9 DATA DECODER COMMON LINE DRIVERS EN BP3 SERIAL INPUT CONTOL LOGIC CLOCK AN1 AN2 BD0 BD1 BD2 BD3 A0 A1 A2 A3 DATA DATA DATA INPUT CLOCK INPUT SHIFT REGISTER SHIFTS RIGHT TO LEFT ON RISING EDGE OF DATA CLOCK NOTE: See Figures 13 and 14 for display segment connections. 22 BP2 WRITE DATA INPUT ACCEPTED OUTPUT DISPLAY TIMING GENERATOR ICM7231, ICM7232 Absolute Maximum Ratings Thermal Information Supply Voltage (V DD - VSS ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Input Voltage (Note 1) . . . . . . . . . . . . . . . . . . . VSS - 0.3 ≤ VIN ≤ 6.5 Display Voltage (Note 1). . . . . . . . . . . . . . . . . . . .0.3 ≤ VDISP ≤ +0.3 Thermal Resistance (Typical, Note 2) θJA ( oC/W) θJC (oC/W) PDIP Package . . . . . . . . . . . . . . . . . . . 60 N/A CERDIP Package . . . . . . . . . . . . . . . . 50 12 Maximum Junction Temperature Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Plastic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering, 10s) . . . . . . . . . . . . 300oC Operating Conditions Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -25oC to 85oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Due to the SCR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside the power supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than -0.3V below ground, but maybe connected to voltages above V DD but not more than 6.5V above VSS . 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications V+ = 5V +10%, VSS = 0V, TA = -25oC to 85oC, Unless Otherwise Specified PARAMETER TEST CONDITIONS Power Supply Voltage, VDD MIN TYP MAX 4.5 >4 5.5 UNITS V Data Retention Supply Voltage, VDD Guaranteed Retention at 2V 2 1.6 - V Logic Supply Current, IDD Current from V DD to Ground Excluding Display. VDISP = 2V - 30 100 µA Shutdown Total Current, IS VDISP Pin 2 Open - 1 10 µA Display Voltage Range, VDISP VSS ≤ VDISP ≤ VDD 0 - V DD V Display Voltage Setup Current, IDISP VDISP = 2V, Current from VDD to VDISP OnChip - 15 30 µA Display Voltage Setup Resistor Value, RD- One of Three Identical Resistors in String 40 75 - kΩ - 1/ 1 % (VDD VDISP) 90 120 Hz V ISP DC Component of Display Signals (Sample Test Only) Display Frame Rate, fDISP See Figure 5 60 Input Low Level, VIL ICM7231, Pins 30 - 35, 37 - 39, 1 ICM7232, Pins 1, 38, 39 (Note 2) - - 0.8 2.0 - - V - 0.1 1 µA - 5 - pF - - 0.4 V Input High Level, VIH Input Leakage, IILK Input Capacitance, CIN 4 Output Low Level, VOL Pin 37, ICM7232, IOL = 1mA Output High Level, VOH VDD = 4.5V, IOH = -500µA 4.1 - - V Operating Temperature Range, TOP Industrial Range -25 - +85 oC AC Specifications VDD = 5V +10% VSS = 0V, -25oC to 85oC PARAMETER TEST CONDITIONS MIN TYP MAX UNITS Chip Select Pulse Width, tCS (Note 1) 500 350 - ns Address/Data Setup Time, tDS (Note 1) 200 - - ns Address/Data Hold Time, tDH (Note 1) 0 -20 - ns Inter-Chip Select Time, tICS (Note 1) 3 - - µs Data Clock Low Time, tCL (Note 1) 350 - - ns Data Clock High Time, tCL (Note 1) 350 - - ns Data Setup Time, tDS (Note 1) 200 - - ns Data Hold Time, tDH (Note 1) 0 -20 - ns Write Pulse Width, tWP (Note 1) 500 350 - ns Write Pulse to Clock at Initialization, tWLL (Note 1) 1.5 - - µs PARALLEL INPUT (ICM7231) See Figure 1 SERIAL INPUT (ICM7232) See Figures 2, 3 23 ICM7231, ICM7232 VDD = 5V +10% VSS = 0V, -25oC to 85oC AC Specifications TEST CONDITIONS MIN TYP MAX Data Accepted Low Output Delay, tODL PARAMETER (Note 1) - 200 400 UNITS ns Data Accepted High Output Delay, tODH (Note 1) - 1.5 3 µs Write Delay After Last Clock, tCWS (Note 1) 350 - - ns Table of Features TYPE NUMBER OUTPUT CODE ANNUNCIATOR LOCATIONS INPUT OUTPUT ICM7231BF Code B Both Annunciators on BP3 Parallel Entry, 4-bit Data, 2-bit 8 Digits plus Annunciators, 3-bit Address 16 Annunciators ICM7232AF Hexadecimal Both Annunciators on BP3 ICM7232BF Code B Serial Entry, 4-bit Data, 2-bit Annunciators, 4-bit Address ICM7232CR Code B 10 Digits plus 20 Annunciators 1 Annunciator BP1 1 Annunciator BP3 Terminal Definitions TERMINAL PIN NO. DESCRIPTION FUNCTION ICM7231 PARALLEL INPUT NUMERIC DISPLAY AN1 30 Annunciator 1 Control Bit High = ON AN2 31 Annunciator 2 Control Bit Low = OFF See Table 3 BD0 32 Least Significant BD1 33 Input Data (See Table 1) HIGH = Logical One (1) LOW = Logical Zero (0) BD2 34 BD3 35 Most Significant A0 37 Least Significant 4-bit Binary Data Inputs 3-bit Digit Address Inputs A1 38 A2 39 Most Significant CS 1 Data Input Strobe/Chip Select (Note 2) Input Address (See Table 2) Trailing (Positive going) edge latches data, causes data input to be decoded and sent out to addressed digit ICM7232 SERIAL DATA AND ADDRESS INPUT Data Input 38 Data+ Address Shift Register Input HIGH = Logical One (1) LOW = Logical Zero (O) WRITE Input 39 Decode, Output, and Reset Strobe When DATA ACCEPTED Output is LOW, positive going edge of WRITE causes data in shift register to be decoded and sent to addressed digit, then shift register and control logic to be reset. When DATA ACCEPTED Output is HIGH, positive going edge of WRITE triggers reset only. Data Clock Input 1 Data Shift Register and Control Logic Clock Positive going edge advances data in shift register. ICM7232: Eleventh edge resets shift register and control logic. DATA ACCEPTED Output 37 Handshake Output Output LOW when correct number of bits entered into shift register. 2 Negative end of on-chip resistor string Display voltage control. When open (or less than 1V from V DD) chip used to generate intermediate voltage is shutdown; oscillator stops, all display pins to VDD . levels for display. Shutdown Input. ALL DEVICES Display Voltage VDlSP Common Line Driver Outputs 3, 4, 5 Segment Line Driver Outputs 6 - 29 6 - 35 Drive display commons, or rows (On ICM7231) (On ICM7232) Drive display segments, or columns. 24 ICM7231, ICM7232 Terminal Definitions TERMINAL PIN NO. DESCRIPTION VDD 40 Chip Positive Supply VSS 36 Chip Negative Supply FUNCTION NOTES: 1. For Design reference only, not 100% tested. 2. CS has a special “mid-level” sense circuit that establishes a test mode if it is held near 3V for several ms. Inadvertent triggering of this mode can be avoided by pulling it high when inactive, or ensuring frequent activity. Timing Diagrams tCS CS INPUT tICS DATA ADDRESS INPUT ADDRESS AND DATA INPUTS VALID tDS ADDRESS AND DATA INPUTS VALID tDH DO NOT CARE FIGURE 1. ICM7231 INPUT TIMING DIAGRAM 25 ICM7231, ICM7232 Timing Diagrams DATA CLOCK INPUT (PER BIT OF DATA) ELEVENTH CLOCK WITH NO WRITE PULSE RESETS SR + LOGIC tCI 2 AN1 DATA VALID DATA INPUT tODL tCI 1 AN2 DATA VALID 3 8 BD0 DATA VALID A1 DATA VALID 9 10 A2 DATA VALID A3 DATA VALID tDS tDH tODH tODL DATA ACCEPTED OUTPUT tWLL tWP tWP tCWS WRITE INPUT RESETS SHIFT REGISTER AND INPUT CONTROL LOGIC WHEN DATA ACCEPTED HIGH DO NOT CARE DECODES AND STORES DATA, RESETS SHIFT REGISTER AND LOGIC WHEN DATA ACCEPTED IS LOW FIGURE 2. ICM7232 ONE DIGIT INPUT TIMING DIAGRAM, WRITING BOTH ANNUNCIATORS MAXCMOS is a registered trademark of Intersil Corporation. 26 ICM7231, ICM7232 Timing Diagrams AN1 ENTER FIRST AN2 BD0 BD1 BD2 BD3 A0 A1 A2 A3 ENTER LAST ICM7232 WRITE ORDER tCI tCI DATA CLOCK INPUT 1 2 7 8 A2 DATA VALID A3 DATA VALID tDH tDS BD0 DATA VALID DATA INPUT 3 BD1 DATA VALID BD2 DATA VALID tODI DATA ACCEPTED OUTPUT tODH tWLL tWP tWP tCWS WRITE INPUT RESETS SHIFT REGISTER AND INPUT CONTROL LOGIC WHEN DATA ACCEPTED HIGH DECODES AND STORES DATA, RESETS SHIFT REGISTER AND LOGIC WHEN DATA ACCEPTED IS LOW DO NOT CARE FIGURE 3. ICM7232 INPUT TIMING DIAGRAM, LEAVING BOTH ANNUNCIATORS OFF ICM7231 Family Description and one segment line, chosen for this example to be the “a, g, d” segment line. This line intersects with BP1 to form the “a” segment, BP2 to form the “g” segment and BP3 to form the “d” segment. Figure 5 also shows the waveform of the “a, g, d” segment line for four different ON/OFF combinations of the “a”, “g” and “d” segments. Each intersection (segment or annunciator) acts as a capacitance from segment line to common line, shown schematically in Figure 6. Figure 7 shows the voltage across the “g” segment for the same four combinations of ON/OFF segments used in Figure 5. The ICM7231 drives displays with 8 seven-segment digits with two independent annunciators per digit, accepting six data bits and three digit address bits from parallel inputs controlled by a chip select input. The data bits are subdivided into four binary code bits and two annunciator control bits. The ICM7232 drives 10 seven-segment digits with two independent annunciators per digit. To write into the display, six bits of data and four bits of digit address are clocked serially into a shift register, then decoded and written to the display. Input levels are TTL compatible, and the DATA ACCEPTED output on the serial input devices will drive one LSTTL load. The intermediate voltage levels necessary to drive the display properly are generated by an on-chip resistor string, and the output of a totally self-contained on-chip oscillator is used to generate all display timing. All devices in this family have been fabricated using Intersil’ MAXCMOS process and all inputs are protected against static discharge. SEGMENT LINES a f BP1 a f b e an2 Triplexed (1/3 Multiplexed) Liquid Crystal Displays c d BP3 an1 BACKPLANE CONNECTIONS SEGMENT LINE CONNECTIONS Figure 4 shows the connection diagram for a typical 7-segment display with two annunciators such as would be used with an ICM7231 or ICM7232 numeric display driver. Figure 5 shows the voltage waveforms of the common lines FIGURE 4. CONNECTION DIAGRAMS FOR TYPICAL 7-SEGMENT DISPLAYS 27 an1 c d an2 e BP2 g b g ICM7231, ICM7232 φ1 φ2 φ3 φ1´ φ2´ φ3´ SEGMENT LINES VDD BP1 BP1 VH VP VL BP2 f a b e g c an2 d an1 VDISP BP3 VDD BP2 VH VL FIGURE 6. DISPLAY SCHEMATIC COMMON LINE WAVEFORMS VP = (V+) - VDISP VDISP φ1 φ2 φ3 φ1´ φ2´ φ3´ +VP VDD BP3 ON CHIP RESISTOR STRING VH VL VDISP SEGMENT LINE ALL OFF VDD VH VH ~75kΩ VL ON a, d OFF VDD d OFF -VP VP V RMS = -------- = V RMS OFF 3 VL +VP ~75kΩ PIN 2 VDISP VH a SEGMENT ON a, d OFF INPUT 0 VL VDISP a, g ON 0 ~75kΩ VDISP a SEGMENT ALL OFF VDD VDD -VP TYPICAL SEGMENT LINE WAVEFORMS +VP VH a, g ON VL d OFF 0 VDISP -VP VDD ALL ON 11 VP V R MS = ---------- × -------- = VRMS ON 3 3 VH VL VDISP NOTES: 1. φ1, φ2, φ3, - BP High with Respect to Segment. +VP 2. φ1´, φ2´, φ3´, - BP Low with Respect to Segment. 3. BP1 Active during φ1, and φ1´. ALL ON 4. BP2 Active during φ2, and φ2´. 5. BP3 Active during φ3, and φ3´. 0 -VP FIGURE 5. DISPLAY VOLTAGE WAVEFORMS V RMS O N 11 Voltage Contrast Ratio = ------------------------------ = ---------- = 1.92 VRMS OFF 3 The degree of polarization of the liquid crystal material and thus the contrast of any intersection depends on the RMS voltage across the intersection capacitance. Note from Figure 7 that the RMS OFF voltage is always VP/3 and that the RMS ON voltage is always 1.92VPEAK /3. NOTES: 1. φ1, φ2, φ3, - BP High with Respect to Segment. 2. φ1´, φ2´, φ3´, - BP Low with Respect to Segment. For a 1/3 multiplexed LCD, the ratio of RMS ON to OFF voltages is fixed at 1.92, achieving adequate display contrast with this ratio of applied RMS voltage makes some demands on the liquid crystal material used. 3. BP1 Active during φ1, and φ1´. 4. BP2 Active during φ2, and φ2´. 5. BP3 Active during φ3, and φ3´. FIGURE 7. VOLTAGE WAVEFORMS ON SEGMENT g(VG) 28 ICM7231, ICM7232 specifying displays the following must be kept in mind: liquid crystal material, polarizer, and seal materials. Figure 8 shows the curve of contrast versus applied RMS voltage for a liquid crystal material tailored for VPEAK = 3.1V, a typical value for 1/3 multiplexed displays in calculators. Note that the RMS OFF voltage VPEAK /3 ≈ 1V is just below the “threshold” voltage where contrast begins to increase. This places the RMS ON voltage at 2.1V, which provides about 85% contrast when viewed straight on. A more important effect of temperature is the variation of threshold voltage. For typical liquid crystal materials suitable for multiplexing, the peak voltage has a temperature coefficient of -7 to -14mV/oC. This means that as temperature rises, the threshold voltage goes down. Assuming a fixed value for VP, when the threshold voltage drops below VPEAK /3 OFF segments begin to be visible. Figure 9 shows the temperature dependence of peak voltage for the same liquid crystal material of Figure 8. 0+ 06 100 θ=0 θ = -10o TA = 25oC 90 PEAK VOLTAGE 5 80 θ CONTRAST (%) 70 = -30o PEAK VOLTAGE FOR 90% CONTRAST (ON) 4 3 2 60 1 VOFF = 1.1VRMS 50 40 θ = +10o 0 -10 30 20 VON = 2.1V PEAK VOLTAGE FOR 10% CONTRAST (OFF) 0 10 20 30 40 AMBIENT TEMPERATURE (oC) 50 FIGURE 9. TEMPERATURE DEPENDENCE OF LC THRESHOLD 10 0 0 1 2 3 APPLIED VOLTAGE (VRMS) For applications where the display temperature does not vary widely, VPEAK may be set at a fixed voltage chosen to make the RMS OFF voltage, V PEAK /3, just below the threshold voltage at the highest temperature expected. This will prevent OFF segments turning ON at high temperature (this at the cost of reduced contrast for ON segments at low temperatures). 4 FIGURE 8. CONTRAST vs APPLIED RMS VOLTAGE All members of the ICM7231 and ICM7232 family use an internal resistor string of three equal value resistors to generate the voltages used to drive the display. One end of the string is connected on the chip to VDD and the other end (user input) is available at pin 2 (VDISP) on each chip. This allows the display voltage input (VDISP) to be optimized for the particular liquid crystal material used. Remember that VPEAK = VDD - VDISP and should be three times the threshold voltage of the liquid crystal material used. Also it is very important that pin 2 never be driven below VSS . This can cause device latchup and destruction of the chip. For applications where the display temperature may vary to wider extremes, the display voltage VDISP (and thus V PEAK) may require temperature compensation to maintain sufficient contrast without OFF segments becoming visible. Display Voltage and Temperature Compensation These circuits allow control of the display peak voltage by bringing the bottom of the voltage divider resistor string out at pin 2. The simplest means for generating a display voltage suitable to a particular display is to connect a potentiometer from pin 2 to VSS as shown in Figure 10. A potentiometer with a maximum value of 200kΩ should give sufficient range of adjustment to suit most displays. This method for generating display voltage should be used only in applications where the temperature of the chip and display won’t vary more than ±5oC (±9oF), as the resistors on the chip have a positive temperature coefficient, which will tend to increase the display peak voltage with an increase in temperature. The display voltage also depends on the power supply voltage, leading to tighter tolerances for wider temperature ranges. Temperature Effects and Temperature Compensation The performance of the LCD material is affected by temperature in two ways. The response time of the display to changes of applied RMS voltage gets longer as the display temperature drops. At very low temperatures (-20oC) some displays may take several seconds to change a new character after the new information appears at the outputs. However, for most applications above 0oC this will not be a problem with available multiplexed LCD materials, and for low-temperature applications, high-speed liquid crystal materials are available. At high temperature, the effect to consider deals with plastic materials used to make the polarizer. Some polarizers become soft at high temperatures and permanently lose their polarizing ability, thereby seriously degrading display contrast. Some displays also use sealing materials unsuitable for high temperature use. Thus, when 29 ICM7231, ICM7232 For battery operation, where the display voltage is generally the same as the battery voltage (usually 3 - 4.5V), the chip may be operated at the display voltage, with VDlSP connected to VSS . The inputs of the chip are designed such that they may be driven above VDD without damaging the chip. This allows, for example, the chip and display to operate at a regulated 3V, and a microprocessor driving its inputs to operate with a less well controlled 5V supply. (The inputs should not be driven more than 6.5V above GND under any circumstances.) This also allows temperature compensation with the ICL7663S, as shown in Figure 12. This circuit allows independent adjustment of both voltage and temperature compensation. OPEN 200kΩ 2 VDISP 40 10nF ICM7231 ICM7232 +5 36 FIGURE 10. SIMPLE DISPLAY VOLTAGE ADJUSTMENT Figure 11A shows another method of setting up a display voltage using five silicon diodes in series. These diodes, 1N914 or equivalent, will each have a forward drop of approximately 0.65V, with approximately 20µA flowing through them at room temperature. Thus, 5 diodes will give 3.25V, suitable for a 3V display using the material properties shown in Figures 4 and 5. For higher voltage displays, more diodes may be added. This circuit provides reasonable temperature compensation, as each diode has a negative temperature coefficient of -2mV/oC; five in series gives -10mV/oC, not far from optimum for the material described. +5V VIN + VOUT1 LOGIC SYSTEM PROCESSOR, ETC. VDD VOUT2 ICL7663S 1.8MΩ VSET ICM7233 300kΩ VTC GND The disadvantage of the diodes in series is that only integral multiples of the diode voltage can be achieved. The diode voltage multiplier circuit shown in Figure 11B allows finetuning the display voltage by means of the potentiometer; it likewise provides temperature compensation since the temperature coefficient of the transistor base-emitter junction (about -2mV/oC) is also multipled. The transistor should have a beta of at least 100 with a collector current of 10µA. The inexpensive 2N2222 shown in the figure is a suitable device. 2.7MΩ VDISP GND DATA BUS FIGURE 12. FLEXIBLE TEMPERATURE COMPENSATION Description Of Operation VDD Parallel Input Of Data And Address (ICM7231) 1N914 DIODES 2 VDISP 40 The parallel input structure of the ICM7231 device is organized to allow simple, direct interfacing to all microprocessors, (see the Functional Block Diagram). In the ICM7231, address and data bits are written into the input latches on the rising edge of the Chip Select input. +5 36 ICM7231 ICM7232 40kΩ The rising edge of the Chip Select also triggers an on-chip pulse which enables the address decoder and latches the decoded data into the addressed digit/character outputs. The timing requirements for the parallel input device are shown in Figure 1, with the values for setup, hold, and pulse width times shown in the AC Specifications section. Note that there is a minimum time between Chip Select pulses; this is to allow sufficient time for the on-chip enable pulse to decay, and ensures that new data doesn’t appear at the decoder inputs before the decoded data is written to the outputs. 10nF FIGURE 11A. STRING OF DIODES VDD 2 VDISP 200kΩ POTENTIOMETER 2N2222 40 Serial Input Of Data And Address (ICM7232) +5 The ICM3232 trades six pins used as data inputs on the ICM7231 for six more segment lines, allowing two more 9-segment digits. This is done at the cost of ease in interfacing, and requires that data and address information be entered serially. Refer to Functional Block Diagram and timing diagrams, Figures 2 and 3. The interface consists of four pins: DATA Input, DATA CLOCK Input, WRITE Input and DATA ACCEPTED Output. The data present at the DATA Input is clocked into a shift register on the rising edge of the 36 ICM7231 ICM7232 40kΩ 10nF FIGURE 11B. TRANSISTOR-MULTIPLIER FIGURE 11. DIODE-BASED TEMPERATURE COMPENSATION 30 ICM7231, ICM7232 (See Figure 14). The “C” devices provide only a “Code B” output for the 7 segments. DATA CLOCK Input signal, and when the correct number of bits has been shifted into the shift register (8 in the ICM7232), the DATA ACCEPTED Output goes low. Following this, a low-going pulse at the WRITE input will trigger the chip to decode the data and store it in the output latches of the addressed digit/character. After the data is latched at the outputs, the shift register and the control logic are reset, returning the DATA ACCEPTED Output high. After this occurs, a pulse at the WRITE input will not change the outputs, but will reset the control logic and shift register, assuring that each data bit will be entered into the correct position in the shift register depending on subsequent DATA CLOCK inputs. TABLE 1. BlNARY DATA DECODING ICM7231 AND ICM7232 CODE INPUT The shift register and control logic will also be reset if too many DATA CLOCK INPUT edges are received; this prevents incorrect data from being decoded. In the ICM7232, the eleventh clock resets the shift register and control logic. The recommended procedure for entering data is shown in the serial input timing diagram, Figure 2. First, when DATA ACCEPTED is high, send a WRITE pulse. This resets the shift register and control logic and initializes the chip for the data input sequence. Next clock in the appropriate number of correct data and address bits. The DATA ACCEPTED Output may be monitored if desired, to determine when the chip is ready to output the decoded data. When the correct number of bits has been entered, and the DATA ACCEPTED Output is low, a pulse at WRITE will cause the data to be decoded and stored in the latches of the addressed digit/character. The shift register and control logic are reset, causing DATA ACCEPTED to return high, and leaving the chip ready to accept data for the next digit/character. Note that for the ICM7232 the eleventh clock resets the shift register and control logic, but the DATA ACCEPTED Output goes low after the eighth clock. This allows the user to abbreviate the data to eight bits, which will write the correct character to the 7-segment display, but will leave the annunciators off, as shown in Figure 3. If only AN2 is to be turned on, nine bits are clocked in; if AN1 is to be turned on, all ten bits are used. The DATA ACCEPTED Output will drive one low-power Schottky TTL input, and has equal current drive capability pulling high or low. Note that in the serial Input devices, it is possible to address digits/characters which don’t exist. As shown in Table 2 when an incorrect address is applied together with a WRITE pulse, none of the outputs will be changed. Display Fonts and Output Codes The standard versions of the ICM7231 and ICM7232 chips are programmed to drive a 7-segment display plus two annunciators per digit. See Table 3 for annunciator input controls. The “A” and “B” suffix chips place both annunciators on BP3. The display connections for one digit of this display are shown in Figure 13. The “A” devices decode the input data into a hexadecimal 7-segment output, while the “B” devices supply Code B outputs (see Table 1). The “C” devices place the left hand annunciator on BP1 and the right hand annunciator (usually a decimal point) on BP3. 31 DISPLAY OUTPUT BD3 BD2 BD1 BD0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 HEX CODE B ICM7231, ICM7232 TABLE 1. BlNARY DATA DECODING ICM7231 AND ICM7232 CODE INPUT TABLE 3. ANNUNClATOR DECODING DISPLAY OUTPUT BD3 BD2 BD1 BD0 1 1 1 1 HEX CODE INPUT CODE B BLANK DISPLAY OUTPUT 1 0 1 1 TABLE 2. ADDRESS DECODING (ICM7231 AND ICM7232) DISPLAY OUTPUT CODE INPUT ICM7232 ONLY A3 A2 A1 A0 DIGIT SELECTED 0 0 0 0 D1 0 0 0 1 D2 0 0 1 0 D3 0 0 1 1 D4 0 1 0 0 D5 0 1 0 1 D6 0 1 1 0 D7 0 1 1 1 D8 1 0 0 0 D9 1 0 0 1 D10 1 0 1 0 NONE 1 0 1 1 NONE 1 1 0 0 NONE 1 1 0 1 NONE 1 1 1 0 NONE 1 1 1 1 NONE TABLE 3. ANNUNClATOR DECODING CODE INPUT DISPLAY OUTPUT AN2 AN1 0 0 0 1 ICM7231A AND ICM7231B ICM7232A AND ICM7232B BOTH ANNUNCIATORS ON BP3 ICM7231C ICM7232C an2 ANNUNCIATOR BP1 an1 ANNUNClATOR BP3 32 ICM7231, ICM7232 SEGMENT LINES SEGMENT LINE CONNECTIONS a f BP1 b g e BP2 an2 c an1 d BP3 BACKPLANE CONNECTIONS FIGURE 13. ICM7231 AND ICM7232 DISPLAY FONTS (“A” AND “B” SUFFIX VERSIONS ) SEGMENT LINES (NOTE 1) SEGMENT LINE CONNECTIONS SEGMENT LINES BP1 (NOTE 1) BP2 an2 a f b g e c d an1 BP3 NOTE: BACKPLANE CONNECTIONS 1. Annunciators can be: STOP , GO , , -arrows that point to information printed around the display opening etc., whatever the designer display opening etc., whatever the designer chooses to incorporate in the liquid crystal display. FIGURE 14. ICM7231 DISPLAY FONTS (“C” SUFFIX VERSIONS) Compatible Displays Compatible displays are manufactured by: G.E. Displays Inc., Beechwood, Ohio (216) 831-8100 (#356E3R99HJ) Epson America Inc., Torrance CA (Model Numbers LDB726/7/8). Seiko Instruments USA Inc., Torrance CA (Custom Displays) Crystaloid, Hudson, OH 33 Typical Applications PERIOD INTERVAL UNIT TEST FREQ. RATIO FREQUENCY OVER RANGE 27 ICM7231CF BD0 - 3 AN2 INPUT A BCD ICM7226A CS AN1 A0 A1 A2 DP FUNCTION INPUT B +5V D1 - D8 RANGE Q0 Q1 Q2 E1 V+ 10K 1µF CD4532 GS D0 - D7 NOTE: The annunciators show function and the decimal points indicate the range of the current operation. the system can be efficiently battery operated. FIGURE 15. 10MHz FREQUENCY/PERIOD POINTER WITH LCD DISPLAY 34 Typical Applications D8 (Continued) D7 D6 D5 D4 D3 D2 D1 COM 1 COM 2 COM 3 X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z ICM7231AF AND ICM7231BF TOP VIEW TO INPUT FIGURE 16. “FORWARD” PIN ORIENTATION AND DISPLAY CONNECTIONS 35 Typical Applications (Continued) D10 D9 D8 SELECT NO FORWARD D7 D6 D5 D4 D3 D2 D1 STOP WAIT GO COM 1 COM 2 COM 3 X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z X Y Z ICM7232CR TOP VIEW PCB TRACES UNDER PACKAGE TO INPUT FIGURE 17. “REVERSE” PIN ORIENTATION AND DISPLAY CONNECTIONS 36 ICM7231, ICM7232 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. 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