Plastic Packages for Integrated Circuits Package Outline Drawing W5x7.28 28 BALL WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) Rev 0, 7/12 1.600 X 2.185±0.02 Y 0.800 G G F F E E 0.400 2.92±0.02 (2X) 0.10 5 4 3 2 28X 0.260±0.03 D D C C B B A A 1.600 2.400 1 1 2 5 4 0.400 3 PIN 1 (A1 CORNER) TOP VIEW BOTTOM VIEW PACKAGE OUTLINE 0.225 0.400 0.275 0.305±0.025 0.505±0.40 0.200±0.03 0.400 TYPICAL RECOMMENDED LAND PATTERN SEATING PLANE 0.05 Z Z 0.260±0.03 0.050 0.015 ZXY Z SIDE VIEW NOTES: 1. Dimensions and tolerance per ASME Y 14.5M - 1994. 2. Dimension is measured at the maximum bump diameter parallel to primary datum Z . 3. Primary datum Z and seating plane are defined by the spherical crowns of the bump. 4. Bump position designation per JESD 95-1, SPP-010. 1