IDT 5P49EE601NLGI8

PRELIMINARY DATASHEET
VERSACLOCK® LOW POWER CLOCK GENERATOR
IDT5P49EE601
Description
Features
The IDT5P49EE601 is a programmable clock generator
intended for low power, battery operated consumer
applications. There are four internal PLLs, each individually
programmable, allowing for up to six differrent output
frequencies. The frequencies are generated from a single
reference clock. The reference clock can come from either
a TCXO or fundamental mode crystal. An additional
32.768kHz crystal oscillator is available to provide a real
time clock or non-critical performance MHz processor
clock.
• Four internal PLLs
• Internal non-volatile EEPROM
• Internal I2C EEPROM master interface
• FAST (400kHz) mode I2C serial interfaces
• Input Frequencies
– TCXO: 10 MHz to 40 MHz
– Crystal: 8 MHz to 30 MHz
– RTC Crystal: 32.768 kHz
• Output Frequency Ranges: kHz to 120 MHz
• Each PLL has an 8-bit reference divider and a 11-bit
The IDT5P49EE601 can be programmed through the use
of the I2C interfaces. The programming interface enables
the device to be programmed when it is in normal operation
or what is commonly known as in system programmable.
An internal EEPROM allows the user to save and restore
the configuration of the device without having to reprogram
it on power-up.
feedback-divider
• 8-bit output-divider blocks
• One of the PLLs support Spread Spectrum generation
capable of configuration to pixel rate, with adjustable
modulation rate and amplitude to support video clock
with no visible artifacts
Each of the four PLLs has an 8-bit reference divider and a
11-bit feedback divider. This allows the user to generate
four unique non-integer-related frequencies. The PLL loop
bandwidth is programmable to allow the user to tailor the
PLL response to the application. For instance, the user can
tune the PLL parameters to minimize jitter generation or to
maximize jitter attenuation.
• I/O Standards:
– Outputs - 1.8V/2.5V/3.3 V LVTTL/ LVCMOS
– Outputs - 1 pair selectable 3.3V LVDS
•
•
•
•
•
•
Spread spectrum generation is supported on one of the
PLLs. The device is specifically designed to work with
display applications to ensure that the spread profile
remains consistent for each HSYNC in order to reduce
ROW noise.
There are total six 8-bit output dividers. One output bank
can be configured to support LVTTL or LVDS. All other
outputs are always set to LVTTL. The outputs are
connected to the PLLs via the switch matrix. The switch
matrix allows the user to route the PLL outputs to any
output bank. This feature can be used to simplify and
optimize the board layout. In addition, each output's slew
rate and enable/disable function can be programmed.
3 independent adjustable VDDO groups.
Programmable Slew Rate Control
Programmable Loop Bandwidth Settings
Programmable output inversion to reduce bimodal jitter
Individual output enable/disable
Power-down/Sleep mode
– 10A max in power down mode
– 32kHz clock output active sleep mode
– 100A max in sleep mode
• 1.8V VDD Core Voltage
• Available in 24pin 4x4mm QFN packages
• -40 to +85 C Industrial Temp operation
Target Applications
•
•
•
•
•
•
Smart Mobile Handset
Personal Navigation Device (PND)
Camcorder
DSC
Portable Game Console
Personal Media Player
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Functional Block Diagram
VDD
VDDO1
VDDO2
VDDO3
X IN /R E F
R E F S E LA
XOUT
P LL A
R E FS E LB
P L LB (S S )
SDA
SCL
C on trol
L ogic
S
R
C
0
/D IV 0
O UT0
S
R
`
C
1
/D IV 1
O UT1
/D IV 2
O UT2
/D IV 3
O UT3
R E F S E LC
S
R
C
2
P L LC
S E L [1:0 ]
S
R
C
3
R E FS E LD
P L LD
S
R
C
4
32 kX IN
O U T 4A
/D IV 4
O U T 4B
32 kX O U T
GND
Note 1: OUT4A & OUT4B pair can be configured to be LVDS or two single-ended LVTTL outputs.
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
OUT3
OUT2
OUT4A
SDA
VDD
X1
GND
X2
Pin Assignment
19
1
SCLK
SEL0
VDDO3
OUT0
VDDO1
X132k
VDD
13
GND
SEL1
OUT1
VDDO2
VDD
GND
7
VDDX
X232k
OUT4B
24- pin QFN
Pin Descriptions
Pin Name
Pin #
I/O
Pin Type
Pin Description
OUT3
1
O
Adjustable
Configurable clock output 3. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
OUT2
2
O
Adjustable
Configurable clock output 2. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
SEL0
3
I
LVTTL
Configuration select pin. Weak internal pull down resistor.
VDDO1
4
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT4. VDDO1
must be greater than or equal to both VDDO2 and VDDO3.
X132k
5
I
LVTTL
32kHz CRYSTAL_IN -- Reference crystal input
X232k
6
O
LVTTL
32kHz CRYSTAL_OUT -- Reference crystal feedback.
VDDx
7
Power
Crystal oscillator power supply. Connect to 1.8V. Use filtered
analog power supply if available.
GND
8
Power
Connect to Ground.
VDD
9
Power
Device power supply. Connect to 1.8V.
VDDO2
10
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT4. VDDO2
must be equal or less than VDDO1.
OUT1
11
O
Adjustable
Configurable clock output 1. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
SEL1
12
I
LVTTL
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
Configuration select pin. Weak internal pull down resistor.
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
GND
13
Power
Connect to Ground.
VDD
14
Power
Device power supply. Connect to 1.8V.
OUT0
15
VDDO3
16
SCLK
17
OUT4B
O
Adjustable
Configurable clock output 0. Single-ended output voltage levels
are register controlled by either VDDO1, VDDO2 or VDDO3.
Power
Device power supply. Connect to 1.8 to 3.3V. Using register
settings, select output voltage levels for OUT0-OUT4. VDDO3
must be equal or less than VDDO1.
I
LVTTL
I2C clock.
18
O
Adjustable
Configurable clock output 4B. Single-ended or differential when
combined with OUT4A. Output voltage levels are controlled by
VDDO1.
OUT4A
19
O
Adjustable
Configurable clock output 4A. Single-ended or differential when
combined with OUT4B. Output voltage levels are controlled by
VDDO1.
SDA
20
I/O
Open Drain Bidirectional I2C data.
VDD
21
Power
Device power supply. Connect to 1.8V.
GND
22
Power
Connect to Ground.
XIN/ REF
23
I
LVTTL
MHz CRYSTAL_IN -- Reference crystal input or external
reference clock input.
XOUT
24
O
LVTTL
MHz CRYSTAL_OUT -- Reference crystal feedback.
Note 1: Outputs are user programmable to drive single-ended 1.8V/2.5V/3.3V LVTTL. Differential LVDS interface
levels can be generated for OUT4A/OUT4B when connected to VDDO1=3.3V and registers configured
appropriately. Alway completely power up VDD and VDDx prior to applying VDDO power.
Note 2: Default configuration CLK1=Buffered MHz Reference output and CLK2=Buffered 32.768kHz output. All
other outputs are off.
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PLL Features and Descriptions
8-bit
VCO
D
1-bit
A
11-bit
M
PLL Block Diagram
Ref-Divider
(D) Values
Feedback
Pre-Divider
(XDIV)
Values
Feedback
(M) Values
Programmable
Spread Spectrum
Loop Bandwidth Generation Capability
PLLA
1 - 255
1 or 41
6 - 2047
Yes
No
PLLB
1 - 255
4
6 - 2047
Yes
Yes
PLLC
1 - 255
1 or 8 bit
divide2
6 - 2047
Yes
No
PLLD
1 - 255
1 or 41
6 - 2047
Yes
No
1.XDIVA or XDIVD=0, A=1. XDIVA or XDIVD=1, A=4.
2.XDIVC =0, A=1. XDIVC=1 turns on 8 bit predivide multiplier, A=FBC2[7:0]. Total feedback divide equals
FBC[10:0] *FBC2[7:0].
Crystal Input (XIN/REF)
Reference Pre-Divider, Reference Divider,
Feedback-Divider and Post-Divider
The crystal oscillators should be fundamental mode quartz
crystals; overtone crystals are not suitable. Crystal
frequency should be specified for parallel resonance with
50 maximum equivalent series resonance.
Each PLL incorporates an 8-bit reference-scaler and a
11-bit feedback divider which allows the user to generate
four unique non-integer-related frequencies. PLLA and
PLLD each have a feedback pre-divider that provides
additional multiplication for kHz reference clock
applications. Each output divider supports 8-bit post-divider.
The following equation governs how the output frequency is
calculated.
Crystal Load Capacitors
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to ground.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. Because load capacitance can only be
increased in this trimming process, it is important to keep
stray capacitance to a minimum by using very short PCB
traces (and no vias) between the crystal and device. Crystal
capacitors must be connected from each of the pins X1 and
X2 to ground.
A*M
)
D
ODIV
FOUT = FIN * (
Where FIN is the reference frequency, A is the feedback
pre-divider value, M is the feedback-divider value, D is the
reference divider value, ODIV is the total post-divider value,
and FOUT is the resulting output frequency. Programming
any of the dividers may cause glitches on the outputs.
The crystal cpacitors are internal to the device and have an
effective value of 8pF.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
(Eq. 2)
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
SPREAD SPECTRUM GENERATION
(PLLB)
Modulation frequency:
PLLB has spread spectrum generation capability, which
users have the option of turning on and off. Spread
spectrum profile, frequency, and spread are fully
programmable (within limits). The programmable spread
spectrum generation parameters are NC[10:0], MOD[12:0],
and NSS[10:0] bits. To enable spread spectrum, set
SSENB_B=0.
Video Example
FMOD = FMID / NC (Eq. 11)
FREF = 27 MHz, FOUT = 27 MHz, 640 pixels per line, center
spread of ±1%. Using FVCO=432MHz, find the necessary
spread spectrum register settings.
FMID = FVCO/8
NC = 640 (integer number of spread periods/screen)
The spread spectrum circuitry was specifically developed to
accommodate video display applications. The spread
modulation frequency can be defined to exactly equal the
horizontal line frequency (HSYNC)
MOD = (25MHz * 640)/(2 * 54MHz) = 160
NSS = (640/2)+(640/8)*(27.27MHz-26.73MHz)/27MHz =
321.
NC[10:0]
These bits are used to determine the number of pulses per
spread spectrum cycle. For video applications, NC is the
number of pixels on the horizontal display row (or integer
multiple of displayed pixels in a row). By matching the
spread period to the screen, no tearing or “shimmer” will be
apparent.
FMOD = 27MHz/640 = 11.8kHz.
Non-Video Example
FREF = 25MHz, FOUT = 27 MHz, 31.25kHz modulation rate,
center spread of ±1%. Find the necessary spread spectrum
register settings.
NC must be an even number to insure that the upward
spread transition has the same number of steps as the
downward spread transition.
FMID = FVCO/ 8
FMOD = 31.25kHz = 50.625MHz/NC.
For non-video applications, this can also be seen as the
number of clock cycles for a complete spread spectrum
period.
NC = 1620
MOD = (25MHz * 1620)/(2 * 50.625MHz) = 400
MOD[12:0]
NSS = (1620/2)+(1620/8)*(27.27MHz-26.73MHz)/27MHz =
814.
These bits relate the VCO frequency to the target average
spread output frequency (FMID).
FMID = (FVCO) / 8
FMAX = FMID + (SS% * FMID)
FMIN = FMID - (SS% * FMID)
MOD = (FREF* NC) / (2 * FMID)
NSS[10:0]
These bits control the amplitude of the spread modulation.
NSS = (NC / 2) + (NC / 8) * (FMAX - FMIN) / FMID
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EEPROM CLOCK GENERATOR
VSYNC, HSYNC, DOT_CLK – Modulation Rate Relationship
VSYNC
HSYNC
Integer multiple of HSYNC periods
DOT_CLK
Modulation
Rate
X/2
X/2
X
X
X = Number of cycles of DOT_CLK per HSYNC period.
X/2 = Number of cycles of DOT_CLK that the modulation edge rises/falls.
Zero capacitor (Cz) = 280pF
LOOP FILTER
Pole capacitor (Cp) = 30pF
The loop filter for each PLL can be programmed to optimize
the jitter performance. The low-pass frequency response of
the PLL is the mechanism that dictates the jitter transfer
characteristics. The loop bandwidth can be extracted from
the jitter transfer. A narrow loop bandwidth is good for jitter
attenuation while a wide loop bandwidth is best for low jitter
generation. The specific loop filter components that can be
programmed are the resistor via the RZ[4:0] bits, zero
capacitor via the CZ[2:0] bits, pole capacitor via the CP[1:0]
bits, and the charge pump current via the IP#[2:0] bits.
Charge pump (Ip) = IP#[2:0] uA
VCO gain (KVCO) = 300MHz/V * 2
The following equations govern how the loop filter is set:
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Example
Fc = 150KHz is the desired loop bandwidth. The total A*M
value is 160. The (damping factor) target should be 0.7,
meaning the loop is critically damped. Given Fc and A*M, an
optimal loop filter setting needs to be solved for that will
meet both the PLL loop bandwidth and maintain loop
stability.
Choose a mid-range charge pump from register table
Icp= 11.9uA.
K* KVCO = 300MHz/V * 40uA = 12000A/Vs
c = 2* Fc = 9.42x105 s-1
PLL Loop Bandwidth:
Charge pump gain (K) = Ip / 2
p = (Cz + Cp)/(Rz * Cz * Cp) = z (1 + Cz / Cp)
VCO gain (KVCO) = 950MHz/V * 2
Solving for Rz, the best possible value Rz=30kOhms
(RZ[1:0]=10) gives
M = Total multiplier value (See the PRE-SCALERS,
FEEDBACK-DIVIDERS, POST-DIVIDERS section for more
detail)
= 1.2
Solving back for the PLL loop bandwidth, Fc=149kHz.
c = (Rz * K* KVCO * Cz)/(M * (Cz + Cp))
The phase margin must be checked for loop stability.
Fc = c / 2
m = (360 / 2) * [tan-1 (9.42x105 s-1 / 1.19x105s-1)
- tan-1(9.42x105 s-1/ 1.23x106 s-1)] = 45°
Note, the phase/frequency detector frequency (FPFD) is
typically seven times the PLL closed-loop bandwidth (Fc)
but too high of a ratio will reduce your phase margin thus
compromising loop stability.
The phase margin would be acceptable with a fairly stable
loop.
To determine if the loop is stable, the phase margin (m)
would need to be calculated as follows.
Phase Margin:
z = 1 / (Rz * Cz)
p = (Cz + Cp)/(Rz * Cz * Cp)
m = (360 / 2) * [tan-1(c/ z) - tan-1(c/ p)]
To ensure stability in the loop, the phase margin is
recommended to be > 60° but too high will result in the lock
time being excessively long. Certain loop filter parameters
would need to be compromised to not only meet a required
loop bandwidth but to also maintain loop stability.
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EEPROM CLOCK GENERATOR
SEL[1:0] Function
Power Down/Sleep Mode is selected by the No_PD bit.
No_PD=0 enables Power Down mode with no outputs.
No_PD=1 enables sleep mode with 32kHz output on OUT2.
The IDT5P49EE601 can support up to three unique
configurations. Users may pre-programmed all these
configurations, and select the configurations using SEL[1:0]
pins. Alternatively, users may use I2C interface to configure
these registers on- the-fly.
SEL1
SEL0
Configuration Selections
0
0
Power Down/Sleep Mode
0
1
Select CONFIG0
1
0
Select CONFIG1
1
1
Select CONFIG2
Configuration OUTx IO Standard
2.5V or 3.3V LVCMOS. Output pair OUT4A/OUT4B can be
configured to support an LVDS output. For LVDS support,
VDDO1 must be set to 3.3V. VDDO1 must have the highest
voltage of any pin on the device. VDDO2 and VDDO3 may
have any value between 1.8V and VDDO1.
Users can configure the individual output IO standard from
a single 3.3V power supply. Each output can support 1.8V/
Programming the Device
I2C may be used to program the IDT5P49EE601.
The frame formats are shown in the following illustration.
– Device (slave) address = 7'b1101010
I2C Programming
The IDT5P49EE601 is programmed through an I2C-Bus
serial interface, and is an I2C slave device. The read and
write transfer formats are supported. The first byte of data
after a write frame to the correct slave address is interpreted
as the register address; this address auto-increments after
each byte written or read.
Framing
First Byte Transmitted on I2C Bus
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
External I2C Interface Condition
EEPROM Interface
after the STOP condition is issued by the Master, during
which time the IDT5P49EE601 will not generate
Acknowledge bits. The IDT5P49EE601 will acknowledge
the instructions after it has completed execution of them.
During that time, the I2C bus should be interpreted as busy
by all other users of the bus.
The IDT5P49EE601 can store its configuration in an internal
EEPROM. The contents of the device's internal
programming registers can be saved to the EEPROM by
issuing a save instruction (ProgSave) and can be loaded
back to the internal programming registers by issuing a
restore instruction (ProgRestore).
On power-up of the IDT5P49EE601, an automatic restore is
performed to load the EEPROM contents into the internal
programming registers. The IDT5P49EE601 will be ready to
accept a programming instruction once it acknowledges its
7-bit I2C address.
2
To initiate a save or restore using I C, only two bytes are
transferred. The Device Address is issued with the
read/write bit set to “0”, followed by the appropriate
command code. The save or restore instruction executes
Progwrite
Progwrite Command Frame
Writes can continue as long as a Stop condition is not sent and each byte will increment the register address.
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VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Progread
Note: If the expected read command is not from the next higher register to the previous read or write command, then set a
known “read” register address prior to a read operation by issuing the following command:
Prior to Progread Command Set Register Address
The user can ignore the STOP condition above and use a repeated START condition instead, straight after the slave
acknowledgement bit (i.e., followed by the Progread command):
Progread Command Frame
Progsave
Note:
PROGWRITE is for writing to the IDT5P49EE601 registers.
PROGREAD is for reading the IDT5P49EE601 registers.
PROGSAVE is for saving all the contents of the
IDT5P49EE601 registers to the EEPROM.
PROGRESTORE is for loading the entire EEPROM
contents to the IDT5P49EE601 registers.
Progrestore
During PROGRESTORE, outputs will be turned off to
ensure that no improper voltage levels are experienced
before initialization.
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EEPROM CLOCK GENERATOR
I2C Bus DC Characteristics
Symbol
Parameter
VIH
Input HIGH Level
VIL
Input LOW Level
VHYS
IIN
VOL
Conditions
Min
Typ
0.7xVDD
Hysteresis of Inputs
Max
Unit
5.5
V
0.3xVDD
V
0.05xVDD
V
Input Leakage Current
VDD = 0V
±1.0
µA
Output LOW Voltage
IOL = 3 mA
0.4
V
I2C Bus AC Characteristics for Standard Mode1
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
100
kHz
Bus free time between STOP and START
4.7
µs
tSU:START
Setup Time, START
4.7
µs
tHD:START
Hold Time, START
4
µs
tSU:DATA
Setup Time, data input (SDA)
250
ns
tHD:DATA
Hold Time, data input (SDA) 1
0
µs
tOVD
Output data valid from clock
3.45
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDA, SCLK)
1000
ns
tF
Fall Time, data and clock (SDA, SCLK)
300
ns
tHIGH
HIGH Time, clock (SCLK)
4
µs
tLOW
LOW Time, clock (SCLK)
4.7
µs
4
µs
tSU:STOP
Setup Time, STOP
1) No activity is allowed on I2C lines until VDD>1.62V.
2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCLK signal)
to bridge the undefined region of the falling edge of SCLK.
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EEPROM CLOCK GENERATOR
I2C Bus AC Characteristics for Fast Mode1
Symbol
FSCLK
tBUF
Parameter
Min
Serial Clock Frequency (SCL)
0
Typ
Max
Unit
400
kHz
Bus free time between STOP and START
1.3
µs
tSU:START
Setup Time, START
0.6
µs
tHD:START
Hold Time, START
0.6
µs
100
ns
0
µs
tSU:DATA
Setup Time, data input (SDA)
tHD:DATA
Hold Time, data input (SDA)
1
tOVD
Output data valid from clock
0.9
µs
CB
Capacitive Load for Each Bus Line
400
pF
tR
Rise Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tF
Fall Time, data and clock (SDA, SCL)
20 + 0.1xCB
300
ns
tHIGH
HIGH Time, clock (SCL)
0.6
µs
tLOW
LOW Time, clock (SCL)
1.3
µs
Setup Time, STOP
0.6
µs
tSU:STOP
1) No activity is allowed on I2C lines until VDD>1.62V.
2) A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIHMIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
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EEPROM CLOCK GENERATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the IDT5P49EE601. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only
over the recommended operating temperature range.
Symbol
Max
Unit
Internal Power Supply Voltage
-0.5 to +4.6
V
VI
Input Voltage
-0.5 to +4.6
V
VO
Output Voltage (not to exceed 4.6 V)
-0.5 to VDD+0.5
V
TJ
Junction Temperature
150
°C
TSTG
Storage Temperature
-65 to +150
°C
VDD
Description
Recommended Operation Conditions
Symbol
VDD
Parameter
Typ
Max
Unit
3
3.3
3.6
V
3.135
3.3
3.465
Power supply voltage for VDD closest to LVTTL and
core
Power supply voltage for VDD closest to LVDS outputs
TA
Min
+85
°C
CLOAD_OUT Maximum load capacitance (3.3V LVTTL only)
15
pF
CLOAD_OUT Maximum load capacitance (1.8V or 2.5V LVTTL only)
8
pF
MHz
FIN
tPU
Operating temperature, ambient
-40
External reference crystal
8
30
External reference clock CLKIN
1
40
0.05
5
Power up time for all VDDs to reach minimum specified
voltage (power ramps must be monotonic)
ms
Capacitance (TA = +25 °C, f = 1 MHz, VIN = 0V)
Symbol
CIN
Parameter
Min
Input Capacitance
Typ
Max
3
Unit
pF
Crystal Specifications
XTAL_FREQ
Crystal frequency
8
30
MHz
XTAL_MIN
Minimum crystal load capacitance
TBD
pF
XTAL_MAX
Maximum crystal load capacitance
35.4
pF
XTAL_VPP
Voltage swing (peak-to-peak, nominal)
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
1.5
14
2.3
3.2
V
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
DC Electrical Characteristics for 3.3 Volt LVTTL 1
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
IOH = 33mA
VOL
Output LOW Voltage
IOH = 33mA
VIH
Input HIGH Voltage
VIL
Input LOW Voltage
IOZDD
Min
Typ
2.4
Max
Unit
VDDO
V
0.4
V
2
V
Output Leakage Current 3-state outputs
0.8
V
5
µA
Max
Unit
VDDO
V
0.4
V
5
µA
Max
Unit
VDDO
V
0.35*VDDO
V
5
µA
DC Electrical Characteristics for 2.5Volt LVTTL 1
Symbol
Parameter
Test Conditions
VOH
Output HIGH Voltage
IOH = 25mA
VOL
Output LOW Voltage
IOH = 25mA
IOZDD
Min
Typ
2.1
Output Leakage Current 3-state outputs
DC Electrical Characteristics for 1.8Volt LVTTL 1
Symbol
Parameter
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
IOZDD
Test Conditions
VDD = 1.71V to 1.89V
Min
Typ
0.65*VDDO
Output Leakage Current 3-state outputs
Power Supply Characteristics for LVTTL Outputs
Symbol
Parameter
ITOT
Total Power VDD Supply Current
Test Conditions
FREFERENCE CLOCK = 25 MHz, CL = 7 pF
Typ
TBD
Max
Unit
mA
Note 1: See “Recommended Operating Conditions” table. Alway completely power up VDD and VDDx prior to applying
VDDO power.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
15
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
DC Electrical Characteristics for LVDS
Symbol
Parameter
Min
Typ
Max
Unit
VOT (+)
Differential Output Voltage for the TRUE binary state
247
454
mV
VOT (-)
Differential Output Voltage for the FALSE binary state
-247
-454
mV
50
mV
1.375
V
50
mV
VOT
VOS
Change in VOT between Complimentary Output States
Output Common Mode Voltage (Offset Voltage)
VOS
1.125
1.2
Change in VOS between Complimentary Output States
IOS
Outputs Short Circuit Current, VOUT+ or VOUT- = 0V or VDD
TBD
TBD
mA
IOSD
Differential Outputs Short Circuit Current, VOUT+ = VOUT-
TBD
TBD
mA
Power Supply Characteristics for LVDS Outputs 1
Symbol
Test Conditions 2
Parameter
Typ
Max
Unit
IDDQ
Quiescent VDD Power
Supply Current
REF = LOW
Outputs enabled, all outputs unloaded
TBD
TBD
mA
IDDD
Dynamic VDD Power Supply
Current per Output
VDD = Max., CL = 0pF
TBD
TBD
µA/MHz
ITOT
Total Power VDD Supply
Current
FREFERENCE CLOCK = 25 MHz, CL = 5 pF
TBD
TBD
mA
1) OUT4A and OUT4B are toggling. Other outputs are powered down.
2) The termination resistors are excluded from these measurements.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
16
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
AC Timing Electrical Characteristics
(Spread Spectrum Generation = OFF)
Symbol
fIN
1 / t1
fVCO
Parameter
Test Conditions
Max.
Units
11
40
MHz
0.001
120
MHz
Single Ended Clock output limit (LVTTL) 2.5V
110
MHz
Single Ended Clock output limit (LVTTL) 1.8V
100
MHz
Differential Clock output limit (LVDS)
150
MHz
Input Frequency
Input Frequency Limit (CLKIN)
Output Frequency
Single Ended Clock output limit (LVTTL) 3.3V
VCO Frequency
Min.
Typ.
VCO operating Frequency Range
100
500
MHz
1
20
MHz
fPFD
PFD Frequency
PFD operating Frequency Range
0.5
fBW
Loop Bandwidth
Based on loop filter resistor and capacitor
values
0.01
10
MHz
t2
Input Duty Cycle
Duty Cycle for Input
40
60
%
t3
Output Duty Cycle
Measured at VDD/2
45
55
%
t4
Slew Rate, SLEWx(bits) = 00
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
3.5
Slew Rate, SLEWx(bits) = 01
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
2.75
Slew Rate, SLEWx(bits) = 10
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
2
Slew Rate, SLEWx(bits) = 11
Single-Ended 3.3V LVCMOS Output clock rise
and fall time, 20% to 80% of VDD (Output
Load = 7 pF)
1.25
Rise Times
LVDS, 20% to 80%
600
t5
Fall Times
t7
Clock Jitter
V/ns
ps
600
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Single output frequency only.
100
ps
Peak-to-peak period jitter, CLK outputs
measured at VDD/2; fPFD >= 10 MHz
Multiple output frequencies switching.
200
ps
200
ps
t6
Output Skew
Skew between any output (Same freq and IO
type, FOUT >10MHz)
t7
Lock Time
PLL Lock Time from Power-up (using MHz
reference clock)2
5
20
ms
PLL Lock Time from Power-up using
32.768kHz reference clock)
1
3
s
1) Input clock (square wave) may be used at 1 MHz.
2) Time from supply voltage crosses VDD=1.62V to PLLs are locked.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
17
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Spread Spectrum Generation Specifications
Symbol
fIN
fMOD
fSPREAD
Parameter
Description
Min
Typ
Max
Unit
Input Frequency Input Frequency Limit
11
40
MHz
Mod Frequency
Modulation Frequency
32
120
kHz
Spread Value
Amount of Spread Value (programmable) - Down Spread
Programmable
Amount of Spread Value (programmable) - Center Spread
Programmable
%fOUT
Note 1: Practical lower frequency is determined by loop filter settings.
Test Circuits and Conditions 1
Test Circuits for DC Outputs
Other Termination Scheme (Block Diagram)
LVTTL: ~7pF for each output
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
LVDS: 100 between differential outputs with 5pF
18
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Programming Registers Table
Default
Register
Addr
Hex
Value
Bit #
7
6
5
4
3
0x00
00
ONXTALB
CSX2[1:0]
0x01
00
INV[0]
SLEW0[0:1]
0x02
00
0x03
00
0x04
00
0x05
00
0x06
00
0x07
00
INV[2]
SLEW2[0:1]
0x08
00
INV[3]
SLEW3[0:1]
0x09
00
INV[4B]
0x0A
00
Reserved
0x0B
00
Reserved
0x0C
00
Reserved
0x0D
00
Reserved
0x0E
00
REFA[7:0]
0x0F
00
0x10
00
0x11
00
2
1
0
Reserved
ONXTALB - MHz Crystal active low
CSX2 [1:0]- internal 32kHz crystal
cap2
00 - 18pF; 10 - 30pF
01 - 24pF; 11 - 36pF
CSX1 [1:0] - Internal 32kHz crystal
cap1
00 - 0pF; 10 - 6pF
01 - 3pF; 11 - 9pF
XTAL32ONB - 32k crystal active low
PS0[2:1]
Reserved
PS1[2:1]
Reserved
Reserved
PS22:1]
Reserved
Reserved
PS3[2:1]
No_PD - Enables/Disables 32kHz
clock output on Config 00.
No_PD=0 - 32kHz is off.
No_PD=1 - 32kHz remains active.
INV[#] - Invert output#
SLEW#[0:1] - output# slew setting
0 0 - 5.1V/ns
0 1 - 4.4V/ns
1 0 - 2.8V/ns
1 1 - 1.8V/ns
PS#[2:1] -Power Select
00 - Reserved
01 - CLK# connects to VDDO1
10 - CLK# connects to VDDO2
11 - CLK# connects to VDDO3s
CSX1[1:0]
XTAL32ONB
No_PD
Reserved
Reserved
INV[1]
SLEW1[0:1]
Reserved
Reserved
Reserved
INV[4A]
SLEW4[0:1]
Reserved
Reserved
Configuration0
REFA[7:0] - Reference Divide PLLA
FBA[10:3)
FBA[10:0] - Feedback Divide PLLA
Reserved
Reserved
XDIVA
FBA[2:0)
RZA[1:0]
IPA[2:0]
0x12
00
REFB[7:0]
0x13
00
FBB[10:3]
0x14
00
0x15
00
0x16
00
0x17
00
0x18
00
REFSELA
XDIVA - FB predivide PLLA;
0 - /1; 1 - /4
RZA[1:0] - Zero Resistor PLLA
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPA[2:0] - charge Pump Current
PLLA
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
REFSELA - Clock input PLLA
0 - MHz input
1 - 32kHz input
REFB[7:0] - Reference Divide PLLB
FBB[10:0] - Feedback Divide PLLB
MOD[4:0]
FBB[2:0]
MOD[12:5]
NC[10:3]
NSS[4:0]
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
Description
PLLB Spread Parameters
MOD[12:0]
NC[10:0]
NSS[12:0]
NC[2:0]
NSS[12:5]
19
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
Default
Register
Addr
Hex
Value
0x19
20
0x1A
00
EEPROM CLOCK GENERATOR
Bit #
7
6
5
4
Reserved
3
2
1
0
IPB[2:0]
RZB[1:0]
Reserved
REFSELB
0x1B
00
REFC[7:0]
0x1C
00
FBC[10:3]
0x1D
00
0x1E
00
0x1F
00
0x20
00
REFD[7:0]
0x21
00
FBD[10:3]
0x22
00
0x23
00
0x24
00
OD0[7:0]
0x25
00
Reserved
0x26
00
Reserved
0x27
00
OD1[7:0]
0x28
00
Reserved
SSENB_B
FBC[10:0] - Feedback Divide PLLC
FBC[2:0]
FBC2 - Feedback Predivide PLLC
Turn on using XDIVC=1
FBC2[7:0]
RZC[1:0]
Reserved
RZD[1:0]
REFSELC
RZC[1:0] - Zero Resistor PLLC
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPC[2:0] - charge Pump Current
PLLC
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
REFSELC
0 - MHz input
1 - 32kHz input
FBD[10:0] - Feedback Divide PLLD
FBD[2:0]
IPD[2:0]
0x29
00
Reserved
0x2A
00
OD2[7:0]
0x2B
00
OD3[7:0]
0x2C
00
OD4[7:0]
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
XDIVC
REFD[7:0] - Reference Divide PLLD
Reserved
XDIVD
RZB[1:0] - Zero Resistor PLLB
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPB[2:0] - charge Pump Current
PLLB
000 - 0.37uA, 100 - 6.3uA
001 - 1.1uA, 101 - 11.9uA
010 - 1.8 uA, 110 - 17.7uA
011 - 3.4uA, 111 - 22.7uA
REFSELB - Clock input PLLB
0 - MHz input
1 - 32kHz input
REFC[7:0] - Reference Divide PLLC
Reserved
IPC[2:0]
Description
REFSELD[1:0]
XDIVD - FB predivide PLLD;
0 - /1; 1 - /4
RZD[1:0] - Zero Resistor PLLD
00 - 5kOhm
01 - 10kOhm
10 - 30kOhm
11 - 80kOhm
IPD[2:0] - charge Pump Current
PLLD
100 - 6.3uA
101 -11.9 uA
110 - 17.7 uA
111 - 22.7uA
REFSELD[1:0]
00 - MHz input
11 - 32kHz input
Others - Reserved
OD#[7:0] - Output Divide#
20
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
Default
Register
Addr
Hex
Value
EEPROM CLOCK GENERATOR
Bit #
7
6
5
4
3
2
1
0
Description
0x2D
00
SCR4[1:0]
SCR3[1:0]
SCR2[1:0]
Reserved
SRC4[1:0] - OD4 source
00 - off; 10 - PLLC
01 - PLLA; 11 - MHz Reference
SRC3[1:0] - OD3 source
00 - off; 10 - PLLA
01 - PLLC; 11 - PLLB
SRC2[1:0] - OD2 source
00 - off; 10 - MHz Reference
01 - PLLC; 11 - 32kHz Reference
0x2E
00
Reserved
SCR1[1:0]
Reserved
Reserved
SRC1[1:0] - OD1 source
00 - off; 10 - PLLB
01 - 32kHz Reference; 11 - PLLD
0x2F
00
SCR0[1:0]
0x30
00
Reserved
SRC0[1:0] - OD0 source
00 - off; 10 - PLLC
01 - PLLB; 11 - PLLD
Reserved
0x31
00
PDB[4]
LVDS_ON
OE[4B]
OE[4A]
0x32
00
OE[3]
OE[2]
Reserved
Reserved
OE[1]
Reserved
Reserved
OE[0]
0x33
00
PDB[3]
PDB[2]
Reserved
Reserved
PDB[1]
Reserved
Reserved
PDB[0]
Reserved
0x34
00
REFA[7:0]
0x35
00
FBA[10:3)
0x36
00
0x37
00
0x38
00
0x39
00
0x3A
00
0x3B
00
0x3C
00
0x3D
00
0x3E
00
0x3F
40
0x40
00
0x41
00
0x42
00
0x43
00
0x44
00
Reserved
Reserved
Configuration1
(See definitions from
Configuration0 above)
FBA[2:0)
RZA[1:0]
XDIVA
IPA[2:0]
PDB[#] - Powerdown OUT#.
PDB#=0, OUT# driven low
OE[#] - Output enable OUT#.
OE#=0, OUT# tri-stated.
If PDB#=OE#=0, OUT# driven low
LVDS_ON
0 - OUT4A/OUT4B - LVCMOS
outputs
1 - OUT4A/OUT4B -LVDS outputs.
VDDO must be 3.3V
REFSELA
REFB[7:0]
FBB[10:3]
MOD[4:0]
FBB[2:0]
MOD[12:5]
NC[10:3]
NSS[4:0]
NC[2:0]
NSS[12:5]
Reserved
IPB[2:0]
RZB[1:0]
REFSELB
Reserved
SSENB_B
REFC[7:0]
FBC[10:3]
FBC[2:0]
Reserved
FBC2[7:0]
IPC[2:0]
0x45
00
0x46
00
RZC[1:0]
0x47
00
0x48
00
0x49
00
0x4A
00
OD0[7:0]
Reserved
XDIV
REFSELC
REFD[7:0]
FBD[10:3]
Reserved
XDIVD
RZD[1:0]
FBD[2:0]
IPD[2:0]
0x4B
00
Reserved
0x4C
00
Reserved
0x4D
00
OD1[7:0]
0x4E
00
Reserved
0x4F
00
Reserved
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
21
REFSELD[1:0]
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
Default
Register
Addr
Hex
Value
EEPROM CLOCK GENERATOR
Bit #
7
6
5
4
3
2
1
0
0x50
00
OD2[7:0]
0x51
00
OD3[7:0]
0x52
00
0x53
00
SCR4[1:0]
SCR3[1:0]
SCR21:0]
Reserved
0x54
00
Reserved
SCR1[1:0]
Reserved
Reserved
0x55
00
SCR0[1:0]
0x56
00
0x57
00
PDB[4]
LVDS_ON
OE[4B]
OE[4A]
0x58
00
OE[3]
OE[2]
Reserved
Reserved
OE[1]
Reserved
Reserved
OE[0]
0x59
00
PDB[3]
PDB[2]
Reserved
Reserved
PDB[1]
Reserved
Reserved
PDB[0]
0x5A
00
REFA[7:0]
0x5B
00
FBA[10:3)
0x5C
00
0x5D
00
0x5E
00
0x5F
00
0x60
00
0x61
00
0x62
00
0x63
00
0x64
00
0x65
40
0x66
00
0x67
00
0x68
00
0x69
00
0x6A
00
Description
OD47:0]
Reserved
Reserved
Reserved
Reserved
Reserved
XDIVA
Configuration2
(See definitions from
Configuration0 above)
FBA[2:0)
RZA[1:0]
IPA[2:0]
REFSELA
REFB[7:0]
FBB[10:3]
MOD[4:0]
FBB[2:0]
MOD[12:5]
NC[10:3]
NSS[4:0]
NC[2:0]
NSS[12:5]
Reserved
IPB[2:0]
RZB[1:0]
REFSELB
Reserved
SSENB_B
REFC[7:0]
FBC[10:3]
FBC[2:0]
Reserved
FBC2[7:0]
IPC[2:0]
0x6B
00
0x6C
00
RZC[1:0]
Reserved
XDIV
REFSELC
0x6D
00
0x6E
00
0x6F
00
0x70
00
OD0[7:0]
0x71
00
Reserved
0x72
00
Reserved
0x73
00
OD1[7:0]
0x74
00
Reserved
0x75
00
Reserved
0x76
00
OD2[7:0]
0x77
00
OD3[7:0]
0x78
00
0x79
00
SCR4[1:0]
SCR3[1:0]
SCR2[1:0]
Reserved
0x7A
00
Reserved
SCR1[1:0]
Reserved
Reserved
SCR0[1:0]
REFD[7:0]
FBD[10:3]
Reserved
XDIVD
FBD[2:0]
IPD[2:0]
RZD[1:0]
REFSELD[1:0]
OD4[7:0]
0x7B
00
0x7C
00
0x7D
00
PDB[4]
LVDS_ON
OE[4B]
OE[4A]
0x7E
00
OE[3]
OE[2]
Reserved
Reserved
OE[1]
Reserved
Reserved
OE[0]
0x7F
00
PDB[3]
PDB[2]
Reserved
Reserved
PDB[1]
Reserved
Reserved
PDB[0]
Reserved
Reserved
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
Reserved
22
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Marking Diagram (NL24)
4601LI
#YYWW$
Notes:
1. “Z” is the device step (1 to 2 characters).
2. YYWW is the last two digits of the year and week that the part was assembled.
3. “$” is the assembly mark code.
4. “G” after the two-letter package code designates RoHS compliant package.
5. “I” at the end of part number indicates industrial temperature range.
6. Bottom marking: country of origin if not USA.
Thermal Characteristics for 24QFN
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
Symbol
Conditions
Min.
Typ.
Max. Units
JA
Still air
29.1
C/W
JA
1 m/s air flow
22.8
C/W
JA
2.5 m/s air flow
21.0
C/W
41.8
C/W
JC
23
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Package Outline and Package Dimensions (24-pin 4mm x 4mm QFN)
Package dimensions are kept current with JEDEC Publication No. 95
Seating Plane
A1
Index Area
N
1
2
(Ref)
ND & NE
Even
(ND-1)x e
(Ref)
L
A3
e
N
1
(Typ)
If ND & NE
2
are Even
2
Sawn
Singulation
E
E2
E2
Top View
A
D
0.08 C
Symbol
A
A1
A3
b
e
N
ND
NE
D x E BASIC
D2
E2
L
Min
(NE-1)x e
(Ref)
2
(Ref)
ND & NE
Odd
C
b
e
Thermal Base
D2
2
D2
Millimeters
Max
0.80
1.00
0
0.05
0.25 Reference
0.18
0.30
0.50 BASIC
24
6
6
4.00 x 4.00
2.3
2.55
2.3
2.55
0.30
0.50
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Package
Temperature
5P49EE601NLGI
5P49EE601NLGI8
See Page 23
See Page 23
Tubes
Tape and Reel
24pin VFQFPN
24pin VFQFPN
-40 to +85 C
-40 to +85 C
Parts that are ordered with a “G” after the two-letter package code are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes
no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No
other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications
such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT
does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
24
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
Revision History
Rev.
Originator
Date
Description of Change
--
R.Willner
10/29/09
Preliminary Datasheet release.
A
R.Willner
11/20/09
No_PD bit inclusion - 32kHz clock on/off in Config 00.
B
R.Willner
3/25/10
Typographical changes. Correct spread spectrum calculations.
C
R.Willner
6/11/10
Typographical changes. Default configuration.
IDT™ VERSACLOCK® LOW POWER CLOCK GENERATOR
25
IDT5P49EE601 REV C 061110
IDT5P49EE601
VERSACLOCK® LOW POWER CLOCK GENERATOR
EEPROM CLOCK GENERATOR
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© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated Device
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Printed in USA