High Performance 1A LDO ISL80101 Features The ISL80101 is a low voltage, high current, single output LDO specified at 1A output current. This LDO operates from input voltages of 2.2V to 6V. Fixed output voltage options are available in 1.8V, 2.5V, 3.3V and 5.0V versions. Other custom voltage options are available upon request. For the adjustable output version of the ISL80101, please refer to the ISL80101-ADJ datasheet. • ±0.2% Initial VOUT Accuracy • ±1.8% VOUT Accuracy Guaranteed Over Line, Load and TJ = -40°C to +125°C • Very Low 130mV Dropout Voltage at VOUT = 2.5V • Very Fast Transient Response • Programmable Soft-starting A sub-micron BiCMOS process is utilized for this product family to deliver the best in class analog performance and overall value. This CMOS LDO consumes significantly lower quiescent current as a function of load compared to bipolar LDOs, which translates into higher efficiency and packages with smaller footprints. State of the art internal compensation achieves a very fast load transient response. An external capacitor on the soft-start pin provides an adjustable soft-starting ramp. The ENABLE feature allows the part to be placed into a low quiescent current shutdown mode. A Power-Good logic output signals a fault condition. • Power-Good Output Table 1 shows the differences between the ISL80101 and others in its family: • Noise-Sensitive Instrumentation Systems TABLE 1. KEY DIFFERENCES BETWEEN FAMILY OF PARTS • Excellent 58dB PSRR at 1kHz • Current Limit Protection • Thermal Shutdown Function • Available in a 10 Ld DFN Package • Pb-Free (RoHS Compliant) Applications • DSP, FPGA and µP Core Power Supplies • Post Regulation of Switched Mode Power Supplies • Industrial Systems PART NUMBER PROGRAMMABLE ILIMIT ILIMIT (DEFAULT) ADJ or FIXED VOUT ISL80101-ADJ No 1.75A ADJ ISL80101 No 1.75A 1.8V, 2.5V, 3.3V, 5.0V ISL80101A Yes 1.62A ADJ ISL80121-5 Yes 0.75A 5.0V • Medical Equipment • Telecommunications and Networking Equipment • Servers • Hard Disk Drives (HD/HDD) Related Literature • See AN1592, “ISL80101 High Performance 1A LDO Evaluation Board User Guide” 10µF CIN 10 9 VIN VOUT VIN VOUT 10k R3 SENSE 2 3 ISL80101 7 6 0.01µF CSS 1 ENABLE PG 140 5.0V ± 1.8% 10µF COUT 100k RPG 4 SS GND 5 DROPOUT VOLTAGE (mV) 5.4V ± 10% 120 100 80 60 40 20 0 VOUT = 2.5V 0 0.2 0.4 0.6 0.8 1.0 OUTPUT CURRENT (A) FIGURE 1. TYPICAL APPLICATION CIRCUIT August 31, 2011 FN6931.1 1 FIGURE 2. DROPOUT vs LOAD CURRENT CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2009, 2011. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL80101 Block Diagram VIN EN CONTROL LOGIC EA REFERENCE + SOFT-START THERMAL SENSOR PG PG + FET DRIVER WITH CURRENT LIMIT VOUT SS ADJ SENSE + - GND Ordering Information PART NUMBER (Notes 1, 3, 4) PART MARKING VOUT VOLTAGE (Note 2) TEMP RANGE (°C) PACKAGE (Pb-Free) PKG DWG. # ISL80101IR18Z DZEB 1.8V -40 to +125 10 Ld 3x3 DFN L10.3x3 ISL80101IR25Z DZFB 2.5V -40 to +125 10 Ld 3x3 DFN L10.3x3 ISL80101IR33Z DZGB 3.3V -40 to +125 10 Ld 3x3 DFN L10.3x3 ISL80101IR50Z DZHB 5.0V -40 to +125 10 Ld 3x3 DFN L10.3x3 ISL80101EVAL2Z Evaluation Board NOTES: 1. Add “-T*” for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. For other output voltages, contact Intersil Marketing. 3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 4. For Moisture Sensitivity Level (MSL), please see device information page for ISL80101. For more information on MSL please see Technical Brief TB363. 2 FN6931.1 August 31, 2011 ISL80101 Pin Configurations ISL80101 (10 LD 3X3 DFN) TOP VIEW VOUT 1 10 VIN VOUT 2 SENSE 3 PG 4 GND 5 9 VIN EPAD 8 NC 7 ENABLE 6 SS Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 2 VOUT 3 SENSE 4 PG 5 GND 6 SS 7 ENABLE 8 NC No connection. Leave floating. 9, 10 VIN Input supply. A minimum of 10µF X5R/X7R input capacitor is required for proper operation. See “External Capacitor Requirements” on page 8 for more details. - EPAD Regulated output voltage. A minimum 10µF X5R/X7R output capacitor is required for stability. See “External Capacitor Requirements” on page 8 for more details. The PGOOD circuit uses this input to monitor the output voltage status, providing a remote voltage sense. This is an open drain logic output used to indicate the status of the output voltage. Logic low indicates VOUT is not in regulation. This pin must be grounded if not used. Ground. External capacitor on this pin adjusts startup ramp and controls inrush current. VIN independent chip enable. TTL and CMOS compatible. EPAD at ground potential. It is recommended to solder the EPAD to the ground plane. 3 FN6931.1 August 31, 2011 ISL80101 Absolute Maximum Ratings Thermal Information VIN Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V VOUT Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V PG, ENABLE, SENSE, SS Relative to GND (Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V ESD Rating Human Body Model (Tested per JESD22 A114F) . . . . . . . . . . . . . . .2.5kV Machine Model (Tested per JESD22 A115C) . . . . . . . . . . . . . . . . . 250V Latch Up (Tested per JESD78C, Class 2, Level A) . . . . . ±100mA at +85°C Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 10 Ld DFN Package (Notes 6, 7) . . . . . . . . 48 7 Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions (Notes 8, 9) Junction Temperature Range (TJ) (Note 8) . . . . . . . . . . . .-40°C to +125°C VIN Relative to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.2V to 6V VOUT Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mV to 5V PG, ENABLE, SENSE/ADJ, SS relative to GND . . . . . . . . . . . . . . . . 0V to 6V PG Sink Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . <10mA CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 5. Absolute maximum voltage rating is defined as the voltage applied for a lifetime average duty cycle above 6V of 1%. 6. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech Brief TB379. 7. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. 8. Extended operation at these conditions may compromise reliability. Exceeding these limits will result in damage. Recommended operating conditions define limits where specifications are guaranteed. 9. Electromigration specification defined as lifetime average junction temperature of +110°C where max rated DC current = lifetime average current. Electrical Specifications Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 2.2µF, TJ = +25°C. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40°C to +125°C. PARAMETER SYMBOL TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNITS DC CHARACTERISTICS DC Output Voltage Accuracy VOUT VOUT + 0.4V < VIN < 6V, 0A < ILOAD < 1A DC Input Line Regulation ΔVOUT/ ΔVIN VOUT + 0.4V < VIN < 6V DC Output Load Regulation ΔVOUT/ ΔIOUT 0A < ILOAD < 1A, All voltage options Ground Pin Current Ground Pin Current in Shutdown IQ ILOAD = 0A, 2.2V < VIN < 6V ILOAD = 1A, 2.2V < VIN < 6V ISHDN ENABLE Pin = 0.2V, VIN = 6V -1.8 1.8 % 1 % -1 % 3 5 mA 5 7 mA 0.2 12 µA 212 mV Dropout Voltage (Note 11) VDO ILOAD = 1A, VOUT = 2.5V 130 Output Short Circuit Current OCP VOUT = 0V, 2.2V < VIN < 6V 1.75 A Thermal Shutdown Temperature TSD 2.2V < VIN < 6V 160 °C Thermal Shutdown Hysteresis (Rising Threshold) TSDn 2.2V < VIN < 6V 30 °C PSRR f = 1kHz, ILOAD = 1A; VIN = 2.2V 58 dB f = 120Hz, ILOAD = 1A; VIN = 2.2V 72 dB ILOAD = 1A, BW = 10Hz < f < 100kHz 63 µVRMS AC CHARACTERISTICS Input Supply Ripple Rejection Output Noise Voltage ENABLE PIN CHARACTERISTICS Turn-on Threshold 2.2V < VIN < 6V 0.3 0.8 1 V Hysteresis (Rising Threshold) 2.2V < VOUT + 0.4V < 6V 10 80 200 mV 4 FN6931.1 August 31, 2011 ISL80101 Electrical Specifications Unless otherwise noted, VIN = VOUT + 0.4V, VOUT = 1.8V, CIN = COUT = 2.2µF, TJ = +25°C. Applications must follow thermal guidelines of the package to determine worst case junction temperature. Please refer to “Applications Information” on page 8 and Tech Brief TB379. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS ENABLE Pin Turn-on Delay COUT = 10µF, ILOAD = 1A ENABLE Pin Leakage Current VIN = 6V, ENABLE = 3V MIN (Note 10) TYP MAX (Note 10) 100 UNITS µs 1 µA SOFT-START CHARACTERISTICS SS Pin Currents (Note 11) IPD VIN = 3.5V, ENABLE = 0V, SS = 1V ICHG 0.5 1 1.3 mA -3.3 -2 -0.8 µA 75 85 92 %VOUT 100 mV 1 µA PG PIN CHARACTERISTICS VOUT PG Flag Threshold VOUT PG Flag Hysteresis 4 PG Flag Low Voltage VIN = 2.5V, ISINK = 500µA PG Flag Leakage Current VIN = 6V, PG = 6V % NOTES: 10. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 11. Dropout is defined as the difference in supply VIN and VOUT when the output is below its nominal regulation.. 5 FN6931.1 August 31, 2011 ISL80101 Typical Operating Performance Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. 200 1.8 VOUT = 2.5V 1.2 160 140 IOUT = 1.0A 0.6 DVOUT (%) DROPOUT VOLTAGE (mV) 180 120 100 IOUT = 0.5A 80 60 0 -0.6 IOUT = 0.1A 40 -1.2 20 0 -40 -25 -10 5 20 35 50 65 80 95 -1.8 -50 110 125 -25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (°C) TEMPERATURE (°C) FIGURE 3. DROPOUT vs TEMPERATURE FIGURE 4. VOUT vs TEMPERATURE 1.8 2.0 1.2 1.6 1.4 0.6 1.2 DVOUT (%) OUTPUT VOLTAGE (V) 1.8 +125°C 1.0 0.8 -40°C +25°C 0.6 0.4 +25°C 0 -0.6 -40°C +125°C -1.2 0.2 0 0 1 3 2 5 4 6 -1.8 0 0.25 SUPPLY VOLTAGE (V) FIGURE 5. OUTPUT VOLTAGE vs SUPPLY VOLTAGE 5 3.0 GROUND CURRENT (mA) GROUND CURRENT (mA) 1.00 FIGURE 6. OUTPUT VOLTAGE vs OUTPUT CURRENT 3.5 2.5 2.0 1.5 +25°C +125°C -40°C 1.0 4 3 2 1 0.5 0 0.50 0.75 OUTPUT CURRENT (A) 0 0.2 0.4 0.6 0.8 LOAD CURRENT (A) FIGURE 7. GROUND CURRENT vs LOAD CURRENT 6 1.0 0 2 3 4 5 6 INPUT VOLTAGE (V) FIGURE 8. GROUND CURRENT vs SUPPLY VOLTAGE FN6931.1 August 31, 2011 ISL80101 Typical Operating Performance Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued) VOLTAGE RAILS AT 50mV/DIV VOLTAGE RAILS AT 50mV/DIV VIN = 3.7V, VOUT = 3.3V VIN = 2.9V, VOUT = 2.5V VIN = 5.4V, VOUT = 5.0V VIN = 2.5V, VOUT = 1.8V IOUT = 500mA IOUT = 10mA IOUT = 1A IOUT = 1mA di/dt = 4A/µs TIME (50µs/DIV) FIGURE 9A. TIME (50µs/DIV) 20µs/DIV FIGURE 9B. FIGURE 9. LOAD TRANSIENT RESPONSE 3.5 ENABLE (2V/DIV) CURRENT (A) 2.5 2.0 6V VOUT (1V/DIV) 2.2V 1.5 1.0 SS (1V/DIV) 0.5 0 (500µs/DIV) PG (1V/DIV) -40 -25 -10 5 20 35 50 65 80 95 110 125 JUNCTION TEMPERATURE (°C) FIGURE 10. CURRENT LIMIT vs TEMPERATURE (VOUT = 0V) FIGURE 11. ENABLE START-UP (Css = 2.2nF) 90 90 80 70 60 PSRR (dB) PSRR (dB) 0mA 100mA 40 50 40 30 30 20 20 10 10 0 100 COUT = 100µF 70 1A 60 50 COUT = 10µF 80 500mA 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 12. PSRR vs FREQUENCY AND LOAD CURRENT 7 0 100 1k 10k FREQUENCY (Hz) 100k 1M FIGURE 13. PSRR vs FREQUENCY AND OUTPUT CAPACITANCE (IOUT = 100mA) FN6931.1 August 31, 2011 ISL80101 Typical Operating Performance Unless otherwise noted: VIN = 2.2V, VOUT = 1.8V, CIN = COUT = 10µF, TJ = +25°C, IL = 0A. (Continued) 10 VIN = 3.8V 1 VIN = 2V/DIV NOISE (µV/√Hz) VIN = 2.25V VOUT = 5mV/DIV 0.1 0.01 IL = 1A TIME (200µs/DIV) 0.001 10 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FIGURE 14. LINE TRANSIENT RESPONSE Applications Information Input Voltage Requirements The ISL80101 is capable of delivering the following fixed output voltages: 1.8V, 2.5V, 3.3V, 5.0V. Due to the nature of an LDO, VIN must be some margin higher than VOUT plus dropout at the maximum rated current of the application if active filtering (PSRR) is expected from VIN to VOUT. The generous dropout specification of this family of LDOs allows applications to design a level of efficiency. Enable Operation The ENABLE turn-on threshold is typically 800mV with 80mV of hysteresis. An internal pull-up or pull-down resistor to change these values is available upon request. As a result, this pin must not be left floating, and should be tied to VIN if not used. A 1kΩ to 10kΩ pull-up resistor is required for applications that use open collector or open drain outputs to control the ENABLE pin. The ENABLE pin may be connected directly to VIN for applications with outputs that are always on. Power-Good Operation PG is a logic output that indicates the status of VOUT and VIN. The PG flag is an open-drain NMOS that can sink up to 10mA during a fault condition. The PG pin requires an external pull-up resistor typically connected to the VOUT pin. The PG pin should not be pulled up to a voltage source greater than VIN. PG goes low when the output voltage drops below 84% of the nominal output voltage or if the part is disabled. PG functions during current limit and thermal shutdown. For applications not using this feature, connect this pin to ground. Soft-Start Operation The soft-start circuit controls the rate at which the output voltage rises up to regulation at power-up or LDO enable. This start-up ramp time can be set by adding an external capacitor from the SS pin to ground. An internal 2µA current source charges up this 8 FIGURE 15. OUTPUT NOISE SPECTRAL DENSITY CSS and the feedback reference voltage is clamped to the voltage across it. The start-up time is set by Equation 1. C SS x0.5 t start = ---------------------2μA (EQ. 1) Equation 2 determines the CSS required for a specific start-up in-rush current, where VOUT is the output voltage, COUT is the total capacitance on the output and IINRUSH is the desired in-rush current. V OUT xC OUT x2μA C SS = --------------------------------------------I INRUSH x0.5V (EQ. 2) The external capacitor is always discharged to ground at the beginning of start-up or enabling. External Capacitor Requirements External capacitors are required for proper operation. Careful attention must be paid to the layout guidelines and selection of capacitor type and value to ensure optimal performance. OUTPUT CAPACITOR The ISL80101 applies state-of-the-art internal compensation to keep the selection of the output capacitor simple for the customer. Stable operation over full temperature, VIN range, VOUT range and load extremes are guaranteed for all capacitor types and values assuming a minimum of 10µF X5R/X7R is used for local bypass on VOUT. This output capacitor must be connected to the VOUT and GND pins of the LDO with PCB traces no longer than 0.5cm. There is a growing trend to use very-low ESR multilayer ceramic capacitors (MLCC) because they can support fast load transients and also bypass very high frequency noise from other sources. However, the effective capacitance of MLCCs drops with applied voltage, age, and temperature. X7R and X5R dieletric ceramic capacitors are strongly recommended as they typically maintain a capacitance range within ±20% of nominal voltage over full operating ratings of temperature and voltage. FN6931.1 August 31, 2011 ISL80101 Additional capacitors of any value in ceramic, POSCAP, alum/tantalum electrolytic types may be placed in parallel to improve PSRR at higher frequencies and/or load transient AC output voltage tolerances. 49 47 For proper operation, a minimum capacitance of 10µF X5R/X7R is required at the input. This ceramic input capacitor must be connected to the VIN and GND pins of the LDO with PCB traces no longer than 0.5cm. Power Dissipation and Thermals The junction temperature must not exceed the range specified in the “Recommended Operating Conditions (Notes 8, 9)” on page 4. The power dissipation can be calculated by using Equation 3: P D = ( V IN – V OUT ) × I OUT + V IN × I GND (EQ. 3) The maximum allowable junction temperature, TJ(MAX) and the maximum expected ambient temperature, TA(MAX) determine the maximum allowable power dissipation, as shown in Equation 4: (EQ. 4) P D ( MAX ) = ( T J ( MAX ) – T A ) ⁄ θ JA θJA is the junction-to-ambient thermal resistance. For safe operation, enure that the power dissipation PD, calculated from Equation 3, is less than the maximum allowable power dissipation PD(MAX). The DFN package uses the copper area on the PCB as a heat-sink. The EPAD of this package must be soldered to the copper plane (GND plane) for effective heat dissipation. Figure 16 shows a curve for the θJA of the DFN package for different copper area sizes. 9 θJA °C/W 45 INPUT CAPACITOR 43 41 39 37 2 4 6 8 10 12 14 16 18 20 22 24 EPAD-MOUNT COPPER LAND AREA ON PCB, mm2 FIGURE 16. 3mmx3mm-10 PIN DFN ON 4-LAYER PCB WITH THERMAL VIAS θJA vs EPAD-MOUNT COPPER LAND AREA ON PCB Thermal Fault Protection The power level and the thermal impedance of the package (+45°C/W for DFN) determine when the junction temperature exceeds the thermal shutdown temperature. In the event that the die temperature exceeds around +160°C, the output of the LDO will shut down until the die temperature cools down to about +130°C. Current Limit Protection The ISL80101 LDO incorporates protection against overcurrent due to any short or overload condition applied to the output pin. The LDO performs as a constant current source when the output current exceeds the current limit threshold noted in the “Electrical Specifications” table on page 4. If the short or overload condition is removed from VOUT, then the output returns to normal voltage regulation mode. In the event of an overload condition, the LDO may begin to cycle on and off due to the die temperature exceeding thermal fault condition and subsequently cooling down after the power device is turned off. FN6931.1 August 31, 2011 ISL80101 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION 7/27/11 FN6931.1 7/20/11 12/21/2009 CHANGE Added Related Literature Main change - Deleted Adjustable Output Voltage Option Version from datasheet, now only refers to fixed output voltage option includes removal of all graphics referring to Adjustable voltage option. Modified page 1 by adding Table of key differences, graphics and changes to text page 2 - Updated Ordering Information by: Removing ADJ Device ISL80101IRAJZ plus Eval boards. Updated Tape and Reel Note by changing "Add "-T" or "TK"…" to "Add "T*"…" Updated Abs Max Rating and Thermal Information by adding ESD ratings and Latchup Changed 10 Ld DFN Tja and Tjc from “45, 4” to “48, 7” Updated DC Output Voltage Accuracy by combining Vout options Removed Feedback Pin (Adj Option Only), Feedback Input Current Specs Removed "(1A Version)" from Output Short circuit Current Spec Removed Adjustable In-Rush Current Limit Characteristics and replaced with Soft-Start Characteristics page 5 - Electrical Spec Note changed from "Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design." To "Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested." Complete Rewrite of Applications Information POD L10.3x3 Changed Note 4 from "Dimension b applies..." to "Lead width applies..." Changed Note callout in Detail X from 4 to 5 Changed height in side view from 0.90 MAX to 1.00 MAX Added Note 4 callout next to lead width in Bottom View In Land Pattern, corrected lead shape for 4 corner pins to "L" shape (was rectangular and did not match bottom view) FN6931.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL80101 To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff FITs are available from our website at: http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 10 FN6931.1 August 31, 2011 ISL80101 Package Outline Drawing L10.3x3 10 LEAD DUAL FLAT PACKAGE (DFN) Rev 6, 09/09 3.00 6 PIN #1 INDEX AREA A B 1 6 PIN 1 INDEX AREA (4X) 3.00 2.00 8x 0.50 2 10 x 0.23 4 0.10 1.60 TOP VIEW 10x 0.35 BOTTOM VIEW 4 (4X) 0.10 M C A B 0.415 PACKAGE OUTLINE 0.200 0.23 0.35 (10 x 0.55) SEE DETAIL "X" (10x 0.23) 1.00 MAX 0.10 C BASE PLANE 2.00 0.20 C SEATING PLANE 0.08 C SIDE VIEW (8x 0.50) C 0.20 REF 5 1.60 0.05 TYPICAL RECOMMENDED LAND PATTERN DETAIL "X" NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal ± 0.05 4. Lead width applies to the metallized terminal and is measured between 0.18mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 indentifier may be either a mold or mark feature. 11 FN6931.1 August 31, 2011