40V, Low Quiescent Current, 150mA Linear Regulator ISL80138 Features The ISL80138 is a high voltage, adjustable VOUT low quiescent current linear regulator ideally suited for “always-on” and “keep alive” applications. The ISL80138 operates from an input voltage of +6V to +40V under normal operating conditions and consumes only 18µA of quiescent current at no load. • Wide VIN Range of 6V to 40V • Adjustable Output Voltage from 2.5V to 12V The ISL80138 features an EN pin that can be used to put the device into a low-quiescent current shutdown mode where it draws only 2µA of supply current. The device features over-temperature shutdown and current limit protection. • Low 2µA of Typical Shutdown Current The ISL80138 is rated over the -40°C to +125°C temperature range and is available in a 14 lead HTSSOP with an exposed pad package. TABLE 1. KEY DIFFERENCES IN FAMILY OF 40V LDO PARTS PART NUMBER MINIMUM IOUT ADJ OR FIXED VOUT ISL80136 50mA ADJ ISL80138 150mA ADJ • Guaranteed 150mA Output Current • Ultra Low 18µA Typical Quiescent Current • ±1% Accurate Voltage Reference • Low Dropout Voltage of 295mV at 150mA • 40V Tolerant Logic Level (TTL/CMOS) Enable Input • Stable Operation with 10µF Output Capacitor • 5kV ESD HBM Rated • Thermal Shutdown and Current Limit Protection • Thermally Enhanced 14 Ld Exposed Pad HTSSOP Package Applications • Industrial Related Literature • Telecommunications • See FN7970, “ISL80136 40V, Low Quiescent Current, 50mA Linear Regulator” VIN = 14V CIN 0.1µF VOUT = 12V OUT IN R1 EN EPAD (GND) ADJ COUT 10µF QUIESCENT CURRENT (µA) 25 20 15 10 5 R2 GND FIGURE 1. TYPICAL APPLICATION January 11, 2012 FN7969.0 1 0 -50 0 50 TEMPERATURE (°C) 100 150 FIGURE 2. QUIESCENT CURRENT vs TEMPERATURE (AT UNITY GAIN). VIN = 14V CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2012. All Rights Reserved Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries. All other trademarks mentioned are the property of their respective owners. ISL80138 Block Diagram VIN EN CONTROL LOGIC FET DRIVER WITH CURRENT LIMIT + EA - VOUT REFERENCE + SOFT-START THERMAL SENSOR ADJ GND Pin Configuration ISL80138 (14 LD HTSSOP) TOP VIEW NC 1 14 OUT IN 2 13 NC NC 3 12 ADJ NC 4 NC 5 THERMAL PAD (GND) 11 NC 10 NC NC 6 9 NC EN 7 8 GND Pin Descriptions PIN NUMBER PIN NAME DESCRIPTION 1, 3, 4, 5, 6, 9, 10, 11, 13 NC Pins have internal termination and can be left unconnected. Connection to ground is optional. 2 IN Input voltage pin. A minimum 0.1µF ceramic capacitor is required for proper operation. Range 6V to 40V. 7 EN 8 GND Ground pin. Enable pin. High on this pin enables the device. Range 0V to VIN. 12 ADJ This pin is connected to the external feedback resistor divider which sets the LDO output voltage. Range 0V to 3V. 14 OUT Regulated output voltage. A 10µF ceramic capacitor is required for stability. Range 0V to 12V. - EPAD It is recommended to solder the EPAD to the ground plane. Ordering Information PART NUMBER (Notes 1, 2, 3) PART MARKING ISL80138IVEAJZ 80138 IAJZ ISL80138EVAL1Z Evaluation Platform TEMP. RANGE (°C) ENABLE PIN OUTPUT VOLTAGE (V) -40 to +125 Yes ADJ PACKAGE (Pb-Free) 14 Ld HTSSOP PKG. DWG. # M14.173B NOTES: 1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see device information page for ISL80138. For more information on MSL please see techbrief TB363. 2 FN7969.0 January 11, 2012 ISL80138 Absolute Maximum Ratings Thermal Information IN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - 0.3V to +45V OUT Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . .. . .GND - 0.3V to 16V ADJ Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to 3V EN Pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to VIN Output Short-circuit Duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Indefinite ESD Rating Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . 5kV Machine Model (Tested per JESD-A115-A) . . . . . . . . . . . . . . . . . . . 200V Charge Device Model (Tested per JESD22-C101C). . . . . . . . . . . . . 2.2kV Latch Up (Tested per JESD78B; Class II, Level A) . . . . . . . . . . . . . . . 100mA Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) 14 Ld HTSSOP Package (Notes 4, 5). . . . . . 37 5 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +175°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions Ambient Temperature Range . . . . . . . . . . . . . . . . . . . . . . -40°C to +125°C IN pin to GND Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6V to +40V OUT pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.5V to +12V EN pin to GND Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +40V CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside. Electrical Specifications Recommended Operating Conditions, unless otherwise noted. VIN = 14V, IOUT = 1mA, CIN = 0.1μF, COUT = 10μF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical specifications are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C. PARAMETER SYMBOL TEST CONDITIONS Input Voltage Range VIN Guaranteed Output Current IOUT VIN = VOUT + VDO ADJ Reference Voltage VOUT EN = High, VIN = 14V, IOUT = 0.1mA to 150mA MIN (Note 8) TYP 6 MAX (Note 8) UNIT 40 150 1.211 V mA 1.223 1.235 V Line Regulation ΔVOUT/ΔVIN 3V ≤ VIN ≤ 40V, IOUT = 1mA 0.04 0.15 % Load Regulation ΔVOUT/ΔIOUT VIN = VOUT +VDO, IOUT = 100µA to 150mA 0.3 0.6 % 7 33 mV 380 525 mV 7 33 mV 295 460 mV EN = LOW 2 3.64 -A EN = HIGH, IOUT = 0mA 18 24 µA EN = HIGH, IOUT = 1mA 22 42 µA EN = HIGH, IOUT = 10mA 34 60 µA EN = HIGH, IOUT = 150mA 90 125 µA PSRR f = 100Hz; VIN_RIPPLE = 500mVP-P; Load = 150mA 66 VEN_H VOUT = Off to On VEN_L VOUT = On to Off Dropout Voltage (Note 6) ΔVDO IOUT = 1mA, VOUT = 3.3V IOUT = 150mA, VOUT = 3.3V IOUT = 1mA, VOUT = 5V IOUT = 150mA, VOUT = 5V Shutdown Current ISHDN Quiescent Current IQ Power Supply Rejection Ratio dB EN FUNCTION EN Threshold Voltage EN Pin Current IEN EN to Regulation Time (Note 7) tEN VOUT = 0V 1.485 0.975 V 0.026 1.65 3 V µA 1.93 ms FN7969.0 January 11, 2012 ISL80138 Electrical Specifications Recommended Operating Conditions, unless otherwise noted. VIN = 14V, IOUT = 1mA, CIN = 0.1μF, COUT = 10μF, TA = TJ = -40°C to +125°C, unless otherwise noted. Typical specifications are at TA = +25°C. Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN (Note 8) TYP MAX (Note 8) UNIT 175 410 mA +165 °C +20 °C PROTECTION FEATURES Output Current Limit ILIMIT VOUT = 0V Thermal Shutdown TSHDN Junction Temperature Rising Thermal Shutdown Hysteresis THYST NOTES: 6. Dropout voltage is defined as (VIN - VOUT) when VOUT is 2% below the value of VOUT when VIN = VOUT + 3V. 7. Enable to Regulation is the time the output takes to reach 95% of its final value with VIN = 14V and EN is taken from VIL to VIH in 5ns. For the adjustable versions, the output voltage is set at 5V. 8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested. 4 FN7969.0 January 11, 2012 ISL80138 Typical Performance Curves VIN = 14V, IOUT = 1mA, VOUT = 5V, TJ = +25°C, unless otherwise specified. 120 30 100 +125°C QUIESCENT CURRENT (µA) QUIESCENT CURRENT (µA) +125°C 80 60 -40°C 40 +25°C 20 0 20 +25°C -40°C 15 10 5 0 0 50 100 LOAD CURRENT (mA) 0 150 FIGURE 3. QUIESCENT CURRENT vs LOAD CURRENT 10 20 INPUT VOLTAGE (V) 30 40 FIGURE 4. QUIESCENT CURRENT vs INPUT VOLTAGE (NO LOAD) 3.0 0.010 OUTPUT VOLTAGE VARIATION (%) SHUTDOWN CURRENT (µA) 25 2.5 VIN = 40V 2.0 1.5 VIN = 14V 1.0 0.5 0 -50 0 50 TEMPERATURE (°C) 100 150 FIGURE 5. SHUTDOWN CURRENT vs TEMPERATURE (EN = 0) 0.005 VOUT = 5V 0 -0.005 -0.010 -50 VOUT = 3.3V 0 50 TEMPERATURE (°C) 100 150 FIGURE 6. OUTPUT VOLTAGE vs TEMPERATURE (LOAD = 50mA) 5.20 OUTPUT VOLTAGE (V) 5.15 500mV/DIV 5.10 EN +125°C 5.05 1V/DIV +25°C 5.00 4.95 VOUT -40°C TIME = 500µs/DIV 4.90 4.85 4.80 0 50 100 LOAD CURRENT (mA) FIGURE 7. OUTPUT VOLTAGE vs LOAD CURRENT 5 150 FIGURE 8. START-UP WAVEFORM FN7969.0 January 11, 2012 ISL80138 Typical Performance Curves VIN = 14V, IOUT = 1mA, VOUT = 5V, TJ = +25°C, unless otherwise specified. (Continued) 70 TIME = 5ms/DIV 60 VOUT = 3.3V PSRR (dB) 50 40 VOUT VOUT = 5V 30 50mA 20 IOUT 0mA 10 0 100 100mV/DIV 1k 10k FREQUENCY (Hz) 100k FIGURE 9. POWER SUPPLY REJECTION RATIO (LOAD = 150mA) 6 1M FIGURE 10. LOAD TRANSIENT RESPONSE FN7969.0 January 11, 2012 ISL80138 Functional Description The output voltage is calculated using Equation 1: Functional Overview ⎛ R1 ⎞ V OUT = 1.223V × ⎜ ------- + 1⎟ R ⎝ 2 ⎠ The ISL80138 is a high performance, high voltage, low-dropout regulator (LDO) with 150mA sourcing capability. The part is rated to operate over the -40°C to +125°C temperature range. Featuring ultra-low quiescent current, it is an ideal choice for “always-on” applications. It works well under a “load dump condition” where the input voltage could rise up to 40V. This LDO device also features current limit and thermal shutdown protection. Enable Control The ISL80138 has an enable pin, which turns the device on when pulled high. When EN is low, the IC goes into shutdown mode and draws less than 2µA. In “always-on” applications, EN can be tied to IN. Current Limit Protection The ISL80138 has internal current limiting functionality to protect the regulator during fault conditions. During current limit, the output sources a fixed amount of current largely independent of the output voltage. If the short or overload is removed from VOUT, the output returns to normal voltage regulation mode. Thermal Fault Protection In the event that the die temperature exceeds a typical value of +165°C, the output of the LDO will shut down until the die temperature cools down to a typical +145°C. The level of power dissipated, combined with the ambient temperature and the thermal impedance of the package, determines if the junction temperature exceeds the thermal shutdown temperature. See the “Power Dissipation” section on page 7 for more details. Application Information Input and Output Capacitors Power Dissipation The junction temperature must not exceed the range specified in “Recommended Operating Conditions” on page 3. The power dissipation can be calculated using Equation 2: P D = ( V IN – V OUT ) × I OUT + V IN × I GND The maximum allowable junction temperature, TJ(MAX) and the maximum expected ambient temperature, TA(MAX) will determine the maximum allowable junction temperature rise (ΔTJ), as shown in Equation 3: ΔT J = T J ( MAX ) – T A ( MAX ) T J ( MAX ) = P D ( MAX ) x θ JA + T A (EQ. 4) Board Layout Recommendations A good PCB layout is important to achieve expected performance. Consideration should be taken when placing the components and routing the trace to minimize the ground impedance and keep the parasitic inductance low. The input and output capacitors should have a good ground connection and be placed as close to the IC as possible. The feedback trace in the adjustable version should be away from other noisy traces. The 14 Ld HTSSOP package uses the copper area on the PCB as a heat-sink. The EPAD of this package must be soldered to the copper plane (GND plane) for effective heat dissipation. Figure 12 shows a curve for θJA of the package for different copper area sizes. θJA (°C/W) 36 34 32 30 28 The ISL80138 output voltage is programmed using an external resistor divider as shown in Figure 11. 26 0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 EPAD-MOUNT COPPER LAND AREA ON PCB, mm2 FIGURE 12. θJA vs EPAD-MOUNT COPPER LAND AREA ON PCB OUT R1 EN (EQ. 3) To calculate the maximum ambient operating temperature, use the junction-to-ambient thermal resistance (θJA) as shown in Equation 4: Output Voltage Setting CIN 0.1µF (EQ. 2) 38 A minimum 0.1µF ceramic capacitor is recommended at the input for proper operation. For the output, a ceramic capacitor with a capacitance of 10µF is recommended for the ISL80138 to maintain stability. The ground connection of the output capacitor should be routed directly to the GND pin of the device and also placed close to the IC. IN (EQ. 1) COUT 10µF ADJ R2 GND FIGURE 11. OUTPUT VOLTAGE SETTING 7 FN7969.0 January 11, 2012 ISL80138 Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE January 11, 2012 REVISION CHANGE FN7969.0 Initial Release. Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on intersil.com: ISL80138 To report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff FITs are available from our website at http://rel.intersil.com/reports/search.php For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 8 FN7969.0 January 11, 2012 ISL80138 Package Outline Drawing M14.173B 14 LEAD HEAT-SINK THIN SHRINK SMALL OUTLINE PACKAGE (HTSSOP) Rev 1, 1/10 A 1 3 3.10 ±0.10 5.00 ±0.10 8 14 SEE DETAIL "X" 6.40 PIN #1 I.D. MARK 4.40 ±0.10 2 3.00 ±0.10 3 0.20 C B A 1 7 B 0.65 EXPOSED THERMAL PAD 0.15 +0.05/-0.06 BOTTOM VIEW END VIEW TOP VIEW 1.00 REF H 0.05 C 1.20 MAX SEATING PLANE 0.25 +0.05/-0.06 0.10 C 0.10 0.90 +0.15/-0.10 GAUGE PLANE 5 0.25 CBA 0°-8° 0.05 MIN 0.15 MAX SIDE VIEW 0.60 ±0.15 DETAIL "X" (3.10) (1.45) NOTES: 1. Dimension does not include mold flash, protrusions or gate burrs. (5.65) (3.00) Mold flash, protrusions or gate burrs shall not exceed 0.15 per side. 2. Dimension does not include interlead flash or protrusion. Interlead flash or protrusion shall not exceed 0.25 per side. 3. Dimensions are measured at datum plane H. 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Dimension does not include dambar protrusion. Allowable protrusion shall be 0.80mm total in excess of dimension at maximum material condition. (0.65 TYP) (0.35 TYP) TYPICAL RECOMMENDED LAND PATTERN Minimum space between protrusion and adjacent lead is 0.07mm. 6. Dimension in ( ) are for reference only. 7. Conforms to JEDEC MO-153, variation ABT-1. 9 FN7969.0 January 11, 2012