Version 1.0 , September 2001 Design Note DN-SMPS Singlestage CoolSET Design of 30W Off-Line SMPS using CoolSET ICE2B265 Authors: Yew Ming Lik Junyang Luo Meng Kiat Jeoh Published by Infineon Technologies AG http://www.infineon.com Power Management & Supply N e v e r s t o p t h i n k i n g Design of 30W Off-Line SMPS using CoolSET ICE2B265 Contents: 1. INTRODUCTION .................................................................................................................................3 2. BLOCK DIAGRAM ..............................................................................................................................3 3. POWER MANAGEMENT......................................................................................................................4 4. START-UP DELAY ..............................................................................................................................4 5. IMPROVED CURRENT MODE..............................................................................................................5 6. SOFT-START .....................................................................................................................................6 7. OSCILLATOR AND FREQUENCY REDUCTION......................................................................................7 8. CURRENT LIMITING ..........................................................................................................................8 9. LEADING EDGE BLANKING ...............................................................................................................8 10. PROPAGATION DELAY COMPENSATION .......................................................................................8 11. PROTECTION UNIT ..........................................................................................................................9 12. OVERLOAD + OPEN LOOP WITH NORMAL LOAD AND AUTO RESTART 13. OVERVOLTAGE DUE TO OPEN LOOP 14. 30W DEMO POWER SUPPLY MODE .............................9 WITH NO LOAD....................................................................10 BOARD .........................................................................................11 15. DESIGN OF THE POWER SUPPLY ....................................................................................................12 15.1. Determine input capacitor C3 and minimum DC input voltage V1MIN ..................................12 15.2 Transformer Calculation .......................................................................................................12 15.3 Current Sense Resistor ..........................................................................................................15 15.4 Soft-start capacitor C7 ...........................................................................................................15 15.5 Capacitor at VCC C6 ...............................................................................................................15 15.6 Start-up Resistor R2 and R3 ...................................................................................................16 15.6 Control Loop Design .............................................................................................................16 16. SUMMARY.....................................................................................................................................18 REFERENCES .......................................................................................................................................20 Page 2 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 Design of 30W Off-Line SMPS using CoolSET ICE2B265 Yew ming lik, Junyang Luo and Meng Kiat Jeoh Infineon Technologies Asia Pacific Pte. Ltd. 168 Kallang Way, Singapore 349253 Email: [email protected], [email protected], [email protected] 1. Introduction The CoolSET ICE2B265 is an integrated pulse width modulator with built in CoolMOS. It is an inexpensive controller combined with the CoolMOS power switch with which designers can obtain all the stringent requirements imposed on the present modern Switched Mode Power Supply (SMPS) like very low standby power, few external components count and minimized PCB size. This application note provides beside functional description of the ICE2B265, it presents also the design of simple low cost and high efficient 30W Flyback SMPS circuit. 2. Block Diagram Fig.1. Block diagram of ICE2B265P The control section of the CoolSET provides several special enhancements to satisfy the needs for low power standby and protection features. It consists of 5 main units, the Power Management, the Softstart, the Improved Current Mode, the Current Limiting, the Standby and the Protection Unit. The Standby Unit enables the frequency reduction to lower the power consumption in standby mode. The Page 3 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 frequency reduction is limited to 21kHz to avoid audible noise. In case of failure modes like open loop, overvoltage or overload due to short circuit the device switches into Auto Restart Mode, which is control by the Protection Unit. With the patented Propagation Delay Compensation circuit integrated in the Current Limiting Unit, the peak current limitation can be controlled precisely. It leads to more cost efficient dimension of the transformer and the secondary diode. 3. Power Management G then ready to shut down the gate drive if the Protection Unit is activated. The soft-start transistor switch T1 is released by the Power-Down Reset. The current through RSOFT-START starts to charge the external soft-start capacitor CSOFT-START. The soft-start is then activated. To avoid uncontrolled ringing at switch-on a hystersis at the Undervoltage Lockout is implemented which means that switch-off is only after active mode when VCC falls below 8.5V. When VCC falls below the off-threshold VCCOFF=8.5V the internal reference is switched off and the Power Down Reset let the transistor switch T1 to discharge the soft-start capacitor CSOFT-START. Thus it is ensured that the soft-start is always activated at every switch-on. 4. Start-up delay During startup, CVCC is charged by the current through RSTART-UP. The IC is activated only when the VCC reaches the on-threshold of VCCON=13.5V. Because of the very low IC current consumption before activation, high value startup resistor can be used to minimize power loss in start-up resistor. The value of RSTART-UP and CVCC will effect the startup delay time, which can be estimated by using equation as follow: Fig.2. Power Management Unit Fig.2 shows the Power Management Unit of the IC. The external supply voltage VCC is monitored by the Undervoltage Lockout. The external capacitor CVCC is charged up by the current through the RSTART-UP, when the SMPS is plugged to the main line. The IC remains inactive before VVCC reaches the on-threshold VCCON=13.5V. The current consumption of the IC at this moment is max. 55uA. When the on-threshold is exceeded, the IC is activated: G G The internal bandgap generates a reference voltage VREF=6.5V to supply the internal circuit. The internal Error-latch in the protection unit is reset by the Power Up Reset. The Error-latch flip-flop is t delay = C VCC × VCCON V1IN − I VCC1 (1) R START −UP tdelay is the duration of the startup time from the moment the SMPS is plugged to the main line until the IC is activated. V1IN is the rectified line input voltage and IVCC1 is the current consumption of the IC before activation. Fig.3 shows the tstart delay of the actual SMPS with RSTART-UP = 2 x 470kΩ, CVCC=47µF and V1IN =380V. (1) indicates that the start-up delay time depends not only on the main input voltage but also mainly on the value of RSTART-UP and CVCC. The tdelay can be shorten by reducing the RSTART-UP value. However, the loss at RSTART-UP will increase. It has to be compromised between shorter startup delay time and loss at startup resistor. Page 4 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 Startup circuit with transistor switch can be implemented to achieve startup without losses and constant shorter delay time. RSTART-UP = 1.5M CVCC = 47uF P= 1 × L × f × i P2 2 (2) Where P is the power stored in the primary inductor, L is the primary inductor, f is the swiching frequency and IP is the peak primary current. V1IN = 380V As can be seen, the line-input voltage does not appear in (2). One of the advantages of the Current Mode is that the line variation does not influence the regulation of the output voltage. However, the Current Mode is extremely susceptible to noise on the sense voltage. A noise spike is generated each time the power Mosfet switch is turned on which might turn off the driver immediately especially when the power is small and the FB signal is low. 13.5V VCC tdelay = 3s Fig.3. Start-up delay time. 5. Improved Current Mode In Current Mode the primary current is sensed by the sense resistor RCS (Fig. 4). The sense voltage VCS is amplified 3.65 times for comparison with FB signal by the PWM Comparator. The current flow is terminated by resetting the PWM-Latch, when the sense voltage reaches the level of the FB signal, which is the program level of the output control loop. To improve the Current Mode during light load, a voltage ramp is implemented in the IC. V1in To Soft-Start Comparator PWM Latch FB S PWM Comparator To Soft-Start Comparator FB Gate Driver L1 S PWM Comparator 0.3V Drain Q Gate Driver 5 CoolMOS C5 0.3V Osci R Q 2 Drain Q V1in PWM Latch L1 R Q 2 R1 10k V1 0.8V Ip x 3.65 Vcs 5 CoolMOS T2 3 C1 20pF Isense Rcs C5 x 3.65 Ip Fig.5. Improved Current Mode Vcs 3 Isense Rcs Fig.4. Current Mode Control The amplified current sense voltage vCS is superimposed on the voltage ramp, which is built by the switch T2, the voltage source st V1 and 1 order low pass filter composed of R1 and C1 (see Fig.5). Thus, the turn-on time of the power MOSFET as well as the peak primary current is well defined by the level of the FB signal. For flyback converter with discontinuous current operation the power stored in the primary inductor is represented by the equation Fig.6. Normal Load Condition Page 5 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 T = 10us Vosc tonmax ton Amplified Vcs on voltage ramp FB Driver. The Gate Driver is turned on only when the Voltage Ramp exceeds 0.3V due to the Comparator C5. The turn-on time can then be continuously reduced to zero by decreasing VFB below that threshold. 6. Soft-Start Voltage ramp 0.8V 0.3V V1in 6.5V Soft-Start Comparator Rsofts Gate Driver SoftS Vsofts L1 1 Fig.6 shows the effect of the Voltage Ramp in normal load condition. The switch T2 is opened at the falling slope of the oscillator. It enables the Voltage Ramp to rise. The Gate Driver turns on the power MOSFET when the Voltage Ramp reaches 0.3V. The primary current starts to flow and is sensed by RCS. The current sense voltage VCS is amplified 3.65 times by the PWM OP, which is then superimposed on the Voltage Ramp. The current flow is terminated when the amplified sense voltage on the Voltage Ramp reaches the FB voltage level. In case of light load (see Fig.7) or no load, the current sense voltage VCS is so small that only the Voltage Ramp remains as a well defined signal for the comparison with the FB-signal. T = 50us Vosc tonmax Voltage ramp 0.8V FB 0.3V ton Gate Driver Fig.7. Light Load Conditions T1 From Power Down Reset PWM Latch S Q R Q 5.6V Csofts 5 Drain Gate Driver CoolMOS PWM Comparator Ip Vcs 2 FB 3 Voltage Ramp and Amplified Vcs Isense Rcs Fig.8. Soft-Start The Soft-Start voltage VSOFTS is generated by charging the external capacitor CSOFTS through the internal pullup resistor RSOFTS (see Fig.8). The Soft-Start comparator compares the Soft-Start voltage VSOFTS at the negative input with the ramp voltage of the superimposed Voltage Ramp at the positive input. In Soft-Start phase VSOFTS is always smaller than the Feedback Voltage VFB. In this case VSOFTS defines the pulse width of the Gate Driver through the SoftStart Comparator by resetting the PWMLatch. The Soft-Start phase is completed when VSOFTS reaches 5.3V (Fig.9). The Soft-Start time is then defined by TSOFT −START = 1.69 × R SOFTS × C SOFTS (3) The transistor switch T1 at Soft-Start is controlled by the Power Down Reset. It is to ensure that the Soft-Start is always activated at the restart of the IC after power down or in Auto Restart mode. The slope of the Voltage Ramp then controls the turn-on time of the Gate Page 6 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 loop to pull down the level of the feedback signal VFB below 4.8V (see Fig.11). Vsofts 5.6V 5.3V Tsoft-start t Gate Driver t Fig.9. Soft-Start Phase The Soft-Start voltage VSOFTS is used not only for minimization of current and voltage stresses on the external power MOSFET switch during start-up, it is also used for activation of the Protection Unit (Fig.10). Fig.11. Start-up Phase 7. Oscillator and Frequency Reduction V1in 6.5V Power Up Reset Rsofts SoftS 1 L1 Error Latch C4 R Q S Q R Q Drain 5 5.3V 5.6V Csofts Rfb 2 MOSFET G2 6.5V FB Gate Driver C3 S Q Ip PWM Latch Vcs 4.8V Clock 3 Isense Rcs Fig.10. Activation of Protection Unit When the Soft-Start phase is over (VSOFTS > 5.3V), the Error Latch will be activated by Comparator C4 if the feedback voltage VFB does not drop below 4.8V, which means that the output voltage VOUT at the secondary side of the SMPS does not reaches its nominal level. To ensure proper start-up of the SMPS, the duration of the Soft-Start phase has to be long enough to enable VOUT to rise to its nominal value. This will cause the control The oscillator, which generates the switching frequency F=67kHz, is integrated in the IC. The oscillator is adjusted so that the Gate driver pulse can reach a maximum duty cycle of DMAX = 0.72. The frequency of the oscillator can be influenced by the feedback voltage VFB as shown in Fig.12. This feature allows a SMPS to operate at lower frequency at light loads thus lowering the switching losses while maintaining good cross regulation performance and low output ripple. The power consumption of the whole SMPS can be reduced very effectively at light load. The minimal reachable frequency is limited to 20kHz to avoid audible noise in any case. f VFB Fig.12. Frequency Reduction vs VFB Page 7 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 8. Current Limiting V1in Clock PWM Comparator PWM Latch S Q R Q Drain 5 Gate Driver CoolMOS Propagation Delay Compensation Vcsth Current Limit Comparator L1 Leading Edge Blanking 200ns 10. Propagation Delay Compensation Ip 10k Vcs 3 D1 primary-side capacitance and secondaryside rectifier reverse recovery time (Fig. 14). This spike causes a premature turnoff of the Gate Driver if it exceeds the threshold voltage VCSTH. To avoid it, the spike is blanked out with a time constant of tLEB = 220ns. During the blanking time the Gate Driver can not be switched off by the Current Limit Comparator. Isense Rcs Fig.13. Current Limiting The cycle by cycle current limiting is performed by the Current Limit Comparator (see Fig.13). The primary current IP is converted into a sense voltage VCS by an external sense resistor RCS. The sense voltage VCS goes through the 200ns Leading Edge Blanking before reaching the Current Limit Comparator. When VCS exceeds the internal threshold voltage VCSTH, the Current Limit Comparator immediately turns off the Gate Driver via the PWM Latch. A Propagation Delay Compensation is added to the Current Limiting circuit to avoid excessive overshoot of the primary current, especially at the high line voltage (refer to chapter 10 Propagation Delay Compensation). In case of overcurrent detection, that is when the sense voltage VCS reaches the threshold voltage of the Current Limit Comparator VCSTH, the shut down of the internal CoolMOS is delayed due to the propagation delay of the circuit between the current sense input ISENSE and the Gate Driver output. This delay causes an overshoot of the peak primary current IPPEAK. The overshoot is serious particularly at high input line voltage. Fig.15 shows an example of different current overshoots at two different line voltages. The example assumes that the primary inductance is 500µH, the current sense resistor RSENSE=1Ω, the propagation delay time tPROP DELAY=200ns and the input line voltages after rectification are V1IN1= 100V and V1IN2 =370V. V1IN1 = 100V V1IN2 = 375V Vcs, Ip 1V L = 500uH, Rcs = 1 Ohm dI1p/dt = V1N1/L = 0.2A/us dI1p/dt = V1N2/L = 0.75A/us IOVERSHOOT2 IOVERSHOOT1 1.04A dI1p/dt = 0.2A/us 1.15A 1A VCSTH = IPLIMIT dI1p/dt = 0.75A/us 9. Leading Edge Blanking 1us tdelay tdelay 0.2V 5us 10us 15us Fig.15. Current overshoot Fig.14. Leading Edge Blanking Each time when the CoolMOS is switched on a leading spike is generated due to the The result of the example obviously shows that if the current sense threshold VCSTH is set at a constant level VCSTH = 1V, the current overshoot IOVERSHOOT2 at high line input voltage of VIN2 = 375V and at tDELAY = 200ns is 15% higher than the actual current limit IPLIMIT. Page 8 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 The Propagation Delay Compensation which is done by means of a dynamic volatge threhold VCSTH as shown in Fig.16 is integrated in the IC to minimize the overshoot. VOSC Tsw ton,max ton Vcs, Ip dI1p/dt = 0.75A/us dI1p/dt = 0.2A/us VCSTH = IPLIMIT 1V, 1A 11. Protection Unit An overload, open loop, overvoltage detection and a thermal shutdown are integrated within the Protection Unit (see Fig.1, Block Diagram). If the Protection Unit is activated, the Error Latch is set that disables the external power MOSFET after a blanking time of 5µs. The blanking is used to avoid mistriggering of the Error Latch by voltage spikes during normal operation mode. VCSTH dynamic tdelay 0.2V 1us tdelay 5us 10us 15us 12. Overload + Open Loop with normal load and Auto Restart Mode Fig.16. Dynamic Voltage Threshold VCSTH At high line input voltage, when the slope of the current sense voltage VCS is steeper, the Gate Driver is switched off earlier due to the lower VCSTH. The effect of the overshoot is then compensated. The Propagation Delay Compensation in the IC is designed so that the tolerance of the internal current limiting is at +/- 5%. The propagation delay time is compensated over temperature within a range of at least dIP dV ≤ 1 CS (4) dt dt In this way, the IC is able to accurately limit the overcurrent (see Fig.17). 0 ≤ R CS × Without compensation With compensation VCS 1.3V Fig.18. Auto Restart Mode 1.2V 1.1V 1.05V +/- 5% Tolerance 1V 0.95V 0.9V 0.2 0.6 1.0 1.4 1.8 Fig.17. Overcurrent Shutdown dVcs/dt [ V/us ] Fig.18 shows the Auto Restart Mode in case of overload or open loop with normal load. The detection of open loop or overload is provided by the Comparator C3, C4 and the AND-gate G2 (see Fig.19). During operation at normal load the supply voltage of the IC VCC is in the range of Page 9 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 8.5V and 13.5V, the Soft-Start voltage VSOFTS is above 5.3V and the V1in 6.5V SoftS 1 Rsofts Power Up Reset Vsofts Error Latch T1 C4 R Q S Q L1 5 CoolMOS 5.6V G2 6.5V R Rfb FB Q Gate Driver Ip Vcs 2 13. Overvoltage due to open loop with no load Drain 5.3V Csofts the Soft-Start Phase, the Error Latch is activated and the SMPS goes into Auto Restart Mode again. C3 S 4.8V Clock Q 3 Isense PWM Latch Rcs Fig.19. FB-Detection feedback voltage VFB stays lower than 4.8V. At this time the Comparator C4 has released one of the input of the AND-gate G2. The comparator C3 is now able to set the Error-Latch in case of open loop or overload, which leads the feedback voltage VFB to rise above 4.8V. 5µs after the VFB reaches the threshold voltage of 4.8V, the Gate Driver is terminated. The SMPS stops to operate which causes the supply voltage of the IC VCC to drop. The IC is turned off when VCC falls to VCCoff = 8.5V. At this time the external soft-start capacitor CSOFTS is discharged by the internal switch T1 due to the Power Down Reset and the consumption current of the IC is reduced to maximum 55µA. The SMPS then goes into Auto Restart Mode. The VCC increases again by charging the capacitor CVCC through the Start-up Resistor RSTART-UP during the IC is inactive. When it reaches the turn-on threshold VCCon =13.5V, the IC is turned on again. The Error Latch is then reset by the Power Up Reset and the internal pull-up resistor RSOFTS starts to charge the external SoftStart capacitor CSOFTS to start the SoftStart Phase. During Soft-Start Phase the detection of overload and open loop by C3 and G2 is disabled by the Comparator C4.. The Soft-Start Phase ends with the SoftStart voltage VSOFTS ≥ 5.3V. If the overload or open loop failure is not removed after 16.5 Fig.20. Auto Restart Mode Fig.20 shows the Auto Restart Mode for open loop and no load condition. In case of this failure mode the SMPS output voltage as well as the VCC increases. Additional comparators C1, C2 and the AND-gate G1 are implemented to detect this failure mode (see Fig.21). V1in 6.5V SoftS 1 Rsofts Power Up Reset Vsofts Error Latch T1 C4 R Q S Q L1 Drain 5.3V 5.6V Csofts 5 CoolMOS G2 R Vcc 7 C1 Q Gate Driver Ip Vcs S 16.5V Clock Q PWM Latch 3 Isense Rcs Fig.21. Overvoltage Detection Page 10 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 The overvotage detection is provided by Comparator C1 only when the Soft-Start voltage VSOFTS is below the threshold of the Comparator C2 at 4.0V and the voltage at pin FB is above 4.8V. During this overvoltage detection phase Comparator C1 can set the Error Latch and terminates the Burst Phase earlier during Auto Restart Mode when VCC exceeds 16.5V. Once the Soft-Start phase is over, which means that the VSOFTS is above 4.0V, the overvoltage detection by C1 is disabled. This will enable the VCC to vary in the range of 8.5V to 21V caused by output load changes at normal operating mode. The specification of the circuits: Input voltage range 85 – 265 VAC 50/60Hz Output 18V/1.67A Maximum output power 14. 30W Demo Power Supply Board POMAX =30W Input power at standby mode PIN ≤ 0.5W at PO = 0W and VIN = 240Vac Fig.22 shows a very simple and low cost 30W switching power supply circuitry utilizing the ICE2B265P. It is designed for used as the power supply of a Digital Photo Printer. Efficiency η ≥ 80% CY1 2.2nF/250V C4 10nF C3 68uF/400V BR1 RS406 D1 MUR520 R1 68k/2W C14 220uF 25V L1 1.5uH 18V/1.67A Vo1 R3 470k/0.5W D2 UF4001 R2 470k/0.5W RT1 NTC C12 1000uF 25V D3 1N4148 GND C2 0.1u/275V C8 0.1u C13 1000uF 25V R5 10 C6 47u/25V EMI1 EV28-3.0 VCC 1 VAR1 EF25/N67 TR1 6 7 C1 0.1u/275V IC3 NC 5 ICE2B265 DRAIN SOFTST GND FB 8 2 ISENSE C11 220pF/1kV 4 R6 1k 3 R4 22 C7 1uF C5 2.2nF R9 24k C10 47nF F1 2A L2 N1 85V - 265V C9 120pF IC1 SFH617-2 R14 0.47 IC2 TL431 R8 220k R11 3.9k Fig.22. 30W SMPS Demoboard using CoolSET ICE2B265 011005 - M.K.Jeoh Page 11 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 15. Design of the Power Supply 15.1. Determine input capacitor C3 and minimum DC input voltage V1MIN Assuming that the conduction time of the bridge rectifier diodes is about 3 ms and substitute the specified values in (5), (6) and (7), we obtain: To choose the value of the input capacitor C5 the following rule of thumb is applied: V ACMIN,PK = 85 V × 2 = 120 V (8) 30 W 20ms ×( − 3ms) 0 .8 2 = 0.26 Ws (9) C5 = 2 to 3 µF per W for 100/115VAC or universal input. WIN = WIN C5 = 1µF per Watt for 230VAC. C5 = 68uF is selected for this design. The minimum DC input voltage V1MIN (see Fig.24) at the lowest line voltage of 85V is a very important parameter for the calculation of the transformer. It can be obtained with good approximation by the following equations: V1MIN = 2 VACMIN ,PK (5) V ACMIN,PK = V ACMIN × 2 (6) The discharged energy W IN is equivalent to the required peak output power POPK for the duration of the discharge time TL/2 – tC. POPK TL ×( − tC ) η 2 (7) (10) V1MIN = 82 V Taking the voltage drop at the bridge rectifier into consideration, the V1MIN should then be: 15.2 Transformer Calculation 15.2.1. Maximum Duty Cycle The transformer is designed so that the SMPS is operated in discontinuous current mode for the whole operating range. The maximum duty cycle dMAX at minimum input voltage V1MIN is chosen as dMAX = 0.5 (11) 15.2.2 Reflected Output Voltage The reflected output voltage VR is the reflected value of the secondary voltage across the primary winding. It can be obtained by the equation 1/TL = FL = AC Line Frequency tC = Conduction Angle of the Bridge Diode Po = Output Power n = efficiency VR = TL tC 2 × 0.26 Ws 68uF V1MIN = 80V. 2 × WIN − C5 VACMIN,PK is the minimum peak input voltage, whereas W IN is the energy which is discharged out of C5. WIN = V1MIN = (120 V )2 − VACMIN,PK L V1MIN d MAX × (V1MIN − VDS ) 1 − d MAX (12) The Drain-Source voltage VDS of the internal CoolMOS is negligible due to the smaller RDSON. VR is then: VR = 0. 5 × 80 V = 80 V 1 − 0 .5 (13) Fig.23 Input Voltage Ripple Page 12 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 15.2.3 Maximum Primary Peak and RMS Current N67 Core loss vs frequency), BMAX = 0.2T is chosen for the calculation of the number of primary turns N1. The maximum primary peak current I1PKMAX is propotional to the maximum output power. It can be derived as follow: I1PKMAX = 2 × POMAX η × V1MIN × dMAX (14) Substitute the known values of POMAX, V1MIN, dMAX and the efficiency η into (14), I1PK becomes: I1PKMAX = 2 × 30 W = 1.875 A 0.8 × 80 V × 0.5 (15) The maximum primary RMS current can be calculated from I1PK,MAX and dMAX: L 1 × I1PK,MAX N1 = (20) B MAX × A MIN AMIN is the minimum cross sectional area 2 of the core. For EF25, AMIN = 51.5mm . N1 = 320 × 2 ≈ 60 0.2 × 51.5 (21) The required core gap LGAP to achieve the primary inductance L1 with the number of primary turns N1 can be calculated by using the equation given in Epcos data book for “Ferrites and Accessories” 1 I1RMS,MAX = I1PK ,MAX I1RMS,MAX = 1.875 A d MAX 3 0 .5 = 0.77 A 3 (16) (17) 15.2.4 Primary Inductance L1 Primary inductance can be determined by the energy equation of the flyback transformer defined below: L1 = η I12PK ,MAX f 0.8 × 1.8752 A × 67kHz (22) K1 and K2 are the core-specific constants. For EF25, K1=90, K2=-0.731 are specified 2 in the datasheet. In the calculation L1/N1 has to be in the dimension of nH. The needed core air gap is then 1 æ 320 × 103 ö −0.731 ÷ =ç mm ç 602 × 90 ÷ è ø = 1.02mm LGAP (23) (18) f is the switching frequency of the SMPS which is around 67kHz. L1 = LGAP LGAP 2 POMAX 2 × 30 W æ L ö K2 =ç 2 1 ÷ ç N × K1 ÷ è 1 ø ≈ 320µH (19) 15.2.5 Number of Primary turns For this design, core size of EF25 is recommended due to its low cost and easy availability. For 67kHz operation, Epcos N67 material is a good choice. In the discontinuous current mode operation, at switching frequency of 67kHz, the maximum flux density in the core BMAX is usually limited by the core loss. To keep the loss in the core at acceptable level (see Epcos datasheet, 15.2.6 Number of Secondary Turn The number of turn for the secondary output can be derived from the reflected output voltage VR in (13) and the number of primary turns N1. During the flyback time all windings will have the same volt per turn VT: VT = VR 80 V V = = 1.33 N1 60 turns turn (24) The number of turns NO1 for 18V-output VO1 is then: N O1 = VO1 + VD VT Page 13 of 22 (25) DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 VD is the output diode forward voltage drop, which is typically about 1V. 18 + 1 ≈ 14 NO1 = 1.33 (26) The bias voltage for the VCC should be around 15V. The number of turn for the bias winding is then: NBIAS V + VD 16 = BIAS = ≈ 12 VT 1.33 (27) To select the proper output rectifier diode, the maximum peak inverse voltage across the diode VD1,PK has to be defined. VD1,PK can be obtained by the equation defined below: VD1,PK The reverse voltage rating of the selected diode VDR should be greater than 1.25x VDPK and the rated DC current has to be at least 3 times the maximum output current. MUR520 is chosen for used in this design. 15.2.8 Maximum Secondary Peak and RMS Current The maximum secondary peak and RMS currents are propotional to the maximum DC output current as follows: 2 I OMAX 1 − d MAX I ORMS,MAX = I OPK ,MAX × (29) 1 − d MAX 3 18V/1.67A IO1PK,MAX 6.68A Max. RMS Current = IO1RMS,MAX = 2.73A Table 1. Max. Peak and RMS Output Current Output capacitor selection is dominated by the RESR (equivalent series resistance) and the ripple current rating of the capacitor. The ripple current, which flows through the output capacitor, can be calculated as follows: I O,RIPPLE = I 2ORMS,MAX − I 2OMAX (31) The ripple current in the output capacitor of the 18V/1.67A will then be: IO1,RIPPLE = 2.732 − 1.672 A 14 = 18 V + ( × 375 V ) 60 = 105.5 V I OPK ,MAX = Max. Peak Current the (28) whereas V1MAX is the maximum DC input voltage. The calculation result is: VD1,PK Secondary Output of 15.2.9. Output Capacitors 15.2.7 Output Rectifier Diodes æN ö VD1,PK = VO1 + çç O1 × V1MAX ÷÷ N è 1 ø output current. The results calculation is listed in Table 1. (30) I01,RIPPLE = 2.16 A (32) The Epcos datasheet of her B41858series aluminum electrolytic capacitor shows that the rms current rating of a 1000µF/25V capacitor at 100kHz switching O frequency and 105 C ambient is 1.69A. 2 pieces of this capactors (Fig.22) have to be used to accommodate the required ripple current of VO1. The RESR of these capacitors are specified as 0.034Ω. The output ripple voltage caused by the parallel of these two RESR, which is RESRTOT = 0.017Ω, is then: VO1,RP = IO1PK,MAX × RESRTOT VO1,RP = 6.68 A × 0.017Ω = 0.11V (36) This switching ripple voltage is further reduced by the additional L-C filter (L3 and C14 in Fig.22). The 220µF/25V with RESR = 0.12Ω is chosen for C14. To eliminate the pole in the control loop caused by the L1C14 filter, L1 has to be around 1.5µH. With this L1-C14 values combination, VO1,RP is reduced to: IOMAX is the maximum DC output current, IOPK,MAX is the maximum peak output current and IORMS,MAX is the maximum RMS Page 14 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 VO' 1,RP = VO1,RP × = 0.11× RESR 2 π f L 4 + RESR 0.12 2 π 67 × 1.5 × 10 −3 + 0.12 PO' 1 = 0.8 × (34) V ≈ 18mV The switching ripple voltage V’O1,RP appears at the output terminal has been attenuated to around 18mV. 2 1 æ 0.95 ö × 320 × 67 × 10 −3 × ç ÷ W 2 è 0.45 ø P’O1 = 38.2W Assuming that the charge-up power to the C’O1 rises linearly during the soft-start phase, the charge power is then only half of 38.2W. TSTART-UP, which is needed to raise the voltage VO1 to 18V, can then be estimated: 15.3 Current Sense Resistor The current sense resistor (R14 in Fig.22) is defined by the maximum primary peak current and the minimum threshold voltage of the Current Limiting VCSTHMIN. R14 = VCSTHMIN 0.95 V = ≈ 0.45Ω I1PK,MAX 2A (35) Since the maximum loss occurred in R14 can be: PR14MAX = I12RMS,MAX R14 (36) PR14MAX = 0.765 2 × 0.45 W = 0.26 W a 1W low inductance recommended. resistor is As mentioned in chapter 6 “Soft-Start” on page 4 and 5, the duration of the soft-start phase TSOFT-START has to be long enough to ensure proper start-up of the SMPS. That means VO1 has to be at 18V before VSOFTS reaches 5.3V (see Fig.11 on page 5, TSOFTSTART > TSTART-UP). To estimate the TSTART-UP, the available power during the soft-start phase, which charges the output capacitors, has to be defined. The total value of all capacitors at the output is: C'O1 = C12 + C13 + C14 = 2220µF (37) In case of hard-start (if soft-start does not exists), the power which will charge C’O1 is: æV ö 1 × L1 × f × çç CSTHMIN ÷÷ 2 è R14 ø 1 VO2 1 × C'O1 x 2 0.5 PO' 1 (39) TSTART −UP = 182 × 2220 µs ≈ 18.8ms 38.2 In the application circuit of Fig.22, the external soft-start capacitor C7 = 1µF is recommended. The internal soft-start resistor RSOFTS = 50kΩ is specified on the datasheet of the IC. The soft-start time TSOFT-START can then be calculated using (3): TSOFT − START = 1.69 × 50 × 1 ms = 84.5ms (40) In this case, TSOFT-START >TSTART-UP and the start-up of the SMPS is secured. 15.4 Soft-start capacitor C7 PO' 1 = η × TSTART −UP = 2 (38) 15.5 Capacitor at VCC C6 The VCC capacitor C6 (CVCC in Fig.22) needs to ensure the power supply of the IC until the power can be provided by the auxiliary bias winding. Regardless the current transfer from the start-up resistor R1 and the auxiliary winding during startup time TSTART-UP, the capacitance value C6 can be estimated as below: C6 = I VCC3 TSTART −UP VCCHY (41) IVCC3 is the IC supply current with active gate-drive. Its maximum value is 8mA as specified on the datasheet. VCCHY = 5V is the turn-on/off hysteresis of the IC supply voltage VCC. Based on the estimated value of TSTART-UP in (39), C6 should then be: C6 = 8mA × 18.8ms ≈ 30µF 5V Page 15 of 22 (42) DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 C6 = 47µF is selected to sustain the Vcc. 15.6 Start-up Resistor R2 and R3 The start-up resistor RSTART-UP consists of R2 and R3, which is connected in series as shown in Fig.22. By using (1) on page 2, the longest start-up delay time, which happens at the lowest line- input voltage VACMIN = 85V can be estimated: t START −DELAY = t START −DELAY = C6 VCCON (43) VACMIN 2 − IVCC1 R START −UP 47µF × 13.5 V 85 V 2 − 55µA 2 × 470kΩ (V 2 ACMAX ≈ 8 .7 s ) (44) 2 PST −LOSS 2 × 470kΩ 1 2 × I1 × L1 × f × η 2 (45) PO = ν 2O RO (46) (47) Substitute PO and I1 in (45) with (46) and (47) and rearrange the equation in term of νO/νFB, we obtain 2 R START −UP (265 V 2 ) = PO = I1 VCSTH = νFB R14 × A ν In worst case, the IC is turned on only in 8.7s after the SMPS is plugged to the main line. The maximum loss occurs in RSTART-UP is roughly: PST −LOSS ≈ Following equations are used to define the DC or low frequency gain of the feedback loop of the power stage (from the control voltage νFB at the feedback-input pin2 to the output voltage node νO): ≈ 0.15 W GPS = νO VCSTH ηL1R O f = × 2 νFB R14 × A ν Aν is the PWM-OP gain, which is equal to 3.65 as specified in the datasheet of ICE2B265. Equation (48) shows that the DC or low frequency gain GPS of the power stage is proportional to the square root of the output load RO and independent of the input voltage variation due to the current mode control. For ROMIN = 10.8Ω (at POMAX = 30W), the minimum gain is 15.6 Control Loop Design GPS,MIN = 14.9 dB. Fig. 24 shows the essential elements of the control loop. V1 L1 Co 7 Vo C14 Ro Resr NC 5 ICE2B265 DRAIN SOFTST GND FB 8 2 ISENSE R14esr I1 0.95 × 0.45 × 3.65 GPS,MAX = 43 GPS,MAX = 0.8 × 320 × 648 × 67 × 10 −3 2 GPS,MAX = 32.7 dB C9 R9 4 C10 3 R14 (49) In case of POMIN = 0.5W, the output load will be ROMAX = 648Ω, the maximum power stage gain will then be 6 VCC 1 0.8 × 320 × 10.8 × 67 × 10 −3 2 0.95 × 0.45 × 3.65 GPS,MIN = 5.6 GPS,MIN = 15.6.1 Power Stage Transfer Function R8 VFB (48) (50) The small signal transfer function of the power stage with its pole and ESR-zero is shown below: Vref EA + Opto Fig.24 The closed Feedback Loop é ù ê 1 + sRESR CO ú GPS (s ) = GPS × ê ú ê 1 + s R O CO ú 2 ëê ûú Page 16 of 22 (51) DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 Co consists of C12 and C13 ( see Fig.22) with the total value of 2000µF and RESR is the ESR values (see page 12) of both capacitor in parallel, Thus RESR = 0.017Ω. The poles and zero at minimum and at maximun power are listed in Table 2 below: Output Power Poles πROCO Fp = 1/π Zeros πRESRCo FZ = 1/2π POMAX = 30W Ω RO = 10.8Ω FPH = 14.7Hz FZ = 4.68kHz POMIN = 0.5W Ω RO = 648Ω FPL = 0.24Hz FZ = 4.68kHz Table 2. Poles and zero The transfer function of the output filter L1C14 can be expressed as follows: 1+ GLC = 1 sC14R14ESR æ L1 1 − 1 + sç ç R14ESR ω2C R 14 14ESR è ö ÷ ÷ ø 1 2π L1C14 (54) = 8.6kHz L1 = 1.55µ µH With this combination of L1 and C14, the influence of the filter on the contol loop can thus be neglected; the small signal transfer function of the power stage is then dominated only by (51). The open loop gain and phase responses of the transfer function for the minimum and maximum output power are shown in Fig.26 and in Fig.27. To close the loop, the feedback loop circuitry as shown in Fig.25 is added. It consists of a compensation network (TL431, R6 – R11, C9 and C10) and the optocoupler IC2. (52) vo 6.5V R6 RFB C14 and L1 have to be selected so that the pole of the filter FPLC is located far a way from the crossover frequency FCO to avoid its influence in the control loop. The control loop bandwidth can only be kept high with high FPLC, which is desirable. The L-C filter has a –2 gain slope with rapid changes of phase shift, which could induce instability in the control loop. To prevent it, the pole has to be compensated by the zero as mentioned on page 12. Based on this consideration, Epcos Alcapacitor B41858-series of C14 = 220µF/35V with R14ESR = 0.084Ω is selected. The zero frequency is then at: FZ14 = 1 = 8.6kHz 2πR14ESR C14 (53) Set the pole equal to zero and solve for the inductance L1: R6=1kΩ is chosen to limit the maximum current that flows into TL431. In order to achieve larger bandwidth and at the same time to get the overall gain response with –1 slope, the crossover frequency FC = 3kHz is selected. The gain of the power stage at FC and at full load can then be derived from (51) Vfb C9 R9 C10 2 R8 IC2 SFH617-3 IC2 TL431 R11 Fig.25 Feedback Loop Circuitry The transfer function of the feedback loop is ν (s) GCRFB 1 + s(C9 + C10 )R 8 = ⋅ GFB (s) = FB ν O (s) R6 sC10R 9 (1 + sC9R 8 ) (55) , where GC is the current transfer ratio of the optocoupler. For SFH617-3, GC = 100%. The internal pull-up resistor at FB (pin2) is specified as RFB = 3.7kΩ. 2 GPSH ( s) = GPSMIN × Page 17 of 22 æF ö 1 + çç C ÷÷ è FZ ø æF ö 1 + çç C ÷÷ è FPH ø 2 (56) DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 C9 = 120pF 2 æ 3kHz ö 1+ ç ÷ è 4.68kHz ø = 0.03 GPSH (s) = 5.2 × 2 æ 3kHz ö 1+ ç ÷ è 14.7Hz ø C10 = 47nF FZFB = 15.4Hz, FPFB = 6kHz GPSH (FC ) = −30.4dB The feedback loop gain with TL431 has to be 30.4dB at FC and must have zero slop response. For further calculation, R9 has to be defined first. R11 determines the bias current of the resistor divider R9 – R11. If R11 = 3.9kΩ is selected, R9 can be calculated by æ V ö R 9 = R11çç O − 1÷÷ è VREF ø (57) æ 18 ö R 9 = 3.9kΩ × ç − 1÷ = 24kΩ . è 2 .5 ø VREF is the reference voltage of TL431. To calculate the feedback loop gain at FC, (55) can be simplified as below: GFB (FC ) = GCRFB R 8 R6 R 9 Fig.26 and Fig.28 also illustrate the responses of the feedback loop circuitry and the total open loop, whereas Fig.27 and Fig.29 show its respective phase responses. 16. Summary This application note introduced briefly the TM features and functions of the CoolSET , the new integrated product that includes TM PWM control IC and the CoolMOS , the new generation Power MOSFET. A low cost 30W SMPS demo-board circuit is developed and its operation is analyzed is detail. The detail explanation of the board and the experiment results are described in the application note “30W Off-line TM SMPS Demoboard using CoolSET ICE2B265”. (58) Since [GFB(FC)] = 30.4dB, R 8 = R 9 × 10 30.4 20 × R6 ≈ 200kΩ GCRFB (59) C9 is obtained by placing the pole at FPFB = 2 x F C. C9 = 1 = 133pF 2πR 8 FPFB (60) In order to have sufficient phase margin, especially at light load, the zero is placed at FZFB = 20Hz. The value of C10 is then C10 = 1 − C9 = 39nH 2πR 8FZFB (61) Based on above calculation, the values of the feedback network components are selected as follows: R8 = 220kΩ Ω Ω R9 = 24kΩ Page 18 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 60 Feedback loop 40 Gpsh ( f ) 20 Gfb ( f ) Power stage 0 Overall open loop G( f) 20 Fig.26 Gain response at POMAX 40 60 1 10 100 1 10 f 3 1 10 4 1 10 5 90 Feedback loop 45 qpsh ( f ) Overall open loop qfb ( f ) 0 qtotal ( f ) 45 Fig.27 Phase response at POMAX Power stage 90 1 10 100 f 1 10 3 4 1 10 5 1 10 60 Feedback loop 40 Gpsl ( f ) Gfb ( f ) Power stage 20 Overall open loop 0 G( f) 20 Fig.28 Gain response at POMIN 40 60 1 10 100 f 1 10 3 1 10 4 1 10 5 90 Feedback loop 45 qpsl ( f ) qfb ( f ) Overall open loop 0 qtotal ( f ) 45 Fig.29 Phase response at POMIN Power stage 90 1 10 100 f 1 10 3 Page 19 of 22 1 10 4 1 10 5 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 References TM 1. Harald Zoellinger and Rainer Kling, “CoolSET ICE2AXXX for Off-line Switch Mode Power Supply”, Infineon Technologies Application Note, AN-SMPS-ICE2AXXX-1, version 1.0, January 2001. TM 2. Infineon Technologies, “CoolSET -II Off-Line SMPS Current Mode Controller with TM 650V/800V CoolMOS on Board, Infineon Technologies Datasheet, version 2.2, February 2001. Revision History Application Note AN-SMPS-ICE2B265-1 Actual Release: V1.0 Date: 25.09.2001 Previous Release: V1.0 Page of Page of Subjects changed since last release actual prev. Rel. Rel. 22 ---------- First Issue Page 20 of 22 DN-SMPS Singlestage Design of 30W Off-Line SMPS using CoolSET ICE2B265 For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see the address list on the last page or our webpage at http://www.infineon.com CoolMOS and CoolSET are trademarks of Infineon Technologies AG. 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