CDP6872 Low Power Crystal Oscillator January 1996 Features Description • Single Supply Operation at 32kHz . . . . . . . 2.0V to 7.0V The CDP6872 is a very low power crystal-controlled oscillators that can be externally programmed to operate between 10kHz and 10MHz. For normal operation it requires only the addition of a crystal. The part exhibits very high stability over a wide operating voltage and temperature range. • Operating Frequency Range. . . . . . . . 10kHz to 10MHz • Supply Current at 32kHz . . . . . . . . . . . . . . . . . . . . . .5µA • Supply Current at 1MHz . . . . . . . . . . . . . . . . . . . .130µA The CDP6872 also features a disable mode that switches the output to a high impedance state. This feature is useful for minimizing power dissipation during standby and when multiple oscillator circuits are employed. • Drives 2 CMOS Loads • Only Requires an External Crystal for Operation Applications Ordering Information • Battery Powered Circuits PART NUMBER • Remote Metering TEMPERATURE RANGE • Embedded Microprocessors PACKAGE CDP6872E -40oC to +85oC 8 Lead Plastic DIP CDP6872M -40oC to +85oC 8 Lead Plastic SOIC (N) CDP6872H -40oC to +85oC DIE • Palm Top/Notebook PC Typical Application Circuit Pinout CDP6872 (PDIP, SOIC) TOP VIEW VDD 0.1µf VDD 1 8 ENABLE OSC IN 2 7 FREQ 2 OSC OUT 3 6 FREQ 1 VSS 4 5 OUTPUT 1 8 2 32.768kHz CRYSTAL 7 CDP6872 3 6 4 5 32.768kHz CLOCK 32.768kHz MICROPOWER CLOCK OSCILLATOR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 1 File Number 4069 CDP6872 Simplified Block Diagram VDD (NOTE 1) 1 8 ENABLE EXTERNAL CRYSTAL OSC IN 2 VDD 3 OSC OUT RF 15pF S1b VDD S1a VDD - 1.4V S1c VDD OUTPUT VRN S2 VDD - 2.2V VDD 15pF LEVEL SHIFTER + S3 VDD - 3.0V 5 BUFFER - VRN S4 VDD - 3.8V 4 BUFFER AMP IBIAS VSS 1 OF 4 DECODE VDD VDD P 6 (NOTE 1) IN FREQ 1 VDD RF (NOTE 1) OUT N P 7 VRN FREQ 2 OSCILLATOR FREQUENCY SELECTION TRUTH TABLE ENABLE FREQ 1 FREQ 2 SWITCH 1 1 1 S1a, b, c 10kHz - 100kHz 1 1 0 S2 100kHz - 1MHz 1 0 1 S3 1MHz - 5MHz 1 0 0 S4 5MHz - 10MHz+ 0 X X X High Impedance NOTE: 1. Logic input pull-up resistors are constant current source of 0.4µA. 2 OUTPUT RANGE Specifications CDP6872 Absolute Maximum Ratings Operating Conditions Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.0V Voltage (any pin). . . . . . . . . . . . . . . . . . . . . . .VSS-0.3V to VDD+0.3V Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC ESD Rating (Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >4000V Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC (SOIC - Lead Tip Only) Operating Temperature (Note 3) . . . . . . . . . . . . . . . . -40oC to +85oC Storage Temperature Range. . . . . . . . . . . . . . . . . . -65oC to +150oC Thermal Information (Typical) Thermal Resistance (oC/W) 8 Lead Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Lead Plastic SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . θJA 125 170 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications VSS = GND, TA = +25oC, Unless Otherwise Specified VDD = 5V VDD = 3V MIN TYP MAX MIN TYP MAX UNITS 2 5 7 - - - V fOSC = 32kHz, EN = 0 Standby - 5.0 9.0 - - - µA fOSC = 32kHz, CL = 10pF (Note 1), EN = 1, Freq1 = 1, Freq2 = 1 - 5.2 10.2 - 3.6 6.1 µA fOSC = 32kHz, CL = 40pF, EN = 1, Freq1 = 1, Freq2 = 1 - 10 15 - 6.5 9 µA fOSC = 1MHz, CL = 10pF (Note 1), EN = 1, Freq1 = 0, Freq2 = 1 - 130 200 - 90 180 µA fOSC = 1MHz, CL = 40pF, EN = 1, Freq1 = 0, Freq2 = 1 - 270 350 - 180 270 µA 4.0 4.9 - - 2.8 - V VOL Output Low Voltage (IOUT = 1mA) - 0.07 0.4 - 0.1 - V IOH Output High Current (VOUT ≥ 4V) - -10 -5 - - - mA IOL Output Low Current (VOUT ≤ 0.4V) 5.0 10.0 - - - - mA (VOUT = 0V, 5V, TA = 25oC, -40oC) - 0.1 - - - - nA (VOUT = 0V, 5V, TA = 85oC) - 10 - - - - nA - 0.4 1.0 - - - µA VIH Input High Voltage Enable, Freq1, Freq2 2.0 - - - - - V VIL Input Low Voltage Enable, Freq1, Freq2 - - 0.8 - - - V Enable Time (CL = 18pF, RL = 1kΩ) - 800 - - - - ns Disable Time (CL = 18pF, RL = 1kΩ) - 90 - - - - ns tR Output Rise Time (10% - 90%, fOSC = 32kHz, CL = 40pF) - 12 25 - 12 - ns tF Output Fall Time (10% - 90%, fOSC = 32kHz, CL = 40pF) - 12 25 - 14 - ns 40 54 60 - - - % Duty Cycle (CL = 40pF) fOSC = 32kHz, (See Typical Curves) - 41 - - 44 - % Frequency Stability vs. Supply Voltage (fOSC = 32kHz, VDD = 5V, CL=10pF) - 1 - - - - ppm/V Frequency Stability vs. Temperature (fOSC = 32kHz, VDD = 5V, CL=10pF) - 0.1 - - - - ppm/oC Frequency Stability vs. Load (fOSC = 32kHz, VDD = 5V, CL=10pF) - 0.01 - - - - ppm/pF PARAMETER VDD Supply Range (fOSC = 32kHz) IDD Supply Current VOH Output High Voltage (IOUT = -1mA) Three-State Leakage Current IIN Enable, Freq1, Freq2 Input Current (VIN = VSS to VDD) Duty Cycle (CL = 40pF) fOSC = 1MHz, Packaged Part Only (Note 4) NOTES: 1. 2. 3. 4. Calculated using the equation IDD = IDD (No Load) + (VDD) (fOSC)(CL) Human body model. This product is production tested at +25oC only. Duty cycle will vary with supply voltage, oscillation frequency, and parasitic capacitance on the crystal pins. 3 CDP6872 Test Circuits section of the circuit. The use of a current source in the reference string allows for wide supply variation with minimal effect on performance. The reduced operating voltage of the oscillator section reduces power consumption and limits transconductance and bandwidth to the frequency range selected. For frequencies at the edge of a range, the higher range may provide better performance. +5V 0.1µF 1VP-P 8 ENABLE 1 50Ω 3 The OSC OUT waveform on pin 3 is squared up through a series of inverters to the output drive stage. The Enable function is implemented with a NAND gate in the inverter string, gating the signal to the level shifter and output stage. Also during Disable the output is set to a high impedance state useful for minimizing power during standby and when multiple oscillators are OR'd to a single node. 7 FREQ 2 2 1000pF CDP6872 4 6 FREQ 1 5 CL VOUT 18pF Design Considerations FIGURE 1. The low power CMOS transistors are designed to consume power mostly during transitions. Keeping these transitions short requires a good decoupling capacitor as close as possible to the supply pins 1 and 4. A ceramic 0.1µF is recommended. Additional supply decoupling on the circuit board with 1µF to 10µF will further reduce overshoot, ringing and power consumption. The CDP6872, when compared to a crystal and inverter alone, will speed clock transition times, reducing power consumption of all CMOS circuitry run from that clock. In production the CDP6872 is tested with a 32kHz and a 1MHz crystal. However for characterization purposes data was taken using a sinewave generator as the frequency determining element, as shown in Figure 1. The 1VP-P input is a smaller amplitude than what a typical crystal would generate so the transitions are slower. In general the Generator data will show a “worst case” number for IDD, duty cycle, and rise/fall time. The Generator test method is useful for testing a variety of frequencies quickly and provides curves which can be used for understanding performance trends. Data for the CDP6872 using crystals has also been taken. This data has been overlaid onto the generator data to provide a reference for comparison. Power consumption may be further reduced by minimizing the capacitance on moving nodes. The majority of the power will be used in the output stage driving the load. Minimizing the load and parasitic capacitance on the output, pin 5, will play the major role in minimizing supply current. A secondary source of wasted supply current is parasitic or crystal load capacitance on pins 2 and 3. The CDP6872 is designed to work with most available crystals in its frequency range with no external components required. Two 15pF capacitors are internally switched onto crystal pins 2 and 3 to compensate the oscillator in the 10kHz to 100kHz frequency range. Theory of Operation The CDP6872 is a Pierce Oscillator optimized for low power consumption, requiring no external components except for a bypass capacitor and a Parallel Mode Crystal. The Simplified Block Diagram shows the Crystal attached to pins 2 and 3, the Oscillator input and output. The crystal drive circuitry is detailed showing the simple CMOS inverter stage and the P-channel device being used as biasing resistor RF . The inverter will operate mostly in its linear region increasing the amplitude of the oscillation until limited by its transconductance and voltage rails, VDD and VRN. The inverter is self biasing using RF to center the oscillating waveform at the input threshold. Do not interfere with this bias function with external loads or excessive leakage on pin 2. Nominal value for RF is 17MΩ in the lowest frequency range to 7MΩ in the highest frequency range. The supply current of the CDP6872 may be approximately calculated from the equation: IDD = IDD(Disabled) + VDD × FOSC × CL where: IDD = Total supply current VDD = Total voltage from VDD (pin1) to VSS (pin4) FOSC = Frequency of Oscillation CL = Output (pin5) load capacitance Example #1: The CDP6872 optimizes its power for 4 frequency ranges selected by digital inputs Freq1 and Freq2 as shown in the Block Diagram. Internal pull up resistors (constant current 0.4µA) on Enable, Freq1 and Freq2 allow the user simply to leave one or all digital inputs not connected for a corresponding “1” state. All digital inputs may be left open for 10kHz to 100kHz operation. VDD = 5V, FOSC = 100kHz, CL = 30pF IDD(Disabled) = 4.5µA (Figure 10) IDD = 4.5µA + (5V)(100kHz)(30pF) = 19.5µA Measured IDD = 20.3µA Example #2: VDD = 5V, FOSC = 5MHz, CL = 30pF IDD(Disabled) = 75µA (Figure 9) IDD = 75µA + (5V)(5MHz)(30pF) = 825µA Measured IDD = 809µA A current source develops 4 selectable reference voltages through series resistors. The selected voltage, VRN, is buffered and used as the negative supply rail for the oscillator 4 CDP6872 Crystal Selection Frequency Fine Tuning For general purpose applications, a Parallel Mode Crystal is a good choice for use with the CDP6872. However for applications where a precision frequency is required, the designer needs to consider other factors. Two Methods will be discussed for fine adjustment of the crystal frequency. The first and preferred method (Figure 2), provides better frequency accuracy and oscillator stability than method two (Figure 3). Method one also eliminates start-up problems sometimes encountered with 32kHz tuning fork crystals. Crystals are available in two types or modes of oscillation, Series and Parallel. Series Mode crystals are manufactured to operate at a specified frequency with zero load capacitance and appear as a near resistive impedance when oscillating. Parallel Mode crystals are manufactured to operate with a specific capacitive load in series, causing the crystal to operate at a more inductive impedance to cancel the load capacitor. Loading a crystal with a different capacitance will “pull” the frequency off its value. For best oscillator performance, two conditions must be met: the capacitive load must be matched to both the inverter and crystal to provide ideal conditions for oscillation, and the frequency of the oscillator must be adjustable to the desired frequency. In Method two these two goals can be at odds with each other; either the oscillator is trimmed to frequency by de-tuning the load circuit, or stability is increased at the expense of absolute frequency accuracy. The CDP6872 has 4 operating frequency ranges. The higher three ranges do not add any loading capacitance to the oscillator circuit. The lowest range, 10kHz to 100kHz, automatically switches in two 15pF capacitors onto OSC IN and OSC OUT to eliminate potential start-up problems. These capacitors create an effective crystal loading capacitor equal to the series combination of these two capacitors. For the CDP6872, in the lowest range, the effective loading capacitance is 7.5pF. Therefore the choice for a crystal, in this range, should be a Parallel Mode crystal that requires a 7.5pF load. Method one allows these two conditions to be met independently. The two fixed capacitors, C1 and C2, provide the optimum load to the oscillator and crystal. C3 adjusts the frequency at which the circuit oscillates without appreciably changing the load (and thus the stability) of the system. Once a value for C3 has been determined for the particular type of crystal being used, it could be replaced with a fixed capacitor. For the most precise control over oscillator frequency, C3 should remain adjustable. This three capacitor tuning method will be more accurate and stable than method two and is recommended for 32kHz tuning fork crystals; without it they may leap into an overtone mode when power is initially applied. In the higher 3 frequency ranges, the capacitance on OSC IN and OSC OUT will be determined by package and layout parasitics, typically 4 to 5pF. Ideally the choice for crystal should be a Parallel Mode set for 2.5pF load. A crystal manufactured for a different load will be “pulled” from its nominal frequency (see Crystal Pullability). Method two has been used for many years and may be preferred in applications where cost or space is critical. Note that in both cases the crystal loading capacitors are connected between the oscillator and VDD; do not use VSS as an AC ground. The Simplified Block Diagram shows that the oscillating inverter does not directly connect to VSS but is referenced to VDD and VRN. Therefore VDD is the best AC ground available. +5V C1 C2 +5V XTAL 2 OSC IN C3 3 OSC OUT 1 VDD C1 + - C2 VREG XTAL CDP6872 2 OSC IN 3 OSC OUT 1 VDD FIGURE 2. + CDP6872 FIGURE 3. 5 VREG CDP6872 Layout Considerations Typical values of the capacitors in Figure 2 are shown below. Some trial and error may be required before the best combination is determined. The values listed are total capacitance including parasitic or other sources. Remember that in the 10kHz to 100kHz frequency range setting the CDP6872 switches in two internal 15pF capacitors. CRYSTAL FREQUENCY LOAD CAPS C1, C2 TRIMMER CAP C3 32kHz 33pF 5-50pF 1MHz 33pF 5-50pF 2MHz 25pF 5-50pF 4MHz 22pF 5-100pF Due to the extremely low current (and therefore high impedance) the circuit board layout of the CDP6872 must be given special attention. Stray capacitance should be minimized. Keep the oscillator traces on a single layer of the PCB. Avoid putting a ground plane above or below this layer. The traces between the crystal, the capacitors, and the OSC pins should be as short as possible. Completely surround the oscillator components with a thick trace of VDD to minimize coupling with any digital signals. The final assembly must be free from contaminants such as solder flux, moisture, or any other potential source of leakage. A good solder mask will help keep the traces free of moisture and contamination over time. Further Reading Al Little “HA7210 Low Power Oscillator: Micropower Clock Oscillator and Op Amps Provide System Shutdown for Battery Circuits”. Intersil Application Note AN9317. Crystal Pullability Figure 4 shows the basic equivalent circuit for a crystal and its loading circuit. Robert Rood “Improving Start-Up Time at 32KHz for the HA7210 Low Power Crystal Oscillator”. Intersil Application Note AN9334. VDD S. S. Eaton “Timekeeping Advances Through COS/MOS Technology”. Intersil Application Note ICAN-6086. C2 C1 CM LM RM E. A. Vittoz et. al. “High-Performance Crystal Oscillator circuits: Theory and Application”. IEEE Journal of Solid-State Circuits, Vol. 23, No3, June 1988, pp774-783. C0 2 OSC IN M. A. Unkrich et. al. “Conditions for Start-Up in Crystal Oscillators”. IEEE Journal of Solid-State Circuits, Vol. 17, No1, Feb. 1982, pp87-90. 3 OSC OUT Marvin E. Frerking “Crystal Oscillator Design and Temperature Compensation”. New York: Van Nostrand-Reinhold, 1978. Pierce Oscillators Discussed pp56-75. FIGURE 4. Where: CM = Motional Capacitance LM = Motional Inductance RM = Motional Resistance C0 = Shunt Capacitance 1 = ----------------------------- = Equivalent Crystal Load C CL 1 1 ------- + ------C C 1 2 If loading capacitance is connected to a Series Mode Crystal, the new Parallel Mode frequency of resonance may be calculated with the following equation: F Where: P = F S C M 1 + ----------------------------------- 2 C +C CL 0 FP = Parallel Mode Resonant Frequency FS = Series Mode Resonant Frequency In a similar way, the Series Mode resonant frequency may be calculated from a Parallel Mode crystal and then you may calculate how much the frequency will “pull” with a new load. 6 CDP6872 Die Characteristics DIE DIMENSIONS: 68 x 64 x 14 ± 1mils METALLIZATION: Type: Si - Al Thickness: 10kÅ ± 1kÅ GLASSIVATION: Type: Nitride (Si3N4) Over Silox (SiO2, 3% Phos) Silox Thickness: 7kÅ ± 1kÅ Nitride Thickness: 8kÅ ± 1kÅ DIE ATTACH: Material: Silver Epoxy - Plastic DIP and SOIC SUBSTRATE POTENTIAL: VSS Metallization Mask Layout (1) VDD (8) ENABLE CDP6872 (7) FREQ 2 CRYSTAL (2) (6) FREQ 1 OUTPUT (5) VSS (4) CRYSTAL (3) 7 CDP6872 Typical Performance Curves CL = 40pF, FOSC = 5MHz, VDD = 5V, VSS = GND 1.0V/DIV. CL = 18pF, FOSC = 5MHz, VDD = 5V, VSS = GND 1.0V/DIV. 20.0ns/DIV. FIGURE 5. OUTPUT WAVEFORM (CL = 40pF) FIGURE 6. OUTPUT WAVEFORM (CL = 18pF) 1050 26 FIN = 5MHz, EN = 1, F1 = 0, F2 = 0, CL = 30pF, VCC = 5V EN = 1, F1 = 1, F2 = 1, FIN = 100kHz, CL = 30pF, VCC = 5V 25 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 1000 950 GENERATOR† (1VP-P) 900 850 XTAL AT +25oC 24 GENERATOR† (1VP-P) 23 22 21 20 XTAL AT +25oC 800 19 750 -100 -50 0 50 100 18 -100 150 -50 TEMPERATURE (oC) 0 50 TEMPERATURE FIGURE 7. SUPPLY CURRENT vs TEMPERATURE 100 150 (oC) FIGURE 8. SUPPLY CURRENT vs TEMPERATURE 7.5 350 EN = 0, F1 = 1, F2 = 1, FIN = 100kHz, VCC = 5V FIN = 5MHz, EN = 0, F1 = 0, F2 = 0, VCC = 5V 7 SUPPLY CURRENT (µA) 300 SUPPLY CURRENT (µA) 20.0ns/DIV. 250 GENERATOR† (1VP-P) 200 150 XTAL AT +25oC 100 GENERATOR† (1VP-P) 6 5.5 5 XTAL AT +25oC 4.5 50 0 -100 6.5 -50 0 50 100 4 -100 150 -50 0 50 100 150 TEMPERATURE (oC) o TEMPERATURE ( C) FIGURE 9. DISABLE SUPPLY CURRENT vs TEMPERATURE FIGURE 10. DISABLE SUPPLY CURRENT vs TEMPERATURE †Refer to Test Circuit (Figure 1). 8 CDP6872 Typical Performance Curves (Continued) 1400 3000 EN = 1, F1 = 0, F2 =1, CL = 18pF, GENERATOR† (1VP-P) EN = 1, F1 = 0, F2 = 0, CL = 18pF, GENERATOR† (1VP-P) 1200 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 2500 VCC = +8V 2000 1500 VCC = +5V 1000 500 VCC = +8V 1000 800 VCC = +5V 600 VCC = +3V 400 200 0 0 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 11. SUPPLY CURRENT vs FREQUENCY FIGURE 12. SUPPLY CURRENT vs FREQUENCY 300 50 EN = 1, F1 = 1, F2 = 0, CL = 18pF, GENERATOR† (1VP-P) EN = 1, F1 = 0, F2 =1, CL = 18pF, GENERATOR† (1VP-P) 40 VCC = +8V SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 250 200 VCC = +5V 150 100 VCC = +3V VCC = +8V 30 VCC = +5V 20 10 50 VCC = +3V 0 0 0 100 200 300 400 500 600 700 800 900 1000 1100 0 10 20 30 40 FREQUENCY (kHz) FIGURE 13. SUPPLY CURRENT vs FREQUENCY EN = 0, F1 = 0, F2 = 0, CL = 18pF, GENERATOR† (1VP-P) VCC = +8V 110 VCC = +5V 100 200 150 100 50 6 7 8 90 100 110 9 10 VCC = +8V VCC = +5V 90 80 70 60 VCC = +3V 50 30 5 80 40 VCC = +3V 4 70 EN = 0, F1 = 0, F2 = 1, CL = 18pF, GENERATOR† (1VP-P) 120 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 60 FIGURE 14. SUPPLY CURRENT vs FREQUENCY 250 0 50 FREQUENCY (kHz) 11 0 1 2 3 4 5 FREQUENCY (MHz) FREQUENCY (MHz) FIGURE 15. DISABLED SUPPLY CURRENT vs FREQUENCY FIGURE 16. DISABLE SUPPLY CURRENT vs FREQUENCY †Refer to Test Circuit (Figure 1). 9 6 CDP6872 Typical Performance Curves (Continued) EN = 0, F1 = 1, F2 = 0, CL = 18pF, GENERATOR† (1VP-P) EN = 0, F1 = 1, F2 = 1, CL = 18pF, GENERATOR† (1VP-P) 11 35 VCC = +8V 10 30 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) VCC = +8V VCC = +5V 25 20 VCC = +3V 15 9 8 7 VCC = +5V 6 5 VCC = +3V 4 10 3 5 2 0 100 200 300 400 500 600 700 800 900 1000 1100 0 10 20 30 40 FREQUENCY (kHz) FIGURE 17. DISABLE SUPPLY CURRENT vs FREQUENCY 60 70 80 90 100 110 FIGURE 18. DISABLE SUPPLY CURRENT vs FREQUENCY EN = 1, F1 = 0, F2 = 1, VCC = +5V, GENERATOR† (1VP-P) EN = 1, F1 = 0, F2 = 0, VCC = +5V, GENERATOR† (1VP-P) 3000 50 FREQUENCY (kHz) 1400 CL = 40pF CL = 40pF 1200 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 2500 2000 1500 CL = 18pF 1000 1000 800 CL = 18pF 600 400 200 500 0 4 5 6 7 8 9 10 11 0 1 2 FREQUENCY (MHz) FIGURE 19. SUPPLY CURRENT vs FREQUENCY 4 5 6 FIGURE 20. SUPPLY CURRENT vs FREQUENCY EN = 1, F1 = 1, F2 = 1, VCC = +5V, GENERATOR† (1VP-P) EN = 1, F1 = 1, F2 = 0, VCC = +5V, GENERATOR† (1VP-P) 35 300 CL = 40pF CL = 40pF 30 250 SUPPLY CURRENT (µA) SUPPLY CURRENT (µA) 3 FREQUENCY (MHz) 200 150 CL = 18pF 100 50 25 20 CL = 18pF 15 10 5 0 0 0 100 200 300 400 500 600 700 800 900 1000 1100 0 FREQUENCY (kHz) FIGURE 21. SUPPLY CURRENT vs FREQUENCY 10 20 30 40 50 60 70 80 FREQUENCY (kHz) 90 100 110 FIGURE 22. SUPPLY CURRENT vs FREQUENCY †Refer to Test Circuit (Figure 1). 10 CDP6872 Typical Performance Curves (Continued) FIN = 100kHz, F1 = 1, F2 = 1, CL = 30pF, VCC = 5V FIN = 5MHz, F1 = 0, F2 = 0, CL = 30pF, VCC = 5V 60 70 55 60 XTAL AT +25oC DUTY CYCLE (%) DUTY CYCLE (%) GENERATOR† (1VP-P) 50 45 40 XTAL AT +25oC 50 40 30 GENERATOR† (1VP-P) 20 35 30 -100 -50 0 50 100 10 -100 150 -50 0 FIGURE 23. DUTY CYCLE vs TEMPERATURE 70 F1 = F2 = 0, VDD = 5V, CL = 18pF, C1 = C2 = 0 70 150 F1 = 0, F2 = 1, VDD = 5V, CL = 18pF, C1 = C2 = 0 DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY 65 DUTY CYCLE (%) DUTY CYCLE (%) 100 FIGURE 24. DUTY CYCLE vs TEMPERATURE 65 60 55 50 60 55 50 45 F1 = 0, F2 = 0 RECOMMENDED FOR 5MHz TO 10MHz RANGE F1 = 0, F2 = 1 RECOMMENDED FOR 1MHz TO 5MHz RANGE 45 40 0 5 10 15 20 0 1 2 FREQUENCY (MHz) FIGURE 25. DUTY CYCLE vs FREQUENCY 3 4 5 6 FREQUENCY (MHz) 7 8 9 FIGURE 26. DUTY CYCLE vs FREQUENCY F1 = 1, F2 = 0, VDD = 5V, CL = 18pF, C1 = C2 = 0 65 47 DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY F1 = F2 = 1, VDD = 5V, CL = 18pF, C1 = C2 = 0 DATA COLLECTED USING CRYSTALS AT EACH FREQUENCY 46 60 DUTY CYCLE (%) DUTY CYCLE (%) 50 TEMPERATURE (oC) TEMPERATURE (oC) 55 50 45 44 43 42 45 41 F1 = 1, F2 = 1 RECOMMENDED FOR 10kHz TO 100kHz RANGE F1 = 1, F2 = 0 RECOMMENDED FOR 100kHz TO 1MHz RANGE 40 40 0 500 1000 1500 2000 2500 3000 3500 0 FREQUENCY (kHz) 50 100 150 FREQUENCY (kHz) FIGURE 27. DUTY CYCLE vs FREQUENCY FIGURE 28. DUTY CYCLE vs FREQUENCY †Refer to Test Circuit (Figure 1). 11 200 CDP6872 Typical Performance Curves (Continued) VCC = 5V, CL = 30pF, GENERATOR† (1VP-P) 6 30 FREQUENCY CHANGE (PPM) 20 EDGE JITTER (% OF PERIOD) 32kHz 1MHz 5MHz 25 10MHz 15 10 5 0 -5 -10 5 4 FIN = 5MHz, F1 = 0, F2 = 0 3 2 1 FIN = 100kHz, F1 = 1, F2 = 1 -15 DEVIATION FROM 5.0V FREQUENCY -20 2 4 VDD SUPPLY VOLTAGE (V) 0 -100 6 FIGURE 29. FREQUENCY CHANGE vs VDD 100 150 FIN = 100kHz, F1 = 1, F2 = 1, CL = 30pF, VCC = 5V FIN = 5MHz, F1 = 0, F2 = 0, CL = 30pF, VCC = 5V 12 12 RISE/FALL TIME (ns) 10 9 Tr GENERATOR† (1VP-P) 8 7 Tf XTAL AT +25oC 6 5 Tr XTAL AT +25oC 4 Tf GENERATOR† (1VP-P) 11 Tf GENERATOR† (1VP-P) 11 RISE/FALL TIME (ns) 0 50 TEMPERATURE (oC) FIGURE 30. EDGE JITTER vs TEMPERATURE 13 10 9 8 Tr GENERATOR† (1VP-P) Tf XTAL AT +25oC 7 6 5 Tr XTAL AT +25oC 4 3 3 2 -100 -50 0 50 TEMPERATURE 100 2 -100 150 -50 0 50 100 150 TEMPERATURE (oC) (oC) FIGURE 31. RISE/FALL TIME vs TEMPERATURE FIGURE 32. RISE/FALL TIME vs TEMPERATURE CL = 18pF, GENERATOR† (1VP-P) VCC = 5V, GENERATOR† (1VP-P) 15 30 Tf (FIN = 100kHz) Tf (FIN = 5MHz) 14 25 Tf (FIN = 5MHz) RISE/FALL TIME (ns) RISE/FALL TIME (ns) -50 Tr (FIN = 5MHz) 20 Tr (FIN = 100kHz) 15 13 Tf (FIN = 100kHz) 12 Tr (FIN = 5MHz) 11 Tr (FIN = 100kHz) 10 9 8 7 10 6 5 5 10 20 30 40 50 60 70 80 90 4 100 110 2 3 4 5 6 7 VCC (+VOLTS) CL (pF) FIGURE 33. RISE/FALL TIME vs CL FIGURE 34. RISE/FALL TIME vs VCC †Refer to Test Circuit (Figure 1). 12 8 9 CDP6872 (Continued) VDD = 5V, VSS = GND 500 620 F1 = 0, F2 = 0 TRANSCONDUCTANCE (µA/V) 540 500 436.5µA/V 460 420 180 380 1µF 1000pF 170 178o 340 2 300 50Ω 260 F1 = 0, F2 = 1 460 160 3 150 100Ω CDP6872 140 PHASE (DEGREES) TRANSCONDUCTANCE (µA/V) 580 VDD = 5V, VSS = GND 420 380 311.6µA/V 340 300 180 260 1000pF 2 50Ω 170 177o 1µF 160 3 150 100Ω CDP6872 140 PHASE (DEGREES) Typical Performance Curves 130 100K 1M FREQUENCY (Hz) 10M 10K FIGURE 35. TRANSCONDUCTANCE vs FREQUENCY VDD = 5V, VSS = GND VDD = 5V, VSS = GND 20 F1 = 1, F2 = 0 200 156.7µA/V 180 160 176.6o 140 120 180 1000pF 170 1µF 100 160 2 50Ω 10K 3 150 100Ω CDP6872 140 130 10M 100K 1M FREQUENCY (Hz) PHASE (DEGREES) TRANSCONDUCTANCE (µA/V) 220 10M FIGURE 36. TRANSCONDUCTANCE vs FREQUENCY TRANSCONDUCTANCE (µA/V) 240 100K 1M FREQUENCY (Hz) 15 F1 = 1, F2 = 1 6.56µA/V 10 5 180 0 170 160 166o 1µF 1000pF 150 140 2 3 100Ω 50Ω CDP6872 10K 100K FREQUENCY (Hz) 130 120 PHASE (DEGREES) 10K 110 1M FIGURE 38. TRANSCONDUCTANCE vs FREQUENCY FIGURE 37. TRANSCONDUCTANCE vs FREQUENCY F1 = F2 = 1, VDD = 5V, CL = 18pF, TA = 25oC, FOSC = 32.768kHz 60 DUTY CYCLE (%) 55 EPSON PART # C-001R32.768K-A 50 XTAL 45 NDK PART # MX-38 RS 3 OSC OUT 2 OSC IN 40 CDP6872 35 0 20 40 60 80 100 120 RS (kΩ) FIGURE 39. DUTY CYCLE vs RS at 32kHz NOTE: Figure 39 (Duty Cycle vs RS at 32kHz) should only be used for 32kHz crystals. RS may be used at other frequencies to adjust Duty Cycle but experimentation will be required to find an appropriate value. The RS value will be proportional to the effective series resistance of the crystal being used. 13 CDP6872 Dual-In-Line Plastic Packages (PDIP) E8.3 (JEDEC MS-001-BA ISSUE D) 8 LEAD DUAL-IN-LINE PLASTIC PACKAGE N INCHES E1 INDEX AREA 1 2 3 N/2 SYMBOL -B- -AE D BASE PLANE A2 -C- SEATING PLANE A L D1 e B1 D1 B 0.010 (0.25) M C L eA A1 eC C A B S C eB NOTES: MILLIMETERS MIN MAX MIN MAX NOTES A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 D1 0.005 - 0.13 10.16 - 5 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. e 0.100 BSC 2.54 BSC - eA 0.300 BSC 7.62 BSC 6 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. eB - 0.430 - 10.92 7 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. L 0.115 0.150 2.93 3.81 4 N 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 8 8 9 Rev. 0 12/93 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). 14 CDP6872 Small Outline Plastic Packages (SOIC) M8.15 (JEDEC MS-012-AA ISSUE C) 8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE N INDEX AREA H 0.25(0.010) M B M INCHES E SYMBOL -B1 2 3 L SEATING PLANE -A- h x 45o A D -C- e A1 B 0.25(0.010) M C 0.10(0.004) C A M B S MIN MAX NOTES A 0.0532 0.0688 1.35 1.75 - 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 8o 0o N α NOTES: MILLIMETERS MAX A1 e α MIN 8 0o 8 7 8o Rev. 0 12/93 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Spec Number 15