SEMICONDUCTOR TECHNICAL DATA L SUFFIX CERAMIC CASE 620 The MC14560B adds two 4–bit numbers in NBCD (natural binary coded decimal) format, resulting in sum and carry outputs in NBCD code. This device can also subtract when one set of inputs is complemented with a 9’s Complementer (MC14561B). All inputs and outputs are active high. The carry input for the least significant digit is connected to VSS for no carry in. P SUFFIX PLASTIC CASE 648 • Diode Protection on All Inputs • Supply Voltage Range = 3.0 Vdc to 18 Vdc • Capable of Driving Two Low–power TTL Loads or One Low–power Schottky TTL Load Over the Rated Temperature Range ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ D SUFFIX SOIC CASE 751B MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit – 0.5 to + 18.0 V Vin, Vout Input or Output Voltage (DC or Transient) – 0.5 to VDD + 0.5 V Iin, Iout Input or Output Current (DC or Transient), per Pin ± 10 mA PD Power Dissipation, per Package† 500 mW Tstg Storage Temperature – 65 to + 150 _C 260 _C TL Lead Temperature (8–Second Soldering) * Maximum Ratings are those values beyond which damage to the device may occur. †Temperature Derating: Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C Ceramic “L” Packages: – 12 mW/_C From 100_C To 125_C TRUTH TABLE* Input Output A4 A3 A2 A1 B4 B3 B2 B1 Cin Cout S4 S3 S2 S1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 0 0 1 1 0 0 0 1 0 1 1 1 0 1 0 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = – 55° to 125°C for all packages. BLOCK DIAGRAM 7 15 14 1 2 3 4 5 6 Cin A1 B1 A2 B2 A3 B3 A4 B4 S1 13 S2 12 S3 11 S4 10 Cout 9 VDD = PIN 16 VSS = PIN 8 * Partial truth table to show logic operation for representative input values. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS ≤ (Vin or Vout) ≤ VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. REV 0 3 1/94 MOTOROLA Motorola, Inc. 1994 1995 CMOS LOGIC DATA MC14560B 1 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Output Voltage Vin = VDD or 0 Symbol – 55_C 25_C 125_C VDD Vdc Min Max Min Typ # Max Min Max Unit “0” Level VOL 5.0 10 15 — — — 0.05 0.05 0.05 — — — 0 0 0 0.05 0.05 0.05 — — — 0.05 0.05 0.05 Vdc “1” Level VOH 5.0 10 15 4.95 9.95 14.95 — — — 4.95 9.95 14.95 5.0 10 15 — — — 4.95 9.95 14.95 — — — Vdc 5.0 10 15 — — — 1.5 3.0 4.0 — — — 2.25 4.50 6.75 1.5 3.0 4.0 — — — 1.5 3.0 4.0 5.0 10 15 3.5 7.0 11 — — — 3.5 7.0 11 2.75 5.50 8.25 — — — 3.5 7.0 11 — — — 5.0 5.0 10 15 – 3.0 – 0.64 – 1.6 – 4.2 — — — — – 2.4 – 0.51 – 1.3 – 3.4 – 4.2 – 0.88 – 2.25 – 8.8 — — — — – 1.7 – 0.36 – 0.9 – 2.4 — — — — IOL 5.0 10 15 0.64 1.6 4.2 — — — 0.51 1.3 3.4 0.88 2.25 8.8 — — — 0.36 0.9 2.4 — — — mAdc Input Current Iin 15 — ± 0.1 — ± 0.00001 ± 0.1 — ± 1.0 µAdc Input Capacitance (Vin = 0) Cin — — — — 5.0 7.5 — — pF Quiescent Current (Per Package) IDD 5.0 10 15 — — — 5.0 10 20 — — — 0.005 0.010 0.015 5.0 10 20 — — — 150 300 600 µAdc IT 5.0 10 15 Vin = 0 or VDD Input Voltage “0” Level (VO = 4.5 or 0.5 Vdc) (VO = 9.0 or 1.0 Vdc) (VO = 13.5 or 1.5 Vdc) VIL “1” Level VIH (VO = 0.5 or 4.5 Vdc) (VO = 1.0 or 9.0 Vdc) (VO = 1.5 or 13.5 Vdc) Output Drive Current (VOH = 2.5 Vdc) (VOH = 4.6 Vdc) (VOH = 9.5 Vdc) (VOH = 13.5 Vdc) (VOL = 0.4 Vdc) (VOL = 0.5 Vdc) (VOL = 1.5 Vdc) Vdc Vdc IOH Source Sink Total Supply Current**† (Dynamic plus Quiescent, Per Package) (CL = 50 pF on all outputs, all buffers switching) mAdc IT = (1.68 µA/kHz) f + IDD IT = (3.35 µA/kHz) f + IDD IT = (5.03 µA/kHz) f + IDD µAdc #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. ** The formulas given are for the typical characteristics only at 25_C. †To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.005. PIN ASSIGNMENT MC14560B 2 A2 1 16 VDD B2 2 15 A1 A3 3 14 B1 B3 4 13 S1 A4 5 12 S2 B4 6 11 S3 Cin 7 10 S4 VSS 8 9 Cout MOTOROLA CMOS LOGIC DATA ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C) Characteristic Symbol Output Rise and Fall Time tTLH, tTHL = (1.5 ns/pF) CL + 25 ns tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns tTLH, tTHL Propagation Delay Time A or B to S tPLH, tPHL = (1.7 ns/pF) CL + 665 ns tPLH, tPHL = (0.66 ns/pF) CL + 297 ns tPLH, tPHL = (0.5 ns/pF) CL + 195 ns tPLH, tPHL VDD Min Typ # Max 5.0 10 15 — — — 100 50 40 200 100 80 Unit ns ns 5.0 10 15 — — — 750 330 220 2100 900 675 A or B to Cout tPLH, tPHL = (1.7 ns/pF) CL + 565 ns tPLH, tPHL = (0.66 ns/pF) CL + 197 ns tPLH, tPHL = (0.5 ns/pF) CL + 145 ns 5.0 10 15 — — — 650 230 170 1800 600 450 Cin to Cout tPLH, tPHL = (1.7 ns/pF) CL + 465 ns tPLH, tPHL = (0.66 ns/pF) CL + 187 ns tPLH, tPHL = (0.5 ns/pF) CL + 135 ns 5.0 10 15 — — — 550 220 160 1500 600 450 ns ns Turn–Off Delay Time Cin to S tPLH = (1.7 ns/pF) CL + 715 ns tPLH = (0.66 ns/pF) CL + 197 ns tPLH = (0.5 ns/pF) CL + 215 ns tPLH Turn–On Delay Time Cin to S tPHL = (1.7 ns/pF) CL + 565 ns tPHL = (0.66 ns/pF) CL + 197 ns tPHL = (0.5 ns/pF) CL + 145 ns tPHL ns 5.0 10 15 — — — 800 350 240 2250 975 750 ns 5.0 10 15 — — — 650 230 170 1800 600 450 * The formulas given are for the typical characteristics only at 25_C. #Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance. 20 ns ALL INPUTS 20 ns VDD 90% 50% 10% 1 2f VSS 20 ns 20 ns VDD 90% 50% 10% ANY INPUT VSS tPHL tPLH VOH ANY OUTPUT VOL Duty Cycle = 50% ANY OUTPUT 50% 10% VOH 90% VOL All outputs connected to respective CL loads f = System clock frequency Figure 1. Power Dissipation Waveforms MOTOROLA CMOS LOGIC DATA tTLH tTHL Figure 2. Switching Time Waveforms MC14560B 3 FUNCTIONAL EQUIVALENT LOGIC DIAGRAM Cin A1 B1 A2 B2 A3 B3 A4 B4 7 13 15 14 12 S1 S2 1 2 11 S3 3 10 4 S4 5 9 6 Cout VDD = PIN 16 VSS = PIN 8 ADD/SUBTRACT MC14561B A1 ZERO One MC14560B and MC14561B permit a BCD digit to be added to or subtracted from a second digit, such as in this typical configuration. A second MC14561B permits either digit to be added to or subtracted from the other, or either word to appear unmodified at the output. Result 0 0 B plus A 0 1 B minus A 1 X B X = Don’t Care F2 F3 F4 MC14560B Cin A1 A2 A3 A4 B1 B2 B3 B4 S1 S2 UNITS S3 S4 Cout MC14561B TRUTH TABLE Add/Subtract F1 B1 A10 Zero A1 A2 A3 A4 COMP COMP Z A1 A2 A3 A4 COMP COMP Z B10 F1 F2 F3 F4 MC14560B Cin A1 A2 A3 A4 B1 B2 B3 B4 S1 S2 TENS S3 S4 Cout Figure 3. Parallel Add/Subtract Circuit MC14560B 4 MOTOROLA CMOS LOGIC DATA APPLICATIONS INFORMATION INTRODUCTION Frequently in small digital systems, simple decimal arithmetic is performed. Decimal data enters and leaves the system arithmetic unit in a binary coded decimal (BCD) format. The adder/subtracter in the arithmetic unit may be required to accept sign as well as magnitude, and generate sign, magnitude, and overflow. In the past, it has been cumbersome to build sign and magnitude adder/subtracters. Now, using Motorola’s MSI CMOS functions, the MC14560 NBCD Adders and MC14561 9’s Complementers, NBCD adder/ subtracters may be built economically, with surprisingly low package count and moderate speed. Some background information on BCD arithmetic is presented here, followed by simple circuits for unsigned adder/ subtracters. The final circuit discussed is an adder/subtracter for signed numbers with complete overflow and sign correction logic. DECIMAL NUMBER REPRESENTATION Because logic elements are binary or two–state devices, decimal digits are generally represented as a group of bits in a weighted format. There are many possible binary codes which can be used to represent a decimal number. One of the most popular codes using 4 binary digits to represent 0 thru 9 is Natural Binary Coded Decimal (NBCD or 8–4–2–1 code). NBCD is a weighted code. If a value of “0” or “1” is assigned to each of the bit positions, where the rightmost position is 20 and the leftmost is 23, and the values are summed for a given code, the result is equal to the decimal digit represented by the code. Thus, 0110 equals 0@23 + 1@22 + 1@21 + 0@20 = 4 + 2 = 6. The 1010, 1011, 1100, 1101, 1110, and 1111 binary codes are not used. Because of these illegal states, the addition and subtraction of NBCD numbers is more complex than similar calculations on straight binary numbers. ADDITION OF UNSIGNED NBCD NUMBERS When 2 NBCD digits, A and B, and a possible carry, C, are added, a total of 20 digit sums (A + B + C) are possible as shown in Table 1. The binary representations for the digit sums 10 thru 19 are offset by 6, the number of unused binary states, and are not correct. An algorithm for obtaining the correct sum is shown in Figure 1. A conventional method of implementing the BCD addition algorithm is shown in Figure 2(a). The NBCD digits, A and B, are summed by a 4 bit binary full adder. The resultant (sum and carry) is input to a binary/BCD code converter which generates the correct BCD code and carry. An NBCD adder block which performs the above function is available in a single CMOS package (MC14560). MOTOROLA CMOS LOGIC DATA Figure 2(b) shows n decades cascaded for addition of n digit unsigned NBCD numbers. Add time is typically 0.1 + 0.2n µs for n decades. When the carry out of the most significant decade is a logical “1”, an overflow is indicated. COMPLEMENT ARITHMETIC Complement arithmetic is used in NBCD subtraction. That is, the “complement” of the subtrahend is added to the minuend. The complementing process amounts to biasing the subtrahend such that all possible sums are positive. Consider the subtraction of the NBCD numbers, A and B: R=A–B where R is the result. Now bias both sides of the equation by 10N – 1 where N is the number of digits in A and B. R + 10N – 1 A – B + 10N – 1 Rearranging, R + 10N – 1 A + (10N – 1 – B) The term (10N – 1 – B), – B biased by 10N – 1, is known as the 9’s complement of B. When A > B, R + 10N – 1 > 10N – 1; thus R is a positive number. To obtain R, 1 is added to R + 10N – 1, and the carry term, 10N, is dropped. The addition of 1 is called End Around Carry (EAC). When A < B, R + 10N – 1 < 10N – 1, no EAC results and R is a negative number biased by 10N – 1; thus R + 10N – 1 is the 9’s complement of R. SUBTRACTION OF UNSIGNED NBCD NUMBERS Nine’s complement arithmetic requires an element to perform the complementing function. An NBCD 9’s complementer may be implemented using a 4 bit binary adder and 4 inverters, or with combinatorial logic. The Motorola MC14561 9’s complementer is available in a single package. It has true and inverted complement disable, which allow straight– through or complement modes of operation. A “zero” line forces the output to “0”. Figure 3 shows an NBCD subtracter block using the MC14560 and MC14561. Also shown are n cascaded blocks for subtraction of n digit unsigned numbers. Subtract time is 0.6 + 0.4n µs for n stages. Underflow (borrow) is indicated by a logical “0” on the carry output of the most significant digit. A “0” carry also indicates that the difference is a negative number in 9’s complement form. If the result is input to a 9’s complementer, as shown, and its mode controlled by the carry out of the most significant digit, the output of the complementer will be the correct negative magnitude. Note that the carry out of the most significant digit (MSD) is the input to carry in of the least significant digit (LSD). This End Around Carry is required because subtraction is done in 9’s complement arithmetic. By controlling the complement and overflow logic with an add/subtract line, both addition and subtraction are performed using the basic subtracter blocks (Figure 4). MC14560B 5 ADDITION AND SUBTRACTION OF SIGNED NBCD NUMBERS Table 1. Sum = A + B + C Binary Sums Decimal Numbers Corrected Binary Sums 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 0000 + Carry 0001 + Carry 0010 + Carry 0011 + Carry 0100 + Carry 0101 + Carry 0110 + Carry 0111 + Carry 1000 + Carry 1001 + Carry 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Non valid 1101 BCD 1110 representation 1111 0000 + Carry 0001 + Carry 0010 + Carry 0011 + Carry + Using MC14560 NBCD Adders and MC14561 9’s Complementers, a sign and magnitude adder/subtracter can be configured (Figure 5). Inputs A and B are signed positive (AS, BS = “0”) or negative (AS, BS = “1”). B is added to or subtracted from A under control of an Add/Sub line (subtraction = “1”). The result, R, of the operation is positive signed, positive signed with overflow, negative signed, or negative signed with overflow. Add/subtract time is typically 0.6 + 0.4n µs for n decades. An exclusive–OR of Add/Sub line and BS produces B′, which controls the B complementers. If BS, the sign of B, is a logical “1” (B is negative) and the Add/Sub line is a “0” (add B to A), then the output of the exclusive–OR (BS′) is a logical “1” and B is complemented. If BS = “1” and Add/Sub = “1”, B is not complemented since subtracting a negative number is the same as adding a positive number. When Add/Sub is a “1” and BS = “0”, BS′ is a “1” and B is complemented. The A complementer is controlled by the A sign bit, AS. When AS = “1”, A is complemented. THOUSANDS HUNDREDS TENS UNITS 6,941 0110 1001 0100 0001 5,870 0101 1000 0111 0000 ADDER Cin 4 BIT BINARY ADDERS DIGIT BINARY SUMS 1011 1100 BINARY SUMS WITH CARRY FROM CONVERTERS ADDER 1 1 1 ADDER 1 Cin Cin 0001 0010 ADDER 0 1011 1011 0001 0001 CODE CONVERTERS Cout Cout Cout Cout CORRECTED SUM 12,811 1 0 0 1 0 1 0 0 0 0 0 0 1 0 0 0 1 Figure 4. Unsigned NBCD Addition Algorithm A B A1 Cin B1 A2 B2 An Bn 4 BIT BINARY FULL ADDER Cout Cin MC14560 BINARY TO NBCD CODE CONVERTER RESULT, R MC14560 Cin Cout MC14560 Cout OVERFLOW R1 (a) MC14560 Block Diagram Cout Cin R2 Rn Typical Add Time = 0.1 + 0.2n µs where n = Number of Decades (b) n–Decade Adder Figure 5. Addition of Unsigned NBCD Numbers MC14560B 6 MOTOROLA CMOS LOGIC DATA translated to ASBS′ Cout. This is equivalent to the majority function M3(ASBS′ Cout). Further evaluation of the maps and truth table reveal that Overflow can be generated by the exclusive–OR function of End Around Carry and Carry Out. This analysis results in a minimum device count consisting of one exclusive–OR package and one dual Majority Logic package to implement BS′, EAC, Sign and Overflow. The logic connections of these devices are shown in Figure 5. The output sign, RS, complements the result of the add/ subtract operation when RS = “1”. This is required because the adder performs 9’s complement arithmetic. Complementing, when RS indicates the result is negative, restores sign and magnitude convention. Several variations of the adder/subtracter are possible. For example, 9’s complement is available at the output of the NBCD adders, and output complementers are eliminated if sign and magnitude output is not required. The truth table and Karnaugh maps for sign, overflow, and End Around Carry are shown in Figures 6 and 7. Note the use of BS′ from the exclusive–OR of Add/Sub and BS. BS′ eliminates Add/Sub as a variable in the truth table. As an example of truth table generation, consider an n decade adder/ subtracter where AS = “0”, BS = “1”, and Add/Sub = “0”. B is in 9’s complement form, 10N – 1 – B. Thus A + (10N – 1 – B) = 10N – 1 + (A – B). There is no carry when A B, and the sign is negative (sign = “1”). When AS and BS are opposite states and Add/Sub is a “0” (add mode), no overflow can occur (overflow = “0”). The other output states are determined in a similar manner (see Figure 6). From the Karnaugh maps it is apparent that End Around Carry is composed of the two symmetrical functions S2 and S3 of three variables with AS BS′ Cout as the center of symmetry. This is the definition of the majority logic function M3(ABC). Similarly the Sign is composed of the symmetrical functions S2(3) and S3(3) but with the center of symmetry v A B A1 VDD A2 A3 A4 C MC14561 C Z A1 Cn A2 A3 A4 F2 F3 F4 B1 B2 B3 AB MC14560 Cin FROM Cout OF MOST SIGNIFICANT DECADE F1 Cn + 1 Cout S1 S2 S3 S4 A1 A2 A3 A4 C VDD C MC14561 Z F1 F2 F3 F4 RESULT, R (a) Basic Subtracter Block A1 LEAST SIGNIFICANT DECADE B1 A2 BASIC Cin C SUBTRACT out BLOCK C B2 An MOST SIGNIFICANT DECADE Cin Cout C Bn Cin Cout C R1 R1 R2 Rn Typical Subtract Time = 0.6 + 0.4n µs where n = Number of Decades “0” INDICATES UNDERFLOW (NEGATIVE RESULT) (b) n–Decade Subtracter Figure 6. Subtraction of Unsigned NBCD Numbers MOTOROLA CMOS LOGIC DATA MC14560B 7 SUMMARY REFERENCES 1. Chu, Y.: Digital Computer Design Fundamentals, New York, McGraw–Hill, 1962. 2. McMOS Handbook, Motorola Inc., 1st Edition. 3. Beuscher, H.: Electronic Switching Theory and Circuits, New York, Van Nostrand Reinhold, 1971. 4. Garrett, L.: CMOS May Help Majority Logic Win Designer’s Vote, Electronics, July 19, 1973. 5. Richards, R.: Digital Design, New York, Wiley– Interscience, 1971. The concepts of binary code representations for decimal numbers, addition, and complement subtraction were discussed in detail. Using the basic Adder and Complementer MSI blocks, adder/subtracters for both signed and unsigned numbers were illustrated with examples. A1 B1 A2 B2 LSD An Bn MSD Cin C BASIC Cout SUBTRACT BLOCK Cin Cin Cout C C R1 ADD/SUBTRACT (“1”/“0”) Cout R2 Rn 1/6 MC14572 OVERFLOW = “1” 1/6 MC14572 UNDERFLOW = “1” (NEGATIVE RESULT) Typical Add/Subtract Time = 0.6 + 0.4 n µs where n = Number of Decades Figure 7. Adder/Subtracter for Unsigned NBCD Numbers MC14560B 8 MOTOROLA CMOS LOGIC DATA Figure 8. Sign and Magnitude Adder/Subtracter with Overflow MOTOROLA CMOS LOGIC DATA MC14560B 9 AS BS VDD ADD/SUB A1 F1 A1 A3 A2 F2 1/4 MC14070 B S′ A3 F3 MC14561 A2 1/4 MC14070 Cin Z C C A1 Z C C F1 A2 A1 A3 S3 E D C B A E D C B Z C C F4 A4 S4 B1 M5 M5 F1 A1 MC14530 F3 R1 A F2 MC14561 S2 MC14560 S1 A4 F4 A4 A3 B2 F2 B3 F3 MC14561 A2 B1 VDD Cout B4 F4 A4 W W Z Z R2 MC14561 MC14560 SIGN 1/4 MC14070 Cout MC14561 B2 Typical Add/Subtract Time = 0.6 + 0.4n µ s where n = Number of Decades EAC MC14561 A2 MC14561 An SIGN OF RS OVERFLOW Rn MC14561 MC14560 Cout MC14561 Bn Inputs AS “1” = Neg BS′ “1” = Neg Cout “1” = Carry 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 Arithmatic Expression for R* (Result) (N = Number of Digits, 10N = Modulus A, B, R are Positive Magnitudes) R=A+8 R=A–B = A + (10N – 1 – B) = A – B + 10N – 1 R=B–A = B + (10N – 1 – A) = B – A + 10N – 1 R=–A–B = (10N – 1 – A) + (10N – 1 – B) = – (A + B) + 2 x 10N – 2 Outputs End Around Carry (EAC) “1” = EAC Sign of R “1” = Negative Overflow “1” = Overflow No EAC (“0”) because R is correct result. Since A and B are positive signed, R is positive signed (“0”). When Cout = “0”, there is no carry (R < 10N) and thus no overflow (“0”). When Cout = “1”, there is a carry (R ≥ 10N) and thus overflow (“1”). v No EAC (“0”) because 9’s complement expression for R is correct result. A B when Cout = “0”; thus sign of R must be negative (“1”). EAC = “1” because expression for R is in error by 1. A > B when Cout = “1”; thus sign of R must be positive (“0”). No EAC (“0”) because 9’s complement expression for R is correct result. B A when Cout = “0”; thus sign of R must be negative (“1”). EAC = “1” because expression for R is in error by 1. B > A when Cout = “1”; thus sign of R must be positive (“0”). EAC = “1” because 9’s complement expression for R is in error by 1. Since A and B are negative signed. R is negative signed (“1”). v There is never an overflow when numbers of opposite sign are added. When Cout = “0”, there is no Carry (R < 0N) and (A + B) > 10N – 1 indicating overflow (“1”). When Cout = “1”, there is a carry (R ≥ 10N) and (A + B) 10N – 1 indicating no overflow (“0”). v * Output of Adders Figure 9. Truth Table Generation for EAC, Sign, and Overflow Logic MC14560B 10 MOTOROLA CMOS LOGIC DATA KARNAUGH MAPS TRUTH TABLE Inputs Outputs End Around Carry AS AS BS′ Cout EAC SGN OVF 0 0 0 0 0 0 0 1 0 1 0 0 1 0 1 1 1 0 0 0 1 0 0 1 0* 0 1 1 0 1 1 1 0 0 1 0 0 1 0 1 1 1 0 0 1 0 1 1 0 0 1 1 1 1 1 0 ę BS = (Add/Sub) BS AS = Sign of A (“1” = Negative) BS = Sign of B (“1” = Negative) Cout = Adder Carry Out Cout Sign (SGN) AS BS′ Cout 1 1 0 1 0* 0 0 1 Overflow (OVF) AS BS′ Cout 0 1 0 0 1 0 0 0 BS′ * = Center of Symmetry EAC = S2 (ASBS′ Cout) + S3 (ASBS′ Cout) = M3 (ASBS′ Cout) SGN = S2 (ASBS′ Cout) + S3 (ASBS′ Cout) = M3 (ASBS′ Cout) ę EAC 0 1 1 1 0 1 0 0 ę Cout = OVF 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 = Figure 10. Mapping of EAC, Sign and Overflow Logic MOTOROLA CMOS LOGIC DATA MC14560B 11 OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 620–10 ISSUE V –A– 16 9 1 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C L DIM A B C D E F G H K L M N –T– K N SEATING PLANE M E F J G D 16 PL 0.25 (0.010) 16 PL 0.25 (0.010) M T A T B M S INCHES MIN MAX 0.750 0.785 0.240 0.295 ––– 0.200 0.015 0.020 0.050 BSC 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0_ 15 _ 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.93 6.10 7.49 ––– 5.08 0.39 0.50 1.27 BSC 1.40 1.65 2.54 BSC 0.21 0.38 3.18 4.31 7.62 BSC 0_ 15 _ 0.51 1.01 S P SUFFIX PLASTIC DIP PACKAGE CASE 648–08 ISSUE R NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. –A– 16 9 1 8 B F C L S –T– K H G D J 16 PL 0.25 (0.010) MC14560B 12 SEATING PLANE M T A M M DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MOTOROLA CMOS LOGIC DATA OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B–05 ISSUE J –A– 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 –B– 1 P 8 PL 0.25 (0.010) 8 M B S G R K F X 45 _ C –T– SEATING PLANE M D 16 PL 0.25 (0.010) M T B S A S J DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 Motorola reserves the right to make changes without further notice to any products herein. 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How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 or 602–303–5454 JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–81–3521–8315 MFAX: [email protected] – TOUCHTONE 602–244–6609 INTERNET: http://Design–NET.com ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 MOTOROLA CMOS LOGIC DATA ◊ *MC14560B/D* MC14560B MC14560B/D 13