TDA8035 High integrated and low power smart card interface Rev. 3.0 — 25 June 2014 Product data sheet COMPANY PUBLIC 1. General description The TDA8035 is the cost efficient successor of the established integrated contact smart card reader IC TDA8024. It offers a high level of security for the card by performing current limitation, short-circuit detection, ESD protection as well as supply supervision. The current consumption during the standby mode of the contact reader is very low as it operates in the 3 V supply domain. The TDA8035 is therefore the ideal component for a power efficient contact reader. 2. Features and benefits 2.1 Protection of the contact smart card Thermal and short-circuit protection on all card contacts VCC regulation: 5 V, 3 V, 1.8 V 5 % on 2 220 nF multilayer ceramic capacitors with low ESR Current spikes of 40 nA/s (VCC = 5 V and 3 V) or 15 nA/s (VCC = 1.8 V) up to 20 MHz, with controlled rise and fall times. Filtered overload detection is approximately 120 mA. Automatic activation and deactivation sequences initiated by software or by hardware in the event of a short-circuit, card take-off, overheating, falling VREG VDD(INTF),VDDP Enhanced card-side ElectroStatic Discharge (ESD) protection of (> 8 kV) Supply supervisor for killing spikes during power on and off: threshold internally fixed externally by a resistor bridge 2.2 Easy integration into your contact reader SW compatible to TDA8024 and TDA8034 5 V, 3 V, 1.8 V smart card supply DC-to-DC converter for VCC generation separately powered from 2.7 V to 5.5 V supply (VDDP and GNDP) Very low power consumption in Deep Shutdown mode Three protected half-duplex bidirectional buffered I/O lines (C4, C7 and C8) External clock input up to 26 MHz Card clock generation up to 20 MHz using pins CLKDIV1 and CLKDIV2 with synchronous frequency changes of fXTAL, fXTAL/2, fXTAL/4 or fXTAL/8 Non-inverted control of pin RST using pin RSTIN Built-in debouncing on card presence contact TDA8035 NXP Semiconductors High integrated and low power smart card interface Multiplexed status signal using pin OFFN Chip Select digital input for parallel operation of several TDA8035 ICs. 2.2.1 Other HVQFN32 package Compliant with ISO 7816, NDS and EMV 4.2 payment systems 3. Applications Pay TV Electronic payment Identification IC card readers for banking 4. Quick reference data Table 1. Quick reference data VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply VDDP power supply voltage 2.7 3.3 5.5 V VDD(INTF) interface supply voltage 1.6 3.3 3.6 V IDDP power supply current - 0.1 3 A - 300 500 A active mode; VCC = +5 V CLK = fXTAL/2; no load - - 5 mA active mode; CLK = fXTAL/2; VCC = +5 V; ICC = 65 mA - - 220 mA active mode; CLK = fXTAL/2; VCC = +3 V; ICC = 65 mA - - 160 mA active mode; CLK = fXTAL/2; VCC = +1.8 V; ICC = 35 mA - - 120 mA deep shutdown mode; fXTAL = stopped; present card - - 1 A shutdown mode; fXTAL = stopped; present card - - 1 A 1.62 1.8 1.98 V deep shutdown mode; fXTAL = stopped; shutdown mode; fXTAL = stopped; IDD(INTF) interface supply current Internal supply voltage VDD supply voltage TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 2 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 1. Quick reference data …continued VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXtal = 10 MHz; GND = 0 V; Tamb = 25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit 5 V card; DC ICC < 65 mA 4.75 5.0 5.25 V 5 V card; AC current spikes of 40 nA/s 4.65 5.0 5.25 V 3 V card; DC ICC < 65 mA 2.85 - 3.15 V 3 V card; AC current spikes of 40 nA/s 2.76 - 3.24 V 1.8 V card; DC ICC < 35 mA 1.71 - 1.89 V 1.8 V card; AC current spikes of 15 nA/s 1.66 - 1.94 V Card supply voltage: pin VCC supply voltage VCC Vripple(p-p) peak-to-peak ripple voltage from 20 kHz to 200 MHz - - 300 mV ICC supply current VCC = 5 V or 3 V - - 65 mA VCC = 1.8 V - - 35 mA total sequence General tdeact deactivation time 35 90 250 s Ptot total power dissipation - - 0.45 W Tamb ambient temperature 25 - +85 C 5. Ordering information Table 2. Ordering information Type number Package Name Description Version TDA8035HN/C1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm SOT617-7 TDA8035HN/C1/S1 HVQFN32 plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 5 0.85 mm; [1] SOT617-7 [1] copper wiring TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 3 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 6. Block diagram VDD(INTF) VDDP 330 nF 10 μF 100 nF 330 nF 100 nF 100 nF VDD(INTF) PORADJ VREG GND VDDP GNDP SAP SAM SBP SBM CS deep shutdown CMDVCCN EN_5V/3VN VUP INTERNAL REGULATOR DEEP SHUTDOWN DCDC CONVERTER 1 μF EN_1.8VN RSTIN CLKDIV1 VCC LATCH INPUT SENSE CLKDIV2 ISO7816 READER INTERFACE reset and supalarm SUPERVISOR HOST INTERFACE UC AUX2UC RST CLK BANDGAP H Z AUX1 I/O VDD(INTF) H Z configurations bus for smartcard reader interface interuption C5 C1 C6 C2 C7 C3 C8 C4 AUX2 TDA8035 INTERNAL OSCILLATOR OFFN 2× 220 nF DEEP SHUTDOWN I/OUC AUX1UC GNDC THERMAL PROTECTION DIGITAL SEQUENCER CRYSTAL OSCILLATOR XTAL1 XTAL2 PRESN 001aan745 Fig 1. Block diagram TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 4 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 7. Pinning information 25 GNDC 26 AUX1 27 AUX2 28 I/O 29 CS 30 PRESN terminal 1 index area 31 AUX1UC 32 AUX2UC 7.1 Pinning I/OUC 1 24 CLK PORADJ 2 23 RST CMDVCCN 3 22 VCC VDD(INTF) 4 CLKDIV1 5 CLKDIV2 6 19 SBP EN_5V/3VN 7 18 VDDP EN_1.8VN 8 17 SBM 21 VUP GNDP 16 20 SAP SAM 15 VREG 14 XTAL2 13 XTAL1 12 GND 11 9 RSTN OFFN 10 TDA8035 001aan746 Transparent top view Fig 2. Pin configuration HVQFN32 7.2 Pin description Table 3. Pin description Symbol Pin Supply Type Description I/OUC 1 VDD(INTF) I/O host data I/O line (internal 10 k pull-up resistor to VDD(INTF)) PORADJ 2 VDD(INTF) I Input for VDD(INTF) supervisor. PORADJ threshold can be changed with an external R bridge CMDVCCN 3 VDD(INTF) I start activation sequence input from the host (active LOW) VDD(INTF) 4 VDD(INTF) supply interface supply voltage CLKDIV1 5 VDD(INTF) I control with CLKDIV2 for choosing CLK frequency (see Table 4) CLKDIV2 6 VDD(INTF) I control with CLKDIV1 for choosing CLK frequency (see Table 4) EN_5V/3VN 7 VDD(INTF) I control signal for selecting VCC = 5 V (HIGH) or VCC = 3 V (LOW) if EN_1.8 VN = High EN_1.8 VN 8 VDD(INTF) I control signal for selecting VCC = 1.8 V (low) RSTIN 9 VDD(INTF) I card reset input from the host (active HIGH) OFFN 10 VDD(INTF) O NMOS interrupt to the host (active LOW) with 10 k internal pull-up resistor to VDD(INTF) (See fault detection) GND 11 - supply ground crystal connection 1 XTAL1 12 VDD(INTF) I XTAL2 13 VDD(INTF) O crystal connection 2 VREG 14 VDDP supply Internal supply voltage SAM 15 VDDP I/O DC-to-DC converter capacitor; connected between SAM and SAP; C = 330 nF or 100 nF (see Figure 13) with ESR < 100 m at Freq=100kHz GNDP 16 - supply DC-to-DC converter power supply ground TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 5 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 3. Pin description …continued Symbol Pin Supply Type Description SBM 17 VDDP I/O DC-to-DC converter capacitor; connected between SBM and SBP; C = 330 nF or 100nF (see Figure 13) with ESR < 100 m at Freq=100kHz VDDP 18 VDDP supply Power supply voltage SBP 19 VDDP I/O DC-to-DC converter capacitor; connected between SBM and SBP; C = 330 nF or 100nF (see Figure 13) with ESR < 100 m at Freq=100kHz SAP 20 VDDP I/O DC-to-DC converter capacitor; connected between SAM and SAP; C = 330 nF or 100nF (see Figure 13) with ESR < 100 m at Freq=100kHz VUP 21 VDDP I/O DC-to-DC converter output decoupling capacitor connected between VUP and GNDP; C = 1 F with ESR < 100 m at Freq=100kHz VCC 22 VCC O supply for the card (C1), decouple to GND with 2 220 nF capacitors with ESR < 100 m RST 23 VCC O card reset (C2) CLK 24 VCC O clock to the card (C3) GNDC 25 - supply card signal ground AUX1 26 VCC I/O auxiliary data line to and from the card (C4), internal 10 k pull-up resistor to VCC AUX2 27 VCC I/O auxiliary data line to and from the card (C8), internal 10 k pull-up resistor to VCC I/O 28 VCC I/O data line to and from the card (C7), internal 10 k pull-up resistor to VCC CS 29 VDD(INTF) I Chip Select input from the host (active High) PRESN 30 VDD(INTF) I Card presence contact input (active LOW); if PRESN is true, then the card is considered as present. A debouncing feature of 4.05 ms typical is built in. AUX1UC 31 VDD(INTF) I/O auxiliary data line to and from the host, internal 10 k pull-up resistor to VDD(INTF) AUX2UC 32 VDD(INTF) I/O auxiliary data line to and from the host, internal 10 k pull-up resistor to VDD(INTF) TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 6 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8. Functional description Remark: The ISO 7816 terminology convention has been adhered to throughout this document, and it is assumed that the reader is familiar with this convention. 8.1 Power supply Power supply voltage VDDP is from 2.7 V to 5.5 V All interface signals with the system controller are referenced to VDD(INTF). All card contacts remain inactive during powering up or powering down. Internal regulator VREG is 1.8 V After powering the device, OFFN remains low until CMDVCCN is set high and PRESN is low. During power off, OFFN falls low when VDDP is below the threshold voltage falling. While the card is not activated, CMDVCCN is kept at high level. To save power consumption, the frequency of the internal oscillator (fosc(int)) used for the activation sequences is put in low frequency mode. This device includes a DC-to-DC converter to generate the 5 V, 3 V or 1.8 V card supply voltage (VCC). The DC-to-DC converter is separately supplied by VDDP and GNDP. The DC-to-DC converter operates as a voltage tripler, doubler or follower according to the respective values of VCC and VDDP. Special care has to me made in the selection of the capacitors of the DC/DC converter specially with respect to capacitor value versus voltage and ESR (see Table 7) The operating mode is as follows (see Figure 3): • • • • • • TDA8035 Product data sheet COMPANY PUBLIC VCC = 5 V and VDDP > 3.8 V; voltage doubler VCC = 5 V and VDDP < 3.6 V; voltage tripler VCC = 3 V and VDDP > 3.8 V; voltage follower VCC = 3 V and VDDP < 3.6 V; voltage doubler VCC = 1.8 V and VDDP > 3.8 V; voltage doubler VCC = 1.8 V and VDDP < 3.6 V; voltage tripler All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 7 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8.2 Voltage supervisor VREG vbg VREG VDDP Deep_shutdown VDD(INTF) vbg Poradj vbg 001aan747 Fig 3. Block voltage supervisor The voltage supervisor is used as a power-on reset, and also as supply drop detection during a card session. The threshold of the voltage supervisor is set internally in the IC for VDDP and VREG. The threshold can be adjusted externally for VDD(INTF) using the PORADJ pin. As long as VREG is less than Vth(VREG) + Vhys(VREG), the IC remains inactive whatever the levels on the command lines are. The inactivity lasts for the duration of tw after VREG has reached a level higher than Vth(VREG) + Vhys(VREG). The outputs of the VDDP, VREG and VDD(INTF) supervisors are combined and sent to a digital controller in order to reset the TDA8035. The reset pulse of approximately 5.7 ms (tw = 2048 1/(fosc(int)_Low) is used internally for maintaining the IC in an inactive mode during the supply voltage power-on (see Figure 4 and Figure 5). A deactivation sequence is performed when: • VREG falls below Vth(VREG) • VDD(INTF) falls below Vth(PORADJ) • VDDP falls below Vth(VDDP) TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 8 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface VDDP Vth_vddp_Ih VREG Vt Supervisor outputs vsup X Tw reset X supalarm X Tw 2 Tw Supervisor inputs Deep_shutdown X Oscint X 180 kHz Vbg X 1.2 V OFFN X IC pins debouncing Fig 4. 001aan748 Voltage supervisor VDDP Vth_Vddp_Ih 2.65 V 2.5 V 1.8 V Vth_vddp_hI VREG 1 1 Vsup 2 2 3 100 μs analog delay 3 Supalarm Tw Tw Reset Tw Start debouncing if a card has been inserted during shutdown mode 001aan749 Fig 5. TDA8035 Product data sheet COMPANY PUBLIC Voltage supervisor All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 9 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8.3 Clock circuitry DIGITAL Enclkin clkxtal MUX XTAL 001aan750 Fig 6. Switch external clock To generate the card clock CLK, the TDA8035 can either use an external clock provided on XTAL1 pin or a crystal oscillator connected on both XTAL1 and XTAL2 pins. The TDA8035 automatically detects when an external clock is provided on XTAL1. Consequently, there is no need for an extra pin to configure the clock source (external clock or crystal). The automatic clock source detection is performed on each activation command (CMDVCCN pin falling edge). During a time window defined by the internal oscillator, the presence of an external clock on XTAL1 pin is checked. If a clock is detected, the crystal oscillator is kept stopped, else, the crystal oscillator is started. It is mandatory when an external clock is used, that the clock is applied on XTAL1 before CMDVCCN falling edge signal. The frequency is chosen as fXTAL, fXTAL/2, fXTAL/4 or fXTAL/8 via the pins CLKDIV1 and CLKDIV2. Both selection inputs are not changed simultaneously. A minimum of 10 ns is required between changes on CLKDIV1 and CLKDIV2. The frequency change is synchronous, which means that during transition, no pulse is shorter than 45 % of the smallest period. This ensures that the first and last clock pulse around the change has the correct width. When changing the frequency dynamically, the change is effective for only 10 periods of XTAL1 after the command. The duty cycle on pin CLK is between 45 % and 55 %: • When an external clock is used on XTAL1 pin and fXTAL is used, the duty cycle is between 48 % and 52 %. The subsequent rise and fall times (tr(i) and tf(i)) conform to values listed in Table 7. It has to connect a 56 pF serial capacitor (see Figure 13). • CLK frequency is fXTAL, fXTAL/2, fXTAL/4 or fXTAL/8: It is guaranteed between 45 % and 55 % of the period by the frequency dividers. Table 4. TDA8035 Product data sheet COMPANY PUBLIC Clock configuration CLKDIV1 CLKDIV2 CLK 0 0 fXTAL/8 0 1 fXTAL/4 1 1 fXTAL/2 1 0 fXTAL All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 10 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8.4 I/O circuitry The three data lines I/O, AUX1 and AUX2 are identical. To enter the idle state, both lines (I/O and I/OUC) are pulled HIGH via a 10 k resistor (I/O to VCC and I/OUC to VDD(INTF)). I/O is referenced to VCC, and I/OUC to VDD(INTF) which allows operation with VCC VDD(INTF). The first side on which a falling edge occurs becomes the master. An anti-latch circuit disables the detection of falling edges on the other line, which becomes the slave. After a time delay td(edge), the logic 0 present on the master side is transmitted to the slave side. When the master side returns to logic 1, the slave side transmits the logic 1 during the time delay tpu and both sides return to their idle states. The active pull-up feature ensures fast Low to High transitions. It is able to deliver more than 1 mA to an output voltage of 0.9 VCC on an 80 pF load. At the end of the active pull-up pulse, the output voltage depends on the internal pull-up resistor and on the load current. The current to and from the cards I/O lines is internally limited to 15 mA. The maximum frequency on these lines is 1.5 MHz. TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 11 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8.5 CS control The CS (Chip Select) input allows multiple devices to operate in parallel. When CS is high, the system interface signals operate as described. When CS is low, the signals CMDVCCN, RSTIN, CLKDIV1, CLKDIV2, EN_5V/3VN and EN_1.8VN are latched. I/OUC, AUX1UC and AUX2UC are set to high impedance pull-up mode and data is no longer passed to or from the smart card. The OFFN output is a 3-state output. 8.6 Shutdown mode and Deep Shutdown mode After power-on reset, the circuit enters the Shutdown mode if CMDVCCN input pin is set to a logic high. A minimum number of circuits are active while waiting for the microcontroller to start a session. 1. All card contacts are inactive (approximately 200 to GND). 2. I/OUC, AUX1UC and AUX2UC are high impedance (10 kW pull-up resistor connected to VDD(INTF)). 3. Voltage generators are stopped. 4. Voltage supervisor is active. 5. The internal oscillator runs at its low frequency. A Deep Shutdown mode can be entered by forcing CMDVCCN input pin to a logic-High state and EN_5V/3VN, EN_1.8VN input pins to a logic-Low state. Deep Shutdown mode can only be entered when the smart card reader is inactive. In Deep Shutdown mode, all circuits are disabled. The OFFN pin follows the status of PRESN pin. To exit Deep Shutdown mode, change the state of one or more of the three control pins. Figure 8 shows the control sequence for entering and exiting. DEACTIVATION SEQUENCE CMDVCCN EN_1.8VN EN_5V/3VN Shutdown Mode (internal pin) Shutdown Activation Shutdown Deep Shutdown Activation debounce OFFN PRESN VCC 001aan751 Fig 7. TDA8035 Product data sheet COMPANY PUBLIC Shutdown mode and Deep Shutdown mode All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 12 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8.7 Activation sequence The following sequence then occurs with crystal oscillator (see Figure 8): T = 64 Toscint (freq high) 1. CMDVCCN is pulled low (t0) 2. Crystal oscillator start-up time (t0). 3. The internal oscillator changes to its high frequency and DC-to-DC starts t1 = t0 + 768 Tosc (freq low) 4. VCC rises from 0 to selected VCC value (5 V, 3 V, 1.8 V) with a controlled slope (t2 = t1 + 3T/2) 5. I/O, AUX1 and AUX2 are enabled (t3 = t1 + 10T), until now, they were pulled LOW 6. CLK is applied to the C3 contact (t4 = t3 + ×) with 200 ns < × < 10 × 1/fXtal 7. RST is enabled (t5 = t1 + 13T). Oscint low frequency high frequency CMDVCCN Xtal1 VUP VCC I/O CLK RST t0 ≈ 3 ms T/2 t1 t2 t3 t4 t5 001aan752 Fig 8. TDA8035 Product data sheet COMPANY PUBLIC Activation sequence at t3 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 13 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8.8 Deactivation sequence When a session is completed, the microcontroller sets the CMDVCCN line to the HIGH state. The circuit then executes an automatic deactivation sequence by counting the sequencer back and ends in the inactive state (see Figure 9): 1. RST goes LOW (t11 = t10 + 3T/64) 2. CLK is stopped LOW (t12 = t11 +T/2) 3. I/O, AUX1 and AUX2 are pulled LOW (t13 = t11 + T) 4. VCC falls to zero (t14 = t11 + 3T/2). The deactivation sequence is completed when VCC reaches its inactive state 5. VUP falls to zero (t15 = t11 + 7T/2) 6. VCC < 0.4 V (tde = t11 + 3T/2 + VCC fall time) 7. All card contacts become low-impedance to GND. I/OUC, AUX1UC and AUX2UC remain pulled up to VDD(INTF) via a 10 k resistor. 8. The internal oscillator reverts to its lower frequency. CMDVCCN RST CLK I/O VCC VUP Xtal1 Oscint high frequency low frequency T/2 t10 t11 t12 t13 t14 t15 001aan753 Fig 9. Deactivation sequence 8.9 VCC regulator VCC buffer is able to deliver up to 65 mA continuously at VCC = 5 V and VCC = 3 V, and 35 mA at VCC = 1.8 V. VCC buffer has an internal overload detection at approximately 125 mA. This detection is internally filtered, allowing the card to draw spurious current pulses of up to 200 mA for some milliseconds, without causing a deactivation. The average current value must remain below the maximum. TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 14 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 8.10 Fault detection The circuit monitors the following fault conditions: • • • • short-circuit or high current on VCC Card removal during transaction VDDP or VDD(INTF) or Vreg dropping overheating. There are two different cases (see Figure 10 on page 16): 1. CMDVCCN High (outside a card session): OFFN is Low when the card is not in the reader, and High when the card is in the reader. The supply supervisor detects a supply voltage drop on VDDP and generates an internal power-on reset pulse, but it does not act upon OFFN. The card is not powered-up, so no short-circuit or overheating is detected. 2. CMDVCCN Low (within a card session): OFFN falls Low in any of the previously mentioned cases. As soon as the fault is detected, an emergency deactivation is automatically performed. When the system controller sets CMDVCCN back to High, it senses OFFN again. After a complete deactivation sequence, the system controller sets CMDVCCN back to High and it senses OFFN again. This is to distinguish between a hardware problem or a card extraction. OFFN reverts to High when the card is still present. A bounce can occur on the PRESN signal during card insertion or withdrawal. The bounce depends on the type of card presence switch within the connector (normally closed or normally open), and on the mechanical characteristics of the switch. To prevent this bounce, a debounce function of approximately 4.05 ms (tdeb = 1280 1/(fosc(int)_Low) is integrated in the device. When the card is inserted, OFFN goes High only at the end of the debounce time (see Figure 11 on page 16). When the card is extracted, an automatic deactivation sequence of the card is performed on the first true/false transition on PRESN. OFFN goes Low. TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 15 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface OFFN PRESN RST CLK I/O VCC VUP Xtal1 Oscint high frequency low frequency T/2 t10 = t11 t12 t13 t14 t15 001aan754 Fig 10. Emergency deactivation sequence (card extraction) PRESN OFFN CMDVCCN tdeb tdeb VCC Deactivation caused by cards withdrawal Deactivation caused by short circuit 001aan757 Fig 11. Behavior of OFFN, CMDVCCN, PRESN and VCC TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 16 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 9. Limiting values All card contacts are protected against a short-circuit with any other card contact. Stress beyond the limiting values can damage the device permanently. The values are stress ratings only and functional operation of the device under these conditions is not implied. Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Min Max Unit VDDP power supply voltage Conditions 0.3 6 V VDD(INTF) interface supply voltage 0.3 4.1 V VIH HIGH-level input voltage 0.3 4.1 V 0.3 5.75 V CS, PRESN, CMDVCCN, CLKDIV2, CLKDIV1, EN_1.8VN, EN_5V/3VN, RSTIN, OFFN, PORADJ, XTAL1, I/OUC, AUX1UC, AUX2UC, VDDP, VDD(INTF) I/O, RST, AUX1, AUX2 and CLK Tamb ambient temperature 25 +85 C Tstg storage temperature 55 +150 C Tj junction temperature +125 C Ptot total power dissipation VESD electrostatic discharge voltage 0.45 W 10 +10 kV Human Body Model (HBM) on all other pins 2 +2 kV Machine Model (MM) on all pins 200 +200 V Field Charged Device Model (FCDM) on all pins 500 +500 V Human Body Model (HBM) on card pins I/O, RST, VCC, AUX1, CLK, AUX2, PRESN within typical application 10. Thermal characteristics Table 6. Thermal characteristics Symbol Package name Parameter Conditions Typ Unit Rth(j-a) HVQFN32 in free air with 4 thermal vias on PCB 55 K/W in free air without thermal vias on PCB 63 K/W TDA8035 Product data sheet COMPANY PUBLIC thermal resistance from junction to ambient All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 17 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 11. Characteristics Table 7. Characteristics of IC VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb=25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Supply voltage VDDP power supply voltage 2.7 3.3 5.5 V VDD(INTF) interface supply voltage 1.6 3.3 3.6 V IDDP power supply current - 0.1 3 A - 300 500 A active mode; CLK = fXTAL/2; VCC = +5 V; no load - - 5 mA active mode; CLK = fXTAL/2; VCC = +5 V; ICC = 65 mA - - 220 mA active mode; CLK = fXTAL/2; VCC = +3 V; ICC = 65 mA - - 160 mA active mode; CLK = fXTAL/2; VCC = +1.8 V; ICC = 35 mA - - 120 mA deep Shutdown mode - - 1 A - - 1 A 1.38 1.45 1.52 V 90 100 110 mV 2.15 2.25 2.35 V 90 100 110 mV deep Shutdown mode; fXTAL = stopped Shutdown mode; fXTAL = stopped IDD(INTF) interface supply current fXTAL = stopped; present card Shutdown mode fXTAL = stopped; present card Vth(VREG) threshold voltage on pin VREG internal voltage regulator falling Vhys(VREG) hysteresis voltage on pin VREG Vth(VDDP) threshold voltage on pin VDDP Vhys(VDDP) hysteresis voltage on pin VDDP tw pulse width Vth(L)(PORADJ) LOW-level threshold voltage on pin PORADJ Vhys(PORADJ) hysteresis voltage on pin PORADJ IL leakage current pin VDDP falling external resistors on PORADJ pin PORADJ 3.0 6.5 8.9 ms 0.81 0.85 0.89 V 30 60 90 mV -1 - +1 A 1.62 1.80 1.98 V - - 200 s VREG Vo output voltage tr rise time TDA8035 Product data sheet COMPANY PUBLIC exit of deep Shutdown mode All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 18 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 7. Characteristics of IC …continued VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb=25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit HIGH-level output voltage VDDP=3.3V, VCC = 5 V, ICC < 65 mA DC 5.10 5.60 7.00 V VDDP=3.3V, VCC = 3 V, ICC < 65 mA DC 3.50 3.95 5.00 V VDDP=3.3V, VCC = 1.8 V, ICC < 35 mA DC 5.10 5.60 7.00 V VDDP=5V, VCC = 5 V, ICC < 65 mA DC 5.10 5.80 7.00 V VDDP=5V, VCC = 3 V, ICC < 65 mA DC - 5.00 - V VDDP=5V, VCC = 1.8 V, ICC < 35 mA DC 5.10 5.80 7.00 V HIGH-level output voltage VDDP=3.3V, VCC = 5 V, ICC < 65 mA DC - - 8.20 V VDDP=3.3V, VCC = 3 V, ICC < 65 mA DC - - 6.00 V VDDP=3.3V, VCC = 1.8 V, ICC < 35 mA DC - - 8.20 V VDDP=5V, VCC = 5 V, ICC < 65 mA DC - - 8.20 V VDDP=5V, VCC = 3 V, ICC < 65 mA DC - 5.00 - V VDDP=5V, VCC = 1.8 V, ICC < 35 mA DC - - 8.20 V connected between SAP and SAM (330 nF [4]) with VDDP=3.3v 231 - 429 nF connected between SAP and SAM (100 nF [4]) with VDDP=5v 70 - 130 nF connected between SBP and SBM (330 nF [4]) with VDDP=3.3v 231 - 429 nF connected between SBP and SBM (100 nF [4]) with VDDP=5v 70 - 130 nF connected on VUP(1uF [4]) 700 - 1300 nF VUP (DC-to-DC converter) VOH SAP (DC-to-DC converter) VOH DC-to-DC converter capacitors CSAPSAM CSBPSBM CVUP DC/DC converter capacitance DC/DC converter capacitance DC/DC converter capacitance Card supply voltage (VCC) [1] Cdec decoupling capacitance connected on VCC (220 nF + 220 nF 10 %) 396 - 484 nF Vo output voltage inactive mode; no load -0.1 - +0.1 V inactive mode; Io = 1 mA -0.1 - +0.3 V TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 19 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 7. Characteristics of IC …continued VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb=25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Io output current inactive mode - - 1 mA VCC supply voltage active mode; 5 V card; ICC < 65 mA DC 4.75 5.0 5.25 V active mode; 3 V card; ICC < 65 mA DC 2.85 3.05 3.15 V active mode; 1.8 V card; ICC < 35 mA DC 1.71 1.83 1.89 V active mode; current pulses of 40 nA/s with ICC < 200 mA, t < 400 ns; 5 V card 4.65 5.0 5.25 V active mode; current pulses of 40 nA/s with ICC < 200 mA, t < 400 ns; 3 V card 2.76 - 3.20 V active mode; current pulses of 15 nA/s with ICC < 200 mA, t < 400 ns; 1.8 V card 1.66 - 1.94 V at grounded pin VCC Vripple(p-p) peak-to-peak ripple voltage from 20 kHz to 200 MHz - - 350 mV ICC supply current VCC = 0 V to 5 V, 3 V - - 65 mA VCC = 0 V to 1.8 V - - 35 mA 5 V card 0.055 0.18 0.8 V/s 3 V card 0.040 0.18 0.8 V/s 1.8 V card 0.025 0.18 0.8 V/s connected on pins XTAL1/XTAL2 (depending on specification of crystal or resonator used) - - 33 pF 2 - 27 MHz 0 - 27 MHz -0.3 - +0.3 VDD(INTF) V SR slew rate Crystal oscillator (XTAL1 and XTAL2) Cext external capacitance fxtal crystal frequency fxtal(XTAL1) crystal frequency on pin XTAL1 VIL LOW-level input voltage VIH HIGH-level input voltage tr(i) input rise time TDA8035 Product data sheet COMPANY PUBLIC with 56 pF serial capacitor 0.7 VDD(INTF) - VDD(INTF)+ 0.3 V fCLK = fXTAL1 = 20 MHz on external clock - - 4 ns fCLK = fXTAL1 = 10 MHz on external clock - - 8 ns fCLK = fXTAL1 = 5 MHz on external clock - - 16 ns All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 20 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 7. Characteristics of IC …continued VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb=25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit tf(i) input fall time fCLK = fXTAL1 = 20 MHz on external clock - - 4 ns fCLK = fXTAL1 = 10 MHz on external clock - - 8 ns fCLK = fXTAL1 = 5 MHz on external clock - - 16 ns - - 200 ns 400 ns Data lines (pins I/O, I/OUC, AUX1, AUX2, AUXIUC, AUX2UC) td delay time falling edge on pins I/O and I/OUC or I/OUC and I/O tw(pu) pull-up pulse width fmax maximum frequency on data lines - - 1 MHz Ci input capacitance on data lines - - 10 pF 200 Data lines to the card (pins I/O, AUX1, AUX2); (Integrated 10 k pull-up resistor connected to VCC) Vo output voltage inactive mode; no load 0 - 0.1 V inactive mode; Io= 1 mA 0 - 0.3 V Io output current inactive mode - - 1 mA IOL = 1 mA 0 - 0.3 V IOL 15 mA VCC - 0.4 - VCC V 0.9 VCC - VCC + 0.1 V VCC + 0.1 V at grounded pin I/O VOL VOH LOW-level output voltage HIGH-level output voltage No DC load IOH < -40 A 5 V or 3 V 0.75 VCC IOH < -20 A 1.8 V 0.75 VCC VCC + 0.1 V IOH -15 mA 0 - 0.4 V 0.3 - +0.8 V 0.6 VCC - VCC + 0.3 V VIL LOW-level input voltage VIH HIGH-level input voltage VCC = +5 V VCC = +3 V or 1.8 V 0.7 VCC - VCC + 0.3 V Vhys hysteresis voltage on I/O 30 75 120 mV IIL LOW-level input current on I/O; VIL = 0 - - 600 A ILH HIGH-level leakage current on I/O; VIH = VCC - - 10 A tr(i) input rise time from VIL max to VIH min - - 1.2 s tf(i) input fall time from VIL max to VIH min - - 1.2 s tr(o) output rise time CL < = 80 pF; 10 % to 90 % from 0 to VCC - - 0.1 s tf(o) output fall time CL < = 80 pF; 10 % to 90 % from 0 to VCC - - 0.1 s Rpu pull-up resistance connected to VCC 8 10 12 k Ipu pull-up current VOH = 0.9 VCC, C = 80 pF -8 -6 -4 mA Data lines to the system; pins I/OC, AUX1C, AUX2C (Integrated k pull-up resistor to VDD(INTF)) VOL LOW-level output voltage TDA8035 Product data sheet COMPANY PUBLIC IOL = 1 mA 0 All information provided in this document is subject to legal disclaimers. - 0.3 V © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 21 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 7. Characteristics of IC …continued VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb=25 C; unless otherwise specified Symbol Parameter Conditions VOH HIGH-level output voltage No DC load IOH 40 A; VDD(INTF) >2 V IOH 20 A; VDD(INTF) <2 V Min Typ Max 0.9 VDD(INTF) - VDD(INTF) + 0.1 V 0.75 VDD(INTF) - Unit VDD(INTF)+ 0.1 V 0.75 VDD(INTF) - VDD(INTF)+ 0.1 V VIL LOW-level input voltage 0.3 0.3 VDD(INTF) V VIH HIGH-level input voltage 0.7 VDD(INTF) VDD(INTF) + 0.3 V Vhys hysteresis voltage on I/Ouc 0.05 VDD(INTF) - 0.25 VDD(INTF) V ILH HIGH-level leakage current VIH = VDD(INTF) 10 A IIL LOW-level input current VIL = 0 600 A Rpu pull-up resistance connected to VDD(INTF) 8 10 12 k tr(i) input rise time from VIL max to VIH min - - 1.2 s tf(i) input fall time from VIL max to VIH min - - 1.2 s tr(o) output rise time CL 30 pF; 10 % to 90 % from 0 to VDD(INTF) - - 0.1 s tf(o) output fall time CL 30 pF; 10 % to 90 % from 0 to VDD(INTF) - - 0.1 s Ipu pull-up current VOH = 0.9 VDD, C = 30 pF -1 - - mA inactive state: osc(int)_Low 230 315 430 kHz active state: osc(int)_High 2.0 2.5 3.0 MHz - Internal oscillator fosc(int) internal oscillator frequency Reset output to the card (RST) Vo output voltage inactive mode; no load 0 - 0.1 V inactive mode; Io= 1 mA 0 - 0.3 V Io output current inactive mode - - 1 mA - - 200 ns IOL= 200 A, VCC = +5 V 0 - 0.3 V IOL= 200 A, VCC = +3 V or 1.8 V 0 - 0.2 V IOL = 20 mA (current limit) VCC - 0.4 - VCC V 0.9 VCC - VCC V IOH = -20 mA (current limit) 0 - 0.4 V CL = 100 pF VCC = +5 V and +3 V - - 0.1 s CL = 100 pF VCC = +18 V - - 0.2 s CL = 100 pF VCC = +5 V and +3 V - - 0.1 s CL = 100 pF VCC = +18 V - - 0.2 s at grounded pin RST td delay time between RSTIN and RST, RST enabled VOL LOW-level output voltage VOH HIGH-level output voltage IOH = -200 A tr rise time tf fall time Clock output to the card (CLK) TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 22 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 7. Characteristics of IC …continued VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb=25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit Vo output voltage inactive mode; no load 0 - 0.1 V inactive mode; Io = 1 mA 0 - 0.3 V inactive mode - - 1 mA IOL = 200 A 0 - 0.3 V IOL = 70 mA (current limit) VCC - 0.4 - VCC V 0.9 VCC - VCC V 0 - 0.4 V - - 16 ns Io output current at grounded pin CLK VOL LOW-level output voltage VOH HIGH-level output voltage IOH = -200 A IOH = -70 mA (current limit) tr rise time CL = 30 pF [2] [2] tf fall time CL = 30 pF - - 16 ns fCLK frequency on pin CLK operational 0 - 20 MHz duty cycle CL = 30 pF [2] 45 - 55 % slew rate rise and fall; CL = 30 pF; VCC = +5 V 0.2 - - V/ns rise and fall; CL = 30 pF; VCC = +3 V 0.12 - - V/ns rise and fall; CL = 30 pF; VCC = +1.8 V 0.072 - - V/ns V SR Control inputs (pins CS, CMDVCCN, CLKDIV1, CLKDIV2, RSTIN, EN_5V/ 3VN, EN_1.8VN) [3] VIL LOW-level input voltage 0.3 - +0.3 VDD(INTF) VIH HIGH-level input voltage 0.7 VDD(INTF) - VDD(INTF) + 0.3 V Vhys hysteresis voltage on control input 0.05 VDD(INTF) - 0.25 VDD(INTF) V ILL LOW-level leakage current VIL = 0 - - 1 A ILH HIGH-level leakage current VIH = VDD(INTF) - - 1 A Card presence input (PRESN); PRESN has an integrated pull down resistor [3] VIL LOW-level input voltage 0.3 - +0.3 VDD(INTF) V VIH HIGH-level input voltage 0.7 VDD(INTF) - VDD(INTF)+ 0.3 V Vhys hysteresis voltage 0.05 VDD(INTF) - 0.10 VDD(INTF) V ILL LOW-level leakage current VIL = 0 - - 1 A ILH HIGH-level leakage current VIH = VDD(INTF) - - 5 A - 0.3 V OFFN output (pin OFFN is an NMOS drain with a k pull-up resistor to VDD(INTF)) VOL LOW-level output voltage IOL = 2 mA 0 VOH HIGH-level output voltage IOH = -15 A 0.75 VDD(INTF) - Rpu pull-up resistance 8 10 12 k - 150 - C V Protections and limitations Tsd shutdown temperature TDA8035 Product data sheet COMPANY PUBLIC at die All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 23 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Table 7. Characteristics of IC …continued VDDP = 3.3 V; VDD(INTF) = 3.3 V; fXTAL = 10 MHz; GND = 0 V; Tamb=25 C; unless otherwise specified Symbol Parameter Conditions Min Typ Max Unit IOlim output current limit on pin I/O -15 - +15 mA on pin CLK -70 - +70 mA on pin RST -20 - +20 mA on pin VCC = 5 V or 1.8 V 90 125 160 mA on pin VCC = 3 V 90 160 260 mA on pin VCC = 5 V or 1.8 V 80 115 150 mA on pin VCC = 3 V 80 150 250 mA shutdown current Isd Timing tact activation time see Figure 8 on page 13 1847 - 3390 s tdeact deactivation time see Figure 9 on page 14 35 90 250 s tact activation time time of the window for sending CLK to the card with XTAL1 1992 2690 3653 s tact(start) = t3; see Figure 8 on 2055 page 13 2766 3749 s 4.05 5.55 ms tact(end) = t5; see Figure 8 on page 13 debounce time tdeb on pin PRESN 2.96 [1] To meet these specifications, VCC is decoupled to CGND using two ceramic multilayer capacitors of low ESR with both capacitors having a value of 220 nF. [2] The transition time and the duty factor definitions are shown in Figure 12 on page 24; d = t1/(t1+ t2) [3] PRESN and CMDVCCN are active LOW; RSTIN is active HIGH; for CLKDIV1 and CLKDIV2 see Table 4. [4] Capacitance should not vary more than +- 30% compared to nominal value, taking all parameters into account (temperature, process variation, biasing voltage, etc. Non exhaustive list) tr tf 90% 90% VOH (VOH + VOL) /2 10% 10% t1 VOL t2 fce666 Fig 12. Definition of output and input transition times TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 24 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 12. Application information (1) Place close to the protected pin with good (low resistive) and straight connection to the main ground (2) Place close to the supply pin with good (low resistive) and straight connection to GNDP (3) Place close to TDA8035´s VCC pin with good connection to GNDC (4) Place close to card connector´s C1 (VCC) pin with good connection to GNDC (5) Optional bridge. If not used, R1 must be O and R2 absent (direct connection to VDD(INTF)) (6) GNDP and GNDC are connected to the main ground with a straight and low resistive connection (7) The card connector represented here has a normally closed presence switch (8) DC/DC converter capacitance value: If VDDP=3.3v, C3=C4= 330nF & C5=1uF If VDDP=5.0v, C3=C4= 100nF & C5=1uF Fig 13. Application diagram TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 25 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 13. Package outline HVQFN32: plastic thermal enhanced very thin quad flat package; no leads; 32 terminals; body 5 x 5 x 0.85 mm A B D SOT617-7 terminal 1 index area E A A1 c detail X e1 1/2 e e 9 16 C C A B C v w b y y1 C L 17 8 e e2 Eh 1/2 e 24 1 terminal 1 index area 32 X 25 Dh 0 2.5 scale Dimensions Unit mm 5 mm A A1 b max 1.00 0.05 0.30 nom 0.85 0.02 0.21 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh 0.2 5.1 5.0 4.9 2.2 2.1 2.0 5.1 5.0 4.9 2.2 2.1 2.0 e e1 0.5 3.5 e2 L v 3.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. Outline version References IEC SOT617-7 JEDEC JEITA --- --- sot617-7_po European projection Issue date 10-02-08 10-02-09 Fig 14. Package outline SOT617-7 TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 26 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 14. Soldering For all "Surface mount reflow soldering" information for the SOT617 packaging, utilize the following NXP Semiconductors documentation link: http://www.nxp.com/documents/application_note/AN10365.pdf 15. Abbreviations Table 8. Abbreviations Acronym Description ESD ElectroStatic Discharge 16. Revision history Table 9. Revision history Document ID Release date Data sheet status Change notice Supersedes TDA8035HN v. 3.0 20140625 Product data sheet - TDA8035HN v. 2.1 Modifications: TDA8035HN v. 2.1 Modifications: TDA8035HN v. 2.0 Modifications: TDA8035HN v. 1.1 Modifications: TDA8035HN v. 1.0 TDA8035 Product data sheet COMPANY PUBLIC • • Section 5 “Ordering information”: type TDA8035HN/C1/S1 added Descriptive title changed 20121203 • • • • TDA8035HN v. 2.0 Section 8.1 “Power supply”: updated Table 7 “Characteristics of IC”: updated Figure 13 “Application diagram”: Table note (7) added Product data sheet - TDA8035HN v. 1.1 - TDA8035HN v. 1.0 All text updated to NXP standards 20110706 • - Table 3 “Pin description”: updated 20111220 • Product data sheet Product data sheet Table 7 “Characteristics of IC”: Vth(L)(PORADJ) values updated 20110419 Product data sheet - All information provided in this document is subject to legal disclaimers. - © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 27 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 17. Legal information 17.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 17.2 Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification — The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 17.3 Disclaimers Limited warranty and liability — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. TDA8035 Product data sheet COMPANY PUBLIC Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). NXP does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 28 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Non-automotive qualified products — Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ standard warranty and NXP Semiconductors’ product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 17.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 18. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 29 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 19. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Ordering information . . . . . . . . . . . . . . . . . . . . .3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5 Clock configuration . . . . . . . . . . . . . . . . . . . . . .10 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .17 Table 6. Table 7. Table 8. Table 9. Thermal characteristics . . . . . . . . . . . . . . . . . . 17 Characteristics of IC . . . . . . . . . . . . . . . . . . . . 18 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 20. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Pin configuration HVQFN32 . . . . . . . . . . . . . . . . .5 Block voltage supervisor . . . . . . . . . . . . . . . . . . . .8 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . . . .9 Switch external clock . . . . . . . . . . . . . . . . . . . . . .10 Shutdown mode and Deep Shutdown mode . . . .12 Activation sequence at t3 . . . . . . . . . . . . . . . . . .13 Deactivation sequence . . . . . . . . . . . . . . . . . . . .14 Emergency deactivation sequence (card extraction) . . . . . . . . . . . . . . . . . . . . . . . . . .16 Behavior of OFFN, CMDVCCN, PRESN and VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Definition of output and input transition times . . .24 Application diagram . . . . . . . . . . . . . . . . . . . . . . .25 Package outline SOT617-7 . . . . . . . . . . . . . . . . .26 TDA8035 Product data sheet COMPANY PUBLIC All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2014. All rights reserved. Rev. 3.0 — 25 June 2014 30 of 31 TDA8035 NXP Semiconductors High integrated and low power smart card interface 21. Contents 1 2 2.1 2.2 2.2.1 3 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 10 11 12 13 14 15 16 17 17.1 17.2 17.3 17.4 18 19 20 21 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Protection of the contact smart card . . . . . . . . . 1 Easy integration into your contact reader . . . . . 1 Other. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 7 Power supply . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage supervisor . . . . . . . . . . . . . . . . . . . . . . 8 Clock circuitry . . . . . . . . . . . . . . . . . . . . . . . . . 10 I/O circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 CS control . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Shutdown mode and Deep Shutdown mode . 12 Activation sequence . . . . . . . . . . . . . . . . . . . . 13 Deactivation sequence . . . . . . . . . . . . . . . . . . 14 VCC regulator . . . . . . . . . . . . . . . . . . . . . . . . . 14 Fault detection . . . . . . . . . . . . . . . . . . . . . . . . 15 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Thermal characteristics . . . . . . . . . . . . . . . . . 17 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information. . . . . . . . . . . . . . . . . . 25 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 26 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 27 Legal information. . . . . . . . . . . . . . . . . . . . . . . 28 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 28 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Contact information. . . . . . . . . . . . . . . . . . . . . 29 Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP Semiconductors N.V. 2014. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: [email protected] Date of release: 25 June 2014