HIP9022 Data Sheet PRELIMINARY October 1998 File Number 4509.1 Dual High Speed Laser Driver Features The HIP9022 Dual High Speed Laser Driver is designed to operate with a constant current drain from the power supply. This current defines the laser operating power. The current is accurately controlled in the range of 0.5A to 2A to deliver constant optical power from the laser when used with an external Power FET and Power Sense resistor. The operating circuit allows flexibility in choosing driver current levels. • Dual High Speed Laser Driver with Data Rates up to 2.5MHz Eight S/H circuits are multiplex bus controlled to provide analog data for the dual laser drivers. The bus is updated during the blanking period of the laser printer scan with a data rate up to 2.5MHz. A “thermo-electric-cooler” control circuit provides temperature control of the laser. Two on-chip ESD diodes protect each laser. A principle advantage of the Dual High Speed Laser Driver is accomplished by managing the high currents externally with discrete Power FETs and thereby not forcing large switching currents to exist on the same IC substrate with the precision control circuitry. • 0.5A to 2A Range of Constant Current Source Controlled to 0.1% Full Scale • Low Signal Transients with Controlled Constant Current Switching • Laser Optical Power Controlled to Better than 0.5% • Thermoelectric Cooler (TEC) Circuit to Control Temperature to within 0.25oC • Multiplexed Sample/Hold (S/H) Bus Interface • Serial Diagnostic Bus with Multiplexed Output • High Current ESD Diodes for Laser Diode Protection Applications • Dual Laser Printer Driver Ordering Information PART NUMBER HIP9022AM TEMP. RANGE (oC) 0 to 100 PACKAGE 68 Ld PLCC PKG. NO. N68.95 Pinout NC VDD ESD LASER PS-1 ESD LASER PS-1 ESD SHUNT DRAIN-1 ESD SHUNT DRAIN-1 ESD SHUNT DRAIN-1 ESD LASER GND ESD LASER GND ESD SHUNT DRAIN-2 ESD SHUNT DRAIN-2 ESD SHUNT DRAIN-2 ESD LASER PS-2 ESD LASER PS-2 RLY_IN RLY_OUT V9P HIP9022 (PLCC) TOP VIEW 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VUP1 SG_1 VLOW1 VEE GNDA1 GNDD1 CC1 XTEN1+ XTEN1CTC1-10K CTC1-27K LASERON1B OC1 TECFB1 TECREF1 TECGDR1 TRES1 10 11 12 13 14 15 16 17 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 18 19 20 21 22 23 24 25 26 VUP2 SG_2 VLOW2 GNDA2 GNDD2 CC2 XTEN2+ XTEN2CTC2-10K CTC2-27K LASERON2B OC2 TECFB2 TECREF2 TECGDR2 TRES2 OT2 OT1 NC INVERT RESETB DIAGINB NULLB SB_H NC VIN VCC A3 A2 A1 A0 DIAG NC TECREFR 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 4-1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999 HIP9022 ESD SHUNT DRAIN-1 4 5 3 ESD LASERPS-1 6 7 X ESD SHUNT ESD DRAIN-2 LASERPS-2 65 64 68 67 66 ESD LASER GND GND 2 1 LASER P.S. 3 TO 5V A6 63 PD 62 +12V ESDD1 8 NC 9V REG. V/I REF. VDD V9P 61 V9P RELAY1 RLY_OUT +9V 1µF 9 LASER A4 + 60 - VUP2 1µF VUP1 10 Q3 LASER GATE DRIVE SG_1 11 59 A3 58 + VLOW1 12 VLOW2 - A5 1µF -5V 1µF SG_2 57 GNDA2 11kΩ 13 VEE 56 OTA GATE 11kΩ DRIVE AMP. VCC + - A2 CURRENT MONITOR 1kΩ AMP. + GNDA1 14 GNDD1 15 CC1 16 A1 X10 X IDL GNDD2 55 CC2 54 0.1µF Q2 XTEN2+ RS 0.25Ω - 53 XTEN2- 12kΩ XTEN1+ 17 XTEN1- 18 52 THERM. COMP ON/OFF 51 CTC2-10K 0.02µF CTC2-27K 0.1µF CTC2-10K 19 50 O. C. COMP. CTC1-27K 20 + LASER_ON1B 49 - 30kΩ 21 PU OC2 48 TEC DRIVER (THERMO ELECTRIC COOLER CIRCUIT) OC1 22 TECFB1 23 LASER_ON2B PU TECFB2 TEC P.S. 3V 47 TECREF2 46 AND TECGDR2 TECREF1 24 OVER/UNDER TEMPERATURE COMPARATOR TECGDR1 25 THERMAL RELATED COMPONENTS VDD ESDD2 LD2 RF3V49092 1µF LD1 VCC RLY_IN 45 44 TRES1 26 TRES2 Q1 RFD3055 OR EQUIV. TEC OT2 1.9V LASER DRIVER-1 OT1 27 NC 28 NOTE: PU = 60kΩ PULLUP RESISTOR TO VCC PD = 60kΩ PULLDOWN RESISTOR TO GND = SCHMITT TRIGGER HYSTERESIS VTEST OUT SAMPLE/HOLD SYSTEM + - PD PD 29 INVERT PU 30 PU 31 PU PU 32 33 NULLB RESETB DIAGINB SB_H 34 NC (THERMO-RESISTOR SENSES LASER TEMP., NEG. TEMP. COEF., TEC COOLS LASER.) LASER DRIVER-2 35 36 VIN VCC PU PU PU 37 38 39 40 A3 A2 A1 A0 DIAG +5V 41 42 43 NC TECREFR (TEMP. REF. RESISTOR) 5 - 10kΩ FIGURE 1. HIGH SPEED LASER DRIVER FUNCTIONAL BLOCK DIAGRAM SHOWN IN QUIESCENT P.S. CURRENT TEST MODE 4-2 HIP9022 Pin Descriptions PIN NUMBER SYMBOL 1, 2 ESD LASER GND 3, 4, 5 DESCRIPTION Laser supply and system ground. ESD SHUNT DRAIN-1 Laser diode ESD protection. 6, 7 SD LASER PS-1 Laser power supply ESD protection. 8 VDD Input for 12V power supply. 9 NC No connection. 10 VUP1 Filter capacitor for internally generated shunt gate upper voltage level (1µF). 11 SG_1 Drive output to shunt Power FET gate. 12 VLOW1 13 VEE 14 GNDA1 Analog Ground. 15 GNDD1 Digital Ground. 16 CC1 17 XTEN1+ Times 10 constant current monitor amplifier input from the high side of the sense resistor. 18 XTEN1- Times 10 constant current monitor amplifier input from the low side of the sense resistor. 19 CTC1-10K Thermal compensation short time constant where TTC = External C x 10kΩ. (External C typically equal 0.02µF). 20 CTC1-27K Thermal compensation long time constant where TTC = External C x 27kΩ. (External C typically equal 0.1µF). 21 LASERON1B Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power FET OFF and the Laser ON. These pins have an internal pull-up. 22 OC1 23 TECFB1 Feedback to stabilize the TEC loop. 24 TECREF1 Feedback to stabilize the TEC loop. 25 TECGDR1 Thermo-Electric Cooler Power FET gate drive. 26 TRES1 27 OT1 Laser out of temperature range indication. 28 NC No connection. 29 INVERT High input converts to operation with Pmos Current source and NDmos shunt Power FET external transistors. Low input converts to operation with NDmos Current source and Pmos high side shunt Power FET external transistors. This pin has an internal pull-down. 30 RESETB When RESETB is held low, three reset actions occur. The LASERONB input is defeated to a Laser Off condition. The SG_1, 2 outputs are switched to VLOW when in the INVERT low mode and to VUP when in the INVERT high mode. The TEC amplifier is turned off to switch the TECGDR1, 2 outputs to Ground. This pin has an internal pull-down. 31 DIAGINB Low level activates the diagnostic mode. This pin has an internal pull-up. 32 NULLB 33 SB_H 34 NC No connection. 35 VIN Analog voltage sampled by selected S/H. The input voltage range is 0 to 5V. There is an internal voltage clamp for voltage outside of this range. There is an internal 2 - 3µs filter for noise rejection. 36 VCC Input for 5V power supply. 37 A3 Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1µF). Input for -5V power supply. Gate drive to the current source Power FET. Laser over-current indicator flag. Thermo-Resistor output to ground connection for TEC control. Auto-zeros the S/H amplifier selected by address when held low. This pin has an internal pull-up. Samples the selected address when held low. The setup time for address is <25ns. This pin has an internal pull-up. Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up. 4-3 HIP9022 Pin Descriptions (Continued) PIN NUMBER SYMBOL 38 A2 Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up. 39 A1 Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up. 40 A0 Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up. 41 DIAG 42 NC 43 TECREFER 44 OT2 45 TRES2 46 TECGDR2 Thermo-Electric Cooler Power FET gate drive. 47 TECREF2 Feedback to stabilize the TEC loop. 48 TECFB2 Feedback to stabilize the TEC loop. 49 OC2 50 LASERON2B Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power FET OFF and the Laser ON. These pins have an internal pull-up. 51 CTC2-27K Thermal compensation long time constant where TTC = External C x 27kΩ. (External C typically equal 0.1µF). 52 CTC2-10K Thermal compensation short time constant where TTC = External C x 10kΩ. (External C typically equal 0.02µF). 53 XTEN2- Times 10 constant current monitor amplifier input from the low side of the sense resistor. 54 XTEN2+ Times 10 constant current monitor amplifier input from the high side of the sense resistor. 55 CC2 56 GNDD2 Digital Ground. 57 GNDA2 Analog Ground. 58 VLOW2 Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1µF). 59 SG_2 Drive output to shunt Power FET gate. 60 VUP2 Filter capacitor for internally generated shunt gate upper voltage level (1µF). 61 V9P 62 RLY_OUT 63 RLY_IN 64, 65 ESD LASER PS-2 66, 67, 68 DESCRIPTION Diagnostic output, A 0V - 5V analog signal output limits internally to a range of -0.3V to 5.3V. The output is the channel addressed by A0 - A3. No connection. External resistor to ground with a resistor value equal to the value of the thermo-resistor at the desired laser temperature. (Typically in the 5kΩ to 10kΩ range) Laser out of temperature range indication. Thermo-Resistor output to ground connection for TEC control. Laser over-current indicator flag. Gate drive to the current source Power FET. Filter capacitor bypass for internally generated 9V power source (1µF). Relay output drive from an N-channel FET controls an external relay to switch the Laser power supply or power supply interlock ON/OFF for both Laser Drivers. Relay input control with 5V CMOS logic. A high switches on the relay. This pin has an internal pulldown. Laser power supply ESD protection. ESD SHUNT DRAIN-2 Laser diode ESD protection. 4-4 HIP9022 Absolute Maximum Ratings Thermal Information Maximum Analog Supply Voltage, VDD . . . . . . . . . . . -0.3V to 14V Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Analog Negative Supply Voltage, VEE . . . . . . . . . . . . . 0.3V to -5.5 Maximum Laser Protection Diode Current . . . . . . . . . . 10A, 200ns Thermal Resistance (Typical, Note 1) θJC (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Maximum Operating Junction Temperature, TJ . . . . . . . . . . . 100oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC Operating Conditions VDD Supply Voltage Range, VDD . . . . . . . . . . . . . . 11.4V to 12.6V VCC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . 4.5V to 5.5V VEE Supply Voltage Range, VEE . . . . . . . . . . . . . . . . -4.5V to -5.5V Laser Power Supply Range, VLAS . . . . . . . . . . . . . . . . . . 3V to 5V TEC Power Supply Range, VTEC . . . . . . . . . . . . . . . . . . . 3V to 5V Laser Operating Current Range, IDL . . . . . . . . . . . . . . . . . 0A to 2A TEC Operating Current Range, ITEC . . . . . . . . . . . . . . . . . 0A to 2A Die Characteristics Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . -VEE , Substrate CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TJ = 100οC, VDD = 12V, VCC = 5V, VEE = -5V, INVERT Low (Figure 1 Configuration) Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 9 - V 150 - - oC - - 125 oC 65 - - mA - 25 75 mA POWER SUPPLIES V9P Voltage, No External Load V9P 1µF Tantalum Capacitor to V9P V9P Thermal Shutdown V9P Thermal Shutdown Recovery V9P Current Limiting VDD Power Supply Current IDD VCC Power Supply Current ICC - 1.5 25 mA VEE Power Supply Current IEE -75 -23 - mA LOGIC/DIGITAL INPUTS (A0-A3, NULLB and SB_H, LASERON1B, LASERON2B with 60kΩ Pullup Resistors; INVERT, RESETB, RLY_IN 60kΩ with Pulldown Resistors) Low Level Input Voltage VIL 0 - 1.5 V High Level Input Voltage VIH 3.5 - VCC + 0.3 V VHYS 0.3 - - V Low Level Input Current (Inputs with Pullups) IIL -140 - - µA High Level Input Current (Inputs with Pulldowns) IIH - - 140 µA VG -4 - VCC V Current Monitor Amp. (A1) Gain AVS 9.8 10 10.2 - Current Monitor Amp. Differential Sense Input Range VIN 0 - 500 mV Current Monitor Amp. Input Offset VIO -5 - 5 mV Current Monitor Amp. Common Mode Input Range VIC 0 - 5 V Minimum Hysteresis CONSTANT CURRENT CONTROLLER OTA Gate Drive Amp. (A2) Voltage Output Range SHUNT CURRENT SWITCH CONTROLLER Shunt Gate Output Rise/Fall time Propagation Delay, LASERONB1, 2 to SG_1, 2 Drive Output Voltage 4-5 (Note 2) VUPPER = 2V, VLOWER = -1V, Gate Load = 5000pF, VUP1, 2; 1µF Filter Capacitor to GND, VLOW1, 2; 1µF Filter Capacitor to GND, Unless Otherwise Specified tR /tF tD 10% -90% Rise, 90% -10% Fall - - 20 ns TJ = 100oC - 80 110 ns TJ = -25o C - 60 95 ns VUPPER 0 - VCC V VLOWER -4 - VCC V HIP9022 Electrical Specifications TJ = 100οC, VDD = 12V, VCC = 5V, VEE = -5V, INVERT Low (Figure 1 Configuration) Unless Otherwise Specified (Continued) PARAMETER MIN TYP MAX UNITS IDRSW -1 - 1 A fSC 0 - 2.5 MHz Low Level Input Voltage VIL 0 - 1.5 V Low Level Input Current IIL -140 - - µA High Level Input Voltage VIH 3.5 - VCC + 0.3 V VHYS 0.3 - - V VIN 0 - VCC - 0.2 V Minimum Sample/Hold Pulse Width - 10 - µs Droop Rate, Constant Current Addresses #’s 1, 2 - - 0.006 V/s Droop Rate, Other Addresses #’s 3 - 8 - - 0.06 V/s Maximum Analog Multiplexing Frequency - - 30 kHz Driver Maximum Output Current Shunt Controller Switching Frequency SYMBOL TEST CONDITIONS ANALOG SAMPLE/HOLD AMPLIFIERS Minimum Hysteresis Analog Input Voltage Range DIAGNOSTIC OUTPUT (DIAG Output) Voltage Follower Voltage Range VO 0 - VCC - 0.2 V Voltage Follower Maximum Clamp Voltage VCL - - VCC + 0.3 V - 140 - % O. C. (OVER CURRENT) COMPARATOR (OC1, 2 Outputs) Threshold (%) O.C. Detection Programmed Current as Ref. Output Voltage, Low Level VOL 0 - 1.5 V Output Current, Low Level IOL - 12 - mA Output Voltage, High Level VOH 3.5 - VCC - 0.5 V Output Current, High Level IOH - 4 - mA VREFR 1.71 1.9 2.09 V VTECG 0 - 9 V TEC REF. RESISTOR AND DRIVE OUTPUT TECREFR Output Voltage to Reference Resistor TECGDR1, 2 Drive Output Voltage OVER/UNDER TEMPERATURE COMPARATOR (To OT Output) Under Temp. Limit TLOW 2.07 2.1 2.13 V Over Temp. Limit THIGH 1.67 1.7 1.73 V Output Voltage, Low Level VOL 0 - 1.5 V Output Current, Low Level IOL - 12 - mA Output Voltage, High Level VOH 3.5 - VCC - 0.5 V Output Current, High Level IOH - 4 - mA IRLY - - 30 mA rDS(ON) - 20 - Ω - - 2 V - - 1 µA RELAY DRIVER Driver Output Current Drain to Source Resistance LASER PROTECTION DIODES See Figure 1 Maximum Diode Forward Voltage Drop Maximum Reverse Diode Current VLDX, VESDX ILDX 10A Peak Current NOTE: 2. The drive control sets the high and low voltages to the gate of the Power FET driver (shunt switch). Both the upper and lower levels are set by values held in two of the sample/hold amplifiers. External capacitors at VUP1, 2 and VLOW1, 2 are required for stabilization. 4-6 HIP9022 Address, Timing and Waveforms DIGITAL CONTROL ADDRESS NUMBERS #11 to 14 INT. TEST S/H #1 to 8 #1 to 8 TEST NULL OR S/H #1 to 8 #9 or 10 #1 to 8 (NULL OR S/H) #15 (RESET) SAMPLE (SH_B INPUT) NULLB INPUT VIN INPUT DIAGNOSTIC (DIAGINB INPUT) FIGURE 2. ADDRESS WITH SAMPLE, NULL, VIN AND DIAGONAL WAVEFORMS TABLE 1. HIP9022 ADDRESS MAP A3 A2 A1 A0 ADDRESS NO. FUNCTION TYPE 0 0 0 0 1 ANALOG VIN(DL) Voltage for Constant Current Level, Laser Driver #1 0 0 0 1 2 ANALOG VIN(DL) Voltage for Constant Current Level, Laser Driver #2 0 0 1 0 3 ANALOG VLOWER Level, Laser Driver #1 0 0 1 1 4 ANALOG VLOWER Level, Laser Driver #2 FUNCTION NAME 0 1 0 0 5 ANALOG VUPPER Level, Laser Driver #1 0 1 0 1 6 ANALOG VUPPER Level, Laser Driver #2 0 1 1 0 7 ANALOG VIN(DL) Thermal Compensation Level, Laser Driver #1 0 1 1 1 8 ANALOG VIN(DL) Thermal Compensation Level, Laser Driver #2 1 0 0 0 9 DIGITAL Test Mode: S/H Amp, Auto Zero Null Voltage (Note 4) 1 0 0 1 10 DIGITAL Test Mode: S/H Amp Output Voltage (Note 4) 1 0 1 0 11 DIGITAL Test Mode: Set VUP and VLOW Amps to Three-State (Note 4) 1 0 1 1 12 DIGITAL VLOW#1 Set to Positive Output (Default is Negative) 1 1 0 0 13 DIGITAL VLOW#2 Set to Positive Output (Default is Negative) 1 1 0 1 14 DIGITAL Thermal Compensation Activated (Default is Deactivated) 1 1 1 0 15 DIGITAL Reset Digital Address (9-14) to Default State 1 1 1 1 16 DIGITAL Idle Condition (S/H Pin Defeated) (Note 3) NOTES: 3. The Idle address is protective in that SB_H input noise cannot disturb the chip if the Idle address is selected; also, the Address inputs are High (selecting Idle state) if the pins are open. 4. Address Numbers 9 - 11 are shaded to indicate test mode conditions and are shown for information only. These addresses are used in original production testing and not required for user applications. However, note that Address No. 15 will force a reset for Address Numbers 9 - 14. 5. Digital Programming: To set the digital addresses, only the proper digital address and a negative pulse >100ns on SB_H is needed. To reset the digital addresses to the default states, Address 15 and a SB_H pulse >100ns is needed. Normally the digital addresses will be set first, and the analog addresses programmed next. The test modes, Address Numbers 9 - 11, will normally only be used during factory testing. An address 15 Reset should normally precede most programming in order to assure that the digital address states begin in their default state. Otherwise, the digital address states will be undefined because there is no power-up-reset. 6. Analog Programming: To program the eight S/H circuits, addresses of 0-5V analog signal on VIN and negative pulses on NullB (10µs) and SB_H (20µs) pins are needed. The NullB pulse is valid only during the SB_H pulse and should occur during the first half of the SB_H pulse. The S/H amplifier is auto-zeroed for zero offset when both NullB and SB_H are low. The input VIN is captured on the S/H storage capacitor during SB_H low. 7. The Diagnostic mode reads map addresses 1 - 8 via the DIAG output when DIAGINB is low. 4-7 HIP9022 Circuit Block Descriptions Laser Drive Circuitry In Figure 3, the gate of the external current source Power FET, Q2 is driven via the Operational Transconductance Amplifier (OTA), A2 on the IC. The voltage on the current sense resistor, RS in the source of the Power FET is monitored by a X10 gain of the feedback amplifier, A1. The stability of the current loop is established with an external 0.1µF capacitor to ground at the gate of the Power FET. The sampled voltage range is 0 to 0.5V when the proper value of sense resistor, RS is chosen (typically 0.25Ω for 2A). The OTA, A2 compares the X10 gain signal to a 0 to 5V reference signal from an on-chip Sample and Hold (First S/H) circuit. The Q2 drain current (Laser Drive current), IDL is: V IN ( DL ) I DL = ------------------------( R S × 10 ) (EQ. 1) where VIN(DL) is the programmed VIN for the First S/H voltage reference signal. The S/H reference for the Laser Drive Current current is updated with other multiplexed S/H circuits from a serial bus and an off-chip D/A converter. Laser constant current is fully controllable by the multiplex analog S/H bus, allowing accurate calibration of the laser output and corrections as the laser ages. In Figure 1, the laser drive current from Q2 is digitally switched to either flow through or is shunted around the laser diode by switching the external Shunt Power FET, Q3 on or off. The gate of the Shunt FET is switched between two voltages (Upper and Lower) which are provide by 2nd and 3rd S/H circuits. These Shunt FET gate drive levels are fully programmable via the multiplexed analog S/H bus. By adjusting these levels to account for the laser power supply, the Shunt FET threshold and channel resistance; minimum Shunt FET gate drive power levels can be established. The Upper and Lower gate voltage driver circuits are two high current OTA amplifiers with two filter capacitors. The upper voltage is programmable in the 0V to VCC range at the input of amplifier A4. The lower voltage is programmable in the range of -4V to VCC. The -4V extension is accomplished by an optional on-chip voltage inverter circuit. The input to amplifier A3 is either direct from the S/H input or inverted by amplifier A5. A laser cools after it has been off for a period of time and is more efficient when it is turned-on. Compensation for the increased efficiency is made by slightly reducing the current level of the constant current source FET. The level will be reduced by a programmable amount of 0 to 5% of full scale. The programmable amount is fixed by the level of compensation to S/H addresses 7 and 8 (see Table 1). The percent of modulation (change) in drive current is calculated as follows: V IN ( TC ) Modulation °⁄ = --------------------- × 5°⁄ ° ° V IN ( DL ) For example, if we control the Laser Drive current with 2V programmed with address 1 and 2 for the First S/H’s, given that VIN(DL) = 2V and RS = 0.25Ω. Then, from EQ. 1, IDL = VIN(DL)/(RS x 10) = 2/(0.25 x 10) = 0.8A. If 2V is programmed to addresses 7 and 8 as Thermal Compensation, VIN(TC) for the 4th S/H’s, then, Mod.% = (2/2) x 5% = 5%. In Figure 3, the correction is applied from the output of the Thermal Compensation circuit (where the current is 2V/20kΩ = 0.1mA) to the input of amplifier A2. The 0.1mA is forced into the 1kΩ resistor (and the low Z output of A1) to increase the voltage at the inverting input of A2 by 0.1V or 5% of the +VIN(DL) input (2V) to A2. The modulation input is limited by the 0 to VCC input range of S/H maximum VIN. Input Data Q2 A2 + 1kΩ 0.1µF CC2 54 A1 + X10 12kΩ XTEN2+ - 53 O. C. COMP. + RS 0.25Ω XTEN2OC2 49 30kΩ VOLT. TO CURRENT 27kΩ 51 CTC2-27K 0.1µF + THERMAL COMP. Thermal Compensation 4-8 55 - The maximum laser on-off switching speeds are dependent on the selection of Shunt FETs. A Harris dual complementary MOSFET, RF3V49092 or RF3S49092 has been designed specifically for this application. With the constant current set at 0.8A, a typical laser switching speed of 20ns has been measured. A 4th S/H circuit is used to set the amplitude of an optional thermal compensation signal which can be used to modulate the constant laser current source as a two pole filtered effect of the laser on-off data. This feature may be disabled when it is not required. This circuit is designed to compensate for the temperature variations in the laser as the laser is turned on and off. The bypass capacitors at the Thermal Comparator (CTCx-10K, CTCx-27K) represent the respective poles for the filter. (EQ. 2) 10kΩ VOLT. TO CURRENT 52 CTC2-10K 0.02µF 20kΩ S/H SYS FIGURE 3. LASER CONSTANT CURRENT SOURCE DRIVER WITH OVER CURRENT DETECTION AND THERMAL COMPENSATION HIP9022 Both analog and digital data is input to control the action of the dual laser driver. Address codes and input data are described in the Table 1 Address Map. Digital data is normally entered first, followed by the analog data via the multiplexed analog bus which updates the S/H stored voltage levels. Four bit digital addresses to pins A3, A2, A1 and A0 are decoded to define the programming functions for data input. It is important to note that Address 15 is a reset for Addresses 9 - 14 and should be performed as the first step in programming because there is no power-onreset on-chip. resistor and drives the gate of the TEC FET driver. As such, the TEC circuit senses the thermo-resistor input as a measure of the laser temperature and the TEC drive is adjusted to maintain a stable Laser temperature slightly below the ambient temperature. An external Power FET is needed to provide the high TEC driver currents. An out of range temperature output for each laser is also provided. Laser Protection Diodes Another feature included on the chip is two high current ESD diodes which, in the printer system, are used to protect the Laser Diodes from ESD damage. Another component of Laser protection in printer systems are relays to disconnect the Lasers when in a non-operating mode. For this purpose, a single relay driver is included. Diagnostic Output Data For the purpose of monitoring on-chip signals, the multiplexed bus can be used to output signals (at the DIAG pin) via an analog diagnostic amplifier. This mode has the capability to monitor the multiplexed output of four (0-5V) analog signals for each laser channel. Note that the diagnostic information at the VLOW (Amplifier A3) output is 2:1 resistor divided to +5V (VCC) to return this signal to a 0 to 5V range. To minimize noise problems the monitoring function is normally performed during the laser scan for only one signal per scan. In addition, there are 3 test modes which allows the bus to present analog signals for testing the performance of the eight S/H circuits. Over Current Flag Output (OC1, OC2) Over-current detection is also included on-chip. The circuit of Figure 3 shows the over current detection circuit. For each laser source current driver, the over current monitor compares the S/H input of amplifier A2 to the output of amplifier A1. If the output voltage of A1 exceeds the input of A2 by 40%, then an over current state exists and the OC output will go high. Invert Option An INVERT input reconfigures the device such that the constant current source can be high side instead of the normal low side. This provides functionality for driving laser diodes in a common cathode configuration as opposed to the normal common anode configuration. The INVERT must be low (or open with the internal pull down) for the Figure 1 circuit. Thermo-Electric-Cooler (TEC) Circuitry Figure 4 shows the Thermal Electric Cooler (TEC) drive circuit with an external reference resistance, a thermoresistor to sense temperature plus feedback components for stable drive. There is a thermo-resistor reference input on the chip for monitoring the laser's temperature via a 5-10kΩ thermo-resistor which must be mounted near the laser. A reference voltage on the external reference resistor is established by a current from a stable bias source. This current is mirrored to the thermo-resistor (one for each laser driver system). A comparator senses the voltage across the reference resistor versus the voltage across the thermo- Reset Action The RESETB (active low) controls three things: (1) The TEC driver is turned off. (2) The Shunt driver is turned on to turn off the laser. (3) The Constant current driver is turned off. + CURRENT MIRROR 1 1.9V 48 + - + 47 - + TECFB2 2 TECREF2 - + 46 45 Q2 TECGDR2 LASER2 TRES2 TEC O.T. TEMP. COMP. 44 THERMORESISTOR (TEMPERATURE SENSOR) OT2 U.T. 43 TECREFR REFERENCE RESISTOR THERMALLY COUPLED COMPONENTS FIGURE 4. TEC (THERMAL ELECTRIC COOLER) CIRCUIT WITH REFERENCE RESISTOR AND THERMAL RESISTOR SENSOR OF LASER TEMPERATURE 4-9 HIP9022 Plastic Leaded Chip Carrier Packages (PLCC) 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER N68.95 (JEDEC MS-018AE ISSUE A) 0.042 (1.07) 0.056 (1.42) 0.004 (0.10) C 0.025 (0.64) R 0.045 (1.14) 0.050 (1.27) TP C L D2/E2 C L E1 E D2/E2 VIEW “A” A1 A D1 D 0.020 (0.51) MAX 3 PLCS 0.020 (0.51) MIN 68 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES MILLIMETERS SYMBOL MIN MAX MIN MAX NOTES A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.985 0.995 25.02 25.27 - D1 0.950 0.958 24.13 24.33 3 D2 0.441 0.469 11.21 11.91 4, 5 E 0.985 0.995 25.02 25.27 - E1 0.950 0.958 24.13 24.33 3 E2 0.441 0.469 11.21 11.91 4, 5 N 68 68 6 Rev. 2 11/97 SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. 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