[ /Title (AN98 62) /Subjec t (ACPI Contro llers for Advan ced Compu ter System s (HIP65 00BEV AL1, HIP65 02BEV AL1)) /Autho r () /Keyw ords (Intersi l Corpor ation, semico nduCto r, acpi, power manag ement, instantl y ACPI Controllers for Advanced Computer Systems (HIP6500BEVAL1, HIP6502BEVAL1) TM Application Note July 2000 AN9862.1 Author: Bogdan M. Duduman Introduction ‰ Connect the Input Power Supply The Advanced Configuration and Power Interface specification (ACPI; [1]), written by a consortium representing Intel, Microsoft and Toshiba, attempts to evolve the current collection of power management methods and configuration interfaces into a well-specified and unified power management and configuration mechanism. The key objective in the ACPI specification is to transfer all control of power management and configuration functions to the operating system, thus enabling Operating System Directed Power Management (OSPM). ACPI-compliant systems will benefit from a robust interface for configuring motherboard devices, a versatile power management interface enabling a wide variety of solutions with full operating-system support, and not lastly, a realm of new, intelligent possibilities added to the already broad span of PC uses. Ensuring that the supply is not plugged into the mains, or that the AC switch is off (if provided), connect the main ATX output connector to J1. The HIP6500B/02B ICs are to be used in conjunction with a second integrated circuit to provide a complete ACPIsanctioned motherboard power regulation solution. The HIP6500B/HIP6020 and HIP6502B/HIP6020 chip sets (HIP6021 can substitute HIP6020 in either chip set) produce the processor core, GTL bus, memory controller hub, and AGP 4x voltages, as well as the 3.3V standby, 2.5V clock, SDRAM/RDRAM memory (or both, simultaneously), 3.3V and 5V dual voltage planes necessary for a complete PIIICamino (or equivalent) system implementation. [2, 3, 5, 6] Quick Start Evaluation Important! Given the specialized nature of the HIP6500B and HIP6502B, the HIP6500B/02BEVAL1 boards are meant to be evaluated only with an ATX power supply. Furthermore, only an ACPI-ready ATX supply can be used to power-up the evaluation boards (720mA capability on 5VSB output; ATX Specification v2.02, [4]). Standard laboratory power supplies are not suitable for powering up this evaluation board. Circuit Setup ‰ Set Up JP1, JP2, and JP2, JP3 Before connecting the input ATX supply to the HIP6500B/02BEVAL1 board, consult the circuit schematic and data sheets and set the JP1 and JP2 configuration jumpers on the HIP6500BEVAL1, and JP2 and JP3 jumpers on the HIP6502BEVAL1 according to the configuration you wish to emulate. These particular configurations are latched in during certain times, but can be subsequently changed at certain times. See HIP6500B/02B data sheets for information on the available configurations and how to set them. 1 ‰ Connect the Output Loads Connect typical standby loads to all the evaluation board’s outputs. Consult Table 1 for maximum loads supported by the design of the HIP6500B/02BEVAL1 in the configuration received; consult the ‘HIP6500B/02BEVAL1 Modifications’ chapter for information on modifying the evaluation board to meet your special needs. ‰ Set Start-Up State (Active Is Recommended) If start-up in active state (S0/S1/S2) is desired, ensure both ‘S3’ (SW2) and ‘S5’ (SW3) switches are in the off position (away from ‘S3’ or ‘S5’ marking). Ensure the ‘ATX ON’ switch is also in the off position. Set either the ‘S3’ or the ‘S5’ standby switch for start-up in either of the standby states. IMPORTANT: only one switch needs to be actuated, so select the standby state by turning on the switch with that name - the signal conditioning circuitry ensures correct S3 and S5 pin stimulation. Operation ‰ Provide Bias Voltage to the Board Plug the ATX supply into the mains. If the supply has an AC switch, turn it on. The ‘5VSB’ (LP4) LED should light up, indicating the presence of 5V standby voltage on board. ‰ Examine Start-Up Waveforms Sleep state start-up is immediate following application of bias voltage. Using an oscilloscope or other laboratory equipment, you may study the ramp-up and/or regulation of the controlled voltages, according to the specific JP1/JP2, or JP2/JP3 configuration previously set and the specific standby state selected. For start-up into an active state (standby switches set off prior to application of bias voltage), flip on the ‘ATX ON’ switch (SW1). This will turn on the main ATX outputs and the HIP6500B/02B will start up into active state. Once turned on, SW1 needs not be turned off until bias is removed from the board. ‰ Examine Output Quality Under Varying Loads In either state (sleep or active) vary the output loads to simulate computer loads typical of the specific operating state the circuit is in. CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000 Application Note 9862 ‰ Examine State Transitions For subsequent transitions into standby states, leave the main ATX outputs enabled (SW1 on); the circuit will automatically turn them off when entering a standby state. To enter a standby state, turn on the respective switch. The ‘S3’ LED will light up to indicate S3 standby state, while S5 state will illuminate both ‘S3’ and ‘S5’ LEDs. However, the HIP6500B/02B will ignore any illegal transition requests, such as from S3 state to S5 state or vice versa, as shown in Figure 1. FULL ACTIVE S0 S1, S2 IDLE ACTIVE STATES SLEEP STATES S3 down the IC quickly. To protect the external switches it is strongly recommended that JP3/1 FAULT LATCH jumper is shunted throughout the operation of the board. Configuring Sleep State Support Sleep state support on the 3.3VDUAL and 5VDUAL outputs of the HIP6500BEVAL1 are user-configurable through jumpers JP1 and JP2. Sleep state support on the 2.5VMEM, 3.3VMEM, and 5VDUAL outputs of the HIP6502BEVAL1 are user-configurable through jumpers JP2 and JP3 (consult data sheets for sleep support details). The configurations can be changed prior to 5VSB application, during active state operation (additionally, during S4/S5 operation for HIP6502B’s memory selection), as well as during chip shutdown (PB1 pressed). During all other times, the configurations are internally latched and any changes in the MSEL, EN3VDL and EN5VDL pins’ logic status are ignored. HIP6500B/02BEVAL1 Reference Design General STR S4, S5 STD, SOFT-OFF LEGEND: STR - SUSPEND TO RAM STD - SUSPEND TO DISK - LEGAL TRANSITION - ILLEGAL TRANSITION (REQUEST IGNORED BY THE HIP6500B/02B) FIGURE 1. HIP6500B/02B LEGAL/ILLEGAL STATE TRANSITIONS Fault Handling In case of a fault condition (input or output under-voltage such as a suddenly shorted output or a loss of an input power rail), the FAULT pin asserts a logic ‘high’, shutting down the ATX supply’s main outputs. To recover from such a shutdown, press the ‘SHUTDOWN/CLEAR FAULT’ button (PB1). Depressing PB1 will reset the IC and initiate a softstart sequence, thus clearing the FAULT, and enabling the main ATX outputs. If jumper JP3/1(respectively, JP3 on the 6500 and JP1 on the 6502 evaluation board) “FAULT LATCH” is removed, the FAULT output will not latch the circuit. The circuit appears to latch off because the FAULT signal shuts down the ATX supply, cutting off the input supply to the faulting output, and thus keeping it from ever recovering from the fault condition. However, it is not recommended to test the circuit against output under-voltages (output short-circuits) with the fault latch jumper removed. Due to the very slow response of the ATX supply in response to a shutdown request, the external N/P-MOS switches (Q4, Q5, Q6, and Q7) in use at the time of testing could fail as a result of sustained over-current through the drain-source junction and bond wires. The FAULT latch circuit acts on the SS pin directly, shutting 2 Both evaluation boards are built on 2-ounce, 4-layer, printed circuit board (see last six pages of this application note for layout plots). Most of the components specific to the evaluation board alone, which are not needed in a real computer application, are placed on the bottom side of the board. Assuming the input supplies and the controlled output planes have their own on-board filtering (capacitors), the only components required to implement this ACPI 5-voltage controller/regulator solution are contained within the white rectangle surrounding the HIP6500B/02B on the top side of the board. All the additional circuitry contained on board has the role of duplicating the computer environment the chip would operate in. Since this additional circuitry would clutter and detract from the readability of the schematic, most of it was grouped in two blocks, named “SIGNAL CONDITIONING” and “FAULT LATCH” (see evaluation board schematics). The boards also contain a serpentine resistor which occupies about 1/3 of both top and bottom sides of the board. The ATX supply requires some minimum loading on the +5V output in order to stay active; lack of this minimum loading causes the ATX to shut down all its outputs, except +5VSB. This minimum load is specified as 1A, but most supplies will stay active with as little as 400-500mA. The embedded resistor is designed to draw a current of about 1A (typical). If the current draw is insufficient to keep the power supply active, try reducing the value of the embedded resistor. Shorting out the W1 footprint, on the back side of the board, effectively shorts out 1/4 of the resistive trace, increasing the current draw by 30%. Similarly, shorting out W2 reduces the trace by 50%, thus doubling the current draw from the +5V output. If either W1 or W2 are shorted, it is advised that active state operation time be reduced as to avoid severe overheating of the board (in case the 5V Application Note 9862 current draw exceeds 1A). For most, if not all cases, neither W1 nor W2 need be shorted. Design Envelope Although different computer systems might have different requirements, the HIP6500BEVAL1 and HIP6502BEVAL1 boards were designed to meet the maximum output loading described in Tables 1 and 2. Note the fact that the addition of all the sleep state output currents exceeds the typical ATX power supply 5VSB output capability (725mA). Real-life sleep state current requirement on each of the outputs could be lower, and their maximums should rarely all occur simultaneously. Output tolerances and current ratings (with the exception of the 2.5VCLK, 3.3VSB, and 2.5/3.3VMEM when operating on internal pass transistors) can be adjusted by properly selecting the components external to the HIP6500B/02B. TABLE 1. HIP6500BEVAL1 MAXIMUM OUTPUT LOADING ACTIVE STATES OUTPUT VOLTAGE 2.5VCLK 2.5/3.3VMEM 3.3VSB 3.3VDUAL 5VDUAL SLEEP STATES TOL. (STATIC/ dIOUT/dt DYNAMIC) IOUT dIOUT/dt IOUT 500mA 0.1A/μs 0 0 5% / 5% 4A 1A/μs 250mA (Note) 1A/μs (Note) 5% / 9% 150mA 0.1A/μs 50mA 0.1A/μs 5% / 5% 3A 0.2A/μs 600mA 0.2A/μs 9% / 9% 2.5A 0.1A/μs 200mA 0.1A/μs 9% / 9% HIP6500B/02BEVAL1 Performance Figures 2 through 6 depict the evaluation board’s performance during a few typical operational situations. To simulate minimum loading conditions, unless otherwise specified, the outputs were loaded with 65Ω resistive loads. Sleep-State Start-Up Figure 2 shows a typical HIP6500BEVAL1 start-up into S3 sleep state while all outputs are enabled (EN3VDL = 0, EN5VDL = 1). As 5VSB is applied to the board, SW1 and SW3 are off, while SW2 is on. At time T0 the input supply exceeds the power-on-reset (POR) threshold. Three milliseconds afterwards, at time T1, the soft-start clamp is removed and the 3.3VSB output starts to ramp up toward its target value, which it reaches at time T2. As its ramping ends shortly after bringing up this first output, the soft-start voltage is quickly brought down and prepared for a second soft-start designed to bring up the remainder of the controlled voltages that are supported in this configuration and state. This second ramp-up begins at time T3 and ends at time T4. The 5VDUAL output has a slightly different rampup than the remainder of the output voltages. The 5VDUAL output is not actively regulated, as is the case with the 2.5VMEM and 3.3VDUAL outputs in S3, but rather switched on through a P-MOS or PNP switch. An error amplifier is thus provided for the 5VDUAL output just for the purpose of providing a smooth, controlled output voltage rise. This error amplifier uses a different, soft-start derived, ramp signal to achieve the controlled rise of the output. NOTE: S3 State Only. TABLE 2. HIP6502BEVAL1 MAXIMUM OUTPUT LOADING IOUT dIOUT/dt IOUT dIOUT/dt TOL. (STATIC/ DYNAMIC) 2.5VCLK 500mA 0.1A/μs 0 0 5% / 5% 2.5VMEM 4A 1A/μs 250mA (Note) 1A/μs (Note) 5% / 9% 3.3VMEM 4A 1A/μs 250mA (Note) 1A/μs (Note) 5% / 9% 3.3VDUAL/ 3.3VSB 3A 0.2A/μs 600mA 0.2A/μs 9% / 9% OUTPUT VOLTAGE 5VDUAL SLEEP STATES 5VSB 5VDUAL 3.3VSB 1.00V/DIV ACTIVE STATES 3.3VDUAL 2.5VMEM 2.5VCLK GND> 2.5A 0.1A/μs 200mA 0.1A/μs 9% / 9% 10ms/DIV T0 T1 NOTE: S3 State Only. The maximum current supported on the 2.5VMEM output (systems employing RDRAM memory) is as high as 7-8A. From a thermal performance perspective, do not operate the evaluation board for extended periods of time at output current levels exceeding the design envelope, as detailed in Tables 1 and 2. 3 T2 T3 T4 FIGURE 2. HIP6500BEVAL1 START-UP IN SLEEP STATE (S3) WITH ALL OUTPUTS ENABLED Application Note 9862 Figure 3 shows a typical HIP6502BEVAL1 start-up into S3 sleep state while all outputs are enabled (MSEL = open, EN5VDL = 1). The start-up sequence is similar to that of the HIP6500BEVAL1 board, with the difference that the new 3.3VDUAL/SB output precedes all the other outputs, and the 3.3VMEM output replaces the 3.3VDUAL. 12VIN (2V/DIV) 5VDUAL 1.00V/DIV 3.3VSB 3.3VDUAL 2.5VCLK 5VSB 2.5VMEM 5VDUAL 1.00V/DIV 3.3VDUAL/SB GND> 10ms/DIV 3.3VMEM 2.5VMEM T0 T1 T2 FIGURE 4. HIP6500BEVAL1 START-UP IN ACTIVE STATE (S0, S1) WITH ALL OUTPUTS ENABLED 2.5VCLK GND> 10ms/DIV T0T1 T4 T2 T3 FIGURE 3. HIP6502BEVAL1 START-UP IN SLEEP STATE (S3) WITH ALL OUTPUTS ENABLED Figure 5 shows the same start-up sequence into an active state (S0, S1) on the HIP6502BEVAL1 evaluation board. Except for the noted different output use and designator differences, the start-up sequences of the boards are extremely similar. Active-State Start-Up 4 12VIN (2V/DIV) 5VDUAL 3.3VDUAL/SB 1.00V/DIV Figure 4 also shows a start-up sequence, but this time into an active state (S0, S1). As the enable pins only configure the sleep state voltage support, this start-up sequence will be the same, regardless of EN3VDL and EN5VDL status. In Figure 4, SW1, SW2 and SW3 are all off and 5VSB is applied to the HIP6500BEVAL1 board. Active state operation is enabled by switching on SW1, a few milliseconds before T0. Invariably, the 3.3VSB output is brought up shortly after 5VSB is applied to the IC, and it can be seen present at the time the main ATX outputs are coming up (T0). At time T0, the input voltages (3.3V, 5V, 12V) exceed the under-voltage thresholds (12V shown, only) and the internal 25ms (typical) timer is initiated. Note the typically poor regulation of the ATX supply resulting in a 10% overshoot at start-up (T0). Between T0 and T1, the 3.3VDUAL and 5VDUAL outputs undergo a quasi soft-start, due to conduction through the body diodes of the active NMOS switches (Q4 and Q6). At time T1 the timer expires and the two N-MOS transistors are turned on; simultaneously, the 2.5VMEM and 2.5VCLK outputs begin a soft-start cycle, reaching regulation limits at time T2. 3.3VMEM 2.5VCLK 2.5VMEM GND> 10ms/DIV T0 T1 T2 FIGURE 5. HIP6502BEVAL1 START-UP IN ACTIVE STATE (S0, S1) WITH ALL OUTPUTS ENABLED Application Note 9862 State Transitions 5VDUAL 5VIN 3.3VDUAL/SB 3.3VMEM 2.5VMEM 1.00V/DIV Figure 6 shows the transition from active state (S0, S1) to S3 sleep state on the HIP6500BEVAL1 board. Prior to time T0, the evaluation board was operating in active mode, with SW1 on and SW2 and SW3 off. At time T0, SW2 is switched on, triggering the turn-off of the ATX and the switch-over of the output regulation from the active ATX output rails to the 5VSB supply. Very shortly after time T0, the ATX responds to the turn-off request, and the 5V input starts to ramp down under the current drawn by the embedded 5Ω serpentine resistor. As it can be noticed in the scope capture, the transitions are devoid of any perturbations. These smooth transitions are desirable in a computer system, power glitches being the leading cause of power-related system crashes. 2.5VCLK GND> 2ms/DIV T0 5VDUAL FIGURE 7. HIP6502BEVAL1 ACTIVE STATE (S0, S1) TO STANDBY STATE (S3) TRANSITION WITH ALL OUTPUTS ENABLED 5VIN 3.3VDUAL 3.3VSB 1.00V/DIV 2.5VMEM 2.5VCLK GND> 2ms/DIV T0 FIGURE 6. HIP6500BEVAL1 ACTIVE STATE (S0, S1) TO STANDBY STATE (S3) TRANSITION WITH ALL OUTPUTS ENABLED Figure 8 highlights the transition back from S3 sleep state to active state (S0, S1) with all outputs enabled, as captured on the HIP6500BEVAL1 board. At time T0, SW2 is switched off, enabling the main ATX outputs. As 3.3VIN, 5VIN, and 12VIN exceed their undervoltage thresholds, the 25ms timer internal to the HIP6500B is initiated. At T1 the time-out expires, conduction on the 3.3VDUAL and 5VDUAL outputs is transferred to the N-MOS switches and the 2.5VCLK output begins its ramp-up. At time T2, all the outputs are functional and ready for active state operation. The 2.5VMEM output is maintained glitch-free throughout the input voltage transition from the standby to the main ATX outputs. Figure 7 shows the transition from active state (S0, S1) to S3 sleep state on the HIP6502BEVAL1 board. Similarly, this board mirrors the functionality and benefits of the HIP6500BEVAL1. 5VDUAL 1.00V/DIV 5VIN 3.3VDUAL 3.3VSB 2.5VMEM 2.5VCLK GND> 10ms/DIV T0 T1 T2 FIGURE 8. HIP6500BEVAL1 STANDBY STATE (S3) TO ACTIVE STATE (S0, S1) TRANSITION WITH ALL OUTPUTS ENABLED 5 Application Note 9862 Figure 9 highlights the transition from S5 sleep state to active state (S0, S1) with no outputs enabled (3.3VSB is always enabled), as captured on the HIP6500BEVAL1 board. At time T0, SW2 is switched off, enabling the main ATX outputs. As 3.3VIN, 5VIN, and 12VIN exceed their undervoltage thresholds (5VIN shown, only), the 25ms timer internal to the HIP6500B is initiated and similar to the startup shown in Figure 8, the 3VDUAL and 5VDUAL outputs undergo a quasi-soft-start as conduction takes place through the body diodes of the pass NMOS switches. At T1 the timeout expires, conduction on the 3.3VDUAL and 5VDUAL outputs is transferred to the N-MOS switches and the 2.5VCLK and 2.5VMEM outputs begin their ramp-up. At time T2, all the outputs are functional and ready for active state operation. 2.5V> 2.5VMEM 50mV/DIV 2.00A/DIV 0A> 2.5V> 50mV/DIV 2.5VCLK 500mA/div 0A> 100μs/div FIGURE 10. HIP6500BEVAL1 ACTIVE STATE (S0, S1) OUTPUT TRANSIENT RESPONSE 5VIN 5VDUAL 1.00V/DIV 3.3VSB 3.3VDUAL 2.5VCLK 2.5VMEM In Figure 11, the outputs shown are separately subjected to load transients while operating in active state (S0, S1). Transient loading of the outputs is as follows: - 3.3VDUAL: 500mA to 3.2A at 0.2A/μs - 5VDUAL: 200mA to 2.5A at 0.1A/μs 3.3V> 3.3VDUAL 200mV/DIV GND> 10ms/DIV T0 T1 T2 FIGURE 9. HIP6500BEVAL1 STANDBY STATE (S5) TO ACTIVE STATE (S0, S1) TRANSITION WITH NO OUTPUTS ENABLED The 25ms time-out employed by the HIP6500B (and HIP6502B) is necessary in order to insure that the main ATX outputs are allowed to stabilize and reach regulation limits before any circuits are connected to, or are allowed to derive their voltages from them. This technique insures glitch-free operation, compatible with virtually any ATX power supply. Transient Response Given the similarity of the two evaluation boards, only HIP6500BEVAL1 results are shown in Figures 10-12; the respective outputs of the HIP6502BEVAL1 exhibit similar performance. All outputs shown in the oscilloscope captures are DC offset by their nominal value and are DC coupled. The current waveforms underneath each of the output voltage waveforms show the (transient) current drawn from the respective output. In Figure 10, the outputs shown are separately subjected to load transients while operating in active state (S0, S1). Transient loading of the outputs is as follows: - 2.5VMEM: 500mA to 3.2A at 1A/μs - 2.5VCLK: 180mA to 700mA at 0.1A/μs 6 0A> 5.0V> 2.0A/DIV 5VDUAL 200mV/DIV 2.0A/DIV 0A> 500μs/DIV FIGURE 11. HIP6500BEVAL1 ACTIVE STATE (S0, S1) OUTPUT TRANSIENT RESPONSE The 3.3VDUAL and 5VDUAL outputs closely follow the AC meandering of the ATX 3.3V and 5V outputs, being separated only by the rDS(ON) of the N-MOS switches (Q4 and Q6). During the transient loading, the 3.3VDUAL output develops a DC offset (compared to the ATX 3.3V), due to the voltage droop across Q4. Specific to this circuit and the particular circuit loading, the offset can easily be identified as the product of the rDS(ON) of the pass transistor and the output current. A similar explanation accompanies the 5VDUAL output waveform. Application Note 9862 In Figure 12, the outputs shown are separately subjected to load transients while operating in sleep state (S3). Transient loading of the outputs is as follows: - 2.5VMEM: 50mA to 200mA at 1A/μs - 3.3VSB: 30mA to 200mA at 0.1A/μs 3.3VIN 1 - 5.00A/DIV 2 - 1.00V/DIV 2.5V> 500mV/DIV 2.5VMEM 100mV/DIV 2.5VMEM 0A> 2.5VMEM OUTPUT CURRENT1 SS (TP7) 200mA/DIV FAULT (TP4)2 GND> 3.3V> 10μs/DIV 100mV/DIV 3.3VSB T0 200mA/DIV 0A> T1 T2 T3 FIGURE 13. HIP6500BEVAL1 2.5VMEM OUTPUT UNDERVOLTAGE RESPONSE WHILE IN ACTIVE STATE (S0, S1) 500μs/DIV FIGURE 12. HIP6500BEVAL1 SLEEP STATE (S3) OUTPUT TRANSIENT RESPONSE Output Short-Circuit Protection Figure 13 depicts the circuit’s behavior in response to a sudden output short-circuit (output under-voltage), applied, in this scope capture, on the 2.5VMEM output, while operating in active state. At time T0 a short-circuit is applied using an electronic load - as a result, the 2.5V output starts to rapidly discharge, crossing the falling under-voltage threshold at time T1. To avoid false triggers, the UV detector is equipped with a 10μs filter. As the output voltage remains below the undervoltage (UV) threshold for more than 10μs, it triggers a fault response at time T2. The logic high output on the FAULT pin sets the external fault latch circuitry which shuts down the ATX supply and quickly discharges the SS capacitor below the chip shutdown level, reached at time T3. The chip reset disables the fault reporting and the latch maintains the circuit in a reset state. The latch is necessary to compensate for the slow response of the ATX supply, by shutting down the controller IC, along with the pass elements. Depressing the CLEAR FAULT button resets the latch and releases the circuit for operation. HIP6500B/02BEVAL1 Modifications Setting the 2.5/3.3VMEM Output to 3.3V (HIP6500BEVAL1 Only) The HIP6500BEVAL1 evaluation board ships populated to demonstrate support for RDRAM or some double data rate (DDR) SDRAM memory, with the memory output set for 2.5V. The HIP6500B, however, is designed for either 2.5V or 3.3V memory output voltage. To change the memory output voltage on the evaluation board perform the following steps: • Replace R3 with a 15kΩ resistor • Remove Q2, and install an N-MOS transistor in its place (HUF76113 or equivalent recommended). Please note the connection diagram and insure the correct connections are established (N-MOS might not fit the provided footprint) With the above modifications, the memory output will be set to 3.3V. In this configuration, the output voltage obtainable in active state is directly related to the ATX 3.3V output, the memory output current, and the r(DS)ON of Q2, according to the following equation: V MEM = V IN – I MEM × r ( DS )ON Improving Output Voltage Tolerance The key to improving the output voltage tolerance is identifying the parameters which affect it, and then taking steps toward improving them. The output DC voltage droop on the 3.3VDUAL and 5VDUAL outputs under applied load is due to the resistive losses across the N-MOS switch’s own rDS(ON) - decreasing the rDS(ON) results in reduced load-dependent voltage drooping. 7 Application Note 9862 High dV/dt spikes present in the output voltage waveform under highly dynamic load application (high dI/dt) are due to the ESR and the ESL of the output capacitance. These spikes coincide with the transient load’s rising and falling edges, and decreasing their amplitude can be achieved by using lower ESR/ESL output capacitors (such as surfacemount tantalum capacitors), and/or the addition of more ceramic capacitors, which have inherently low ESR/ESL. The addition of more input-side capacitance and decreasing the input-side capacitor banks’ ESR can also help in situations where the input-side ripple is affecting the output regulation. Such an example is excessive ATX 3.3V ripple reducing the collector-to-emitter voltage available for Q2 (2.5V setting), and thus inducing an output droop component - in such instance, the addition of input-side capacitance and reduction of the ESR component can reduce the output excursion. Conclusion The HIP6500B and HIP6502B are sophisticated integrated circuits that envelop all the required circuitry for ACPI implementation in computer motherboards and computer systems. The circuits employ intelligent switching methods for smooth power plane transitions, noise immunity circuits for nuisance trip avoidance, and a direct interface to the south bridge and logical circuitry for simplified control and configuration. 8 References For Intersil documents available on the internet, see web site http://www.intersil.com/ [1] Advanced Configuration and Power Interface Specification, Revision 1.0, December 1996, Intel/Microsoft/Toshiba. (http://www.teleport.com/~acpi/). [2] HIP6020 Data Sheet, Intersil Corporation, Power Management Products Division, FN4683, (http://www.intersil.com/). [3] HIP6021 Data Sheet, Intersil Corporation, Power Management Products Division, FN4684. [4] ATX Specification, Version 2.02, October 1998, Intel Corporation (http://www.teleport.com/~atx/). [5] HIP6500B Data Sheet, Intersil Corporation, Power Management Products Division, FN4870. [6] HIP6502B Data Sheet, Intersil Corporation, Power Management Products Division, FN4871. Application Note 9862 HIP6500BEVAL1 Schematic 4, 6, 19, 20 ATX CONNECTOR J1 10 1, 2, 11 9 14 +5VIN + +12VIN C1 220μF +3.3VIN + +5VSB + C4 220μF (MINIMUM ATX LOAD: 4-6Ω) C3 10μF + C5 1μF 12V PS_ON 17 C8 1μF Q1 BSS84ZX 3V3 3, 5, 7, 13, 15, 16, 17 R1 300 GND 5V SW1 ‘ATX ON’ TP3 ‘3.3VDUAL’ 3V3DLSB 1/3 QA2 ZDM4206 Q3 2SD1802 Q4 HUF76113T3S +3.3VDUAL 3V3DL R2 620 LP1 ‘FAULT’ + C14 1μF 3V3SB C17 150μF LP2 ‘S3’ RN1 4x680 5 12 14 3 13 S3 LP3 ‘S5’ EN5VDL EN3VDL 15 + C11 1μF +2.5VCLK C12 + 150μF C13 1μF 5VDLSB Q5 FDV304P TP6 ‘5VDUAL’ +5VDUAL 5VDL 10 11 16 GND RN3 2x1k SIGNAL CONDITIONING DLA Q6 HUF76113T3S + 20 TP2 ‘VCLK’ VCLK 9 8 TP1 ‘VMEM’ +2.5/3.3VMEM C9,10 2x150μF + S5 +5VSB 4 6 C6 220μF VSEN2 R3 1k TP5 ‘3.3VSB’ C16 1μF 1 S D Q2 MJD44H11 DRV2 U1 HIP6500B FAULT/MSEL G 2 7 18 C15 220μF TP4 ‘FAULT’ C7 1μF 5VSB 19 +3.3VSB PCB RESISTOR SEE NOTE 2 C2 1μF C18 150μF C19 1μF SS TP7 ‘SS’ C20 0.1μF R4 51 PB1 ‘SHUTDOWN / CLEAR FAULT’ JP3 ‘FAULT LATCH’ JP1 ‘EN5VDL’ +5VSB +5VSB SW2 ‘S3’ SW3 ‘S5’ JP2 ‘EN3VDL’ +5VIN LP5 ‘+5V’ FAULT LATCH LP4 ‘+5VSB’ R5 620 LP6 ‘FAULT LATCH’ 9 1/3 DA3 MA121CT TO PS_ON (ATX CONNECTOR) Application Note 9862 HIP6502BEVAL1 Schematic 4, 6, 19, 20 ATX CONNECTOR J1 10 1, 2, 11 9 14 +5VIN PCB RESISTOR SEE NOTE 2 + +12VIN C1 220μF C2 1μF (MINIMUM ATX LOAD: 4-6Ω) +3.3VIN + +5VSB + C4 220μF C3 10μF + C5 1μF 12V PS_ON 17 C8 1μF Q1 BSS84ZX 3V3 R1 300 5V 18 1 GND SW1 ‘ATX ON’ TP3 ‘3.3VDUAL / 3.3VSB’ 3V3DLSB 1/3 DA1 MA121CT Q3 2SD1802 Q4 HUF76113T3S +3.3VDUAL/+3.3VSB R2 620 3V3DL LP1 ‘FAULT’ + C14 1μF FAULT +3.3VMEM TP5 ‘3.3VMEM’ RN1 4x680 12 14 C17,18 2x150μF LP2 ‘S3’ 3 13 + 15 S3 LP3 ‘S5’ MSEL 20 11 16 GND RN3 2x1k SIGNAL CONDITIONING C13 1μF Q5 FDV304P 5VDLSB DLA Q7 HUF76113T3S TP6 ‘5VDUAL’ +5VDUAL 5VDL + 8 TP2 ‘VCLK’ +2.5VCLK 10 EN5VDL C11 1μF C12 + 150μF 9 S5 +5VSB 5 + VCLK Q6 HUF76113T3S VSEN1 +2.5VMEM C9,10 2x150μF 6 TP1 ‘2.5VMEM’ Q2 MJD44H11 VSEN2 U1 HIP6502B TP4 ‘FAULT’ C16 1μF DRV2 4 C15 220μF C19 150μF C20 1μF SS C21 0.1μF TP7 ‘SS’ R3 51 PB1 ‘SHUTDOWN / CLEAR FAULT’ JP1 ‘FAULT LATCH’ JP2 ‘EN5VDL’ SW2 ‘S3’ C6 220μF 2 7 19 3, 5, 7, 13, 15, 16, 17 C7 1μF 5VSB +5VSB +5VSB SW3 ‘S5’ FAULT LATCH JP3 ‘2.5V ONLY’ ‘3.3V ONLY’ +5VIN LP5 ‘+5V’ LP4 ‘+5VSB’ R4 620 LP6 ‘FAULT LATCH’ 10 1/3 DA3 MA121CT TO PS_ON (ATX CONNECTOR) Application Note 9862 Signal Conditioning and Fault Latch Circuits S3 +5VSB S5 RN2 4X10K DA2 MA121CT SW2 ‘S3’ SW3 ‘S5’ DA1 MA121CT QA2 ZDM4206 QA1 ZDM4206 FIGURE 14. SIGNAL CONDITIONING BLOCK ‘FAULT LATCH’ JP3 SS D1 MA111CT RN5 2X1K +5VSB QA3 ZDT6718 RN4 4X1K R5 620 DA3 MA121CT LP6 ‘FAULT LATCH’ TO PS_ON (ATX CONNECTOR) FIGURE 15. FAULT LATCHING BLOCK 11 Application Note 9862 Bill of Materials for HIP6500BEVAL1 REF PART NO. DESCRIPTION PACKAGE QTY VENDOR C1, 4, 6, 15 EEUFC1E221 Aluminum Electrolytic Capacitor, 25V, 220μF, 117mΩ 8 x 11.5 4 Panasonic C3 TAJC106M020R Tantalum Capacitor, 20V, 10μF, 2Ω 3.2 x 6.0 1 AVX C2, 5, 7, 8, 11, 13, 14, 16, 19 1μF Ceramic Ceramic Capacitor, Y5V, 16V, 1.0μF 0805 9 Any C9, 10, 12, 17, 18 EEUFC1V151 Al. Electrolytic Capacitor, 35V, 150μF, 117mΩ 8 x 11.5 5 Panasonic C20 0603YC104MAT2A Ceramic Capacitor, X7R, 16V, 0.1μF 0603 1 AVX D1 MA111CT-ND Switching Diode, 80V, 100mA Mini 2P 1 Digikey DA1-3 MA121CT-ND Diode Array, 80V, 100mA Mini 6P 3 Digikey J1 39-29-9203 20-pin Mini-Fit, Jr.™ Header Connector 1 Molex JP1-3 68000-236 Jumper Header 0.1” spacing 6/36 Berg 71363-102 Jumper Shunt 0.1” spacing 3 Berg LP1-6 L63111CT-ND Miniature LED, Through-Board Indicator 6 Digikey PB1 P8007S-ND Push-Button, Miniature 1 Digikey Q1 BSS84ZXCT-ND Logic P-MOSFET, 50V, 10Ω SOT-23 1 Digikey Q2 (Note 1) MJD44H11 NPN Bipolar, 80V, 8A TO-252AA 1 Motorola Q3 2SD1802 NPN Bipolar, 50V, 3A TO-252AA 1 Sanyo Q4,6 HUF76113T3S UltraFET™ MOSFET, 30V, 31mΩ SOT-223 2 Intersil Q5 FDV304P Logic P-MOSFET, 25V, 1.5Ω SOT-23 1 Fairchild QA1, 2 ZDM4206NCT-ND Small-Signal Dual MOSFET, 60V, 1Ω SM-8 2 Digikey QA3 ZDT6718CT-ND Small-Signal Bipolar Pair, 20V, 1.5A SM-8 1 Digikey R1 300Ω Resistor, 5%, 0.1W 0603 1 Any R2, 5 620Ω Resistor, 5%, 0.1W 0603 2 Any R3 (Note 2) 1.0kΩ Resistor, 5%, 0.1W 0603 1 Any R4 51Ω Resistor, 5%, 0.1W 0603 1 Any RN1 Y9681CT-ND 4-Resistor Network, 680Ω, 5%, 0.1W 3.2 x 1.6 1 Digikey RN2 Y9103CT-ND 4-Resistor Network, 10kΩ, 5%, 0.1W 3.2 x 1.6 1 Digikey RN3, 5 Y8102CT-ND 2-Resistor Network, 1kΩ, 5%, 0.1W 1.6 x 1.6 2 Digikey RN4 Y9102CT-ND 4-Resistor Network, 1kΩ, 5%, 0.1W 3.2 x 1.6 1 Digikey SW1 GT12MSCKE Miniature Switch, Single Pole, Single Throw 1 C&K SW2, 3 GT11MSCKE Miniature Switch, Single Pole, Double Throw 2 C&K TP1-3, 5, 6 1314353-00 Test Point, Scope Probe 5 Tektronics TP4, 7 SPCJ-123-01 Test Point 2 Jolo U1 HIP6500BCB ACPI Multiple Linear Controller 1 Intersil +2.5/3.3VMEM, +2.5VCLK, +3.3VDUAL, +3.3VSB, +5VDUAL, GND 1514-2 Terminal Post 10 Keystone SOIC-20 NOTES: 1. Q2 has to be replaced by an NMOS transistor when 3.3V VMEM output is desired (see circuit diagram for proper connection). 2. R3 has to be replaced by a 15kΩ resistor when 3.3V VMEM output is desired. 12 UltraFET™ is a trademark of Intersil Corporation. Mini-Fit, Jr.™ is a trademark of Molex, Inc. Application Note 9862 Bill of Materials for HIP6502BEVAL1 REF PART # DESCRIPTION PACKAGE QTY VENDOR C1, 4, 6, 15 EEUFC1E221 Aluminum Electrolytic Capacitor, 25V, 220μF, 117mΩ 8 x 11.5 4 Panasonic C3 TAJC106M020R Tantalum Capacitor, 20V, 10μF, 2Ω 3.2 x 6.0 1 AVX C2, 5, 7, 8, 11, 13, 14, 16, 20 1μF Ceramic Ceramic Capacitor, Y5V, 16V, 1.0μF 0805 9 Any C9, 10, 12, 17-19 EEUFC1V151 Al. Electrolytic Capacitor, 35V, 150μF, 117mΩ 8 x 11.5 6 Panasonic C21 0603YC104MAT2A Ceramic Capacitor, X7R, 16V, 0.1μF 0603 1 AVX D1 MA111CT-ND Switching Diode, 80V, 100mA Mini 2P 1 Digikey DA1-3 MA121CT-ND Diode Array, 80V, 100mA Mini 6P 3 Digikey J1 39-29-9203 20-pin Mini-Fit, Jr.™ Header Connector 1 Molex JP1-3 68000-236 Jumper Header 0.1” spacing 7/36 Berg 71363-102 Jumper Shunt 0.1” spacing 3 Berg LP1-6 L63111CT-ND Miniature LED, Through-Board Indicator 6 Digikey PB1 P8007S-ND Push-Button, Miniature 1 Digikey Q1 BSS84ZXCT-ND Logic P-MOSFET, 50V, 10Ω SOT-23 1 Digikey Q2 MJD44H11 NPN Bipolar, 80V, 8A TO-252AA 1 Motorola Q3 2SD1802 NPN Bipolar, 50V, 3A TO-252AA 1 Sanyo Q4, 6, 7 HUF76113T3S UltraFET™ MOSFET, 30V, 31mΩ SOT-223 3 Intersil Q5 FDV304P Logic P-MOSFET, 25V, 1.5Ω SOT-23 1 Fairchild QA1, 2 ZDM4206NCT-ND Small-Signal Dual MOSFET, 60V, 1Ω SM-8 2 Digikey QA3 ZDT6718CT-ND Small-Signal Bipolar Pair, 20V, 1.5A SM-8 1 Digikey R1 300Ω Resistor, 5%, 0.1W 0603 1 Any R2, 4 620Ω Resistor, 5%, 0.1W 0603 2 Any R3 51Ω Resistor, 5%, 0.1W 0603 1 Any RN1 Y9681CT-ND 4-Resistor Network, 680Ω, 5%, 0.1W 3.2 x 1.6 1 Digikey RN2 Y9103CT-ND 4-Resistor Network, 10kΩ, 5%, 0.1W 3.2 x 1.6 1 Digikey RN3, 5 Y8102CT-ND 2-Resistor Network, 1kΩ, 5%, 0.1W 1.6 x 1.6 2 Digikey RN4 Y9102CT-ND 4-Resistor Network, 1kΩ, 5%, 0.1W 3.2 x 1.6 1 Digikey SW1 GT12MSCKE Miniature Switch, Single Pole, Single Throw 1 C&K SW2, 3 GT11MSCKE Miniature Switch, Single Pole, Double Throw 2 C&K TP1-3, 5, 6 1314353-00 Test Point, Scope Probe 5 Tektronics TP4, 7 SPCJ-123-01 Test Point 2 Jolo U1 HIP6502BCB ACPI Multiple Linear Controller 1 Intersil +2.5VCLK, +2.5VMEM, +3.3VMEM, +3.3VDUAL/3.3VSB, +5VDUAL, GND 1514-2 Terminal Post 10 Keystone 13 SOIC-20 Application Note 9862 HIP6500BEVAL1 Layout TOP SILK SCREEN HIP6500BEVAL1 REV B CALL 1-888-INTERSIL TOP LAYER 14 Application Note 9862 HIP6500BEVAL1 Layout (Continued) GROUND LAYER POWER LAYER 15 Application Note 9862 HIP6500BEVAL1 Layout (Continued) BOTTOM LAYER BOTTOM SILK SCREEN 16 Application Note 9862 HIP6502BEVAL1 Layout TOP SILK SCREEN HIP6502BEVAL1 REV B CALL CALL 1-888-INTERSIL TOP LAYER 17 Application Note 9862 HIP6502BEVAL1 Layout (Continued) GROUND LAYER POWER LAYER 18 Application Note 9862 HIP6502BEVAL1 Layout (Continued) BOTTOM LAYER BOTTOM SILK SCREEN 19 Application Note 9862 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. 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