SN54LV273, SN74LV273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS195B – FEBRUARY 1993 – REVISED APRIL 1996 D D D D SN54LV273 . . . J OR W PACKAGE SN74LV273 . . . DB, DW, OR PW PACKAGE (TOP VIEW) CLR 1Q 1D 2D 2Q 3Q 3D 4D 4Q GND 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12 10 11 VCC 8Q 8D 7D 7Q 6Q 6D 5D 5Q CLK 2D 2Q 3Q 3D 4D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 8D 7D 7Q 6Q 6D 4Q GND CLK 5Q 5D The ’LV273 are positive-edge-triggered flip-flops with direct clear (CLR) input. Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low level, the D-input signal has no effect at the output. 20 2 SN54LV273 . . . FK PACKAGE (TOP VIEW) description These octal D-type flip-flops are designed for 2.7-V to 5.5-V VCC operation. 1 8Q D EPIC (Enhanced-Performance Implanted CMOS) 2-µ Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Latch-Up Performance Exceeds 250 mA Per JEDEC Standard JESD-17 Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW), Ceramic Flat (W) Packages, Chip Carriers (FK), and (J) 300-mil DIPs 1D 1Q CLR VCC D The SN74LV273 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area. The SN54LV273 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV273 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1996, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV273, SN74LV273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS195B – FEBRUARY 1993 – REVISED APRIL 1996 FUNCTION TABLE (each flip-flop) INPUTS CLR CLK D OUTPUT Q L X X L H ↑ H H H ↑ L L H L X Q0 logic symbol† CLR CLK 1D 2D 3D 4D 5D 6D 7D 8D 1 R 11 C1 3 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for DB, DW, J, PW, and W packages. logic diagram (positive logic) 1D CLK 11 2D 3 3D 4 7 1D C1 8 1 1D C1 R 6D 13 1D C1 R 7D 14 8D 17 18 1D C1 R 1D C1 R 1D C1 R 1D C1 R C1 R R R 2 1Q 2 5D CLK(I) 1D CLR 4D 5 2Q 6 3Q POST OFFICE BOX 655303 9 4Q 12 5Q • DALLAS, TEXAS 75265 15 6Q 16 7Q 19 8Q SN54LV273, SN74LV273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS195B – FEBRUARY 1993 – REVISED APRIL 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0 or VI > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA Maximum power dissipation at TA = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W DW package . . . . . . . . . . . . . . . . . . 1.6 W PW package . . . . . . . . . . . . . . . . . . . 0.7 W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils. recommended operating conditions (see Note 4) SN54LV273 VCC Supply voltage VIH High level input voltage High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VIL Low level input voltage Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V VI VO Input voltage MAX MIN MAX 2.7 5.5 2.7 5.5 2 2 3.15 3.15 0 Output voltage 0 IOH High level output current High-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V IOL Low level output current Low-level VCC = 2.7 V to 3.6 V VCC = 4.5 V to 5.5 V ∆t /∆v Input transition rise or fall rate TA Operating free-air temperature NOTE 4: Unused inputs must be held high or low to prevent them from floating. SN74LV273 MIN 0.8 1.65 1.65 0 0 V V 0.8 VCC VCC UNIT VCC VCC –6 –6 –12 –12 6 6 12 12 V V V mA mA 0 100 0 100 ns / V – 55 125 – 40 85 °C PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV273, SN74LV273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS195B – FEBRUARY 1993 – REVISED APRIL 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL VCC† TEST CONDITIONS IOH = – 100 µA IOH = – 6 mA MIN to MAX IOH = –12 mA IOL = 100 µA 4.5 V 3V VO = VCC or GND, GND IO = 0 ICC VI = VCC or GND, GND IO = 0 nICC One input at VCC – 0.6 V, Other inputs at VCC or GND Ci VI = VCC or GND IOZ TYP SN74LV273 MAX MIN TYP VCC – 0.2 2.4 VCC – 0.2 2.4 3.6 3.6 MIN to MAX IOL = 6 mA IOL = 12 mA MAX UNIT V 0.2 0.2 3V 0.4 0.4 4.5 V 0.55 0.55 3.6 V ±1 ±1 5.5 V ±1 ±1 3.6 V ±5 ±5 5.5 V ±5 ±5 3.6 V 20 20 5.5 V 20 20 3 V to 3.6 V 500 500 VI = VCC or GND II SN54LV273 MIN 3.3 V 2.5 2.5 5V 3 3 V µA µA µA µA pF F † For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions. timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN54LV273 VCC = 5.5 V ± 0.5 V fclock Clock frequency tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX 0 60 VCC = 3.3 V ± 0.3 V MIN MAX 0 50 VCC = 2.7 V MIN MAX 0 40 CLR low 6 10 12 CLK high or low 7 10 12 Data 8 12 14 CLR inactive 2 2 2 3 2 2 UNIT MHz ns ns ns timing requirements over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) SN74LV273 VCC = 5.5 V ± 0.5 V fclock Clock frequency tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ VCC = 2.7 V MIN MAX MIN MAX MIN MAX 0 60 0 50 0 40 CLR low 6 10 12 CLK high or low 7 10 12 Data 8 12 14 CLR inactive 2 2 2 3 2 2 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 VCC = 3.3 V ± 0.3 V POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns SN54LV273, SN74LV273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS195B – FEBRUARY 1993 – REVISED APRIL 1996 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN54LV273 FROM (INPUT) TO (OUTPUT) tpd CLK Q 11 16 16 22 26 ns tPHL CLR Q 13 22 14 24 30 ns PARAMETER fmax VCC = 5 V ± 0.5 V MIN TYP MAX 60 100 VCC = 3.3 V ± 0.3 V MIN TYP MAX 50 80 VCC = 2.7 V MIN MAX 40 UNIT MHz switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) SN74LV273 PARAMETER FROM (INPUT) TO (OUTPUT) fmax VCC = 5 V ± 0.5 V MIN TYP MAX 60 100 VCC = 3.3 V ± 0.3 V MIN TYP MAX 50 80 VCC = 2.7 V MIN MAX 40 UNIT MHz tpd CLK Q 11 16 16 22 26 ns tPHL CLR Q 13 22 14 24 30 ns operating characteristics, TA = 25°C PARAMETER Cpd TEST CONDITIONS Power dissi dissipation ation capacitance ca acitance per er fli flip-flop -flo CL = 50 pF F, VCC 3.3 V TYP 5V 41 UNIT 32 f = 10 MHz pF F PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV273, SN74LV273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SCLS195B – FEBRUARY 1993 – REVISED APRIL 1996 PARAMETER MEASUREMENT INFORMATION S1 1 kΩ From Output Under Test Vz Open GND CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Vz GND 1 kΩ WAVEFORM CONDITION Vm Vi Vz LOAD CIRCUIT VCC = 4.5 V to 5.5 V 0.5 × VCC VCC 2 × VCC VCC = 2.7 V to 3.6 V 1.5 V 2.7 V 6V Vi Vm Timing Input 0V tw tsu Vi Input Vm th Vi Vm Vm Data Input Vm 0V 0V VOLTAGE WAVEFORMS PULSE DURATION VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Vi Vm Input 0V VOH Vm Output Vm VOL Output VOH Vm 0V Vm VOL tPLZ Output Waveform 1 S1 at Vz (see Note B) tPLH tPHL Vm Vm tPZL tPHL tPLH Vi Output Control Vm Output Waveform 2 S1 at GND (see Note B) VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Vm tPZH 0.5 × Vz VOL + 0.3 V VOL tPHZ Vm VOH – 0.3 V VOH [0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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