SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 D D D D description These dual positive-edge-triggered D-type flip-flops are designed for 2-V to 5.5-V VCC operation. A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. SN54LV74A . . . J OR W PACKAGE SN74LV74A . . . D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LV74A . . . FK PACKAGE (TOP VIEW) 1D 1CLR NC VCC 2CLR D EPIC (Enhanced-Performance Implanted CMOS) Process Typical VOLP (Output Ground Bounce) < 0.8 V at VCC, TA = 25°C Typical VOHV (Output VOH Undershoot) > 2 V at VCC, TA = 25°C Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat (W) Packages, Chip Carriers (FK), and DIPs (J) 1CLK NC 1PRE NC 1Q 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 2D NC 2CLK NC 2PRE 1Q GND NC 2Q 2Q D NC – No internal connection The SN54LV74A is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74LV74A is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. EPIC is a trademark of Texas Instruments Incorporated. Copyright 1998, Texas Instruments Incorporated UNLESS OTHERWISE NOTED this document contains PRODUCTION DATA information current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 FUNCTION TABLE INPUTS OUTPUTS PRE CLR CLK D Q Q L H X X H L H L X X H H† L L X X L H† H H ↑ H H L H H ↑ L L H H H L X Q0 Q0 † This configuration is unstable; that is, it does not persist when PRE or CLR returns to its inactive (high) level. logic symbol‡ 4 1PRE 1CLK 1D 1 1CLR 6 9 11 2CLK 1Q R 10 2PRE 1Q C1 2 1D 5 S 3 2Q 12 2D 8 13 2CLR 2Q ‡ This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages. logic diagram, each flip-flop (positive logic) PRE CLK C C C Q TG C C C C D TG TG TG C C C Q CLR 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Output voltage range, VO (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC + 0.5 V Input clamp current, IIK (VI < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA Output clamp current, IOK (VO < 0 or VO > VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182°C/W NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. This value is limited to 7 V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions (see Note 4) SN54LV74A VCC VIH VIL VI VO IOH IOL ∆t/∆v Supply voltage High level input voltage High-level Low level input voltage Low-level VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V MIN MAX MIN MAX 2 5.5 2 5.5 1.5 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC × 0.7 VCC = 2 V VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 0 Output voltage 0 Low level output current Low-level Input transition rise or fall rate VCC = 2 V VCC = 2.3 V to 2.7 V V V 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 VCC × 0.3 5.5 VCC × 0.3 5.5 VCC –50 0 0 –2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V UNIT VCC × 0.7 0.5 Input voltage High level output current High-level SN74LV74A VCC –50 V V V µA –2 –6 –6 –12 –12 VCC = 2 V VCC = 2.3 V to 2.7 V 50 50 2 2 VCC = 3 V to 3.6 V VCC = 4.5 V to 5.5 V 6 6 12 mA µA mA 12 VCC = 2.3 V to 2.7 V VCC = 3 V to 3.6 V 0 200 0 200 0 100 0 100 VCC = 4.5 V to 5.5 V 0 20 0 20 ns/V TA Operating free-air temperature –55 125 –40 85 °C NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER VOH VOL SN54LV74A TEST CONDITIONS VCC IOH = –50 µA IOH = –2 mA 2 V to 5.5 V IOL = 50 µA IOL = 2 mA VI = VCC or GND VI = VCC or GND, Ioff VI or VO = 0 to 5.5 V Ci VI = VCC or GND SN74LV74A MAX MIN VCC–0.1 2 3V 2.48 2.48 4.5 V 3.8 TYP MAX UNIT V 3.8 2 V to 5.5 V 0.1 0.1 2.3 V 0.4 0.4 3V 0.44 0.44 4.5 V 0.55 0.55 5.5 V ±1 ±1 µA 5.5 V 20 20 µA 0V 5 5 µA IOL = 6 mA IOL = 12 mA II ICC TYP VCC–0.1 2 2.3 V IOH = –6 mA IOH = –12 mA MIN IO = 0 3.3 V 2.1 2.1 5V 2.1 2.1 V pF timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ SN54LV74A MIN MAX SN74LV74A MIN PRE or CLR low 8 9 9 CLK 8 9 9 Data 8 9 9 PRE or CLR inactive 7 7 7 0.5 0.5 0.5 MAX UNIT ns ns ns timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ MIN MAX SN74LV74A MIN PRE or CLR low 6 7 7 CLK 6 7 7 Data 6 7 7 PRE or CLR inactive 5 5 5 0.5 0.5 0.5 PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. 4 SN54LV74A POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MAX UNIT ns ns ns SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 timing requirements over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) TA = 25°C MIN MAX PARAMETER tw Pulse duration tsu Setup time before CLK↑ th Hold time, data after CLK↑ SN54LV74A MIN MAX SN74LV74A MIN PRE or CLR low 5 5 5 CLK 5 5 5 Data 5 5 5 PRE or CLR inactive 3 3 3 0.5 0.5 0.5 MAX UNIT ns ns ns switching characteristics over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d* tpd d PRE or CLR CLK PRE or CLR CLK LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN54LV74A MIN MAX SN74LV74A MIN CL = 15 pF* 50 100 40 40 CL = 50 pF 30 70 25 25 Q or Q CL = 15 pF Q or Q CL = 50 pF MAX UNIT MHz 9.8 14.8 1 17 1 17 11.1 16.4 1 19 1 19 13 17.4 1 20 1 20 14.2 20 1 23 1 23 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d* tpd d PRE or CLR CLK PRE or CLR CLK LOAD CAPACITANCE MIN TA = 25°C TYP MAX SN54LV74A MIN MAX SN74LV74A MIN CL = 15 pF* 80 140 70 70 CL = 50 pF 50 90 45 45 Q or Q CL = 15 pF Q or Q CL = 50 pF MAX UNIT MHz 6.9 12.3 1 14.5 1 14.5 7.9 11.9 1 14 1 14 9.2 15.8 1 18 1 18 10.2 15.4 1 17.5 1 17.5 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tpd d* tpd d PRE or CLR CLK PRE or CLR CLK LOAD CAPACITANCE TA = 25°C MIN TYP MAX SN54LV74A MIN MAX SN74LV74A MIN CL = 15 pF* 130 180 110 110 CL = 50 pF 90 140 75 75 Q or Q CL = 15 pF Q or Q CL = 50 pF MAX UNIT MHz 5 7.7 1 9 1 9 5.6 7.3 1 8.5 1 8.5 6.6 9.7 1 11 1 11 7.2 9.3 1 10.5 1 10.5 ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 5) SN74LV74A PARAMETER MIN TYP MAX UNIT VOL(P) VOL(V) Quiet output, maximum dynamic VOL 0.1 0.8 V Quiet output, minimum dynamic VOL –0.04 –0.8 V VOH(V) VIH(D) VIL(D) Quiet output, minimum dynamic VOH 3.2 High-level dynamic input voltage V 2.31 V Low-level dynamic input voltage 0.99 V VCC 3.3 V TYP UNIT 5V 23 NOTE 5: Characteristics are for surface-mount packages only. operating characteristics, TA = 25°C PARAMETER Cpd 6 Power dissipation dissi ation ca capacitance acitance TEST CONDITIONS CL = 50 pF F, POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 f = 10 MHz 21 pF F SN54LV74A, SN74LV74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS SCLS381D – AUGUST 1997 – REVISED JUNE 1998 PARAMETER MEASUREMENT INFORMATION RL = 1 kΩ From Output Under Test Test Point From Output Under Test VCC Open S1 TEST GND CL (see Note A) CL (see Note A) S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open Drain Open VCC GND VCC LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS VCC 50% VCC Timing Input 0V tw tsu VCC 50% VCC 50% VCC Input th VCC 50% VCC Data Input 50% VCC 0V 0V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATION VCC 50% VCC Input 50% VCC tPLH In-Phase Output 50% VCC VOH 50% VCC VOL 50% VCC VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES INVERTING AND NONINVERTING OUTPUTS Output Waveform 2 S1 at GND (see Note B) 50% VCC 0V Output Waveform 1 S1 at VCC (see Note B) tPLH VOH 50% VCC VOL 50% VCC tPZL tPHL tPHL Out-of-Phase Output 0V VCC Output Control tPLZ 50% VCC tPZH ≈ VCC VOL + 0.3 V VOL tPHZ 50% VCC VOH – 0.3 V VOH ≈0V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLING NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. 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