page 27 of TMS320DM6446 EVM schematic

5
4
3
2
REV
1
DESCRIPTION
DATE
APPROVED
NOTES, UNLESS OTHERWISE SPECIFIED:
D
1.
RESISTANCE VALUES IN OHMS.
2.
CAPACTITANCE VALUES IN MICROFARADS.
3.
REFERENCE DESIGNATORS USED:
4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS
OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED
CIRCUITS THEY SHOULD BE PLACED NEAR.
5.
OBSERVE THE FOLLOWING LAYOUT NOTES:
6.
BOARD PROPERTIES
A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE
B1. General layers 50 +/- 5 OHM MATCHED IMPEDANCE
B2. USB layer 90 ohm differential
C.
D.
E.
F.
G.
H.
C
Initial schematic ready for layout - Alpha Release
02/17/05
RRP
B
Beta Release
09/27/05
RRP
C
Gamma Release
10/28/05
RRP
D
Production Release
02/18/06
RRP
E
Production Update - DM6446 symbol updated to current Data Sheet
02/18/07
RRP
D
SCHEMATIC CONTENTS
OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING
INNER LAYERS 1.0 OZ CU
FR4 BOARD MATERIAL
MINIMUM TRACE WIDTH/SPACING 4 MILS
MINIMUM VIA SIZE 10/19 MIL
LAYER STACKUP:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
A
TOP - SIGNAL ROUTING
GROUND PLANE
INNER1 - SIGNAL ROUTING
VCC3 PLANE (3.3V BOARD)
INNER2 - SIGNAL ROUTING
INNER3 - SIGNAL ROUTING
VCC PLANE 2
INNER4 - SIGNAL ROUTING
GROUND PLANE
BOTTOM - SIGNAL ROUTING
B
01
02
03
04
05
06
07
08
09
10
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
EVM TITLE SHEET
EVM BLOCK DIAGRAM
EMIF INTERFACE
DDR INTERFACE
VIDEO INTERFACE
I/O INTERFACE
USB & SD/MMC/MS CONTROLLER
EMULATION & CLOCKS
POWER PINS
CONFIGURATION CONTROL/BOOT OPTIONS
11
12
13
14
15
16
17
18
19
20
DDR2 MEMORY
SRAM/NAND FLASH
NOR FLASH
EMIF LEVEL SHIFTER
EMIF CPLD MULTIPLEXER
SD/MMC/MS CONNECTOR
SM/xD CONNECTOR
ATA INTERFACE
COMPACT FLASH CONNECTOR
RS232 INTERFACE
21
22
23
24
25
26
27
28
29
30
USB 2.0 INTERFACE
ETHERNET INTERFACE
TVP5146 LEVEL SHIFTER
TVP5416 VIDEO DECODER
VIDEO OUT
AIC33 AUDIO INTERFACE
SPDIF OUTPUTS & USER LEDS
MSP430 & IR INTERFACE
EMIF EXPANSION CONNECTOR
VIDEO INPUT/OUTPUT CONNECTORS
31
32
33
34
35
EMAC/GIO & McBSP/SPI & SD CONNECTORS
VLYNQ CONNECTOR
DAVINCI EMULATION HEADER
POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC
POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONNECTOR
I2C ADDRESS TABLE
BASE
SHEET
0x50
I2C ROM
6
0x1B
AIC33
26
0x5D
TVP5146
24
0x38
IO EXPANDER 0
(LED)
28
0x39
IO EXPANDER 1
(PLL/USER_SW)
28
0x3A
IO EXPANDER 2
(USB/CD_RESET)
28
0x23
MSP430
C
28
B
REVISION STATUS OF SHEETS
E
E
E
E
E
31
32
33
34
35
DWN
R.R.P.
CHK
A
REV
E
E
E
E
E
E
E
E
E
E
SH
21
22
23
24
25
26
27
28
29
30
REV
E
E
E
E
E
E
E
E
E
E
T.W.K.
ENGR
R.R.P.
ENGR-MGR
R.R.P.
QA
SH
11
12
13
14
15
16
17
18
19
20
REV
E
E
E
E
E
E
E
E
E
E
SH
1
2
3
4
5
6
7
8
9
10
C.M.D.
MFG
NEXT ASSY
USED ON
R.R.P.
RLSE
5
APPLICATION
R.R.P.
4
DATE
02/17/2005
DATE
02/17/2005
DATE
02/17/2005
DATE
02/17/2005
DATE
03/01/2004
DATE
02/17/2005
DATE
02/17/2005
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
Title Block
DWG NO
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
3
A
Sheet
1
1
of
35
5
4
3
2
1
Compact Flash Connector
SH:19
ATA Connector
SH:18
SMC/xD Connector
SH:17
Power Supply (3.3V)
& System Reset Logic
D
1.8V to 3.3V
Level Shifters
SH:34
D
SH:14,15
Power Supply (1.8V & DSP Core)
& DC #7 Connector
SRAM (4MB)
SH:12
DC #1 Connector
SH:35
SH:29
NAND Flash (64MB)
SH:12
Config Control &
EM_CS2 Select
NOR Flash (16MB)
SH:13
SH:10
Switch
VLYNQ Connector
SH:14
PLLs
Crystal/Osc
SH:8
SH:32
EMIF/VLYNQ
SH:3
SH:8
C
SD/MMC/MS
SD/MMC/MS Connector
SH:7
SH:16
Emulator
Emulator Header
SH:33
SH:8
C
DC #6 Connector
SH:31
DDR2 IF
DDR2 SDRAM (256MB)
SH:11
(4) DACs
SH:4
USB 2.0
USB 2.0 IF
SH:21
Video Decoder
(TVP5146)
SH:24
B
Video Out
DC #5 Connector
SH:5
SH:30
McBSP
DC #3 Connector
SH:7
SH:31
Power Pins
SH:9
SH:23
SH:25
SH:3-9
SH:7
Level Shifter
& Switch
(4) DAC Video Outputs
SH:5
DaVinci
Image In
DC #4 Connector
SH:30
Switch
SH:5
B
SH:7
SPDIF Outputs
Ethernet IF
SH:22
SH:27
Switch
PWM0
SH:22
SH:5
EMAC/
GPIOs
DC #2 Connector
SH:31
VCXO/PLL
(Audio & Video
Clock Generation)
Stereo Codec
(AIC33)
Timer In
SH:8
SH:26
SH:5
SH:6
UART
(Debug Term)
UART0
SH:6
SH:20
SPI
UART1
SH:6
DC #3 Connector
SH:31
SH:3
MSP430
IR/RTC/SC
A
SPECTRUM DIGITAL INCORPORATED
Resistor
Pop Option
PWM [2:1]
SH:5
SH:28
SH:28
A
DC #4 Connector
SH:30
I2C
Title:
Page Contents:
TMS320DM6446 EVALUATION MODULE
DAVINCI BLOCK DIAGRAM
SH:6
5
(8) LEDs
EEPROM
SH:27
SH:6
Size:B
DWG NO
Date: Wednesday, March 14, 2007
4
3
2
Revision:
E
508162-0001
Sheet
1
2
of
35
5
4
3
2
RN7
RN3
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
D
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
1
U28B
EM_D[0:15] 12,13,14,29
EM_A[3:21] 12,13,14,29
RPACK8-10
RPACK8-10
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
E5
D3
F5
E3
E4
D2
F4
C1
EM_D00/DD00/HD00
EM_D01/DD01/HD01
EM_D02/DD02/HD02
EM_D03/DD03/HD03
EM_D04/DD04/HD04
EM_D05/DD05/HD05
EM_D06/DD06/HD06
EM_D07/DD07/HD07
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
F3
E2
G5
G4
D1
F2
H5
E1
EM_D08/DD08/HD08
EM_D09/DD09/HD09
EM_D10/DD10/HD10
EM_D11/DD11/HD11
EM_D12/DD12/HD12
EM_D13/DD13/HD13
EM_D14/DD14/HD14
EM_D15/DD15/HD15
RN9
EM_A21/GPIO10/VLYNQ_TXD0
EM_A20/GPIO11/VLYNQ_RXD0
EM_A19/GPIO12/VLYNQ_TXD1
EM_A18/GPIO13/VLYNQ_RXD1
EM_A17/GPIO14/VLYNQ_TXD2
EM_A16/GPIO15/VLYNQ_RXD2
EM_A15/GPIO16/VLYNQ_TXD3
EM_A14/GPIO17/VLYNQ_RXD3
1
2
3
4
5
6
7
8
T3
R3
R4
P5
R2
R5
P3
P4
RN2
EM_A13/GPIO18
EM_A12/GPIO19
EM_A11/GPIO20
EM_A10/GPIO21
EM_A9/GPIO22
EM_A8/GPIO23
EM_A7/GPIO24
EM_A6/GPIO25
N4
R1
P2
P1
M4
N3
N2
N1
1
2
3
4
5
6
7
8
EM_A5/GPIO26
EM_A4/GPIO27
EM_A3/GPIO28
EM_A2/(CLE)/HCNTL0
K3
K4
K2
J1
EM_A1/(ALE)/HHWIL
J2
EM_A0/DA2/HCNTL1/GPIO53
J4
1
2
3
4
5
6
7
8
EM_BA1/DA1/GPIO52
EM_BA0/DA0/HINTn
H2
J3
EM_CS5n/GPIO8/VLYNQ_CLOCK
EM_CS4n/GPIO9/VLYNQ_SCRUN
EM_CS3n
EM_CS2n/HCSn
T1
T2
B1
C2
GPIO51/ATA_CS1
GPIO52/ATA_CS0
H1
J5
EM_WEn/WEn/IOWRn/DIOWn/HDS2n
EM_OEn/REn/IORDn/DIORn/HDS1n
EMRWn/INTRQ/HRWn
G2
H4
G3
RPACK8-10
RN8
16
15
14
13
12
11
10
9
RPACK8-10
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
EM_A21
EM_A20
EM_A19
EM_A18
EM_A17
EM_A16
EM_A15
EM_A14
D
EM_A13
EM_A12
EM_A11
EM_A10
EM_A9
EM_A8
EM_A7
EM_A6
EM_A5
EM_A4
EM_A3
CLE_EM_A2 12,13,15,29
ALE_EM_A1 12,13,15,29
ATA2_EM_A0 12,13,15,29
ATA1_EM_BA1 12,13,15,29
ATA0_EM_BA0 15,29
RPACK8-10
R179
C
CPU.VLYNQ_CLK
VLYNQ_CLK
22
R394
NO-POP
VLYNQ_CLK 32
C
C170
NO-POP
C171
NO-POP
VCC_1.8V
R171
243
F1
15,29 W AIT/BUSY
B
EM_WAIT/(RDY_BUSYn)/IORDYn/HRDYn
DMARQ/UART_RXD1
DMACK/UART_TXD1
G1
H3
R180
R167
R169
22
22
22
R175
R174
22
22
VLYNQ_SCRUN
VLYNQ_SCRUN 32
EM_CS3
29
EM_CS2
10,15
ATA_CS1
ATA_CS0
15,29
15,29
R170
R168
R203
22
22
22
WRITE_WE 12,13,15,29
READ_OE 12,13,15,29
INTRQ_EM_RNW 15,29
R173
R172
22
22
UART_RXD1/DMARQ 15
UART_TXD1/DMACK 15
B
TMS320DM6446
VCC_1.8V
R161
1K
15,29 INTRQ_EM_RNW
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
DAVINCI EMIF INTERFACE
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
3
of
35
5
4
3
2
11 DDR_D[0:31]
1
DDR_A[0:12] 11
RN17
U28A
U1
U2
V1
V2
W2
U3
V3
W3
DDR_D00
DDR_D01
DDR_D02
DDR_D03
DDR_D04
DDR_D05
DDR_D06
DDR_D07
DDR_D8
DDR_D9
DDR_D10
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
V4
W4
U5
V5
W5
V6
W6
V7
DDR_D08
DDR_D09
DDR_D010
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
W14
V14
W15
V15
U15
W16
V16
T17
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
V17
U17
U18
W17
V18
W18
V19
U19
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_A00
DDR_A01
DDR_A02
DDR_A03
DDR_A04
DDR_A05
DDR_A06
DDR_A07
DDR_A08
DDR_A09
DDR_A10
DDR_A11
DDR_A12
DDR_BS00
DDR_BS01
DDR_BS02
DDR_CSn
DDR_CLK0
DDR_CLK0n
W13
U13
V13
U12
V12
W12
W11
V11
V10
U11
U10
W10
W9
4
3
2
1
BDDR_A0
BDDR_A1
BDDR_A2
BDDR_A3
BDDR_A4
BDDR_A5
BDDR_A6
BDDR_A7
BDDR_A8
BDDR_A9
BDDR_A10
BDDR_A11
RN10
4
3
2
1
RN12
4
3
2
1
U8
V9
U9
BDDR_A12 RN11 4
BDDR_BS00
3
BDDR_BS01
2
BDDR_BS02
1
T9
BDDR_CS
W7
W8
BDDR_CLK
R206
BDDR_CLK_N R205
DDR_CKE
V8
DDR_RASn
U7
DDR_CASn
T7
DDR_WEn
T8
R41
5
6
7
8
DDR_A0
DDR_A1
DDR_A2
DDR_A3
D
RPACK4-47
5 DDR_A4
6 DDR_A5
7 DDR_A6
8 DDR_A7
RPACK4-47
5 DDR_A8
6 DDR_A9
7 DDR_A10
8 DDR_A11
RPACK4-47
5 DDR_A12
6 DDR_BS00
7 DDR_BS01
8 DDR_BS02
ROUTE CLOCK DIFFERENTIAL WITH 15 MIL SPACING BETWEEN
DDR_BS00 11
DDR_BS01 11
DDR_BS02 11
47
DDR_CS
47
47
DDR_CLK
DDR_CLK_N
RPACK4-47
5
6
7
8
BDDR_CKE
BDDR_RAS
BDDR_CAS
DDR_CS 11
DDR_CLK 11
DDR_CLK_N 11
RN13
4
3
2
1
B
11 VREF_STL
VREF_STL
T15
DDR_VREF
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
BDDR_DQS0
BDDR_DQS1
BDDR_DQS2
BDDR_DQS3
R181
R182
R220
R221
47
47
47
47
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
T4
T6
T14
T16
BDDR_DQM0
BDDR_DQM1
BDDR_DQM2
BDDR_DQM3
R33
R32
R51
R52
47
47
47
47
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_ZP
T13
R219
200
DDR_ZN
T12
R204
200
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
11
11
11
11
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
11
11
11
11
TP39
11
11
11
11
TP40
VCC_1.8V
R53
DDR_VDDDLL
T10
DDR_VSSDLL
T11
R218
R8
1
RSV7
DDR_CKE
DDR_WE
DDR_RAS
DDR_CAS
BDDR_WE
U4
U6
U14
U16
C216
0.22uF
PLACE RESISTOR BY DATA TERMINATOR PINS
BALANCE LINE LENGTHS WITH DATA BYTES LENGTHS
C
DDR_CKE
DDR_WE
DDR_RAS
DDR_CAS
1
C
DDR_D0
DDR_D1
DDR_D2
DDR_D3
DDR_D4
DDR_D5
DDR_D6
DDR_D7
L10
1
D
RPACK4-47
0.22
1
2
BLM21PG221SN1D
B
0
C189
0.1uF
TP7
C190
1uF
TMS320DM6446
1
TP38
1
TP17
1
TP6
1
TP45
SURFACE MOUNT TEST POINT PADS
USED FOR VERIFYING DDR TIMINGS
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
DAVINCI DDR INTERFACE
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
4
of
35
5
4
3
2
1
VCC_3.3V
VCC_3.3V
U28I
VCC_1.8V
C267
C268
C269
0.1uF
0.1uF
0.1uF
C265
+
23,30
23,30
23,30
23,30
23,30
23,30
23,30
23,30
23,30
CI7/CCD15/UART_RXD2
CI6/CCD14/UART_TXD2
CI5/CCD13/UART_CTS2
CI4/CCD12/UART_RTS2
CI3/CCD11
CI2/CCD10
CI1/CCD09
CI0/CCD08
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
L18
L17
L16
L15
K19
K18
K17
K16
YI7/CCD07
YI6/CCD06
YI5/CCD05
YI4/CCD04
YI3/CCD03
YI2/CCD02
YI1/CCD01
YI0/CCD00
M19
PCLK
23,30
VD
L19
23,30
HD
M18
YOUT7/R7
YOUT6/R6
YOUT5/R5
YOUT4/R4/AEAW4
YOUT3/R3/AEAW3
YOUT2/G7/AEAW2
YOUT1/G6/AEAW1
YOUT0/G5/AEAW0
RN21
COUT7/G4
COUT6/G3
COUT5/G2
COUT4/B7
COUT3/B6/DSP_BT
COUT2/B5/EM_WIDTH
COUT1/B4/BTSEL1
COUT0/B3/BT_SEL0
HD
8
7
6
5
4
3
2
1
C16
B19
B18
A18
B17
A17
B16
A16
9
10
11
12
13
14
15
16
YOUT7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
RPACK8-33
9
10
11
12
13
14
15
16
R296
10K
R298
10K
R300
10K
7
6
5
PLL.SR
PLL.FS2
PLL.FS1
30
30
28 PLL.CSEL
30
30
10,30
10,30
10,30
10,30
VCLK
D19
VSYNC
C18
R233
22
VSYNC
30
HSYNC
C17
R232
22
HSYNC
30
VPBECLK
C19
R234
22
VCLK
C71
10 uF
0.1uF
U55
28
28
28
COUT7
COUT6
COUT5
COUT4
COUT3
COUT2
COUT1
COUT0
RPACK8-33
22
R299
10K
30
30
30
10,30
10,30
10,30
10,30
10,30
RN18
R236
PCLK
VD
8
7
6
5
4
3
2
1
E18
E17
E16
E15
D18
D17
D16
D15
5
N19
N18
N17
N16
N15
M17
M16
M15
VDD3
VDD2
VDD1
20
13
1
DGND3
DGND2
DGND1
17
16
4
SCKO3
SCKO2
SCKO1
SCKO0
3
2
19
18
MCKO2
MCKO1
15
14
4 R291
2
3
1
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
R301
NO-POP
30
SR
FS2
FS1
12
CSEL
10
XT1
11
XT2
R294
R292
R293
R295
R297
R216
22
PWM1/R2/GPIO46
B15
R194
22
33
VCC
8
AGND
9
R302
0
VCC_1.8V
C266
0.1uF
C270
0.1uF
PLL1705
2
VPBECLK 30
PWM0/GPIO45
C15
PWM2
3
1
30
C271
NO-POP
Y5
VCC_3.3V
C310
NO-POP
VID_CLK 30
C
VCC_3.3V
R307
1K
C311
0.1uF
27MHz
R304
2.2K
U54
1
2
3
4
R303 100K
22.1K 1%
8
7
6
5
X1
X2
NC1
NC2
VIN
VDD
GND CLKOUT
R365
33
PI6CX100-27W
VCC_1.8V
B
Q1
2N3904
C273
1
33
TP67
1
R305
R290
4
U57
SN74AUC1G125
30
PWM1
VCC_1.8V
TMS320DM6446
D
VCC_3.3V
27 3V3.DC_PCLK
A15
AUDIO_CLK 26,31
NO-POP
33
NO-POP
NO-POP
C
PWM2/B2/GPIO47
33
U56
SN74AUC1G125
5
D
30
30
30
30
30
30
30
30
C312
10pF
C272
0.1uF
L22
BLM21PG221SN1D
B
CPLD_TIMER_IN 15
R18
TP55
C233
.001uF
P17
VSSA_1P8V
P16
VDDA_1P1V
1
R62
DAC_IOUT_A
P19
DAC_IOUTA 25
DAC_IOUT_B
P18
DAC_IOUTB 25
DAC_IOUT_C
R19
DAC_IOUTC 25
DAC_IOUT_D
T19
DAC_IOUTD 25
DAC_VREF
R17
VREF_0.5V
DAC_RBIAS
R16
R239
VCC_3.3V
0.22
C66
10uF
+
C230
.1uF
C231
.001uF
T18
R242
1K
R243
0
VSSA_1P1V
R241
4.02K
C234
.1uF
R240
4.99K
7.5K
3
C232
.1uF
L21
BLM21PG221SN1D
1
VDDA_1P8V
+
VREF_1.24V
C235
1uF
VREF =1.24 VOLTS
SPECTRUM DIGITAL INCORPORATED
Title:
4
Page Contents:
R244
NO-POP
TMS320DM6446 EVALUATION MODULE
DAVINCI VIDEO INTERFACE
TLV431ADBV
Size:B
TMS320DM6446
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
U39
5
1
0.22
C65
10uF
TP61
2
33
U28G
1
R63
DSP_CORE_VDD
A
R366
1
TP53
1
2
TP66 100pF
TP54
Sheet
1
5
of
35
5
4
3
2
1
U28C
GPIOV33_0/TXEN
GPIOV33_1/TXCLK
GPIOV33_2/COL
GPIOV33_3/TXD0
B13
A13
A12
B12
GIOV33_0
GIOV33_1
GIOV33_2
GIOV33_3
22,31
22,31
22,31
22,31
GPIOV33_4/TXD1
GPIOV33_5/TXD2
GPIOV33_6/TXD3
GPIOV33_7/RXD0
D12
A11
C12
E12
GIOV33_4
GIOV33_5
GIOV33_6
GIOV33_7
22,31
22,31
22,31
22,31
GPIOV33_8/RXD1
GPIOV33_9/RXD2
GPIOV33_10/RXD3
GPIOV33_11/RXCLK
C11
B11
E11
A10
GIOV33_8 22,31
GIOV33_9 22,31
GIOV33_10 22,31
GIOV33_11 22,31
GPIOV33_12/RXDV
GPIOV33_13/RXER
GPIOV33_14/CRS
GPIOV33_15/MDIO
D11
D10
C10
E10
GIOV33_12
GIOV33_13
GIOV33_14
GIOV33_15
GPIOV33_16/MDC
B10
GIOV33_16 22,31
GPIO0/LCD_OE
GPIO1/C_WEn
GPIO2/G0
GPIO3/B0/LCD_FIELD
GPIO4/R0/C_FIELD
GPIO5/G1
GPIO6/B1
GPIO38/R1
C13
E13
D13
C14
B14
E14
A14
D14
GIO0
GIO1
GIO2
GIO3
GIO4
GIO5
GIO6
GIO38
D
D
22,31
22,31
22,31
22,31
VCC_3.3V
C
UART_RXD0/GPIO35
UART_TXD0/GPIO36
D5
C5
SCL/GPIO43
SDA/GPIO44
C4
B4
UART_RXD0
UART_TXD0
R197
SPI_EN0/GPIO37
SPI_CLK/GPIO39
SPI_DO/GPIO41
SPI_DI/GPIO40
A4
A3
A2
B3
SPI_EN1/HDDIR/GPIO42
B2
1
2
3
4
GPIO7
B
C3
R198
R201
VCC_1.8V
R215
2.2K
R214
2.2K
R213
100K
C
C195
0.1uF
U33
PCA9306
UART_RXD0 20
UART_TXD0 20
22
8
7
6
5
RN14
VCC_1.8V
30
30
30
30
30
30
30
30
SPI_EN0
31
SPI_CLK
SPI_DO
SPI_DI
31
31
31
2 VREF1
C194
0.1uF
VREF2
7
I2C_CLK
3
SCL1
SCL2
6
I2C_DATA
4 SDA1
SDA2
5
GND
ENABLE
8
1
RPACK4-22
3V3.I2C_CLK
3V3.I2C_DATA
3V3.I2C_CLK 24,27,28
3V3.I2C_DATA 24,27,28
1V8.I2C_CLK 26,30,31
22
22
SPI_EN1
ATA_DIR
31
15
1V8.I2C_DATA 26,30,31
1V8.MSP430_INT
R410
10K
VCC_3.3V
B
VCC_3.3V
TMS320DM6446
C162
0.1uF
R212
2.2K
VCC_1.8V
R211
2.2K
U34
1
2
3
4
R424
10K
A0
A1
NC
VSS
VCC
WP
SCL
SDA
8
7
6
5
24WC256
15 1V8.MSP430_INT
EEPROM ( 32KBytes )
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
DAVINCI I/O INTERFACE
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
6
of
35
5
4
3
2
1
U28F
RN16
D
FSX/GPIO31
C8
FSR/GPIO32
C7
DX/GPIO33
B7
RPACK4-22
4
3
2
1
5
6
7
8
DR/GPIO34
A7
CLKX/GPIO29
B8
R200
22
CLKR/GPIO30
A8
R199
22
SD_DATA0
D8
SD_DATA1
E9
SD_DATA2
D9
SD_DATA3
C9
SD_CMD
B9
R196
22
SD_CLK
A9
R195
22
FSX
FSR
DX
DR
31
31
27,31
31
D
CLKX
31
CLKR
31
RN15
1
2
3
4
8
7
6
5
SD_DATA0
SD_DATA1
SD_DATA2
SD_DATA3
16,31,32
16,31,32
16,31,32
16,31,32
RPACK4-22
SD_CMD 16,31,32
SD_CLK
16,31,32
74CBTLV3245
U53
TMS320DM6446
C
1
VCC_3.3V L15
TP49
1
TP48
R61
1
2
BLM21PG221SN1D
0.22
U28H
C60
10uF
+
C212
0.1uF
C211
0.01uF
J19
USB_VDDA3P3.1
J18
USB_VSSA3P3.2
R309
360
USB_VBUS
J17
USB_VBUS 21
USB_ID
J16
USB_ID
21
USB_DP
G19
USB_DP
21
USB_DM
H19
USB_R1
H18
2
3
4
5
6
7
8
9
A1
A2
A3
A4
A5
A6
A7
A8
B1
B2
B3
B4
B5
B6
B7
B8
18
17
16
15
14
13
12
11
19
1
G
NC
VCC
20
GND
10
B_FSX
B_FSR
B_DX
B_DR
B_CLKX
B_CLKR
26
26
26
26
26
26
C
VCC_3.3V
C274
0.1uF
TP46
1
2
BLM21PG221SN1D
31 McBSP_EN
1
L13
1
TP47
VCC_1.8V
R60
0.22
C59
10uF
B
H17
USB_VDD1P8
+
C209
0.1uF
C206
1uF
R308
10K
USB_DM 21
C207
0.01uF
H16
USB_VSS1P8
G18
USB_VDDA1P2LDO
G17
USB_VSSA1P2LDO
U53 is a switch used for DC3 to allow the McBSP
to be disconnected from on-board circuitry.
Signal levels are at 1.8 Volt logic levels on both
sides of switch
B
R217
10K
USB_VSSREF
G16
Place R217 as close to device as possible
TMS320DM6446
Place C206 as close to device as possible, between 2 to 5 millimeters
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
DAVINCI USB & SD/MMC/MMC CONTROLLER
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
7
of
35
15 TIMER_IN
U28E
L4
13,15,26,29,30,31,34 1.8V.SYS_RESETz
CLK_OUT1/TIM_IN/GPIO49
E19
RESETn
OPTIONAL OSCILLATOR POPULATION
CLK_OUT0/GPIO48
33 DSP_RTCK
B6
RTCK
33 DSP_TCK
A6
TCK
33 DSP_TMS
E6
TMS
33 DSP_TRST#
D7
TRSTn
DSP_TDI
33 DSP_TDO
B5
TDO
33 DSP_EMU1
C6
EMU1
33 DSP_EMU0
D6
EMU0
33
VCC_1.8V
TP19
TDI
VCC_1.8V
R238
NO-POP
M24XI
F17
R237
M2
C147
1uF
C138
0.1uF
C137
1000pF
M3
PLLVDD18
RSV24
NO-POP
1
L5
1
2
1
TP18
NO-POP
18pF
RSV6
MXVSS
C141
.1uF
U12
C139
R177
GND
L2
Y2
27MHz
L1
L2
1
2
1
2
BLM21PG221SN1D
18pF
EIA0402
R178
L3
OUT
EN
NO-POP/24 MHz
VCC_1.8V
R176
NO-POP
MXI/CLKIN
3
VCC
NO-POP
4
VCC
EN
1
3
OUT
GND
2
0
NO-POP/27 MHz
1
TP20
4
0
TP10
DSP_CORE_VDD
18pF
VCC_1.8V
M1
U40
EIA0402
C144
0.22
1
2
BLM21PG221SN1D
C227
.1uF
R235
M24VSS
CRYSTAL AND CAPS REMOVED WHEN
OSCILLATOR IS USED
L14
24MHz
C229
F18
1
R35
VCC_1.8V
TP8
1
1
2
BLM21PG221SN1D
F19
18 pF
Y3
MXO
L6
CLKOUT0 29
C228
M24XO
A5
K1
R34
NO-POP
TP9
C148
NO-POP
C142
NO-POP
C140
NO-POP
1
TMS320DM6446
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
DAVINCI EMULATION & CLOCKS
DWG NO
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
Sheet
8
of
35
5
4
3
2
1
U28D
TP32
R202
D4
RSV5
CPU_VCC_3.3V
+
1
VCC_3.3V
0
1
TP22
R36
+
0.025
C30
22uF
CPU_VCC_3.3V
C127
NO-POP
D
TP41
F13
F12
F11
F10
TP42
R54
+
C132
NO-POP
TP30
TP31
R42
CPU_DSP_CORE_VDDIMX
0.025
+
C130
NO-POP
C
K11
K9
K8
J13
J11
J10
J9
H12
H11
H10
H8
CVDDDSP.11
CVDDDSP.10
CVDDDSP.9
CVDDDSP.8
CVDDDSP.7
CVDDDSP.6
CVDDDSP.5
CVDDDSP.4
CVDDDSP.3
CVDDDSP.2
CVDDDSP.1
TP11
T5
R15
R13
R11
R9
P14
P12
P10
P8
P6
N13
N11
N9
N7
DVDDR2.14
DVDDR2.13
DVDDR2.12
DVDDR2.11
DVDDR2.10
DVDDR2.9
DVDDR2.8
DVDDR2.7
DVDDR2.6
DVDDR2.5
DVDDR2.4
DVDDR2.3
DVDDR2.2
DVDDR2.1
1
TP21
1
VCC_1.8V
CVDD.10
CVDD.9
CVDD.8
CVDD.7
CVDD.6
CVDD.5
CVDD.4
CVDD.3
CVDD.2
CVDD.1
R37
0.025
CPU_VCC_1.8V
+
C125
NO-POP
B
CPU_VCC_1.8V
A
N5
M14
M6
L13
L7
K14
K6
J15
J7
H14
H6
G15
G9
G7
F14
F8
F6
E7
DVDD18.18
DVDD18.17
DVDD18.16
DVDD18.15
DVDD18.14
DVDD18.13
DVDD18.12
DVDD18.11
DVDD18.10
DVDD18.9
DVDD18.8
DVDD18.7
DVDD18.6
DVDD18.5
DVDD18.4
DVDD18.3
DVDD18.2
DVDD18.1
F16
L5
M24VDD
MXVDD
0.1uF
C181
0.1uF
CPU_DSP_CORE_VDD
+
C49
22uF
C48
22uF
C187
C185
C208
C201
C199
C200
C183
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C169
C186
C167
C182
C168
0.1uF
0.1uF
0.1uF
CPU_DSP_CORE_VDDIMX
+
+
C40
22uF
1
1
DSP_CORE_VDDIMX
M12
M10
M8
L11
L10
L9
L8
K12
K10
F15
C174
0.1uF
D
+
CPU_DSP_CORE_VDD
0.025
C180
0.1uF
W19
A19
W1
A1
1
1
DSP_CORE_VDD
DVDD33.4
DVDD33.3
DVDD33.2
DVDD33.1
RSV4
RSV2
RSV3
RSV1
C177
C29
22uF
C184
0.1uF
0.1uF
0.1uF
C
CPU_VCC_1.8V
+
VSS.45
VSS.44
VSS.43
VSS.42
VSS.41
VSS.40
VSS.39
VSS.38
VSS.37
VSS.36
VSS.35
VSS.34
VSS.33
VSS.32
VSS.31
VSS.30
VSS.29
VSS.28
VSS.27
VSS.26
VSS.25
VSS.24
VSS.23
VSS.22
VSS.21
VSS.20
VSS.19
VSS.18
VSS.17
VSS.16
VSS.15
VSS.14
VSS.13
VSS.12
VSS.11
VSS.10
VSS.9
VSS.8
VSS.7
VSS.6
VSS.5
VSS.4
VSS.3
VSS.2
VSS.1
+
C31
22uF
R14
R12
R10
R7
R6
P15
P13
P11
P9
P7
N14
N12
N10
N8
N6
M13
M11
M9
M7
M5
L14
L12
L6
K15
K13
K7
K5
J14
J12
J8
J6
H15
H13
H9
H7
G14
G13
G12
G11
G10
G8
G6
F9
F7
E8
C28
22uF
C215
C214
C213
C210
C111
C204
C179
C188
C134
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C135
C203
C176
C178
0.1uF
0.1uF
CPU_VCC_1.8V
+
+
C58
22uF
C47
22uF
C113
C145
0.1uF
0.1uF
0.1uF
C136
0.1uF
0.1uF
C175
0.1uF
C115
0.1uF
CPU_VCC_1.8V
C202
+
C27
22uF
0.1uF
C143
C146
C205
0.1uF
0.1uF
0.1uF
B
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
TMS320DM6446
Size:B
TMS320DM6446 EVALUATION MODULE
DAVINCI POWER PINS
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
9
of
35
5
4
3
2
1
BOOT CONFIGURATION SWITCH
D
D
PINS
FUNCTION
MODE
SWITCH S1
16
15
14
13
12
11
10
9
Selects ARM Boot Mode
Non-secure device
BTSEL[1:0]
00 = Boot from ROM (NAND)
S1-2=XXX S1-1=XXX
01 = Boot from AEM IF
S1-2=XXX S1-1=XXX
10 = Boot from ROM (HPI)
S1-2=XXX S1-1=XXX
11 = Boot from ROM (UART)
S1-2=XXX S1-1=XXX
RN28
RPACK8-NO-POP
R228
NO-POP
R227
10K
1
2
3
4
5
6
7
8
COUT[1:0]
VCC_1.8V
RN29
RPACK8-1K
S3
Selects AEM IF CS2 Bus Width
COUT2
8_16
C
0 = 8-bit
S1-3=XXX
1 = 16-bit
S1-3=XXX
DSP BOOT
COUT3
DSP_BT
0 = ARM boots GEM
S1-4=XXX
1 = GEM Self-Boots
S1-4=XXX
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R229
R230
1K
1K
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
COUT0
COUT1
COUT2
COUT3
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
C
DIP_SWITCH-10
SPARE SWITCH
USER_SW 28
Address Bus Width
S1-5=XXX
S1-6=XXX
ALL ADDRESS LINES GPIO
S1-7=XXX
YOUT[4:0]
AEAW [4:0]
S1-8=XXX
J4
3,15 EM_CS2
S1-9=XXX
B
1
3
5
7
2
4
6
8
FLASH_CEz 13
SRAM_CEz 12
NAND_CEz 12
DC_EM_CS2 29
B
CONN 4x2
ONLY ONE DEVICE CAN BE SELECTED
AT A TIME AT POWER UP.
TO RECONFIGURE BOARD
POWER DOWN EVM,
CHANGE JUMPER TO DESIRED DEVICE.
SPECTRUM DIGITAL INCORPORATED
A
Title:
TMS320DM6446 EVALUATION MODULE
Page Contents:
DAVINCI CONFIGURATION CONTROL/BOOT OPTIONS
Size:B
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
10 o f
35
5
4
3
2
1
4 DDR_A[0:12]
VCC_1.8V
VCC_1.8V
U20
D
V2
U7
R2
U3
U8
U2
T7
T3
A12
A11
A10
A9
A8
A7
A6
A5
DDR_A4
DDR_A3
DDR_A2
DDR_A1
DDR_A0
T8
T2
R7
R3
R8
P1
P3
P2
A4
A3
A2
A1
A0
BA2
BA1
BA0
DDR_BS02
DDR_BS01
DDR_BS00
4 DDR_BS02
4 DDR_BS01
4 DDR_BS00
C
R151
0
4 DDR_CS
4 DDR_CAS
4 DDR_RAS
4 DDR_WE
4 DDR_CKE
4 DDR_CLK
4 DDR_CLK_N
4 DDR_DQS0
4 DDR_DQM1
4 DDR_DQM0
AA9
AA8
AA2
AA1
D2
V8
A9
A8
A2
A1
H2
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
V3
V7
N9
RFU.1
RFU.2
ODT
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
P8
P7
N7
N3
N2
CS#
CAS#
RAS#
WE#
CKE
DDR_CLK
DDR_CLK_N
M8
N8
CK
CK#
DDR_DQS0
D8
E7
H8
J7
UDQS#/NU
UDQS
LDQS#/NU
LDQS
DDR_DQM1
DDR_DQM0
E3
J3
UDM
LDM
DDR_DQS1
4 DDR_DQS1
B
U32
DDR_A12
DDR_A11
DDR_A10
DDR_A9
DDR_A8
DDR_A7
DDR_A6
DDR_A5
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
VDDQ.5
VDDQ.6
VDDQ.7
VDDQ.8
VDDQ.9
VDDQ.10
M9
H1
R9
D1
V1
F3
F7
K1
K3
K7
K9
D9
F1
F9
H9
VDDL
M1
VREF
M2
C224
C150
C151
C154
0.1uF
0.1uF
0.1uF
0.1uF
C156
C155
C152
C157
0.1uF
0.1uF
0.1uF
0.1uF
C153
0.1uF
+ C18
22 uF
DDR_A12
DDR_A11
DDR_A10
DDR_A9
DDR_A8
DDR_A7
DDR_A6
DDR_A5
V2
U7
R2
U3
U8
U2
T7
T3
A12
A11
A10
A9
A8
A7
A6
A5
DDR_A4
DDR_A3
DDR_A2
DDR_A1
DDR_A0
T8
T2
R7
R3
R8
P1
P3
P2
A4
A3
A2
A1
A0
BA2
BA1
BA0
DDR_BS02
DDR_BS01
DDR_BS00
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
VDDQ.5
VDDQ.6
VDDQ.7
VDDQ.8
VDDQ.9
VDDQ.10
M9
H1
R9
D1
V1
F3
F7
K1
K3
K7
K9
D9
F1
F9
H9
VDDL
M1
DQ15
DQ14
DQ13
DQ12
E9
E1
G9
G1
BDDR_D15
BDDR_D14
BDDR_D13
BDDR_D12
DQ11
DQ10
DQ9
DQ8
G3
G7
F2
F8
BDDR_D11
BDDR_D10
BDDR_D9
BDDR_D8
DQ7
DQ6
DQ5
DQ4
J9
J1
L9
L1
DQ3
DQ2
DQ1
DQ0
L3
L7
K2
K8
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSSQ.1
VSSQ.2
VSSQ.3
VSSQ.4
VSSQ.5
VSSQ.6
VSSQ.7
VSSQ.8
VSSQ.9
VSSQ.10
VSSDL
U9
T1
H3
D3
M3
G8
J8
D7
J2
E2
L8
L2
E8
H7
G2
M7
1
2
3
4
RPACK4-47
8DDR_D13
7DDR_D15
6DDR_D8
5DDR_D10
1
2
3
4
BDDR_D7
BDDR_D6
BDDR_D5
BDDR_D4
BDDR_D5
BDDR_D7
BDDR_D0
BDDR_D2
RN27
RN6
BDDR_D12
BDDR_D14
BDDR_D11
BDDR_D9
1
2
3
4
8DDR_D5
7DDR_D7
6DDR_D0
5DDR_D2
RPACK4-47
RPACK4-47
8DDR_D12
7DDR_D14
6DDR_D11
5DDR_D9
BDDR_D3
BDDR_D2
BDDR_D1
BDDR_D0
BDDR_D4
BDDR_D6
BDDR_D3
BDDR_D1
1
2
3
4
8DDR_D4
7DDR_D6
6DDR_D3
5DDR_D1
RN5
R152
0
RPACK4-47
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
V3
V7
N9
RFU.1
RFU.2
ODT
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
P8
P7
N7
N3
N2
CS#
CAS#
RAS#
WE#
CKE
DDR_CLK
DDR_CLK_N
M8
N8
CK
CK#
DDR_DQS2
D8
E7
H8
J7
UDQS#/NU
UDQS
LDQS#/NU
LDQS
DDR_DQM3
DDR_DQM2
E3
J3
UDM
LDM
4 DDR_DQS3
4 DDR_DQS2
4 DDR_DQM3
4 DDR_DQM2
MT47H64M16BT
AA9
AA8
AA2
AA1
D2
V8
A9
A8
A2
A1
H2
VREF
M2
DQ15
DQ14
DQ13
DQ12
E9
E1
G9
G1
BDDR_D31
BDDR_D30
BDDR_D29
BDDR_D28
DQ11
DQ10
DQ9
DQ8
G3
G7
F2
F8
BDDR_D27
BDDR_D26
BDDR_D25
BDDR_D24
DQ7
DQ6
DQ5
DQ4
J9
J1
L9
L1
BDDR_D23
BDDR_D22
BDDR_D21
BDDR_D20
DQ3
DQ2
DQ1
DQ0
L3
L7
K2
K8
BDDR_D19
BDDR_D18
BDDR_D17
BDDR_D16
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSSQ.1
VSSQ.2
VSSQ.3
VSSQ.4
VSSQ.5
VSSQ.6
VSSQ.7
VSSQ.8
VSSQ.9
VSSQ.10
VSSDL
U9
T1
H3
D3
M3
G8
J8
D7
J2
E2
L8
L2
E8
H7
G2
M7
DDR_DQS3
C221
0.1uF
C219
0.1uF
C225
0.1uF
C57
22 uF
+
C102
NO-POP
D
VCC_1.8V
C149
C223
0.1uF
C217
0.1uF
0.1uF
C218
0.1uF
R208
1K 1%
VREF_STL 4
VREF_STL
BDDR_D[0:15]
RN26
BDDR_D13
BDDR_D15
BDDR_D8
BDDR_D10
+
C222
0.1uF
C220
0.1uF
VREF_STL
R207
1K 1%
BDDR_D[16:31]
RN20
BDDR_D26 1
BDDR_D29 2
BDDR_D24 3
BDDR_D31 4
RPACK4-47
8 DDR_D26
7 DDR_D29
6 DDR_D24
5 DDR_D31
BDDR_D28
BDDR_D30
BDDR_D25
BDDR_D27
RN30
RN19
BDDR_D23
BDDR_D18
BDDR_D16
BDDR_D21
1
2
3
4
1
2
3
4
8 DDR_D28
7 DDR_D30
6 DDR_D25
5 DDR_D27
RPACK4-47
RPACK4-47
8 DDR_D23
7 DDR_D18
6 DDR_D16
5 DDR_D21
BDDR_D19
BDDR_D17
BDDR_D22
BDDR_D20
1
2
3
4
8
7
6
5
RN31
C
DDR_D19
DDR_D17
DDR_D22
DDR_D20
RPACK4-47
B
MT47H64M16BT
128 MEGABYTES
128 MEGABYTES
4 DDR_D[0:31]
SPECTRUM DIGITAL INCORPORATED
A
Title:
TMS320DM6446 EVALUATION MODULE
Page Contents:
Size:B
DDR2 MEMORY
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Thursday, March 08, 2007
5
A
Sheet
1
11 o f
35
5
4
3
2
1
VCC_1.8V
B.EM_A19
B.EM_A18
B.EM_A17
B.EM_A16
B.EM_A15
B.EM_A14
B.EM_A13
B.EM_A12
B.EM_A11
B.EM_A10
VCC_1.8V
R137
10K
R138
10K
3,13,15,29 CLE_EM_A2
3,13,15,29 ALE_EM_A1
3,13,15,29 ATA2_EM_A0
3,13,15,29 ATA1_EM_BA1
EM_A9
EM_A8
EM_A7
EM_A6
EM_A5
EM_A4
EM_A3
CLE_EM_A2
ALE_EM_A1
ATA2_EM_A0
ATA1_EM_BA1
10 SRAM_CEz
C
SRAM_CE2
WRITE_WE
READ_OE
3,13,15,29 WRITE_WE
3,13,15,29 READ_OE
R134
0
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
B5
A6
CS1
CS2
G5
A2
WE
OE
B2
A1
UB
LB
EM_D[0:15] 3,13,14,29
C91
0.1uF
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
B6
C5
C6
D5
E5
F5
F6
G6
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
B1
C1
C2
D2
E2
F2
F1
G1
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
NC.1
E3
D
C
D1
E6
R136
0
H6
G2
H1
D3
E4
F4
F3
G4
G3
H5
H4
H3
H2
D4
C4
C3
B4
B3
A5
A4
A3
C90
0.1uF
VSS.1
VSS.2
3,13,14,29 EM_A[3:21]
D
U7
VCC.1
VCC.2
D6
E1
13,14,29 B.EM_A[10:21]
SAMSUNG->K1S3216BCD
SRAM ( 4MBytes )
VCC_1.8V
VCC_1.8V
R135
10K
R141
10K
VCC_1.8V
U6
B
A6
R/B
B2
RE
A4
CE
B3
CLE
ALE_EM_A1
A2
ALE
WRITE_WE
A5
WE
A1
WP
E6
LOCKPRE
15 NAND_BUSY
READ_OE
VCC_1.8V
10 NAND_CEz
CLE_EM_A2
R140
10K
VCC.1
VCC.2
F6
G4
I/O07
I/O06
I/O05
I/O04
I/O03
I/O02
I/O01
I/O00
G6
H5
G5
H4
H3
H2
G2
F2
VSS.1
VSS.2
VSS.3
A3
H1
H6
R139
NO-POP
B
C93
.1uF
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
NC.12
NC.13
NC.14
NC.15
NC.16
NC.17
NC.18
NC.19
NC.20
NC.21
NC.22
NC.23
NC.24
NC.25
NC.26
NC.27
R113
NO-POP
C92
.1uF
SPECTRUM DIGITAL INCORPORATED
NAND FLASH ( 64MBytes )
B1
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
F1
F3
F4
F5
G1
G3
A
Title:
Page Contents:
Size:B
SAMSUNG K9K1208/Q/D/U/0C
K9K1G08 supports 128 MEGABYTES
5
4
3
TMS320DM6446 EVALUATION MODULE
SRAM/NAND FLASH
DWG NO
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
2
A
Sheet
1
12 o f
35
5
4
3
U13
3,12,15,29 ATA1_EM_BA1
3,12,15,29 ATA2_EM_A0
3,12,15,29 ALE_EM_A1
3,12,15,29 CLE_EM_A2
D
ATA1_EM_BA1
ATA2_EM_A0
ALE_EM_A1
CLE_EM_A2
EM_A3
EM_A4
EM_A5
EM_A6
EM_A7
EM_A8
EM_A9
B.EM_A10
B.EM_A11
B.EM_A12
B.EM_A13
B.EM_A14
B.EM_A15
B.EM_A16
B.EM_A17
B.EM_A18
B.EM_A19
B.EM_A20
B.EM_A21
VCC_1.8V
R142
10K
NO-POP/AM29LV256M
31
26
25
24
23
22
21
20
10
9
8
7
6
5
4
3
54
19
18
11
12
15
2
1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
FLASH_CEz
READ_OE
WRITE_WE
10 FLASH_CEz
3,12,15,29 READ_OE
3,12,15,29 WRITE_WE
53
BYTE
32
34
13
CE
OE
WE
14
RESET
16
WP/ACC
1
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
35
37
39
41
44
46
48
50
36
38
40
42
45
47
49
51
RY/BY
17
VCC
VIO
43
29
VSS2
VSS1
52
33
NC1
NC2
NC3
NC4
NC5
27
28
30
55
56
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
VCC_1.8V
D
R143
10K
VCC_3.3V
3,12,14,29 EM_A[3:21]
12,14,29 B.EM_A[10:21]
2
EM_D[0:15] 3,12,14,29
VCC_1.8V
C94
.1uF
C173
.1uF
C
C
1.8V.SYS_RESETz
8,15,26,29,30,31,34 1.8V.SYS_RESETz
EM_WPn
VCC_1.8V
R114
10K
16 MBytes
VCC_1.8V
UX13
R115
10K
ATA1_EM_BA1
ATA2_EM_A0
ALE_EM_A1
CLE_EM_A2
EM_A3
EM_A4
EM_A5
EM_A6
EM_A7
EM_A8
EM_A9
B.EM_A10
B.EM_A11
B.EM_A12
B.EM_A13
B.EM_A14
B.EM_A15
B.EM_A16
B.EM_A17
B.EM_A18
B.EM_A19
B.EM_A20
B.EM_A21
R116
NO-POP
B
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
NC/A24
NC/A25
FLASH_CEz
READ_OE
B4
F8
CE
OE
WRITE_WE
G8
WE
D4
RSTn
C6
WPn
E6
CLK
F6
ADV
1.8V.SYS_RESETz
EM_WPn
A
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
F2
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
F4
F5
H5
G7
E7
WAIT
F7
VPP
A4
VCC.1
VCC.2
VCCQ.1
VCCQ.2
VCCQ.3
H3
A6
D5
G4
D6
VSS.1
VSS.2
VSS.3
VSS.4
B2
H4
H2
H6
RFU.1
RFU.2
RFU.3
RFU.4
RFU.5
F1
H1
G2
B8
E8
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
B
VCC_1.8V
C166
.1uF
C165
.1uF
C172
.1uF
C120
.1uF
SPECTRUM DIGITAL INCORPORATED
Title:
Page Contents:
A
TMS320DM6446 EVALUATION MODULE
NOR FLASH
Revision:
E
PC28F128P30T85
Size:B
DWG NO
508162-0001
Date: Wednesday, March 14, 2007
5
4
3
2
Sheet
1
13 o f
35
5
4
3
U11 is a switch used to enable Vlynq functions.
Signal levels are at 1.8 Volt logic levels on both
sides of switch
17
L
A TO B1
C
C116
C117
5.6pF
5.6pF
S
2
4
6
9
11
13
15
18
21
23
25
27
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
10B1
11B1
12B1
54
52
50
47
45
43
41
39
36
34
32
30
3
5
7
10
12
14
16
20
22
24
26
28
55
56
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
NC.12
NC.13
NC.14
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
10B2
11B2
12B2
53
51
48
46
44
42
40
37
35
33
31
29
SN74CBTLV16292DGGR
VLYNQ_RXD0
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD3
C373
560pF
B.VLNQ_TXD0
B.VLNQ_TXD1
B.VLNQ_TXD2
B.VLNQ_TXD3
R412
R413
R414
R415
22
22
22
22
R416
R417
R418
R419
22
22
22
22
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD3
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD3
D
32
32
32
32
WLAN_INTR 32
SLP_CLK_EN 32
ELP_REQ/WAKEUP 32
PM_EN
32
B.EM_A[10:21] 12,13,29
B.EM_A21
B.EM_A19
B.EM_A17
B.EM_A15
B.EM_A20
B.EM_A18
B.EM_A16
B.EM_A14
B.EM_A13
B.EM_A12
B.EM_A11
B.EM_A10
C
GND.1
GND.2
GND.3
GND.4
EM_A21
EM_A19
EM_A17
EM_A15
EM_A20
EM_A18
EM_A16
EM_A14
EM_A13
EM_A12
EM_A11
EM_A10
32
32
32
32
C121
0.1uF
VCC.1
10K
1
28 VLYNQ_ONz
3,12,13,29 EM_A[3:21]
U11
8
19
38
49
D
1
VCC_3.3V
VCC_3.3V
R144
2
VLYNQ_RXD0
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD3
R393
NO-POP
VCC_1.8V
C119
NO-POP
VCC_3.3V
R392
NO-POP
C118
NO-POP
B
B
3,12,13,29 EM_D[0:15]
C89
0.1uF
C106
0.1uF
U8
7
18
VCCB
VCCB
EM_D15
EM_D14
EM_D13
EM_D12
EM_D11
EM_D10
EM_D9
EM_D8
2
3
5
6
8
9
11
12
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
VCCA
VCCA
42
31
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
47
46
44
43
41
40
38
37
3V3.EM_D15
3V3.EM_D14
3V3.EM_D13
3V3.EM_D12
3V3.EM_D11
3V3.EM_D10
3V3.EM_D9
3V3.EM_D8
13
14
16
17
19
20
22
23
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
36
35
33
32
30
29
27
26
3V3.EM_D7
3V3.EM_D6
3V3.EM_D5
3V3.EM_D4
3V3.EM_D3
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
1
48
1DIR
1OEn
24
25
2DIR
2OEn
GND
GND
GND
GND
GND
GND
GND
GND
4
10
15
21
45
39
34
28
DIR
L
H
A
15 1V8.EM_DATA_BUF_DIR
15 1V8.EM_DATA_BUF_EN
C105
0.1uF
C88
0.1uF
3V3.EM_D[0:15] 17,18,19
SPECTRUM DIGITAL INCORPORATED
BUS
B->A
B<-A
Title:
Page Contents:
Size:B
4
TMS320DM6446 EVALUATION MODULE
EMIF LEVEL SHIFTER
DWG NO
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
SN74AVCB164245VR
5
A
Sheet
1
14 o f
35
5
4
3
2
1
L62
VCC_1.8V
VCC_3.3V
NO-POP
C126
0.1uF
16
17
18
19
20
21
26
27
3,10 EM_CS2
3,29 ATA_CS1
3,29 ATA_CS0
3 UART_TXD1/DMACK
3 UART_RXD1/DMARQ
DLOOP1
C
6
ATA_DIR
3,29 ATA0_EM_BA0
8
33
TIMER_IN
R368
31 TIMER_IN_DC3
DLOOP2
R369
NO-POP
3,29 INTRQ_EM_RNW
6 1V8.MSP430_INT
DLOOP3
3,29 W AIT/BUSY
DLOOP4
DLOOP5
8,13,26,29,30,31,34 1.8V.SYS_RESETz
ISR_TCK
ISR_TMS
ISR_TDI
ISR_TDO
VCC_1.8V
VCC_3.3V
BLM41P750SPT
R191
10K
B2.PIN52
B2.PIN53
B2.PIN54
B2.PIN55
B2.PIN56
B2.PIN57
B2.PIN58
B2.PIN61
52
53
54
55
56
57
58
61
3V3.ATA.DMARQ 18
3V3.ATA.INTRQ_EM_RNW 18
3V3.ATA.WAIT/BUSY 18
3V3.ATA.CS0 18
B1.PIN16
B1.PIN17
B1.PIN18
B1.PIN19
B1.PIN20
B1.PIN21
B1.PIN26
B1.PIN27
B2.PIN66
B2.PIN67
B2.PIN68
B2.PIN69
B2.PIN70
B2.PIN71
B2.PIN72
B2.PIN73
66
67
68
69
70
71
72
73
3V3.ATA.CS1 18
3V3.ATA.DA2 18
3V3.ATA.DMACK 18
3V3.ATA.DA1 18
3V3.ATA.DA0 18
3V3.ATA.DIOR 18
3V3.ATA.DIOW 18
3V3.ATA_RESETn 18
28
29
30
33
34
35
36
37
B1.PIN28
B1.PIN29
B1.PIN30
B1.PIN33
B1.PIN34
B1.PIN35
B1.PIN36
B1.PIN37
B2.PIN74
B2.PIN75
B2.PIN76
B2.PIN77
B2.PIN78
B2.PIN81
B2.PIN82
B2.PIN83
74
75
76
77
78
81
82
83
38
39
40
41
42
47
48
49
50
51
B1.PIN38
B1.PIN39
B1.PIN40
B1.PIN41
B1.PIN42
B1.PIN47
B1.PIN48
B1.PIN49
B1.PIN50
B1.PIN51
B2.PIN84
B2.PIN85
B2.PIN86
B2.PIN87
B2.PIN88
B2.PIN89
B2.PIN90
B2.PIN91
84
85
86
87
88
89
90
91
3V3.CF.WAIT/BUSY 19
3V3.CF.WRITE_WE 19
3V3.CF.READ_OE 19
3V3.CF.ATA_CS0 19
3V3.CF.ATA_CS1 19
3V3.CF.ATA0_EM_BA0 19
3V3.CF.ATA1_EM_BA1 19
3V3.CF.ATA2_EM_A0 19
12
14
43
44
B1.GCLK0
B1.GCLK1
B1.DEV_OE
B1.DEV_CLRn
TCK.B1
TMS.B1
TDI.B1
TDO.B1
92
95
96
97
98
99
100
1
3V3.SM.ALE_EM_A1 17
3V3.SM.CLE_EM_A2 17
3V3.SM.WRITE_WE 17
3V3.SM.READ_OE 17
3V3.SM.SM_CEz 17
3V3.SM.WAIT/BUSY 17
24
22
23
25
B2.PIN92
B2.PIN95
B2.PIN96
B2.PIN97
B2.PIN98
B2.PIN99
B2.PIN100
B2.PIN1
B2.GCLK2
B2.GCLK3
62
64
93
79
60
46
32
10
B
B2.VCCIO1C
B2.VCCIO1B
B2.VCCIO1A
3,12,13,29 WRITE_WE
3,12,13,29 READ_OE
C109
0.1uF
L63
U14
GNDINTB
GNDINTA
B1.PIN2
B1.PIN3
B1.PIN4
B1.PIN5
B1.PIN6
B1.PIN7
B1.PIN8
B1.PIN15
C108
0.1uF
C104
0.1uF
D
MSP430_INT 28
3V3.SYS_RESETz 22,24,28,31
R165
R192
0
0
3V3.ATA_BUFF_DIR 18
3V3.ATA_BUFF_ENz 18
SPAREIO3 28
3V3.UART_RXD1 28,31
3V3.UART_TXD1 28,31
SPAREIO2 28
SPAREIO1 28
3V3.CF.INTRQ_EM_RNW 19
C
B
CPLD_TIMER_IN 5
65
11
2
3
4
5
6
7
8
15
GNDIO6
GNDIO5
GNDIO4
GNDIO3
GNDIO2
GNDIO1
14 1V8.EM_DATA_BUF_DIR
14 1V8.EM_DATA_BUF_EN
12 NAND_BUSY
3,12,13,29 CLE_EM_A2
3,12,13,29 ALE_EM_A1
3,12,13,29 ATA2_EM_A0
3,12,13,29 ATA1_EM_BA1
B1.VCCIO1C
B1.VCCIO1B
B1.VCCIO1A
45
31
9
D
C107
0.1uF
94
80
59
C131
0.1uF
63
13
C129
0.1uF
VCCINT2
VCCINT1
C128
0.1uF
VCC_3.3V
VCC_3.3V
EPM240GTC100
VCC_3.3V
VCC_3.3V
CPLD REVISION 508163-0001B
R406
10K
R43
10K
R3
10K
ISR_TCK
28 3V3.SM_CEz
28 CFn_SEL
28 ATA_SEL
ISR_TDO
ISR_TMS
19,28 3V3.CF_PWR_ON
VCC_1.8V
VCC_1.8V
A
RN24
1
2
3
4
SPECTRUM DIGITAL INCORPORATED
J17
8
7
6
5
RPACK4-10K
ISR_TCK
ISR_TDO
ISR_TMS
ISR_TDI
1
3
5
7
9
2
4
6
8
10
Title:
Page Contents:
TMS320DM6446 EVALUATION MODULE
EMIF DATA BUS LEVEL SHIFTER
Revision:
E
SMT FEMALE HEADER 5X2
Size:B
DWG NO
508162-0001
Date: Wednesday, March 14, 2007
5
A
4
3
2
Sheet
1
15 o f
35
5
4
3
2
1
J5 TERMINATION
D
1-2
MEMORY STICK
2-3
MEMORY STICK PRO
1-2
MMC CARD
D
VCC_3.3V
1-2
SD CARD
C95
U5
1
2
3
0.1uF
5
VCC_3.3V
2
SN74LVC1G125
HEADER 3
4
R127
0
3
1
J5
VCC_3.3V
VCC_3.3V
SELECTS TERMINATION FOR SD/MMC/MS
+ C10
10uF
C
R123
51K
R124
51K
R122
51K
R120
51K
R126
51K
C78
VCC_3.3V
.1uF
C
R117
51K
R121
100K
WP
20
VCC_3.3V
R119
NO-POP
B
R125
NO-POP
28
MS.CLK
MS.DATA3
MS.DATA2
MS.DATA0
MS.DATA1
MS.CMD.BS
INS
SD_DATA0
SD_DATA1
7,31,32 SD_DATA0
7,31,32 SD_DATA1
MS.INS
19
18
17
16
15
14
13
12
11
10
21
SD_CLK
7,31,32 SD_CLK
SD.DAT2
SD.DAT3
SD.CMD
SD.VSS1
SD.VDD
SD.CLK
SD.VSS2
SD.DAT0
SD.DAT1
MS.VSS2
MS.VCC
MS.SCLK
MS.DATA3
MS.XINS
MS.DATA2
MS.SDIO/DATA0
MS.DATA1
MS.BS
MS.VSS1
COM
7,31,32 SD_DATA2
7,31,32 SD_DATA3
7,31,32 SD_CMD
9
1
2
3
4
5
6
7
8
22
SD_DATA2
SD_DATA3
SD_CMD
GND.1
23
J3
SCDB2A101
VCC_3.3V
R118
NO-POP
B
R73
51K
R99
0
R108
51K
SD/MMC.INS 28
WHEN USING DAT3 CARD DETECTION
PULL DOWN IS POPULATED WITH 470K OHM
RESISTOR AND PULL UP IN NOT POPULATED
SD/MMC.WP 28
MS.DATA1
MS.DATA0
MS.DATA2
MS.DATA3
MS.CLK
SPECTRUM DIGITAL INCORPORATED
A
TMS320DM6446 EVALUATION MODULE
Title:
Page Contents:
5
4
3
2
A
SD/MMC/MS CONNECTOR
Size:B
DWG NO
Date:
W ednesday, March 14, 2007
Revision:
E
508162-0001
Sheet
1
16 o f
35
5
4
3
2
1
VCC_3.3V
C9
10uF
+
1
2
3
4
D
15 3V3.SM.WAIT/BUSY
15 3V3.SM.READ_OE
15 3V3.SM.SM_CEz
3V3.CLE_EM_A2
3V3.ALE_EM_A1
3V3.WRITE_WE
3V3.WAIT/BUSY
3V3.READ_OE
3V3.SM_CEz
SMC2
SMC3
SMC4
SM.xD.WP SMC5
SMC19
SMC20
SMC21
SMC11
SMC18
R106
10K
SM.CLE
SM.ALE
SM.WE
SM.WP
SM.R/B
SM.RE
SM.CE
SM.CD
SM.OPTION
SMC12
SMC22
SMC1
SMC10
SM.VSS1
SM.VSS2
SM.I/O1
SM.I/O2
SM.I/O3
SM.I/O4
SM.I/O5
SM.I/O6
SM.I/O7
SM.I/O8
SM.SENS.1
SM.SENS.2
15 3V3.SM.CLE_EM_A2
15 3V3.SM.ALE_EM_A1
15 3V3.SM.WRITE_WE
C
SMC6
SMC7
SMC8
SMC9
SMC13
SMC14
SMC15
SMC16
SMCSW1
SMCSW2
3V3.EM_D0
3V3.EM_D1
3V3.EM_D2
3V3.EM_D3
3V3.EM_D4
3V3.EM_D5
3V3.EM_D6
3V3.EM_D7
SMC17
J15
SM.LVD
100K
SM.VCC1
SM.VCC2
100K
VCC_3.3V
SM.26
SM.25
5
6
7
8
14,18,19 3V3.EM_D[0:15]
RN22
8
7
6
5
RN23
SMCWP2
SMCWP1
4
3
2
1
D
xD.VSS2
XD19
xD.CD
xD.R/B
xD.RE
xD.CE
xD.CLE
xD.ALE
xD.WE
xD.WP
xD.VSS1
xD.I/O0
xD.I/O1
xD.I/O2
xD.I/O3
xD.I/O4
xD.I/O5
xD.I/O6
xD.I/O7
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XD8
XD9
XD10
XD11
XD12
XD13
XD14
XD15
XD16
XD17
xD.VCC1
xD.VCC2
XD18
XD20
R76
10K
3V3.WAIT/BUSY
3V3.READ_OE
3V3.SM_CEz
3V3.CLE_EM_A2
3V3.ALE_EM_A1
3V3.WRITE_WE
SM.xD.WP
xD.CD
28
3V3.EM_D0
3V3.EM_D1
3V3.EM_D2
3V3.EM_D3
3V3.EM_D4
3V3.EM_D5
3V3.EM_D6
3V3.EM_D7
C
VCC_3.3V
Chant Sincere SM/xD Connector
SM/xD_CONNECTOR
VCC_3.3V
R107
10K
B
SM.CD
B
28
VCC_3.3V
R78
10K
SM.xD.WP 28
R77
NO-POP
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
SM/xD CONNECTOR
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
17 o f
35
5
4
3
2
ATA.DD[0:15]
ATA_RESETn
15 3V3.ATA_RESETn
1
VCC_3.3V
D
D
VCC_3.3V
VCC_3.3V
MOUNTING HOLES
R158
20K
C86
.1uF
C101
.1uF
U9
14,17,19 3V3.EM_D[0:15]
3V3.EM_D15
3V3.EM_D14
3V3.EM_D13
3V3.EM_D12
3V3.EM_D11
3V3.EM_D10
3V3.EM_D9
3V3.EM_D8
3V3.EM_D7
3V3.EM_D6
3V3.EM_D5
3V3.EM_D4
3V3.EM_D3
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
C
C103
.1uF
7
18
Vcc
Vcc
Vcc
Vcc
42
31
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1OE
1DIR
2OE
2DIR
48
1
25
24
GND
GND
GND
GND
4
10
15
21
28
34
39
45
GND
GND
GND
GND
C87
.1uF
R112
10K
ATA_RESETn
Z6
R156
ATA.DD15
ATA.DD14
ATA.DD13
ATA.DD12
ATA.DD11
ATA.DD10
ATA.DD9
ATA.DD8
ATA.DD7
ATA.DD6
ATA.DD5
ATA.DD4
ATA.DD3
ATA.DD2
ATA.DD1
ATA.DD0
ATA.DD7
ATA.DD6
ATA.DD5
ATA.DD4
ATA.DD3
ATA.DD2
ATA.DD1
ATA.DD0
VCC_3.3V
RPACK8-33
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
ATA.DMARQ
ATA.DIOW
ATA.DIOR
ATA.IORDY
ATA.DMACK
ATA.INTRQ
ATA.DA1
ATA.DA0
ATA.CS0
ATA_DASPn
R47
R45
22
22
R46
22
R48
R58
R57
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
33
33
33
VCC_5V
DIR
L
H
SN74LVT16245B/SN74CB3Q16245
15 3V3.ATA_BUFF_DIR
BUS
B->A
B<-A
1
Z7
1
1
33
JP1
RN4
Z8
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
RN1
KEY
RPACK8-33
ATA.DD8
16
ATA.DD9
15
ATA.DD10
14
ATA.DD11
13
ATA.DD12
12
ATA.DD13
11
ATA.DD14
10
ATA.DD15
9
1
2
3
4
5
6
7
8
Z9
VCC_3.3V
R401
NO-POP
ATA_CSEL
1
TP34
TEST POINT
C
IOCS16
R55
R56
33
33
ATA.DA2
ATA.CS1
1
TP33
TEST POINT
R44
0
NC
HEADER 22X2
R223
2K
DS10
LED,GRN
R148
5.6K
15 3V3.ATA_BUFF_ENz
ATA.DMARQ
R150
82
3V3.ATA.DMARQ 15
VCC_5V
B
B
R155
1K
15 3V3.ATA.DA0
15 3V3.ATA.DA1
15 3V3.ATA.DA2
15 3V3.ATA.DMACK
15 3V3.ATA.CS0
15 3V3.ATA.CS1
15 3V3.ATA.DIOR
15 3V3.ATA.DIOW
ATA.DA0
ATA.DA1
ATA.DA2
ATA.DMACK
ATA.IORDY
R157
82
3V3.ATA.WAIT/BUSY 15
82
3V3.ATA.INTRQ_EM_RNW 15
VCC_5V
ATA.CS0
ATA.CS1
ATA.DIOR
ATA.DIOW
R154
10K
ATA.INTRQ
R153
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
ATA INTERFACE
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
18 o f
35
5
4
3
2
1
VCC_3.3V
R111 NO-POP
U10
R109
100K
D
4
VIN
VOUT
3
5
ON/OFF
VOUT
2
R2
1
6
R1/C1
+
C16
10uF
FDC6331L
C15
.1uF
R110
2K
15 3V3.CF.ATA0_EM_BA0
15 3V3.CF.ATA1_EM_BA1
15 3V3.CF.ATA2_EM_A0
15,28 3V3.CF_PWR_ON
CF_A0
CF_A1
CF_A2
VCC_3.3V
R23
10K
R22
1K
R26
R25
R21
20K
10K
20K
C
15 3V3.CF.INTRQ_EM_RNW
15 3V3.CF.WAIT/BUSY
28 3V3.CF_RESETz
VCC_3.3V
B
D
C17
.1uF
15 3V3.CF.WRITE_WE
P1
38
13
VCC
VCC
20
19
18
17
16
15
14
12
11
10
8
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
44
REG
35
IOWR
34
IORD
39
7
32
9
36
CSEL
CE1
CE2
OE
WE
37
42
24
RDY/BSY
WAIT
WP
CD1
CD2
26
25
43
41
INPACK#
RESET
VS1
VS2
33
40
1
50
GND
GND
BVD2
BVD1
45
46
3V3.EM_D[0:15] 14,17,18
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
21
22
23
2
3
4
5
6
47
48
49
27
28
29
30
31
3V3.EM_D0
3V3.EM_D1
3V3.EM_D2
3V3.EM_D3
3V3.EM_D4
3V3.EM_D5
3V3.EM_D6
3V3.EM_D7
3V3.EM_D8
3V3.EM_D9
3V3.EM_D10
3V3.EM_D11
3V3.EM_D12
3V3.EM_D13
3V3.EM_D14
3V3.EM_D15
C
VCC_3.3V
R28
100K
R20
100K
3V3.CF_CD1 28
3V3.CF_CD2 28
B
Compact Flash Connector
R400
NO-POP
15 3V3.CF.READ_OE
15 3V3.CF.ATA_CS0
15 3V3.CF.ATA_CS1
R24
0
R27
0
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
COMPACT FLASH CONNECTOR
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
19 o f
35
5
4
3
2
1
D
D
VCC_3.3V
C245
U42
6 UART_TXD0
UART_TXD0
6
VCCB
4
B1
2
GND1
VCC_3.3V VCC_3.3V
C246
.1uF
.1uF
VCCA
1
A1
3
DIR
5
R355
10K
3V3.UART_TXD0
U64
SN74AVC1T45
MAX3221
11
DIN
10
INVALID
R354
10K
L46
DOUT
13
FORCEOFF
16
FORCEON
12
1uH
C300
R356
0
C243
C244
.1uF
6
UART_RXD0
6 UART_RXD0
VCCB
4
B1
2
GND1
VCCA
+
1
A1
3
DIR
5
ROUT
1
ENABLE
S_A_RXD
8
2
C1+
C2+
5
4
C1-
C2-
6
3
V+
V-
7
C302
1uF
+
3V3.UART_RXD0
C299
1uF
15
+
VCC
SN74AVC1T45
B
RIN
GND
U43
.1uF
9
P6
10pF
C294
C295
10pF
10pF
C
1
6
2
7
3
8
4
9
5
1uH
S_A_RXD
S_A_TXD
C298
1uF
DSUB9-Male
C296
1uF
14
VCC_3.3V
L47
+
VCC_1.8V
C297
10pF
10
C
11
VCC_1.8V
B
VCC_3.3V
DIR
FUNCTION
L
B-->A
H
A-->B
R357
L54
10
C301
.1uF
+
1
C77
47uF
2
BLM21PG221SN1D
L55
1
2
BLM21PG221SN1D
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
RS232 INTERFACE
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
20 o f
35
5
4
3
2
TP74
1
22,31 GIOV33_15
TP73
1
NO-POP
VCC_5V
R133
1
R429
TP75
1
0
THESE FOOTPRINTS ARE OVERLAYED
ONLY 1 OF 3 IS POPULATED AT 1 TIME
VCC_3.3V VCC_3.3V
VCC_5V
D
D6
VCC_3.3V
NO-POP
D
VCC_5V
C374
0.1uF
R378
1K
C351
.1uF
2
1
28 USB.DRVVBUSz
4
1
U15
SN74LVC1G07
Q2
S
4
G
2
3
3
1K
R166
10K
U59
SN74AHC1G08
1
1B
ATTACH
2B
3B
DD+
4B
GND
R427
NO-POP
HEADER 3
D
1uF
1
SHIELD1
1
SHIELD2
2
USB_SHIELD
USB_SHIELD
USB-miniAB/A/B connector
FULL SIZE B CONNECTOR
TP76
1
IRLML6401
C197
TP72 TP71
GIOV33_16
Q3
NO-POP
1
2
3
5
R379
J10B
J7
5
R430
10K
R428
NO-POP
C350
.1uF
R337
1.5K
J10A
22,31
1
C
7 USB_VBUS
7 USB_DM
7
USB_DP
C
USB_DM
USB_DP
USB_ID
1
TP59
Selects Termination
for Host/Client
configurations
R377
100K
2AB
D-
3AB
D+
4AB
ID
5AB
GND
0
+
C133
100uF
VBUS
+
C69
4.7uF
5
6
7
8
R132
1AB
SHIELD5
SHIELD6
SHIELD7
SHIELD8
7
TP60
C293
MINI A-B CONNECTOR
USB-miniAB/A/B connector
100nF
Q3
USB_SHIELD
R425-R429
B
B
TP71-TP74
For host mode Capacitor Minimum Capacitance
is 100uF, this design uses 104.7uF
both C133 and C69 installed.
For Peripheral or OTG the
Capacitancer should be 4.7 uF
so remove R132 thus C69 provides capacitance
J10C
L52
1
1A
SHIELD3
VBUS-A
2A
3A
DD+
4A
GND
2
SHIELD4
BLM21PG221SN1D
L53
1
3
USB_SHIELD
4
USB_SHIELD
USB-miniAB/A/B connector
FULL SIZE A CONNECTOR
2
BLM21PG221SN1D
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
USB 2.0 INTERFACE
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
21 o f
35
5
4
VCC_3.3V
3
2
VCC_3.3V
LED1-
AVCC3.3
1
P2
RJ45 HALO HFJ11-2450E-L21
C
MII_RXDV
MII_RXER
XSPCLK_MDCLK
XSPDO_MDIO
MDINT_TP
SYS_RSTz
TXSLEW0
TXSLEW1
PAUSE
SLEEP
56
54
TX_EN
TX_ER
62
63
52
48
47
46
45
COL
CRS
RX_CLK
RXD0
RXD1
RXD2
RXD3
49
53
3
43
42
64
4
5
6
33
32
RX_DV
RX_ER
MDDIS
MDC
MDIO
MDINT#
RESET#
TxSLEW0
TxSLEW1
PAUSE
SLEEP
27
28
29
30
31
21
TDI
TDO
TMS
TCK
TRST#
7
11
18
41
50
61
GND1
GND2
GND3
GND4
GND5
GND6
TP58
MDINT
TPFOP
TPFON
19
20
TPFIP
TPFIN
23
24
N/C1
N/C2
N/C3
9
10
44
LED/CFG1
38
LED/CFG2
37
LED/CFG3
36
RBIAS
17
TEST0
TEST1
PWRDWN
34
35
39
VCCA
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
GND
22
12
13
14
15
16
25
SD/TP#
26
R276
100
R277
100
LXT_RDP_c
LXT_RDM_c
SPEED
LXT_TDP
R275
100
LXT_TDM
270pF
R288
49.9
REFCLK/XI
XO
RBIAS
R284
3
5
6
RXD+
RXD-CT
RXD-
D
L56
1
2
BLM21PG221SN1D
L57
1
2
BLM21PG221SN1D
VCC_3.3V
L31
EXC-3BB102H
C303
AVCC3.3
VCC_3.3V
PWRDWN
R287
PWRDWN
R281
R282
SLEEP
PAUSE
R278
R279
NO POP
10k
R286
R285
TXSLEW1
NO POP
10k
10k
C259
C257
0.01uF
VCC_3.3V
TXSLEW0
R260
R283
NO POP
10k
.1uF
VCC_3.3V
C226
C248
10pF
U41
CBTLV16210DGGR
LXT971ALE
1
.1uF
R258
NO-POP
NC
1OE
48
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
2
3
4
5
6
7
9
10
11
12
2OE
47
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
13
14
16
18
19
20
21
22
23
24
ENET_ENABLEz
0
MTXD0
MTXD1
MTXD2
MTXD3
MTXEN
R259
360
EIA0402
EIA0402
RPACK8-33
16
15
14
13
12
11
10
9
46
45
44
43
42
40
39
38
37
36
35
34
33
31
30
29
28
27
26
25
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
R407
10K
GIOV33_3 6,31
GIOV33_4 6,31
GIOV33_5 6,31
GIOV33_6 6,31
GIOV33_0 6,31
GIOV33_15 6,31
GIOV33_16 6,31
R222
B
360
ENET_ENABLEz
ENET_ENABLEz 31
GIOV33_13 6,31
GIOV33_12 6,31
GIOV33_10 6,31
GIOV33_9 6,31
GIOV33_8 6,31
GIOV33_7 6,31
GIOV33_11 6,31
GIOV33_14 6,31
GIOV33_2 6,31
GIOV33_1 6,31
SPECTRUM DIGITAL INCORPORATED
Title:
GND
GND
GND
GND
22
22
Page Contents:
A
TMS320DM6446 EVALUATION MODULE
ETHERNET INTERFACE
41
32
17
8
Place terminations
close to PHY source
pins.
Size:B
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
C
10k
10k
.1uF
A
R262
R261
TXD+
TXD-CT
TXD-
LXT_RDM
Y6
25MHz
3V3.SYS_RESETz 15,24,28,31
1
2
3
4
5
6
7
8
C263
0.01uF
22.1k
C264
10pF
RN34
NC1
GND
1
4
2
270pF
1
2
B
0
0
R358
49.9
C304
R289
R274
R257
7
8
LXT_RDP
C260
15
MII_COL
MII_CRS
MII_RCLK
MII_RXD0
MII_RXD1
MII_RDX2
MII_RXD3
TX_CLK
TXD0
TXD1
TXD2
TXD3
LINK/
ACTIVITY
VCC
MTXEN
R280
1.5k
55
57
58
59
60
COLLISION/
DUPLEX
STATUS
LED2LED2+
LED1LED1+
2
MII_TXCLK
MTXD0
MTXD1
MTXD2
MTXD3
VCCA
U58
8
40
C258
.1uF
VCCD
C247
.1uF
VCCIO1
VCCIO2
C262
.1uF
51
C261
.1uF
D
LED1-
S1
S0
LINKLED-
13
14
AVCC3.3
LXT_TDCT
VCC_3.3V
BLM41P750SPT
12
11
10
9
1
L32
LINKLED-
Route pairs together,
pairs are (3 and 6) and
(1 and 2).
Sheet
1
22 o f
35
5
4
3
2
1
VCC_1.8V
VCC_3.3V
D
D
C67
0.1uF
24 TVP5146VIDEO[0:7]
C68
0.1uF
TVP5146VIDEO0
TVP5146VIDEO1
TVP5146VIDEO2
TVP5146VIDEO3
TVP5146VIDEO4
TVP5146VIDEO5
TVP5146VIDEO6
TVP5146VIDEO7
24 TVP5146PCLK
24 TVP5146VSYNC
24 TVP5146HSYNC
C
R64
360
C62
0.1uF
U66
42
31
VCCA
VCCA
VCCB
VCCB
7
18
47
46
44
43
41
40
38
37
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2
3
5
6
8
9
11
12
36
35
33
32
30
29
27
26
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
13
14
16
17
19
20
22
23
4
10
15
21
45
39
34
28
GND
GND
GND
GND
GND
GND
GND
GND
1DIR
1OEn
1
48
2DIR
2OEn
24
25
RPACK8-33
B. YI0
16
B. YI1
15
B. YI2
14
B. YI3
13
B. YI4
12
B. YI5
11
B. YI6
10
B. YI7
9
Y I0
Y I1
Y I2
Y I3
Y I4
Y I5
Y I6
Y I7
5
6
7
8
YI0
YI1
YI2
YI3
YI4
YI5
YI6
YI7
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
PCLK
VD
HD
5,30
5,30
5,30
RPACK4-33
R226
0
1.8V_DC3_PCLK 31
C
R231
0
SN74AVCB164245VR
DIR
L
H
RN33
1
2
3
4
5
6
7
8
4
3
2
1
RN32
C61
0.1uF
VCC_1.8V
BUS
B->A
B<-A
30 CAPTURE_EN
R264
10K
B
B
U66 is a tri-stateable logic translator used for DC4
to allow the TVP5146 to be disconnected
from on-board circuitry.Signal levels are at 1.8V logic
levels on B side and 3.3V on A sides of translator.
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
TVP5146 LEVEL SHIFTER
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
23 o f
35
5
4
3
2
1.8VA_DDEC
3.3VD_DDEC
3.3VD_DDEC
0.1uF
R328
DDEC_GND
3.3VD_DDEC
1.8VA_DDEC
C290
0.1uF
NO POP
C287
C285
C341
C284
C334
C336
C291
C288
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
35
FSS/GPIO
33
PWRDWN
34
RESETB
38
48
61
IOVDD1
IOVDD2
IOVDD3
C250
.1uF
31
41
55
67
C289
DVDD1
DVDD2
DVDD3
DVDD4
0.1uF
4
5
20
21
C286
0.1uF
CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD
C283
0.1uF
11
14
25
78
C346
0.1uF
CH2_A18VDD
CH3_A18VDD
CH4_A18VDD
CH1_A18VDD
C327
0.1uF
12
C329
D
PLL_A18VDD
C337
0.1uF
76
1.8VD_DDEC
A18VDD_REF
3.3VA_DDEC
3.3VA_DDEC 1.8VD_DDEC
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
R329
2K
DDEC_GND
15,22,28,31 3V3.SYS_RESETz
J11
6,27,28 3V3.I2C_DATA
29
SDA
6,27,28 3V3.I2C_CLK
28
SCL
80
VI_1_A
1
VI_1_B
2
VI_1_C
749181-1
L39
C
3
2.7uH
L40
4
C348
1
C344
680pF
C342
330pF
.1uF
R376
75
0.1uF
0.1uF
DDEC_GND
5
DDEC_GND
DDEC_GND
6
DDEC_GND
7
DDEC_GND
L42
2.7uH
L41
LUMA
C338
C367
C340
330pF
680pF
VI_2_A
8
VI_2_B
9
VI_2_C
C339
2.7uH
3.3VD_DDEC
R265
HS/CS/GPIO
72
R335
22
TVP5146HSYNC 23
VS/VBLK/GPIO
73
R331
22
TVP5146VSYNC 23
FID/GPIO
71
4.7K
R333
R327
2K
NO POP
GLCO/12CA
37
1
TP57
AVID/GPIO
36
1
TP56
R375
75
16
DATACLK
40
VI_3_A
17
VI_3_B
INTREQ
30
18
VI_3_C
XTAL1
74
R266
TP62
DDEC_GND
DDEC_GND
C345
C330
0.1uF
0.1uF
C328
J12
L43 2.7uH
2
1
C325
680pF
C332
330pF
DDEC_GND
DDEC_GND
23
81
C335
0.1uF
DDEC_GND
DDEC_GND
DDEC_GND
DDEC_GND
1
L37
VCC_3.3V
2
BLM41P750SPT
VCC_1.8V
1.8VD_DDEC
3.3VA_DDEC
1
L38
VCC_3.3V
DDEC_GND
100K
R336
75
THERMAL
Y4
14.31818mhz
0
C349
C292
33pF
33pF
C331
DDEC_GND
10
15
24
79
3
6
19
22
26
13
77
1.8VA_DDEC
XTAL2
0.1uF
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
VCC_1.8V
R332
VI_4_A
R374 .1uF
75
DDEC_GND
B
2.2K
C333
L44 2.7uH
DDEC_GND
C326
330pF
TVP5146PCLK 23
DGND1
DGND2
DGND3
DGND4
DGND5
IOGND1
IOGND2
IOGND3
RCA JACK
.1uF
22
R334
1
SPECTRUM DIGITAL INCORPORATED
27
32
42
56
68
39
49
62
DDEC_GND
CH2_A18GND
CH3_A18GND
CH4_A18GND
CH1_A18GND
CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND
AGND
A18GND_REF
PLL_A18GND
DDEC_GND
C
4.7K
R330
.1uF
330pF
B
2
BLM41P750SPT
Title:
Page Contents:
3.3VD_DDEC
A
TMS320DM6446 EVALUATION MODULE
TVP5146 VIDEO DECODER
Revision:
E
DDEC_GND
1
L23
2
BLM41P750SPT
1
L28
DDEC_GND
2
BLM41P750SPT
Size:B
DWG NO
508162-0001
Date: Wednesday, March 14, 2007
5
D
TVP5146VIDEO7
TVP5146VIDEO6
TVP5146VIDEO5
TVP5146VIDEO4
TVP5146VIDEO3
TVP5146VIDEO2
TVP5146VIDEO1
TVP5146VIDEO0
57
58
59
60
63
64
65
66
69
70
DDEC_GND
DDEC_GND
RN35
RPACK8-33
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
43
44
45
46
47
50
51
52
53
54
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
C347
330pF
2
TVP5146VIDEO[0:7] 23
3.3VD_DDEC
U51
TVP5146
C343
2.7uH
C368
A
1
4
3
2
Sheet
1
24 o f
35
5
4
3
VCC_3.3V
2
1
DAC_3V3
3V3A_VOUT
L12
BLM41P750SPT
L16
+ C63
10uF
C256
0.1uF
BLM41P750SPT
+ C64
220uF
C255
0.01uF
L36
R338
DENC_GND
DENC_GND
R339
D
1uH
75
C354
C353
10pF
10pF
DENC_GND
DENC_GND
1130 1%
D
DAC_3V3
12uH
L27
12uH
C352
0.1uF
U50
6
L20
DENC_GND
3 +
5 DAC_IOUTA
R269
1K
R342
4 R340
1K
27pF
L35
1
1812LS-273XJB
C251
R341
267 1%
VOUT_ON
DENC_GND
DENC_GND
DENC_GND
1uH
75
OPA357AIDBV
2
5
1812LS-273XJB
C357
C356
10pF
10pF
DENC_GND
DENC_GND
DENC_GND
DENC_GND
R343
1130 1%
L33
DAC_3V3
R350
C
6
U49
L19
12uH
L26
12uH
R270
1K
R344
1K
27pF
749181-1
R345
267 1%
OPA357AIDBV
VOUT_ON
DENC_GND
DENC_GND
J9
C363
C362
10pF
10pF
DENC_GND
DENC_GND
C
4 -
1812LS-273XJB
C252
2
5
1812LS-273XJB
C355
0.1uF
DENC_GND
1
3 +
5 DAC_IOUTB
1uH
75
3
4
1
2
DENC_GND
DENC_GND
R351
1130 1%
5
6
DAC_3V3
DENC_GND
12uH
DENC_GND
1
3 +
5 DAC_IOUTC
1812LS-273XJB
R272
1K
L34
R346
R353
267 1%
27pF
1uH
75
4 R352
1K
C254
2
5
1812LS-273XJB
J8
OPA357AIDBV
VOUT_ON
C361
C360
10pF
10pF
DENC_GND
DENC_GND
DENC_GND
6
B
DUAL RCA JACK
DENC_GND
DENC_GND
5
3
DENC_GND
DENC_GND
DENC_GND
2
4
L24
C359
0.1uF
1
12uH
6
L17
B
U47
R347
1130 1%
L18
12uH
L25
6
DAC_3V3
12uH
3 +
5 DAC_IOUTD
R271
1K
1812LS-273XJB
C253
27pF
4 R348
1K
2
5
1812LS-273XJB
A
C358
0.1uF
U48
R349
267 1%
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
DENC_GND
1
OPA357AIDBV
R380
DAC_3V3
SPECTRUM DIGITAL INCORPORATED
VOUT_ON
Title:
R381 NO-POP
Page Contents:
DENC_GND
TMS320DM6446 EVALUATION MODULE
VIDEO OUTPUT
DENC_GND
DENC_GND
DENC_GND
DENC_GND
DENC_GND
Size:B
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
10K
Sheet
1
25 o f
35
VCC_1.8V
L29
VCC_3.3V
BLM21PG221SN1D
+
C249
.1uF
C279
.1uF
C70
10uF
C280
.1uF
C278
.1uF
L30
BEAD M2301
+
LINE_IN
VCC_1.8V
C322 .1uF
1uF
C324 .1uF
R388
R387
5.6K
C366
220pF
BLM21PG221SN1D
MIC_IN
C323
.1uF
C282
.1uF
C281
.1uF
C320
.1uF
R321
R371
330
0
C319
.1uF
0
R370
47K
R323
C321
.1uF
R372
330
R373
10K
8,13,15,29,30,31,34 1.8V.SYS_RESETz
VCC_1.8V
7
B_CLKX
7
B_CLKR
7
B_FSX
7
B_FSR
R324
R326
R325
R322
10K
NO-POP
NO-POP
10K
TP63
TP64
1
1
H9
C9
D9
DVDD
IOVDD
DVSS
A6
A5
B7
B6
LINE1L+
LINE1LLINE1R+
LINE1R-
A4
B5
B4
A3
LINE2L+
LINE2LLINE2R+
LINE2R-
A2
A1
B3
B2
MICBIAS
MIC3R
MIC3L
MICDET
H8
RESET
B8
B9
A8
A9
MFP0
MFP1
MPF2
MFP3
BCLK
WCLK
DIN
DOUT
SELECT
MCLK
R314
10
R316
10
G9
F9
E9
F8
E8
R317
10
G8
R315
DRVDD.1
DRVDD.2
AVDD_ADC
AVSS_ADC.1
AVSS_ADC.2
AVDD_DAC
AVSS_DAC.1
AVSS_DAC.2
C1
H1
B1
C2
D2
J1
G2
H2
HPLOUT
HPLCOM
DRVSS.1
DRVSS.2
HPRCOM
HPROUT
D1
E1
E2
F2
F1
G1
MONO_LO+
MONO_LO-
J2
J3
LEFT_LO+
LEFT_LORIGHT_LO+
RIGHT_LO-
J4
J5
J6
J7
P4
C72
C73
33uF,6.3V
33uF,6.3V
L50
BLM21PG221SN1D
L51
BLM21PG221SN1D
7
B_DR
R312
R384
20K
C75
10uF,6.3V
L48
BLM21PG221SN1D
GPIO1
GPIO2
J9
J8
SCL
SDA
C8
D8
P5
R367
20K
2
3
C76
10uF,6.3V
L49
BLM21PG221SN1D
10
R318
10K
R382
20K
DUAL RCA JACK
R310
10
10
TP69
1
B_DX
3
Headphone Out
10
R320
1
2
4
R383
20K
TVL320AIC33IZQE
7
C275
U52
5.6K
L45
C317
220pF
C318
.1uF
1
1U
2
C276
.1uF
+
5
1
3
C277
+
1L
5U
4U
C365
220pF
+
P3
C74
10uF
.1uF
Dual-Stereo
4
6
C316
.1uF
5.6K
R386
5.6K
5L
4L
C315
.1uF
+
R385
C314
.1uF
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
R313
20K
TP65
1
R319
20K
R311
20K
5,31 AUDIO_CLK
SPECTRUM DIGITAL INCORPORATED
Title:
6,30,31 1V8.I2C_DATA
6,30,31 1V8.I2C_CLK
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
AIC33 AUDIO INTERFACE
DWG NO
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
Sheet
26 o f
35
5
4
3
2
1
VCC_3.3V
C306
0.1uF
J13RCA JACK
5
U63
C305
2
0.1uF
R360 220
4
1
SPDIF OUT
D
3
1
SN74LVC1G125
2
VCC_3.3V
VCC_1.8V
D
R361
R359
100
0
U62
6
R362
100K
B1
A1
2
B2
A2
3
GND1
4
DIR
C307
.1uF
R363
33
VCC_3.3V
VCC_3.3V
C309
C364
0.1uF
SN74AVC2T45
DIR
L
H
C
FUNCTION
B-->A
A-->B
0.1uF
5
U61
2
4
SN74LVC1G125
1
GND
2
VCC
3
IN
U65
R364
3V3.DC_PCLK 5
OPTICAL SPDIF OUT
MP1
7
5
1
4
30 1V8.DC_PCLK
VCCA
MP2
DX
VCCB
3
1
7,31
8
5
C308
.1uF
C
TOTX141P
0
VCC_3.3V
R65
330
VCC_3.3V
R66
330
R67
330
R68
330
R69
330
R70
330
R71
330
R72
330
DS8
DS7
DS6
DS5
DS4
DS3
DS2
DS1
LED
LED
LED
LED
LED
LED
LED
LED
C79
.1uF
USER CONTROLLED LEDS
U2
B
16
15
14
13
12
11
10
9
6,24,28 3V3.I2C_DATA
6,24,28 3V3.I2C_CLK
VDD
SDA
SCL
INT
P7
P6
P5
P4
A0
A1
A2
P0
P1
P2
P3
GND
1
2
3
4
5
6
7
8
B
PCF8574A
SPECTRUM DIGITAL INCORPORATED
A
5
4
3
2
A
Title:
TMS320DM6446 EVALUATION MODULE
Page Contents:
SPDIF OUTPUTS & USER LEDS
Size:B
DWG NO
Date:
W ednesday, March 14, 2007
Revision:
E
508162-0001
Sheet
1
27 o f
35
5
4
3
2
1
VCC_3.3V
VCC_3.3V
C83
.1uF
D4
BAT17
R74
10K
R75
100
U3
D
D
3
1
2
L1
MSP430_3V3
VCC_3.3V
D3
BAT17
+
C84
.1uF
C13
10uF 6.3V
C85
R104
47K
R101
10K
R105
100K
R103
2
VCC
BHT1
8
9
10
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
P1.0/TACLK
P1.1/TA0
P1.2/TA1
21
22
23
19 3V3.CF_CD1
19 3V3.CF_CD2
19
20
3
P2.3/CA0/TA1
P1.3/TA2
P2.4/CA1/TA2
P2.5/ROSC
P1.4/SMCLK/TCK
24
15 3V3.SM_CEz
17
SM.CD
17
xD.CD
15,19 3V3.CF_PWR_ON
11
12
13
14
15
16
17
18
P3.0/STE0/A5
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P3.5/URXD0
P3.6/A6
P3.7/A7
16 SD/MMC.INS
16
MS.INS
C
16 SD/MMC.WP
17 SM.xD.WP
R273
0
7
RST/NMI
6
XIN
1
25
P1.5/TA0/TMS
26
430_TMS
P1.6/TA1/TDI
27
430_TDI
P1.7/TA2/TDO
28
430_TDO
TEST
10 USER_SW
15 SPAREIO3
15 SPAREIO2
15 SPAREIO1
VDD
SDA
SCL
INT
P7
P6
P5
P4
A0
A1
A2
P0
P1
P2
P3
GND
XOUT
Y1
1
2
3
4
5
6
7
8
430_TCK
430_TMS
430_TDI
430_TDO
4
1
2
3
4
16
15
14
13
12
11
10
9
6,24,27 3V3.I2C_DATA
6,24,27 3V3.I2C_CLK
5
PLL.CSEL
PLL.SR
PLL.FS1
PLL.FS2
5
5
5
5
3V3.I2C_CLK 6,24,27
MSP430_INT 15
C
J2
32.768KHz
VCC_3.3V
U18
0
430_TEST/VPP
1
VSS
C100
.1uF
3V3.I2C_DATA 6,24,27
TP4
MSP430F1232IPW
RN25
RPACK4-10K
B
R98
430_TCK
8
7
6
5
15,22,24,31 3V3.SYS_RESETz
VCC_3.3V
VCC_3.3V
0
2
U4
BA2032SM
TSOP34840
0.1uF
R102
NO-POP
1
C1
10uF 6.3V
+
BLM41P750SPT
13
11
9
7
5
3
1
NC1
TCLKEN
RST/NMI
ACLKEN
GND
ACLK
TCK
TEST/VPP
TMS
XOUT
TDI/VPP VCC_MSP
TDO/TDI
NC2
14
12
10
8
6
4
2
430_TEST/VPP
B
MSP430_3V3
HEADER 7X2
R97
NO-POP
3V3.UART_TXD1 15,31
R96
NO-POP
3V3.UART_RXD1 15,31
PCF8574A
VCC_3.3V
VCC_1.8V
VCC_3.3V
VCC_3.3V
VCC_3.3V
16
15
14
13
12
11
10
9
6,24,27 3V3.I2C_DATA
6,24,27 3V3.I2C_CLK
A
VDD
SDA
SCL
INT
P7
P6
P5
P4
A0
A1
A2
P0
P1
P2
P3
GND
C163
1
2
3
4
5
6
7
8
2
1
USB.DRVVBUSz 21
VDDIMX_EN 35
VLYNQ_ONz 14
3V3.CF_RESETz 19
R422
10K
R421
NO-POP
0.1uF
5
U35
4
3
C193
.1uF
R224
10K
VCC_3.3V
1V8.WLAN_RESETz 32
U30
SN74LVC1G06
SPECTRUM DIGITAL INCORPORATED
Title:
A
TMS320DM6446 EVALUATION MODULE
PCF8574A
Page Contents:
ATA_SEL 15
CFn_SEL
5
4
3
2
15
Size:B
MSP430 & IR INTERFACE
DWG NO
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
Sheet
1
28 o f
35
5
4
3
2
1
12,13,14 B.EM_A[10:21]
D
3,12,13,14 EM_A[3:21]
D
3,12,13,14 EM_D[0:15]
DC1
B.EM_A21
B.EM_A19
B.EM_A17
B.EM_A15
B.EM_A13
B.EM_A11
EM_A9
EM_A7
EM_A5
EM_A3
3,12,13,15 ALE_EM_A1
C
3,15 ATA_CS1
3,12,13,15 ATA1_EM_BA1
3,12,13,15 WRITE_WE
3,15 W AIT/BUSY
EM_D15
EM_D13
EM_D11
EM_D9
EM_D7
EM_D5
EM_D3
EM_D1
3
EM_CS3
8,13,15,26,30,31,34 1.8V.SYS_RESETz
VCC_3.3V
VCC_5V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
B.EM_A20
B.EM_A18
B.EM_A16
B.EM_A14
B.EM_A12
B.EM_A10
EM_A8
EM_A6
EM_A4
CLE_EM_A2 3,12,13,15
ATA2_EM_A0 3,12,13,15
ATA_CS0 3,15
ATA0_EM_BA0 3,15
READ_OE 3,12,13,15
INTRQ_EM_RNW 3,15
EM_D14
EM_D12
EM_D10
EM_D8
EM_D6
EM_D4
EM_D2
EM_D0
DC_EM_CS2 10
CLKOUT0 8
VCC_3.3V
VCC_1.8V
HEADER 35x2
B
C
B
EMIF CONNECTOR
SPECTRUM DIGITAL INCORPORATED
A
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
EMIF EXPANSION CONNECTOR
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
29 o f
35
5
4
3
2
1
VIDEO INPUT CONNECTOR
DC4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
8,13,15,26,29,31,34 1.8V.SYS_RESETz
D
6
GIO1
5
PWM1
5,23
5,23
5,23
5,23
YI0
YI2
YI4
YI6
5,23
PCLK
R225
27 1V8.DC_PCLK
5
5
5
5
NO-POP
CI0
CI2
CI4
CI6
6,26,31 1V8.I2C_CLK
VCC_1.8V
C
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
CAPTURE_EN 23
GIO4
6
PWM2
5
YI1
YI3
YI5
YI7
5,23
5,23
5,23
5,23
HD
VD
5,23
5,23
CI1
CI3
CI5
CI7
5
5
5
5
D
1V8.I2C_DATA 6,26,31
VCC_1.8V
C
VCC_3.3V
VCC_3.3V
HEADER 25X2
VCC_5V
VCC_5V
VIDEO OUTPUT CONNECTOR
DC5
B
6
6
6
GIO0
GIO3
GIO6
5,10
5,10
5
5
COUT0
COUT2
COUT4
COUT6
5
5
5
VPBECLK
VID_CLK
VCLK
5,10
5,10
5,10
5
R268
R267
YOUT0
YOUT2
YOUT4
YOUT6
6,26,31 1V8.I2C_CLK
6,26,31 1V8.I2C_DATA
VCC_1.8V
NO-POP
NO-POP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
GIO2
GIO5
GIO38
6
6
6
COUT1
COUT3
COUT5
COUT7
5,10
5,10
5
5
HSYNC
5
VSYNC
5
YOUT1
YOUT3
YOUT5
YOUT7
5,10
5,10
5
5
B
1.8V.SYS_RESETz 8,13,15,26,29,31,34
VCC_1.8V
VCC_3.3V
VCC_3.3V
HEADER 25X2
SPECTRUM DIGITAL INCORPORATED
A
VCC_5V
Title:
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
VIDEO INPUT/OUTPUT CONNECTORS
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
VCC_5V
Sheet
1
30 o f
35
5
4
3
2
1
DC2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
6,22 GIOV33_0
6,22 GIOV33_2
6,22 GIOV33_4
D
6,22 GIOV33_6
6,22 GIOV33_8
6,22 GIOV33_10
6,22 GIOV33_12
6,22 GIOV33_14
6,22 GIOV33_16
22 ENET_ENABLEz
VCC_1.8V
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
GIOV33_1 6,22
GIOV33_3 6,22
GIOV33_5 6,22
D
GIOV33_7 6,22
GIOV33_9 6,22
GIOV33_11 6,22
GIOV33_13 6,22
GIOV33_15 6,22
3V3.SYS_RESETz 15,22,24,28
3V3.UART_RXD1 15,28
3V3.UART_TXD1 15,28
VCC_3.3V
VCC_3.3V
HEADER 20X2
VCC_5V
VCC_5V
C
C
DC3
6
6
6
SPI_EN1
SPI_DI
SPI_CLK
7
7
7
DR
CLKR
FSR
8,13,15,26,29,30,34 1.8V.SYS_RESETz
7 McBSP_EN
5,26 AUDIO_CLK
R263
NO-POP
VCC_3.3V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
SPI_EN0 6
SPI_DO 6
TIMER_IN_DC3 15
DX
CLKX
FSX
7,27
7
7
1V8.I2C_CLK 6,26,30
1V8.I2C_DATA 6,26,30
1.8V_DC3_PCLK 23
VCC_3.3V
B
HEADER 15X2
VCC_5V
VCC_1.8V
DC6
7,16,32 SD_CLK
7,16,32 SD_DATA0
7,16,32 SD_DATA2
1
3
5
7
9
2
4
6
8
10
SD_CMD 7,16,32
SD_DATA1 7,16,32
SD_DATA3 7,16,32
SPECTRUM DIGITAL INCORPORATED
A
Title:
HEADER 5X2
TMS320DM6446 EVALUATION MODULE
Page Contents:
EMAC/GIO & McBSP/SPI & SD CONNECTORS
Size:B
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
31 o f
35
5
4
3
2
NO-POP
R10
0
NO-POP
VCC_5V
L59
C12
C7
C11
J16
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
C
Resistors are only populated for modules
requiring the upper VLYNQ data pairs
14 VLYNQ_TXD3
14 VLYNQ_TXD2
VLYNQ_TXD3
R7
NO-POP
VLYNQ_TXD2
R6
NO-POP
Resistors are only populated for modules
requiring the upper VLYNQ data pairs
B
14 VLYNQ_RXD2
14 VLYNQ_RXD3
R12
R11
LED1_GRNP
LED1_GRNN
LED2_YELP
LED2_YELN
96
99
94
95
92
91
90
87
85
84
81
80
79
78
75
76
60
57
58
53
54
51
52
47
46
41
44
39
42
35
38
33
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
86
73
59
45
C/BE0
C/BE1
C/BE2
C/BE3
20
26
25
29
30
34
48
56
61
64
66
65
68
67
72
71
28 1V8.WLAN_RESETz
VLYNQ_RXD2
VLYNQ_RXD3
11
13
12
14
NO-POP
NO-POP
INTA
RST
CLK
REQ
GNT
PME
IDSEL
PAR
IRDY
FRAME
TRDY
CLKRUN
STOP
SERR
DEVSEL
PERR
BLM41P750SPT
D
97
18
C6
103
104
105
106
107
108
109
110
111
113
115
116
117
118
119
120
122
123
AC_SYNC
M66EN
AC_SDATA_IN
AC_SDATA_OUT
AC_BIT_CLK
AC_CODEC_ID0#
AC_CODEC_ID1#
AC_RESET#
MOD_AUDIO_MON
AUDIO_GND
SYS_AUDIO_OUT
SYS_AUDIO_IN
SYS_AUDIO_OUT.GND
SYS_AUDIO_IN.GND
AUDIO_GND.1
AUDIO_GND.3
MPCIACT
VCC5VA
C3
C8
0.1uF
0.1uF
VCC_1.8V
L60
C110
33uF
C112
C114
0.1uF
0.1uF
BLM41P750SPT
+
C
VCC_1.8V
1
2
TIP
RING
3
4
5
6
7
8
9
10
8PMJ-3
8PMJ-1
8PMJ-6
8PMJ-2
8PMJ-7
8PMJ-4
8PMJ-8
8PMJ-5
16
21
22
36
43
93
98
100
112
121
RESERVED_A
RESERVED_B
RESERVED_C
RESERVED_E
RESERVED_F
RESERVED_G
RESERVED_H
RESERVED_I
RESERVED_J
RESERVED_K
17
INTB
EMC1
EMC2
EMC3
EMC4
EMC1
EMC2
EMC3
EMC4
R397
1K
R398
1K
VCC_1.8V
R409
10K
R399
NO-POP
R408
10K
SLP_CLK_EN 14
ELP_REQ/WAKEUP 14
PM_EN
14
W LAN_INTR 14
VCC_1.8V
R390
10K
R18
NO-POP
R391
NO-POP
R17
0
R19
NO-POP
R14
0
R15
NO-POP
R16
0
R8
NO-POP
R9
0
R4
NO-POP
R5
0
114
102
101
83
82
77
69
62
55
50
49
37
32
27
23
74
15
SD_CLK
B
7,16,31
VLYNQ_CLK 3
SD_CMD 7,16,31
VLYNQ_RXD0 14
SD_DATA3 7,16,31
VLYNQ_RXD1 14
SD_DATA2 7,16,31
VLYNQ_TXD0 14
SD_DATA1 7,16,31
VLYNQ_TXD1 14
SPECTRUM DIGITAL INCORPORATED
GND.1
GND.2
GND.3
GND.4
GND.5
GND.6
GND.7
GND.8
GND.9
GND.10
GND.11
GND.12
GND.13
GND.14
GND.15
GND.16
CH8GND
A
+
C2
33uF
+5V.1
+5V.2
C4
+3.3VAUX.1
+3.3VAUX.2
BLM41P750SPT
+
C5
33uF
124
24
L61
89
88
63
40
31
28
19
70
D
R13
3 VLYNQ_SCRUN
+3.3V.1
+3.3V.2
+3.3V.3
+3.3V.4
+3.3V.5
+3.3V.6
+3.3V.7
+3.3V.8
VCC_3.3V
7,16,31 SD_DATA0
1
VCC_3.3V
L58
Title:
mPCI
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
VLYNQ INTERFACE
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
32 o f
35
5
4
3
2
R94
39
1
DSP_EMU0 8
S2/S1 SETTINGS
S1 1-2
S1 4-5
S2 1-2
S2 4-5
TI COMPATABLE EMULATOR
VCC_1.8V
D
D
R85
NO-POP
R86
NO-POP
S1
1
2
3
4
5
6
CASD20TB
VCC_3.3V
R84
2.2K
VCC_1.8V
U1
R79
10K
C
R80
10K
C80
5
SENSE1
4
CT
3
MR
VDD
6
RESET
1
GND
R83
2.2K
C81
0.1uF
C
R93
2
39
DSP_EMU1 8
TPS3808G09DBVR
NO-POP
VCC_1.8V
34 POR_RSTz
VCC_1.8V
R82
10K
R81
2.2K
S2
1
2
3
R89
0
C82
NO-POP
4
5
6
CASD20TB
B
B
J1
8 DSP_TDO
8 DSP_RTCK
R90
R91
1
3
5
7
9
11
13
15
17
19
0
0
CTI_TCK
CTI_EMU0
TMS
TDI
TVD
TDO
TCKRTN
TCLK
EMU0
SRST
EMU2
EMU4
TRSTn
TDIS
KEY
GND.1
GND.2
GND.3
EMU1
GND.4
EMU3
GND.5
VCC_1.8V
2
4
6
8
10
12
14
16
18
20
R87
NO-POP
CTI_EMU1
20 PIN CTI INTERFACE
R88
0
EMULATOR_RSTn 34
R95
NO-POP
SPECTRUM DIGITAL INCORPORATED
A
R92
33
DSP_TCK 8
Title:
DSP_TRST# 8
DSP_TDI
Page Contents:
TMS320DM6446 EVALUATION MODULE
DAVINCI EMULATION HEADER
8
Size:B
DSP_TMS 8
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
Sheet
1
33 o f
35
5
4
2
5
7
33
1V2_PWR_OK
33
Sets
Voltage
R30
3.74K 1%
1
D
R160
NO-POP
AGND
3.3 sq in AGND,
min thermal pad
R31
C25
C26
71.5K 1%
F1
0.1uF
2
R389
J14
no-pop
CENTER
SHUNT
SLEEVE
L4
D7
SMCJ6A
+
R100
220
2.5 MM JACK
RASM712
C14
47uF
BLM41P750SPT
C96
0.1uF
C24
+
C39
10uF LESR
0.1uF
C97
8200pF
VCC_5V
C22
470pF
U19
0.039uF
VCC_5V
F_4.0A
POWER INPUT
R130
2K 1%
21
20
19
18
17
POWERPAD
RT
SYNC
SS/ENA
VBIAS
16
15
14
VIN3
VIN2
VIN1
13
12
11
PGND3
PGND2
PGND1
1
2
3
4
5
AGND
VSENSE
COMP
PWRGD
BOOT
D
TP16
1
3300pF 107 1%
C23
R128
R131
10K
10K 1%
R129
3V3_PWR_OK 35
C21
VCC_3.3V C99
0.047uF
L3
6
7
8
9
10
PH1
PH2
PH3
PH4
PH5
R29
3.3 uH
0.025
+
C20
100uF 4V
+
NO-POP
1
R159
NO-POP
1
1
Connect
at pin 1
TP5
4
6
1
3
8
1V8_PWR_OK
2
1
SW1
SW ITCH
3
TP15
TP28
TP14
C369
100uF 4V
1
C98
1000pF
TPS54310PWP
C19
+
DS9
3.3V @1.5Amp Max
100 uF
GREEN
C
C
VCC_3.3V
VCC_1.8V
VCC_1.8V
U44
R254
10K
R253
10K
BOX MOUNTING HOLES
Z1
SENSE1
4
CT
3
C241
MR
RESET
1
GND
2
1.8V.SYS_RESETz 8,13,15,26,29,30,31
33 EMULATOR_RSTn
R256
0
NO-POP
D5
Z3
Z4
1
1
R255
1K
C242
0.1uF
6
VDD
TPS3808G09DBVR
Z2
1
1
5
VCC_3.3V
BAS16-7
VCC_3.3V
VCC_3.3V
U45
Z5
1
R251
10K
B
R250
10K
J6
C239
5
SENSE1
4
CT
RESET
1
3
MR
GND
2
B
POR_RSTz 33
TPS3808G09DBVR
NO-POP
VCC_3.3V
R252
10K
C240
0.1uF
6
VDD
VCC_3.3V
1
2
VCC_3.3V
DSP_CORE_VDD
HEADER 2
U46
R246
10K
R248
0
R247
10K
S4
A
AA
B
BB
C237
5
SENSE1
4
CT
RESET
1
3
MR
GND
2
R249
10K
C238
0.1uF
6
TPS3808G09DBVR
NO-POP
R245
VDD
PBSW_RSTz
SENSE THRESHOLD FOR TPS3808G01 IS 0.405 VOLTS
PUSHBUTTON SW
SENSE THRESHOLD FOR TPS3808G09 IS 0.840 VOLTS
33
C236
1uF
SPECTRUM DIGITAL INCORPORATED
Title:
X1
X2
X3
X4
X5
Page Contents: POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC
1
1
1
1
1
TP27
TP70
TMS320DM6446 EVALUATION MODULE
Size:B
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
CASE SHIELDING TABS FOR POWER SUPPLY
1
TP1
1
TP68
1
TP2
1
1
TP3
1
A
Sheet
1
34 o f
35
4
3
Connect
at pin
1
3V3_PWR_OK
R423
R39
10.2K 1%
0
R162
NO-POP
C37
C38
71.5K 1%
0.1uF
L7
BLM41P750SPT
C122
0.1uF
C44
+
C45
10uF LESR
0.1uF
C123
8200pF
VCC_5V
C35
470pF
U27
0.039uF
D
VCC_5V
R147
2K 1%
AGND
3.3 sq in AGND,
min thermal pad
R40
1V2_PWR_OK
1
21
20
19
18
17
POWERPAD
RT
SYNC
SS/ENA
VBIAS
16
15
14
VIN3
VIN2
VIN1
13
12
11
PGND3
PGND2
PGND1
AGND
VSENSE
COMP
PWRGD
BOOT
1
2
3
4
5
3300pF
C36
TP37
1
107 1%
R145
D
R186
10K
10K 1%
R146
1V8_PWR_OK
C34
0.047uF
PH1
PH2
PH3
PH4
PH5
1V8_PWR_OK 35
VCC_1.8V
C160
L8
6
7
8
9
10
R38
0.025
2.7 uH
NO-POP
C41
C124
100uF 4V
1000pF
+
1
34 3V3_PWR_OK
2
Sets
Voltage
1
5
TP26
TP29
1
TP36
TPS54310PWP
C33
+
Connect at pin 1
100 uF
CORE VOLTAGE SUPPORT FOR 0.95 TO 1.2 VOLTS
1.2V -> 28.0K 1%
1.05V -> 56.0K 1%
0.95V -> 150K 1%
R49
28.0K 1%
71.5K
R163
NO-POP
L9
BLM41P750SPT
C158
0.1uF
VCC_3.3V
C54
+
C56
10uF LESR
0.1uF
21
20
19
18
17
POWERPAD
RT
SYNC
SS/ENA
VBIAS
16
15
14
VIN3
VIN2
VIN1
13
12
11
PGND3
PGND2
PGND1
R2
10K
10K
C42
560pF
U38
AGND
VSENSE
COMP
PWRGD
BOOT
C43
3300pF
1
2
3
4
5
R183
107 1%
1V2_PWR_OK
R184
10K 1%
C196
C53
1V2_PWR_OK 35
DSP_CORE_VDD
NO-POP
DSP_CORE_SUPPLY
TP43
0.047uF
PH1
PH2
PH3
PH4
PH5
L11
6
7
8
9
10
R59
2.7 uH
0.025
+
C51
+
C52
100uF 4V
TP35
TP44
C191
1000pF
TPS54310PWP
1
100 uF
C50
S
0.039uF
+
100 uF
S
0.1uF
NO-POP
C
R395
D
1V8_PWR_OK
R164
C46
TP12
1
C159
0.01uF
D
3V3_PWR_OK
C55
R185
1.65K 1%
AGND
3.3 sq in AGND, min
thermal pad
1
R50
VCC_5V
1
C
U36
AO3404
28 VDDIMX_EN
B
VCC_5V
G
VCC_5V
VCC_5V
10K
U37
DTR1C/DTR2B
DTR2E
3
DTR1B
2
DTR1E
1
TP25
1
C192
NO-POP
C32
UMC2N
+
S
6
DSP_CORE_VDDIMX
R209
DTR2C
D
4
100 uF
S
R210
NO-POP
D
R187
NO-POP
G
B
U31
AO3404
DSP_CORE_SUPPLY
VCC_1.8V
G
DSP_CORE_SUPPLY
DC7
A
28 VDDIMX_EN
R189
0
1
3
5
7
9
R188
G
VCC_1.8V
100K
SPECTRUM DIGITAL INCORPORATED
2
4
6
8
10
R1
10K
1000pF
Title:
TMS320DM6446 EVALUATION MODULE
Page Contents: POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONN
Size:B
HEADER 5X2
DWG NO
4
3
2
Revision:
E
508162-0001
Date: Wednesday, March 14, 2007
5
A
C161
Sheet
1
35 o f
35