section 2.4 (page 2-7) of Davinci-DM644x EVM Technical Reference

Davinci-DM644x
Evaluation Module
Technical
Reference
2007
DSP Development Systems
DaVinci-DM644x Evaluation
Module Technical Reference
508165-0001 Rev. E
March 2007
SPECTRUM DIGITAL, INC.
12502 Exchange Drive, Suite 440 Stafford, TX. 77477
Tel: 281.494.4505
Fax: 281.494.5310
[email protected] www.spectrumdigital.com
IMPORTANT NOTICE
Spectrum Digital, Inc. reserves the right to make changes to its products or to discontinue any
product or service without notice. Customers are advised to obtain the latest version of relevant
information to verify that the data being relied on is current before placing orders.
Spectrum Digital, Inc. warrants performance of its products and related software to current
specifications in accordance with Spectrum Digital’s standard warranty. Testing and other quality
control techniques are utilized to the extent deemed necessary to support this warranty.
Please be aware that the products described herein are not intended for use in life-support
appliances, devices, or systems. Spectrum Digital does not warrant nor is Spectrum Digital liable for
the product described herein to be used in other than a development environment.
Spectrum Digital, Inc. assumes no liability for applications assistance, customer product design,
software performance, or infringement of patents or services described herein. Nor does Spectrum
Digital warrant or represent any license, either express or implied, is granted under any patent right,
copyright, or other intellectual property right of Spectrum Digital, Inc. covering or relating to any
combination, machine, or process in which such Digital Signal Processing development products or
services might be or are used.
WARNING
This equipment is intended for use in a laboratory test environment only. It generates, uses, and can
radiate radio frequency energy and has not been tested for compliance with the limits of computing
devices pursuant to subpart J of part 15 of FCC rules, which are designed to provide reasonable
protection against radio frequency interference. Operation of this equipment in other environments
may cause interference with radio communications, in which case the user at his own expense will be
required to take whatever measures necessary to correct this interference.
Copyright © 2007 Spectrum Digital, Inc.
Contents
1
Introduction to the DM644x Evaluation Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Provides you with a description of the DM644x Evaluation Module, key features, and
block diagram.
1.1 Key Features
..........................................................
1.2 Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 Basic Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Configuration Switch Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 Power Supply
.........................................................
2
Board Components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the operation of the major board components on the DM644x Evaluation Module.
2.1 EMIF Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.1 DDR2 Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.2 Flash, NAND Flash, SRAM Memory Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1.3 ATA Interface
......................................................
2.1.4 Compact Flash Interface
............................................
2.1.5 Memory Card Interface
..............................................
2.1.6 VLYNQ Interface
..................................................
2.1.7 UART Interface
..................................................
2.1.8 EMIF Buffer/Decoder Control CPLD
....................................
2.2 Input Video Port Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.1 On Chip Video Output DACs
............................................
2.2.2 AIC33 Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Ethernet Interface
.......................................................
2.4 I2C Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4.1 I/O Expanders
........................................................
2.4.2 MSP430 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 SPDIF Analog, and Optical Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Daughter Card Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 DM644x Core CPU Clock
..............................................
2.8 USB Clock
...........................................................
2.9 Battery
..............................................................
1-1
1-2
1-3
1-4
1-5
1-6
1-7
2-1
2-2
2-2
2-2
2-2
2-3
2-3
2-3
2-3
2-3
2-4
2-4
2-5
2-6
2-7
2-7
2-8
2-9
2-9
2-10
2-10
2-10
2-11
3
Physical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Describes the physical layout of the DM644x Evaluation Module and its connectors.
3.1 Board Layout
........................................................
3.2 Connectors
........................................................
3.2.1 J1, Emulation Header
.................................................
3.2.2 J2, MSP430 JTAG Header
..............................................
3.2.3 J3, SD/MMC/MS Connector
............................................
3.2.4 J4, CS2 Select
.......................................................
3.2.5 J5, SD/MMC/MS Termination Select
......................................
3.2.6 J6, External RESET Interface
...........................................
3.2.7 J7, USB Host/Client Termination
........................................
3.2.8 J8, Dual RCA Jack
...................................................
3.2.9 J9, Video Out
.......................................................
3.2.10 J10, USB Connector
................................................
3.2.11 J11, Video In
.......................................................
3.2.12 J12, Video In
.......................................................
3.2.13 J13, SPDIF Out
....................................................
3.2.14 J14, +5V Input
.....................................................
3.2.15 J15, SM/xD Interface
................................................
3.2.16 J16, Mini PCI VLYNQ Interface
.......................................
3.2.17 J17, FPGA Programming Header
......................................
3.3 Peripheral Connectors
.................................................
3.3.1 P1, Compact Flash Connector
.........................................
3.3.2 P2, Ethernet Interface
................................................
3.3.3 P3, Line In/Mic Interface
..............................................
3.3.4 P4, Headphone Out
..................................................
3.3.5 P5, Dual Output RCA Jack
............................................
3.3.6 P6, UART0
........................................................
3.4 JP1, ATA Interface Connector
...........................................
3.5 LEDs
................................................................
3.6 Switches
.............................................................
3.6.1 S1, EMU0/1 Select Switch
.............................................
3.6.2 S2, TRSTn Select Switch
.............................................
3.6.3 S3, Processor Configuration/Boot Load Options
...........................
3.6.4 S4, RESET
........................................................
3.6.5 SW1, Power On/Off
..................................................
3.7 Daughter Card Connectors
..............................................
3.7.1 DC1, EMIF Expansion Connector
......................................
3.7.2 DC2, GIOV33/Ethernet Connector
......................................
3.7.3 DC3, SPI, McBSP, I2C Connector
.......................................
3.7.4 DC4, Video Input Connector
...........................................
3.7.5 DC5, Video Output Connector
..........................................
3.7.6 DC6, SD Interface Connector
..........................................
3.7.7 DC7, Power Connector
...............................................
3.8 Test Points
........................................................
A Schematics
..............................................................
Contains the schematics for the DM644x Evaluation Module
B Mechanical Information
..................................................
Contains the mechanical information about the DM644x Evaluation Module
3-1
3-3
3-5
3-6
3-6
3-7
3-8
3-8
3-9
3-9
3-10
3-10
3-11
3-12
3-12
3-13
3-13
3-14
3-15
3-16
3-16
3-17
3-18
3-18
3-19
3-20
3-21
3-22
3-23
3-23
3-24
3-25
3-26
3-27
3-27
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-33
3-34
A-1
B-1
About This Manual
This document describes the board level operations of the DM644x Evaluation Module
(EVM). The EVM is based on the Texas Instruments DM644x Processor.
The DM644x Evaluation Module is a table top card that allows engineers and software
developers to evaluate certain characteristics of the DM644x processor to determine if
the processor meets the designers application requirements. Evaluators can create
software to execute on board or expand the system in a variety of ways.
Notational Conventions
This document uses the following conventions.
The DM644x Evaluation Module will sometimes be referred to as the DM644x EVM or
EVM.
Program listings, program examples, and interactive displays are shown in a special
italic typeface. Here is a sample program listing.
equations
!rd = !strobe&rw;
Information About Cautions
This book may contain cautions.
This is an example of a caution statement.
A caution statement describes a situation that could potentially damage your software,
or hardware, or other equipment. The information in a caution is provided for your
protection. Please read each caution carefully.
Related Documents, Application Notes and User Guides
Information regarding DaVinciTM technology can be found at the following Texas
Instruments website:
http://www.ti.com/corp/docs/landing/davinci/index.html
Table 1: Manual History
Revision
History
A
Production Release
B
Corrected I2C address of TVP5146
C
Corrected Pin 70, Table 30, DC1 connector
D
Updated schematics, silkscreens, dimensions
E
Updated schematics, silkscreens, dimensions
Table 2: Board History
PWB
Revision
History
C
Production Release
D
Added Intel Flash Memory
E
DDR2 ODT Resistors, DM6446 Symbol Update
Chapter 1
Introduction to the
DM644x EVM
Chapter One provides a description of the DM644x EVM along with the key
features and a block diagram of the circuit board.
Topic
1.1
1.2
1.3
1.4
1.5
1.6
Page
Key Features
Functional Overview
Basic Operation
Memory Map
Configuration Switch Settings
Power Supply
1-2
1-3
1-4
1-5
1-6
1-7
1-1
Spectrum Digital, Inc
1.1 Key Features
The DM644x EVM is a standalone development platform that enables users to
evaluate and develop applications for the TI DaVinci processor family. Schematics,
logic equations and application notes are available to ease hardware development and
reduce time to market.
IR
TI JTAG
SD/
MMC/
MS
S1
S2
MSP430
JTAG
Compact
Flash
DC1 (EMIF)
PWR
SW
I2C
GPIO
3V
BAT
SM/xD
J5
User LEDs
MSP430
NAND
Flash
NOR
Flash
EMIF
CPLD
DC6
I2C
DaVinci
S3
Config
DDR
ATA Hard Disk
DDR
DDR
3.3V Board Supply Voltage
I2C
EEPROM
Altera
JTAG
I2C
GPIO
I2C
GPIO
Serial Media
DC7
1.8V I/O Voltage
1.2V DSP Core Voltage
Video Ports
DC5 (VIDEO OUT)
EMAC
DC4 (VIDEO IN)
DC3
DC2
DAVINCI
TVP
5146
ENET
PHY
S/PDIF
Drivers
AIC33
EVALUATION MODULE
10/100
ENET
UART
+5V
S/PDIF
Analog
S/PDIF
Optical
AUDIO
OUT
HP OUT
AUDIO
IN
VIDEO
IN
SVHS
IN
USB
DAC OUT
SVHS
OUT
A TEXAS INSTRUMENTS TECHNOLOGY
Figure 1-1, Block Diagram DM644x EVM
The EVM comes with a full complement of on board devices that suit a wide variety of
application environments. Key features include:
• A Texas Instruments DM644x processor with an ARM processor operating up to
300 Mhz. and a C64xx DSP operating up to 600 Mhz.
• 1 video input port, supports composite or S video
• 4 video DAC outputs - component, RGB, composite
• 256 Mbytes of DDR2 DRAM
• UART, Media Card interface (SD card, xD card, SM card, MS card, MMC)
• 16 Mbytes of non-volatile Flash memory, 64 Mbytes NAND Flash, 4 Mbytes SRAM
• AIC33 stereo codec
1-2
DM644x EVM Technical Reference
Spectrum Digital, Inc
• USB2 Interface
• 10/100 MBS Ethernet Interface
• IR Remote Interface, real time clock, via MSP430
• Configurable boot load options
• JTAG emulation interface
• 8 user LEDs
• Single voltage power supply (+5V)
• Expansion connectors for daughter card use
• ATA Interface, Vlynq Interface
• SPDIF Interface, analog, and optical
1.2 Functional Overview of the DM644x EVM
The DM644x on the DaVinci EVM interfaces to on-board peripherals through the
16-bit wide EMIF peripheral interface pins. The DDR2 memory is connected to its own
dedicated 32 bit wide bus. The EMIF bus is also connected to the Flash, SRAM,
NAND, and daughter card expansion connectors which are used for add-in boards.
On board video decoder and on chip encoders interface video streams to the DM644x
processor. One decoder and 4 on chip DAC channels are standard on the EVM. On
screen display functions are implemented in software on the DM644x processor.
An on-board AIC33 codec allows the DSP to transmit and receive analog audio
signals. The I2C bus is used for the codec control interface, while the McBSP controls
the audio stream. Signal interfacing is done through 3.5mm audio jacks that correspond
to microphone input, line input, and line output. The codec can select the line input as
the active input.
The EVM includes 8 LEDs, IR interface, and Real time clock which can be used to
provide the user with interactive feedback. These interfaces are implemented via
software on a MSP430 and are accessed by reading and writing to the I2C registers.
Media cards, ATA interface, VLYNQ, and ethernet MAC interfaces are integrated
peripheral on the DM644x processor exploiting its system on a chip architecture.
An included 5V external power supply is used to power the board. On-board switching
voltage regulators provide the +1.2V CPU core voltage and +3.3V for peripherals and
+1.8V memory and DM644x I/O. The board is held in reset until these supplies are
within operating specifications.
1-3
Spectrum Digital, Inc
Code Composer communicates with the EVM through an external emulator via the
20 pin external JTAG connector.
1.3 Basic Operation
The EVM is designed to work with TI’s Code Composer Studio development, or
standard GDB tool environments. Code Composer communicates with the board
through an external JTAG emulator. To start, follow the instructions in the Quick Start
Guide to install Code Composer. This process will install all of the necessary
development tools, documentation and drivers.
Detailed information about the EVM including examples and reference material is
available on the EVM’s CD-ROM.
1-4
DM644x EVM Technical Reference
Spectrum Digital, Inc
1.4 Memory Map
The DaVinci family of processors have a large byte addressable address space, some
limitations to byte addressing are determined by peripheral interconnection to the
Davinci device. Program code and data can be placed anywhere in the unified address
space. Addresses are multiple sizes depending on hardware implementation. Refer to
the appropriate device data sheets for more details.
The memory map shows the address space of a generic DaVinci processor on the left
with specific details of how each region is used on the right. By default, the internal
memory sits at the beginning of the address space. Portions of memory can be
remapped in software as L2 cache rather than fixed RAM.
The part incorporates a dual EMIF interface. One dedicated EMIF directly interfaces to
the DDR2 memory. The other EMIF has 4 separate addressable regions called chip
enable spaces (CS2-CS5). The Flash, NAND Flash, or SRAM are mapped into CE2
space and selectable via J4. Daughter cards use CE2 and CE3. When CE2 is used for
daughter card interfacing J4 must be set appropriately. CS4 and CS5 are reserved for
the VLYNQ interface on the EVM.
Address
0x00000000
Generic DaVinci
Address Space
DM644x EVM
ARM Instruction RAM
ARM Instruction RAM
ARM Data RAM
ARM Data RAM
AEMIF CS2
Flash/NAND/SRAM/DC
AEMIF CS3
DC
AEMIF CS4
VLNQ
AEMIF CS5
VLNQ
DDR
DDR
0x00040000
0x02000000
0x04000000
0x06000000
0x08000000
0x80000000
Figure 1-2, Memory Map, DM644x EVM
1-5
Spectrum Digital, Inc
1.5 Configuration Switch Settings
The EVM has a single 10 position configuration switch that allow users to control the
operational state of the processor when it is released from reset. The configuration
switch is labeled S3 on the EVM board.
Switch S3 configures the boot mode that will be used when the DSP starts executing.
By default the switches are configured to EMIF boot (out of 8-bit Flash) in little endian
mode. The table below shows the settings for switch S3.
Table 1: Configuration Switch S3 Settings
1-6
Position
Name
Function
Boot Mode
1
COUT0
Boot Mode 0
2
COUT1
Boot Mode 1
3
COUT2
Bus width: 0=8 bit, 1=16 bit
4
COUT3
0=ARM boots DSP,
1=C64xx self boots
5
YOUT4
6
YOUT3
7
YOUT2
8
YOUT1
9
YOUT0
10
USER
00 - Boot from ROM NAND
01 - Boot from AEMIF
10 - Boot from ROM HPI
11 - Boot from ROM UART
For Demos
DM644x EVM Technical Reference
Spectrum Digital, Inc
1.6 Power Supply
The EVM operates from a single +5V external power supply connected to the main
power input (J14), a 2.5 MM. barrel-type plug. Internally, the +5V input is converted into
+1.2V, +1.8V and +3.3V using Texas Instruments swift voltage regulators. The +1.2V
supply is used for the DSP core while the +3.3V supply is used for the DSP's I/O buffers
and other chips on the board. The +1.8 volt supply is used for DM644x I/O, low voltage
memory, and peripherals, and DDR2 memory.
There are four power test points on the EVM; TP14, TP25, TP26, and TP43. These test
points provide a convenient mechanism to check the EVM’s multiple power supplies.
The table below shows the voltages for each test point and what the supply is used for.
Table 2: Power Test Points
Test Point
Voltage
Voltage Use
TP43
+1.2 V
DM644x Core
TP25
+1.2 V
DM644x Core/Power Down
TP26
+1.8 V
DDR2 Memory, DSP I/O,
and logic
TP14
+3.3V
DSP I/O and logic
1-7
Spectrum Digital, Inc
1-8
DM644x EVM Technical Reference
Chapter 2
Board Components
This chapter describes the operation of the major board components on
the DM644x EVM.
Topic
2.1
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.2
2.2.1
2.2.2
2.2.3
2.3
2.4
2.4.1
2.4.2
2.5
2.6
2.7
2.8
2.9
Page
EMIF Interfaces
DDR2 Memory Interface
Flash, NAND Flash, SRAM Memory Interface
ATA Interface
Compact Flash Interface
Memory Card Interface
VLYNQ Interface
UART Interface
EMIF Buffer/Decoder Control CPLD
Input Video Port Interfaces
On Chip Video Output DACs
AIC33 Interface
Audio PLL/VCXO Circuit/PLL1705 Clock Generator
Ethernet Interface
I2C Interface
I/O Expanders
MSP430
SPDIF Analog, and Optical Interfaces
Daughter Card Interface
DM644x Core CPU Clock
USB Clock
Battery
2-2
2-2
2-2
2-2
2-3
2-3
2-3
2-3
2-3
2-4
2-4
2-5
2-6
2-7
2-7
2-8
2-9
2-9
2-10
2-10
2-10
2-11
2-1
Spectrum Digital, Inc
2.1 EMIF Interfaces
A separate 16 bit EMIF with four chip enables divide up the address space and allow
for asynchronous accesses on the EVM. CE4 and CE5 are reserved for VLYNQ use
allowing the EVM two dedicated chip enables. CE2 is used for Flash, NAND Flash,
SRAM, and xD and SM Media cards. Both CE2 and/or CE3 can be routed to the
daughter card interface connectors.
Table 1: EMIF Interfaces
Chip Select
Function
CE2
NOR Flash, NAND Flash, SRAM
(see JP4 definition)
CE2
Daughter Card Interface
(see JP4 definition)
CE3
Daughter Card Interface
2.1.1 DDR2 Memory Interface
The DM644x device incorporates a dedicated 32 bit wide DDR2 memory bus. The EVM
uses two gigabit 16 bit wide memories on this bus, for a total of 256 megabytes of
memory for program, data, and video storage. The internal DDR controller uses a
PLL to control the DDR memory timing. The interface supports rates up to 166 Mhz.,
and is clocked on differential edges for optimal performance. Memory refresh for DDR2
is handled automatically by the DM644x internal DDR controller.
2.1.2 Flash, NAND Flash, SRAM Memory Interface
The DM644x has 16 megabytes of NOR Flash, or 64 megabytes of NAND Flash, or
4 megabytes of SRAM memory mapped into the CE2 space. This NOR Flash memory,
and NAND Flash memory are used primarily for boot loading. SRAM is used for
debugging application code. The CE2 space is configured as 16 bits wide on the
DM644x EVM for NOR Flash and SRAM usage, and 8 bit wide for NAND flash usage.
2.1.3 ATA Interface
The DM644x integrates a standard ATA interface on chip. This interface is multiplexed
with the EMIF interface at +1.8 volt levels. The EVM incorporates a standard Lap drive
Hard Disk Drive connector, JP1. Level translators are used to translate the data to
+3.3 volt interface levels and a CPLD is used to translate the control interface to
+3.3V levels. Buffer control is implemented via the CPLD. The drive is selected via I2C
I/O expander U35 bit P6. When the hard drive is in use other peripherals such as the
compact Flash interface and the xD/SM media cards on the EM bus are not accessible
without reconfiguring the EMIF or I2C select lines.
2-2
DM644x EVM Technical Reference
Spectrum Digital, Inc
2.1.4 Compact Flash Interface
The EVM incorporates a PIO type Compact Flash interface. The Compact Flash is
selected via I2C expander U35 bit P5. The interface is multiplexed on the EMIF
interface. When the Compact Flash interface is in use other interfaces such as the ATA
or xD/SM card on the EMIF cannot be used without reconfiguring the EMIF or interface
selects.
2.1.5 Memory Card Interface
The EVM supports a number of media card interfaces. On the EMIF the EVM supports
xD/SM interfaces. These are selected via U35 I2C I/O expander. On the peripheral
interface the EVM supports MMC/MS/MSPro/SD.
When the xD/SM interface is used other interfaces such as the ATA or CF interface on
the EMIF cannot be used without reconfiguring the EMIF or interface selects.
2.1.6 VLYNQ Interface
The DM644x brings its internal VLYNQ interface out to a mini PCI connector J16. The
VLYNQ interface is multiplexed on the EM bus and this bus must be reconfigured after
boot up to support VLYNQ. A multiplexer is used to minimize board layout stubs and
allow as direct as possible interface for the VLYNQ signals.
2.1.7 UART Interface
The internal UART0 on the DM644x device is driven to connector J6. The UART’s
interface is level shifted and routed to the RS-232 line drivers prior to being brought
out to a DB-9 connector, J6.
2.1.8 EMIF Buffer/Decoder Control CPLD
The EMIF buffer and decode functions are implemented with a CPLD. The EVM board
incorporates an Altera MAX II EPM240TCG100 device. The device has 2 banks of
I/O. One bank is used for +1.8 volt signals. The other bank is for+3.3 volt signals.
This allows the device to do level shifting.
The CPLD incorporates the ATA control interface, CF control interface, xD/SM control
interface along with a divide by 8 counter for video synchronization. The CPLD also
incorporates various logic functions for buffer control and glue logic.
2-3
Spectrum Digital, Inc
IR
TI JTAG
SD/
MMC/
MS
S1
S2
MSP430
JTAG
Compact
Flash
DC1 (EMIF)
PWR
SW
I2C
GPIO
3V
BAT
SM/xD
J5
User LEDs
MSP430
NAND
Flash
NOR
Flash
EMIF
CPLD
DC6
I2C
DaVinci
S3
Config
DDR
3.3V Board Supply Voltage
ATA Hard Disk
DDR
DDR
I2C
GPIO
I2C
EEPROM
Altera
JTAG
I2C
GPIO
Serial Media
DC7
1.8V I/O Voltage
1.2V DSP Core Voltage
Video Ports
DC5 (VIDEO OUT)
EMAC
DC4 (VIDEO IN)
DC3
DC2
DAVINCI
TVP
5146
S/PDIF
Drivers
AIC33
ENET
PHY
EVALUATION MODULE
10/100
ENET
UART
+5V
S/PDIF
Analog
S/PDIF
Optical
AUDIO
OUT
HP OUT
AUDIO
IN
VIDEO
IN
SVHS
IN
USB
DAC OUT
SVHS
OUT
A TEXAS INSTRUMENTS TECHNOLOGY
Figure 2-1, DM644x CPLD Block Diagram
2.2 Input Video Port Interfaces
The DM644x EVM supports video capture via the devices internal video ports. A Texas
Instruments TVP5146 is used to decode composite video or S-video inputs into the
device after being level shifted. J11 is used for the S-video inputs and J12 for the
composite inputs on the EVM.
User inputs can be driven via daughter card connector DC4 when the on board level
translator is tristate via driving control Capture Enable signal high on DC4.
2.2.1 On Chip Video Output DACs
The DM644x incorporates 4 output DACs to interface to various output standards. The
DACs are buffered via opamps and driven to a quad RCA jack, J8. The outputs of the
DACs are programmable to support composite video, component video, or RGB.
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DM644x EVM Technical Reference
Spectrum Digital, Inc
2.2.2 AIC33 Interface
The EVM uses a Texas Instruments TLV320AIC33 stereo codec for input and output of
audio signals. The codec samples analog signals on the microphone or line inputs and
converts them into digital data so it can be processed by the DSP. When the DSP is
finished with the data it uses the codec to convert the samples back into analog signals
on the line output so the user can hear the output.
The codec communicates using two serial channels, one to control the codec’s internal
configuration registers and one to send and receive digital audio samples. The I2C bus
is used as the unidirectional control channel. The control channel is generally only used
when configuring the codec, it is typically idle when audio data is being transmitted,
The McBSP is used as the bi-directional data channel. All audio data flows through the
data channel. Many data formats are supported based on the three variables of
sample width, clock signal source and serial data format. The EVM examples generally
use a 16-bit sample width with the codec in master mode so it generates the frame
sync and bit clocks at the correct sample rate without effort on the DSP side.
The codec has a programmable clock from a PLL1705 PLL device. The internal sample
rate generator subdivides the default system clock to generate common audio
frequencies. The sample rate is set by a codec register. The figure below shows the
codec interface on the DM644x EVM.
AIC33 Codec
MIC IN
2
IC
SCL
SDA
Control
I2C Format
SCL
SDA
LINE IN
Control Registers
Analog
Digital
LINE OUT
DR
DX
CLKR
CLKX
FSR
FSX
McBSP
I2S Format
DOUT
DIN
BCLK
WCLK
MIC IN
ADC
LINE IN
DAC
LINE OUT
HP OUT
HP OUT
Figure 2-2, DM644x EVM CODEC INTERFACE
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Spectrum Digital, Inc
2.2.3 Audio PLL/VCXO Circuit/PLL1705 Clock Generator
The DM644x EVM implements a multiple PLL clock generator for creating the Audio
clocks for the board.
In streaming video applications the audio and video sequences can lose
synchronization. The DM644x uses a VCXO interpolation circuit to incrementally speed
up or slow down the STCLK input to allow for this synchronization to remain locked.
The PWM0 and timer inputs on DM644x are used to control this feature. The PWM0 pin
drives a PICX100-27W Voltage Controlled Oscillator which is divided by 8 in the CPLD
and fed back into the timer input pin.
The STCLK is also a source clock for the PLL1705 programmable PLL device. This
device creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK.
The PLL1705 is programmable via an I2C and Expander U18. Software sequencing on
the I/O expander is required to interface correctly to the PLL1708’s programmable
inputs.
The diagram below is a simplified diagram of this clocking scheme.
To I/O Expander
P
L
L
M
S
P P
L L
L L
MM
CD
PLL1705
DM644x
TIMER PWM0
IN
SCK03
SCK02
SCK01
SCK00
MCK02
MCK01
AUDIO_CLK
VID_CLK
XT1
STCLK
VCXO
Circuit Using
PICX100-27
CPLD /8
Counter
Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator
2-6
DM644x EVM Technical Reference
Spectrum Digital, Inc
2.3 Ethernet Interface
The DM644x integrates an ethernet MAC on chip. This interface is routed to the PHY
via CBT switches. The EVM uses an Intel LXT971 PHY. The 10/100 Mbit interface is
isolated and brought out to a RJ-45 standard ethernet connector, P2. The PHY directly
interfaces to the DM644x. The ethernet address is stored in the I2C serial ROM during
manufacturing.
The RJ-45 has 2 LEDs integrated into its connector. The LEDs are green and yellow
and indicate the status of the ethernet link. The green LED, when on, indicates link and
when blinking indicates link activity. The yellow LED, when illuminated, indicates full
duplex mode.
When configuring the PHY use the high drive option in the PHY register 26 to
compensate for the routing length and extra capacitance of the CBT switches.
2.4 I2C Interface
The I2C bus on the DM644x is ideal for interfacing to the control registers of many
devices. On the DM644x EVM the I2C bus is used to configure the video decoder,
stereo Codec, I/O expanders, and communicate with the MSP430. An I2C ROM is also
interfaced via the serial bus. The format of the bus is shown in the figure below.
Start Slave Address W
ACK Sub Address ACK-S Data ACK-S Stop
Write Sequence
Start Slave Address R
Data
STOP
Read Sequence
Figure 2-4, I2C Bus Format
The addresses of the on board peripherals are shown in the table below.
Table 2: I2C Memory Map
Device
Address
R/W
Function
TVP5146
0x5D
R/W
Capture 1 Decoder
PCF 8574A
0x38
R/W
LEDs
PCF 8574A
0x39
R/W
PLL/User Switch
PCF 8574A
0x3A
R/W
Peripheral Selects
TLV320AIC33
0x1B
R/W
CODEC
24WC256
0x50
R/W
I2C EEPROM
MSP430
0x23
R/W
LEDs, IR, RTC
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Spectrum Digital, Inc
2.4.1 I/O Expanders
The DM644x EVM uses three I2C expanders to handle various bit I/O functions. Each
of these is an bit I/O expander, a PCF8574A. At Power Up Reset the expanders are
initialized to 0xFF, all ones. The functions for each of the I/O expanders are shown in
the tables below.
Table 3: U2 I/O Expander
Pin Number
Function
States
P0
User LED DS8
0 = Turns LED On, 1 = Turns LED Off
P1
User LED DS7
0 = Turns LED On, 1 = Turns LED Off
P2
User LED DS6
0 = Turns LED On, 1 = Turns LED Off
P3
User LED DS5
0 = Turns LED On, 1 = Turns LED Off
P4
User LED DS4
0 = Turns LED On, 1 = Turns LED Off
P5
User LED DS3
0 = Turns LED On, 1 = Turns LED Off
P6
User LED DS2
0 = Turns LED On, 1 = Turns LED Off
P7
User LED DS1
0 = Turns LED On, 1 = Turns LED Off
Table 4: U18 I/O Expander
Pin Number
Function
P0
PLL Program Interface, PLL CSEL Pin
P1
PLL Program Interface, PLL SR Pin
P2
PLL Program Interface, PLL FS1 Pin
P3
PLL Program Interface, PLL FS2 Pin
P4
Spare IO1
P5
Spare IO2
P6
Spare IO3
P7
User DIP Switch *
* - useful as input only
High Input - Switch in “ON” Position
Low Input - Switch in “OFF” Position
2-8
DM644x EVM Technical Reference
Spectrum Digital, Inc
Table 5: U35 I/O Expander
Pin Number
Function
State
P0
USB Bus Drive
0 = Enable USB Bus Drive
P1
VDD IMX Enable
0 = Disables VDDIMX supply
P2
VLYNQ
0 = Turns on VLYNQ Mux U11
P3
Compact Flash Reset
Drives Reset Low to CF Adapter
P4
Not Used
P5
WLAN Reset
0 = Removes Reset from WLAN
P6
ATA Select *
0 = Enables ATA Interface
P7
Compact Flash Select *
0 = Enables CF Interface
* Only one interface, ATA or CF, can be enabled at a time
2.4.2 MSP430
The DM644x EVM incorporates infrared remote, real time clock, and some bit I/O in a
MSP430 microcontroller. The I2C interface is used on the DM644x processor to
communicate to the MSP430. The MSP430 acts as a slave device on the I2C bus.
2.5 SPDIF Analog, and Optical Interfaces
The McBSP’s DX pin on the DM644x can be configured to operate as a SPDIF
transmitter. The DM644x EVM supports a single SPDIF output with both analog and
optical interfaces. The analog SPDIF output pin is routed to a level translator then to a
driver and filter circuit before being output on J13. The same level translator is used for
another driver which then drives the optical transmitter U65. When the SPDIF interface
is enabled the TLV320AIC33 codec is disabled.
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Spectrum Digital, Inc
2.6 Daughter Card Interfaces
The EVM provides expansion connectors that can be used to accept plug-in daughter
cards. The daughter card allows users to build on their EVM platform to extend its
capabilities and provide customer and application specific I/O. The expansion
connectors are for all major interfaces including memory, peripherals, and video
expansion.
The pin outs for this interface are documented in Section 3.
The memory connector provides access to the DSP’s EMIF signals to interface with
memories and memory mapped devices.
The video capture port is brought out to the daughter card interface. Four signals are
used to disable the on board video peripherals so that they can be used by the
expansion connector. The table below indicates the operation of these signals.
Table 6: Daughter Card Video Enable
Signal
State To Enable
Daughter Card
Use
DM644x Signals
Enables
CAPTURE_EN
1
DC4 YI0-YI7
PCLK,VD,HD
McBSP_EN
1
DC3 McBSP
ENET_ENABLE
1
DC2 GIOV33 pins
Other than the buffering, most daughter card signals are not modified on the board.
2.7 DM644x Core CPU Clock
The DM644x EVM uses a 27 Megahertz crystal to generate the input clock. The
DM644x has an internal PLL which can multiply the input clock to generate the internal
clock. The PLL multiplier is set via software on the DM644x device.
2.8 USB Clock
The DM644x EVM uses a 24 Mhz crystal for the USB II clock generator. The USB
controller is completely integrated in the DM644x device.
2-10
DM644x EVM Technical Reference
Spectrum Digital, Inc
2.9 Battery
The DM644x EVM incorporates a battery holder to provide backup power to the
MSP430’s real time clock when the power is not applied to the board. The optional
battery should be +3 volt 20 millimeter coin type Lithium single cell.
Some common part numbers for batteries which should operate in the EVM are shown
in the table below.
Table 7: Battery Part Numbers
Part Numbers
CR2032
DL2032
BR2032
CR2025
BR2025
CR2016
BR2016
DL2016
These batteries are available from Duracell, Eveready, Panasonic, Ray-O-Vac, Sanyo,
Sony, Sieko, Toshiba, Varta, and other battery manufacturers.
2-11
Spectrum Digital, Inc
2-12
DM644x EVM Technical Reference
Chapter 3
Physical Description
This chapter describes the physical layout of the DM644x EVM and its
interfaces.
Topic
3.1
3.2
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
3.2.8
3.2.9
3.2.10
3.2.11
3.2.12
3.2.13
3.2.14
3.2.15
3.2.16
3.2.17
3.3
3.3.1
3.3.2
3.3.3
3.3.4
Page
Board Layout
Connectors
J1, Emulation Header
J2, MSP430 JTAG Header
J3, SD/MMC/MS Connector
J4, CS2 Select
J5, SD/MMC/MS Termination Select
J6, External RESET Interface
J7, USB Host/Client Termination
J8, Dual RCA Jack
J9, Video Out
J10, USB Connector
J11, Video In
J12, Video In
J13, SPDIF Out
J14, +5V Input
J15, SM/xD Interface
J16, Mini PCI VLYNQ Interface
J17, FPGA Programming Header
Peripheral Connectors
P1, Compact Flash Connector
P2, Ethernet Interface
P3, Line In/Mic Interface
P4, Headphone Out
3-3
3-5
3-6
3-6
3-7
3-8
3-8
3-9
3-9
3-10
3-10
3-11
3-12
3-12
3-13
3-13
3-14
3-15
3-16
3-16
3-17
3-18
3-18
3-19
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Spectrum Digital, Inc
Topic
3.3.5
3.3.6
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.8
3-2
P5, Dual Output RCA Jack
P6, UART0
JP1, ATA Interface Connector
LEDs
Switches
S1, EMU0/1 Select Switch
S2, TRSTn Select Switch
S3, Processor Configuration/Boot Load Options
S4, RESET
SW1, Power On/Off
Daughter Card Connectors
DC1, EMIF Expansion Connector
DC2, GIOV33/Ethernet Connector
DC3, SPI, McBSP, I2C Connector
DC4, Video Input Connector
DC5, Video Output Connector
DC6, SD Interface Connector
DC7, Power Connector
Test Points
Page
3-20
3-21
3-22
3-23
3-23
3-24
3-25
3-26
3-27
3-27
3-27
3-28
3-29
3-30
3-31
3-32
3-33
3-33
3-34
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.1 Board Layout
The DM644x EVM is a 8.75 x 4.5 inch (210 x 115 mm.) ten (10) layer printed circuit
board which is powered by an external +5 volt only power supply. Figure 3-1 shows the
layout of the DM644x EVM.
DC5
J5
DC6
J8
J3
J9
J4
J7
J10
DC1
J11
J1
S1
DC4
S2
J17
J12
S3
P3
DS10
P4
P1
P5
DC7
DC3
BHT1
DC2
J2
J13
DS1-DS8
P2
P6
J6
SW1
S4
DS9
J14
Figure 3-1, DM644x EVM, Interfaces Top Side
3-3
Spectrum Digital, Inc
JP1
J15
J16
Figure 3-2, DM644x EVM, Interfaces, Bottom Side
3-4
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.2 Connectors
The EVM has seventeen (17) connectors providing interfaces to various peripherals.
These connectors are described in the following sections.
Table 1: Connectors
Connector
Size
Function
Board Side
J1
20
Emulation Header
Top
J2
2x7
MSP430 JTAG
Top
J3
24
SD/MMC/MS
Top
J4
8
CS2 Select
Top
J5
3
SD/MMC/DC
Termination Select
Top
J6
2
External
RESET Interface
Top
J7
2
USB Host/Client
Termination
Top
J8
8
DAC Connector
Top
J9
4
Video Out
Top
J10
2
USB
Top
J11
4
Video In
Top
J12
2
Video In
Top
J13
2
SPDIF Out
Top
J14
2
+5V In
Top
J15
46
SM/xD
Bottom
J16
2x62
Mini PCI for VLYNQ
Bottom
J17
2x5
CPLD Programming
Header (Factory Use)
Top
3-5
Spectrum Digital, Inc
3.2.1 J1, Emulation Header
The J1 Emulation Header is located on the top side of the board and is used to provide
an interface to JTAG emulators. The connections for this connector is shown on page
33 of the schematics in appendix A. The pinout for the J1 connector is shown in the
table below.
Table 2: J1, Emulation Header
Pin #
Signal
Pin #
Signal
1
DSP_TMS
2
TRSTn
3
DSP_TDI
4
TDIS
5
VCC_1.8V
6
Key-clipped
7
DSP_TDO
8
GND
9
DSP_RTCK
10
GND
11
CTI_TCK
12
GND
13
CTI_EMU0
14
CTI_EMU1
15
EMULATOR_RSTn
16
GND
17
NC
18
NC
19
NC
20
GND
3.2.2 J2, MSP430 JTAG Header
The J2 MSP430 JTAG Header is located on the top side of the board and is used to
provide a programming interface to the MSP430 microcontroller. The connections for
this connector are shown on page 28 of the schematics in appendix A. The pinout for
the J2 connector is shown in the table below.
Table 3: J21, MSP430 JTAG Header
3-6
Pin #
Signal
Pin #
Signal
1
430_TDO
2
NC
3
430_TDI
4
MSP430_3V3
5
430_TMS
6
NC
7
430_TCK
8
430_TEST/VPP
9
GND
10
11
NC
12
NC
13
NC
14
NC
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.2.3 J3, SD/MMC/MS Connector
The J3 SD/MMC/MS connector is located on the top side of the board and is used to
provide an interface to a SD/MMC/MD card. The connections for this connector is
shown on page 16 of the schematics in appendix A. The pinout for the J3 connector is
shown in the table below.
Table 4: J3, SD/MMC/MS Connector
Pin #
Signal
Pin #
Signal
1
SD_DATA3
2
SD_CMD
3
GND
4
VCC_3.3V
5
SD_CLK
6
GND
7
SD_DATA0
8
SD_DATA1
9
SD_DATA2
10
GND
11
MS.CMD.BS
12
MS.DATA1
13
MS.DATA0
14
MS.DATA2
15
MS.INS/
VCC_3.3V
16
MS.DATA3
17
MS.CLK
18
VCC_3.3V
19
GND
20
VCC_3.3V
21
SD/MMC.INS/
VCC_3.3V
22
GND
23
GND
24
3-7
Spectrum Digital, Inc
3.2.4 J4, CS2 Select
The J4 connector is actually a 8 position jumper located on the top side of the board
and is used to select the type of memory that the CS2 signal is routed to. The CS2 can
be routed to the four signals shown in the figure below. Only one (1) device can be
selected at a time. To reconfigure this signal, power down the EVM, change the jumper,
and then power the board back up. Do NOT change this jumper with the power on. The
connections for this connector is shown on page 10 of the schematics in appendix A.
1
Route EM_CS2 to FLASH_CEz
FLASH
SRAM
Route EM_CS2 to SRAM_CEz
NAND
Route EM_CS2 to NAND_CEz
DC
Route EM_CS2 to DC_EM_CS2
J4
Figure 3-3, J4, CS2 Select
3.2.5 J5, SD/MMC/MS Termination Select
The J5 connector is a 3 position jumper located on the top side of the board and is used
to select the termination (ground or VCC_3.3V)for the SD/MMC/MS connector (J3).
Either the +3.3V (1-2 position) or Ground (2-3 position) must be selected. To
reconfigure this termination, power down the EVM, change the jumper, and then power
the board back up. Do NOT change this jumper with the power on. The connections for
this connector are shown on page 16 of the schematics in appendix A.
1
J5
3
2
1
GND
+3.3V
Figure 3-4, J5, SD/MMC/MS Termination Select
Table 5: J5, SD/MMC/MS Termination Select
3-8
Media Type
Position
SD
1-2
MMC
1-2
MS
1-2
MS PRO
2-3
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.2.6 J6, External RESET Interface
The J6 connector is a 2 position jumper located on the top side of the board and is used
to externally reset the board. This connector is unpopulated as shipped from the
factory. This circuitry parallels the RESET switch, S4. The connections for this
connector are shown on page 34 of the schematics in appendix A.
J6
1
2
PBSW_RSTz
GND
Figure 3-5, J6, External RESET Interface
3.2.7 J7, USB Host/Client Termination
GND
J7
USB_ID
+3.3V
The J7 connector is a 3 position jumper located on the top side of the board and is used
to select the termination for the USB host/client configuration on USB connector J10.
Either the +3.3V (1-2 position) or Ground (2-3 position) must be selected. This signal
must be terminated. To reconfigure this termination, power down the EVM, change the
jumper, and then power the board back up. Do NOT change this jumper with the power
on. The connections for this connector are shown on page 21 of the schematics in
appendix A.
2
3
1
Figure 3-6, J7, USB Host/Client Termination
3-9
Spectrum Digital, Inc
3.2.8 J8, Dual RCA Jack
The J8 connector is a dual RCA jack providing 4 DAC outputs. Do NOT plug into these
connectors with the power on. The figure below shows this connector as viewed from
the card edge. The position of each DAC output is identified. The connections for this
connector are shown on page 25 of the schematics in appendix A.
DAC C-TOP
DAC B-TOP
DAC D-BOTTOM
DAC A-BOTTOM
Figure 3-7, J8, Dual RCA Jack
3.2.9 J9, Video Out
Connector J9 is a four pin mini din connector which interfaces to an output display
device. This connector brings out the DAC B (DAC B-TOP from J8) and DAC C
(DAC C-TOP from J8). Do NOT plug into this connector with the power on. The figure
below shows this connector as viewed from the card edge. The connections for this
connector are shown on page 25 of the schematics in appendix A.
Pin 3
Pin 1
Pin 4
Pin 2
Figure 3-8, J9, Front View, Mini Din Connector
Table 6: J9, Video Out, Mini Din Connector
3-10
Pin #
Signal Name
1
Ground
2
Ground
3
DAC_IOUTB
4
DAC_IOUTC
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.2.10 J10, USB Connector
Connector J10 is a USB connector. Three different connectors can be mounted at
location J10. The default connector is USB host. The three tables below show the
signals on each possible connector. The connections for this connector are shown on
page 21 of the schematics in appendix A.
Table 7: J10B, USB Peripheral Connector
Pins
Signal
1A
USB_VBUS
2B
USB_DM
3B
USB_DP
4B
GND
1,2
USB_SHIELD
Table 8: J10B, Mini A-B USB On The Go Connector
Pins
Signal
1AB
USB_VBUS
2AB
USB_DM
3AB
USB_DP
4AB
USB_ID
5AB
GND
5,6,7,8
USB_SHIELD
Table 9: J10C, USB Host Connector
Pins
Signal
1A
USB_VBUS
2A
USB_DM
3A
USB_DP
4A
GND
3,4
USB_SHIELD
3-11
Spectrum Digital, Inc
3.2.11 J11, Video In
Connector J11 is a four pin mini din connector which interfaces to the TVP5146
encoder. This connector brings in a video signal (LUMA) to pin 9 on the TVP5146.
Do NOT plug into this connector with the power on. The figure below shows this
connector as viewed from the card edge. The connections for this connector are shown
on page 24 of the schematics in appendix A.
Pin 3
Pin 1
Pin 4
Pin 2
Figure 3-9, J11,Front View, Mini Din Connector
Table 10: J11, Video In, Mini Din Connector
Pin #
Signal Name
1
GND
2
GND
3
LUMA
4
Chroma
3.2.12 J12, Video In
J12 is an RCA jack used as a video input to the TVP5146 encoder. This connector
brings in a video signal to pin 8 on the TVP5146. Do NOT plug into this connector with
the power on. The figure below shows this connector as viewed from the card edge.
The connections for this connector are shown on page 24 of the schematics in
appendix A.
Pin 2, Shield (ground)
Pin 1, Signal Input
Figure 3-10, J12, Video In RCA Jack
Table 11: J12, Video In, RCA Jack
3-12
Pin #
Signal Name
1
Pin 8, TVP5146
2
GND
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.2.13 J13, SPDIF Out
J12 is an RCA jack used as an output from the DX signal on the DM644x. This
connector brings out the SPDIF signal. Do NOT plug into this connector with the power
on. The figure below shows this connector as viewed from the card edge. The
connections for this connector are shown on page 27 of the schematics in appendix A.
Pin 2, Shield (ground)
Pin 1, Signal Output
Figure 3-11, J13, SPDIF Out, RCA Jack
Table 12: J13, SPDIF, RCA Jack
Pin #
Signal Name
1
SPDIF Analog output
2
GND
3.2.14 J14, +5V Input
Connector J14 is the input power connector. This connector bring in +5 volts to the
EVM. This is 2.5mm. jack. Inside of the jack is tied to On/Off power switch SW1.
The other side is tied to ground and LED DS9. The figure below shows this connector
as viewed from the card edge. The connections for this connector are shown on page
34 of the schematics in appendix A.
+5V
J14
Ground
PC Board
Front View
Figure 3-12, J14, +5 Volt Input Connector
3-13
Spectrum Digital, Inc
3.2.15 J15, SM/xD Interface
Connector J14 provides an interface to SM/xD memory cards. This connector is located
on the bottom side of the board. Do NOT plug into this connector with the power on.
The table below shows the signals on this connector. The connections for this
connector are shown on page 34 of the schematics in appendix A.
Table 13: J15, SM/xD Interface
3-14
Connector
Pin Name
EVM
Signal
Connector
Pin Name
EVM
Signal
SM.I/01
3V3.EM.D0
SM.LVD
NC
SM.I/02
3V3.EM.D1
SM.VCC1
VCC_3.3V
SM.I/03
3V3.EM.D2
SM.VCC2
VCC_3.3V
SM.I/04
3V3.EM.D3
SM.VSS1
GND
SM.I/05
3V3.EM.D4
SM.VSS2
GND
SM.I/06
3V3.EM.D5
xD.VSS2
GND
SM.I/07
3V3.EM.D6
xD.CD
xD.CD/VCC_3.3V
SM.I/08
3V3.EM.D7
xD.R/B
3V3.WAIT/BUSY
SM.CLE
3V3.CLE_EM_A2
xD.RE
3V3.READ_OE
SM.ALE
3V3.ALE_EM_A1
xD.CE
3V3.SM_CEz
SM.WE
3V3.WRITE_WE
xD.CLE
3V3.CLE_EM_A2
SM.WP
GND
xD.ALE
3V3.ALE_EM_A1
SM.R/B
3V3.WAIT/BUSY
xD.WE
3V3.WRITE_WE
SM.RE
3V3.READ.OE
xD.WP
SM.Xd.wp
SM.CE
3V3.SM_CEz
xD.VSS1
GND
SM.CD
SM.CD/
VCC_3.3V
xD.I/O0
3V3.EM_D0
SM.OPTION
GND
xD.I/O1
3V3.EM_D1
SM.26
GND
xD.I/O2
3V3.EM_D2
SM.25
GND
xD.I/O3
3V3.EM_D3
SM.SENS.1
GND
xD.I/O4
3V3.EM_D4
SM.SENS.2
GND
xD.I/O5
3V3.EM_D5
xD.VCC1
VCC_3.3V
xD.I/O6
3V3.EM_D6
xD.VCC2
VCC_3.3V
xD.I/O7
3V3.EM_D7
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.2.16 J16, Mini PCI VLYNQ Interface
Connector J16 provides an interface to TI supported VNLYNQ cards. This mini-PCI
connector is located on the bottom side of the board. Do NOT plug into this connector
with the power on. The table below shows the signals on this connector. The
connections for this connector are shown on page 32 of the schematics in appendix A.
Table 14: J16, VLYNQ Card Interface
Pin #
1,2,7-9,11-14,17,
18,EMC1,EMC2,
EMC3,EMC4,93,98,
100,112,121,
104-110,113,
115-120,122-124
15,20,23,25,26,27
32,33,34,35,37,41,
42,45-49,50-62,
64-69,71-87,
90-92,94-96,
99,101,102,114
Signal
NC
GND
10,111
VCC_1.8V
19,28,31,40,63,70,
88,89,97,103
VCC_3.3V
3
SLP_CLK_EN
4
SLP_REG/WAKEUP
5
PM_EN
6
WLAN_INTR
16
SD_CLK/VLYNQ_CLK
21
SD_CMD/VLYNQ_RXD0
22
SD_DATA3/VLYQ_RXD1
24
VLYNQ_SCRUN/SD_DATA0
26
1V8.WLAN_RESET
29
VLYNQ_RXD2
30
VLYNQ_RXD3
36
SD_DATA2/VLYNQ_TXD0
38
VLYNQ_TXD2
39
VLYNQ_TXD3
43
SD_DATA1/VLYNQ_TXD1
3-15
Spectrum Digital, Inc
3.2.17 J17, FPGA Programming Header
Connector J17 is a 10 pin header that provides a programming interface to the
FPGA, U14. This connector is located on the top side of the board. Do NOT plug into
this connector with the power on. The table below shows the signals on this connector.
This connector is for factory use only. Reprogramming this CPLD affects the
functionality of your EVM.
Table 15: J17, FPGA Programming Header
Pin #
Signal
Pin #
Signal
1
ISR_TCK
2
GND
3
ISR_TDO
4
VCC_1.8V
5
ISR_TMS
6
NC
7
NC
8
NC
9
ISR_TDI
10
GND
3.3 Peripheral Connectors
Table 16: Peripheral Connectors
3-16
Connector
Pins
Signal
Board Side
P1
50
Compact Flash
Top
P2
8
Ethernet
Top
P3
4
Line In/Mic
Top
P4
2
HP Out
Top
P5
4
Line Out
Top
P6
8
UART0
Top
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.3.1 P1, Compact Flash Connector
The P1 connector is located on the top side of the board and is used to provide an
interface to a Compact Flash memory card. This is a 2 x 25 pin male connector. The
connections for this connector is shown on page 19 of the schematics in appendix A.
The pinout for the P1 connector is shown in the table below.
Table 17: P1, Compact Flash Connector
Pin #
Signal
Pin #
Signal
1
GND
2
3V3.EM_D3
3
3V3.EM_D4
4
3V3.EM_D5
5
3V3.EM_D6
6
3V3.EM_D7
7
3V3.CF.ATA_CS0
8
GND
9
GND
10
GND
11
GND
12
GND
13
Pin 3, U10
14
GND
15
GND
16
GND
17
GND
18
3V3.CF.ATA2_EM_A0
19
3V3.CF.ATA1_EM_BA1
20
3V3.CF.ATA0_EM_BA0
21
3V3.EM_D0
22
3V3.EM_D1
23
3V3.EM_D2
24
NC
25
VCC_3.V/3V3.CF_CD2
26
VCC_3.V/3V3.CF_CD1
27
3V3.EM_D11
28
3V3.EM_D12
29
3V3.EM_D13
30
3V3.EM_D14
31
3V3.EM_D15
32
3V3.CF.ATA_CS1
33
NC
34
3V3.CF.READ_OE
35
3V3.CF.WRITE_WE
36
VCC_3.3V
37
3V3.CF.INTRQ_EM_RNW
38
Pin 3, U10
39
GND
40
NC
41
3V3.CF_RESETz
42
3V3.CF.WAIT/BUSY
43
NC
44
VCC_3.3V
45
NC
46
NC
47
3V3.EM_D8
48
3V3.EM_D9
49
3V3.EM_D10
50
GND
3-17
Spectrum Digital, Inc
3.3.2 P2, Ethernet Interface
The P2 connector is located on the top side of the board and is used to provide an
Ethernet interface. This is a standard RJ-45 connector. The connections for this
connector is shown on page 22 of the schematics in appendix A. The pinout for the P2
connector is shown in the table below.
Table 18: P2, Ethernet Interface
Pin #
Signal
Pin #
Signal
1
LXT_TDP
2
LXT_TDM
3
LXT_RDP
4
LXT_TDCT
5
NC
6
LXT_RDM
7
NC
8
GND
9
VCC_3.3V
10
LED1-
11
VCC_3.3V
12
LINKLED-
3.3.3 P3, Line In/Mic Interface
The P2 connector is provides a stereo input (lower) and microphone input (upper) to
the TVL320AIC33 on the EVM. This connector is located on the top side of the board.
A view of the connector from the card edge is shown in the figure below. The signals
present on this connector are defined in the following table. The connections for this
connector is shown on page 26 of the schematics in appendix A.
MIC
(upper)
Stereo Line In
(lower)
Figure 3-13, P3, Line In/Mic Interface
Table 19: P3, Line In/Mic Interface
3-18
Pin #
Signal
Input
1
Isolated Ground
Mic
2
MIC3L/MIC3R
Mic
3
MIC3L/MIC3R
Mic
4
Isolated Ground
Line In
5
LINE1R+/LINE2R+
Line In
6
LINE1L+/LINE2L+
Line In
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.3.4 P4, Headphone Out
The P4 connector is a stereo headphone output from the TVL320AIC33 on the EVM.
This connector is located on the top side of the board. A view of the connector from the
card edge is shown in the figure below. The signals present on this connector are
defined in the following table. The connections for this connector is shown on page 26
of the schematics in appendix A.
Stereo Line Out
Figure 3-14, P4, Headphone Out Interface
Table 20: P4, Headphone Out Interface
Pin #
Signal
1
Isolated Ground
2
HPLOUT
3
HPROUT
4
NC
3-19
Spectrum Digital, Inc
3.3.5 P5, Dual Output RCA Jack
The P5 connector is a dual output RCA jack bringing audio from the TVL320AIC33 on
the EVM. This connector is located on the top side of the board. A view of the
connector from the card edge is shown in the figure below. The signals present on this
connector are defined in the following table. The connections for this connector is
shown on page 26 of the schematics in appendix A.
RED
WHITE
Figure 3-15, P5, Dual Output RCA Jack
Table 21: P5, Dual Output RCA Jack
3-20
Pin #
Signal
1
Isolated Ground
2
LEFT_LO+
3
RIGHT_LO+
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.3.6 P6, UART0
The P6 connector is a 9 pin make D-connector which provides a UART interface to the
EVM. This connector interfaces to the MAX 3221 RS-232 line driver (U64) and is
located on the top side of the board. A view of the connector from the card edge is
shown in the figure below. The signals present on this connector are defined in the
following table. The connections for this connector is shown on page 20 of the
schematics in appendix A.
5
4
9
3
8
1
2
7
6
Figure 3-16, P6, DB9 Male Connector
The pin numbers and their corresponding signals are shown in the table below. This
corresponds to a standard dual row to DB-9 connector interface used on personal
computers.
Table 22: P6, UART0 Pinout
Pin #
Signal Name
Direction
1
NC
N/A
2
S_A_RXD
In
3
S_A_TXD
Out
4
NC
N/A
5
GND
N/A
6
NC
N/A
7
S_A_TXD
Out
8
S_A_TXD
Out
9
NC
N/A
10,11
Earth Ground
N/A
3-21
Spectrum Digital, Inc
3.4 JP1, ATA Interface Connector
The JP1 connector is located on the bottom side of the board and is used to provide an
ATA interface to a hard disk drive. This is a 2 x 22 pin male connector. The connections
for this connector is shown on page 18 of the schematics in appendix A. The pinout for
the JP1 connector is shown in the table below.
Table 23: JP1, ATA Interface
3-22
Pin #
Signal
Pin #
Signal
1
ATA RESETn
2
GND
3
ATA.DD7
4
ATA.DD8
5
ATA.DD6
6
ATA.DD9
7
ATA.DD5
8
ATA.DD10
9
ATA.DD4
10
ATA.DD11
11
ATA.DD3
12
ATA.DD12
13
ATA.DD2
14
ATA.DD13
15
ATA.DD1
16
ATA.DD14
17
ATA.DD0
18
ATA.DD15
19
GND
20
NC
21
ATA.DMARQ
22
GND
23
ATA.DIOW
24
GND
25
ATA.DIOR
26
GND
27
ATA.IORDY
28
ATA_CSEL, TP34
29
ATA.DMACK
30
GND
31
ATA.INTRQ
32
GND
33
ATA.DA1
34
TP33
35
ATA.DA0
36
ATA.DA2
37
ATA.CS0
38
ATA.CS1
39
ATA.DASPn
40
GND
41
VCC_5V
42
VCC_5V
43
GND
44
NC
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.5 LEDs
The EVM has ten (10) LEDs which are located on the top side of the board. Eight of
these LEDs (DS1-8) are under user control and addressed over the I2C bus. One LED
(DS9) indicates the presence of +5 volts on the board. The remaining LED (DS10)
indicates a hard disk drive is plugged into the EVM. Additional information regarding
the LEDs are shown in the table below.
Table 24: LEDs
LED #
Use
Color
Schematic
Page
DS1
User Defined
Green
27
DS2
User Defined
Green
27
DS3
User Defined
Green
27
DS4
User Defined
Green
27
DS5
User Defined
Green
27
DS6
User Defined
Green
27
DS7
User Defined
Green
27
DS8
User Defined
Green
27
DS9
+5V
Green
34
DS10
+3.3V
Red
18
3.6 Switches
The EVM has five (5) switches. The function of these switches are shown in the table
below.
Table 25: Switches
Switch
Function
Type
Board
Side
Schematic
Page
S1
EMU0/1 Selection
DIP
Top
33
S2
TRSTn Select
DIP
Top
33
Boot
Configuration
Options
Top
10
S3
DIP
S4
RESET
Push button
Top
34
SW1
Power On/Off
Toggle
Top
34
3-23
Spectrum Digital, Inc
3.6.1 S1, EMU0/1 Select Switch
S1 is a 2 position DIP switch providing 4 options in selecting the state of the EMU0 and
EMU1 pins on the processor. The connections for this switch are shown on page 33
of the schematics in appendix A. A view of the switch is shown in the figure below. The
selection options with this switch are in the table below.
EMU1
H
L
H
L
S1
EMU0
Figure 3-17, S1, EMU0/1 Select Switch
Table 26: S1, EMU0/1 Select
State at Reset
EMU0
EMU1
Function
L
L
Emulation Debug ARM JTAG Enabled
L
H
Not Defined
H
L
Not Defined
H
H
Emulation Debug *
Both ARM & DSP JTAG Enabled
* is the factory shipped configuration
3-24
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.6.2 S2, TRSTn Select Switch
S2 is a 2 position DIP switch providing 4 options in selecting the state of the TRST
signal for JTAG emulation. The connections for this switch are shown on page 33
of the schematics in appendix A. A view of the switch is shown in the figure below. The
selection options with this switch are in the table below.
TRSTn
A
S2
B
TRSTn
Figure 3-18, S2, TRST Select
Table 27: S2, TRST Select
Switch
Position
Function
A
Right
TRST Pull up
A
Left
TRST Pull down *
B
Right
TRST low on power up
Reset
B
Left
Delay via capacitor
(capacitor not populated) *
* is the factory shipped configuration
3-25
Spectrum Digital, Inc
3.6.3 S3, Processor Configuration/Boot Load Options
S2 is a 10 position DIP switch providing 9 options in selecting the processor
configuration and boot load modes. when a switch is in the “ON” position the specific
function is selected. The connections for this switch are shown on page 10 of the
schematics in appendix A. A view of the switch is shown in the figure below. The
selection options with this switch are in the table below.
ON
1
S3
COUT0
2
COUT1
3
COUT2
4
COUT3
5
YOUT4
6
YOUT3
7
YOUT2
8
YOUT1
9
YOUT0
10
SPARE
Figure 3-19, S3, Processor Configuration/
Boot Load Options
Table 28: S3, Processor Configuration/Boot Load Options
3-26
Position
Name
Function
1
COUT0
Bootmode 0
2
COUT1
Bootmode 1
3
COUT2
Bus width: 0=8 bit, 1=16 bit
4
COUT3
0=ARM boots DSP,
1=C64xx self boots
5
YOUT4
6
YOUT3
7
YOUT2
8
YOUT1
9
YOUT0
10
USER
For Demos
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.6.4 S4, RESET
Switch S4 is a push button rest switch that will RESET the processor. This switch is in
parallel with J6. The connections for this switch are shown on page 34 of the
schematics in appendix A.
3.6.5 SW1, Power On/Off
Switch S1 is a toggle switch that provides power to the EVM. The connections for this
switch are shown on page 34 of the schematics in appendix A.
3.7 Daughter Card Connectors
The EVM has seven connectors that are available for daughter card connections.
These connectors make many of the signals on the EVM available to be used by
external logic. The signals on each of the connectors are described in the following
tables. The table below lists the connectors.
Table 29: Daughter Card Connectors
Connector
Size
Function
Board
Side
Schematic
Page
DC1
2x35
EMIF
Top
29
DC2
2x20
GIOV33/Ethernet
Top
31
DC3
2x15
2C
Top
31
DC4
2x20
Video In
Top
30
DC5
2x25
Video Out
Top
30
DC6
2x5
SD Interface
Top
31
DC7
2x5
Power
Top
35
SPI, McBSP, I
3-27
Spectrum Digital, Inc
3.7.1 DC1, EMIF Expansion Connector
Table 30: DC1, EMIF Expansion Connector
3-28
Pin #
Signal
Pin #
Signal
1
B.EM_A21
2
B.EM_A20
3
B.EM_A19
4
B.EM_A18
5
B.EM_A17
6
B.EM_A16
7
B.EM_A15
8
B.EM_A14
9
GND
10
GND
11
B.EM_A13
12
B.EM_A12
13
B.EM_A11
14
B.EM_A10
15
B.EM_A9
16
B.EM_A8
17
B.EM_A7
18
B.EM_A6
19
GND
20
GND
21
B.EM_A5
22
B.EM_A4
23
B.EM_A3
24
CLE_EM_A4
25
B.EM_A1
26
ATA2_EM_A0
27
GND
28
GND
29
ATA_CS1
30
ATA_CS0
31
ATA1_EM_BA1
32
ATA0_EM_BA0
33
WRITE_WE
34
READ_OE
35
WAIT/BUSY
36
INTRQ_EM_RNW
37
GND
38
GND
39
EM_D15
40
EM_D14
41
EM_D13
42
EM_D12
43
EM_D11
44
EM_D10
45
GND
46
GND
47
EM_D9
48
EM_D8
49
EM_D7
50
EM_D6
51
EM_D5
52
EM_D4
53
GND
54
GND
55
EM_D3
56
EM_D2
57
EM_D1
58
EM_D0
59
EM_CS3
60
DC_EM_CS2
61
1.8V.SYS_RESETz
62
CLKOUT0
63
GND
64
GND
65
VCC_3.3V
66
VCC_3.3V
67
GND
68
GND
69
VCC_5V
70
VCC_1.8V
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.7.2 DC2, GIOV33/Ethernet Connector
Table 31: DC2, GIOV33/Ethernet Connector
Pin #
Signal
Pin #
Signal
1
GND
2
GND
3
GIOV33_0
4
GIOV33_1
5
GIOV33_2
6
GIOV33_3
7
GIOV33_4
8
GIOV33_5
9
GND
10
GND
11
GIOV33_6
12
GIOV33_7
13
GIOV33_8
14
GIOV33_9
15
GIOV33_10
16
GIOV33_11
17
GND
18
GND
19
GIOV33_12
20
GIOV33_13
21
GIOV33_14
22
GIOV33_15
23
GIOV33_16
24
GND
25
GND
26
3V3.SYS_RESETz
27
ENET_ENABLEz
28
GND
29
VCC_1.8V
30
3V3.UART_RXD1
31
VCC_1.8V
32
3V3.UART_TXD1
33
GND
34
GND
35
VCC_3.3V
36
VCC_3.3V
37
VCC_5V
38
VCC_5V
39
GND
40
GND
3-29
Spectrum Digital, Inc
3.7.3 DC3, SPI, McBSP, I2C Connector
Table 32: DC3, SPI, McBSP, I2C Connector
3-30
Pin #
Signal
Pin #
Signal
1
SPI_EN1
2
SPI_EN0
3
SPI_DI
4
SPI_DO
5
SPI_CLK
6
TIMER_IN_DC3
7
GND
8
GND
9
DR
10
DX
11
CLKR
12
CLKX
13
FSR
14
FSX
15
GND
16
GND
17
1.8V.SYS_RESETz
18
1.8V.I2C_CLK
19
McBSP_EN
20
1.8V.I2C_DATA
21
AUDIO_CLK
22
GND
23
GND
24
1.8V_DC3_PCLK
25
VCC_3.3V
26
VCC_3.3V
27
GND
28
GND
29
VCC_5V
30
VCC_1.8V
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.7.4 DC4, Video Input Connector
Table 33: DC4, Video Input Connector
Pin #
Signal
Pin #
Signal
1
1.8V.SYS_RESETz
2
CAPTURE_EN
3
GND
4
GND
5
GIO1
6
GIO4
7
GND
8
GND
9
PWM1
10
PWM2
11
GND
12
GND
13
Y10
14
Y11
15
Y12
16
Y13
17
Y14
18
Y15
19
Y16
20
Y15
21
GND
22
GND
23
GND
24
HD
25
PCLK/1V8.DC_PCLK
26
VD
27
GND
28
GND
29
CI0
30
CI1
31
CI2
32
CI3
33
CI4
34
CI5
35
CI6
36
CI7
37
GND
38
GND
39
1V8.I2C_CLK
40
1V8.I2C_DATA
41
VCC_1.8V
42
VCC_1.8V
43
GND
44
GND
45
VCC_3.3V
46
VCC_3.3V
47
GND
48
GND
49
VCC_5V
50
VCC_5V
3-31
Spectrum Digital, Inc
3.7.5 DC5, Video Output Connector
Table 34: DC5, Video Output Connector
3-32
Pin #
Signal
Pin #
Signal
1
GIO0
2
GIO2
3
GIO3
4
GIO5
5
GIO6
6
GIO38
7
GND
8
GND
9
COUT0
10
COUT1
11
COUT2
12
COUT3
13
COUT4
14
COUT5
15
COUT6
16
COUT7
17
GND
18
GND
19
VPBECLK/VID_CLK
20
HSYNC
21
GND
22
GND
23
VCLK
24
VSYNC
25
GND
26
GND
27
YOUT0
28
YOUT1
29
YOUT2
30
YOUT3
31
YOUT4
32
YOUT5
33
YOUT6
34
YOUT7
35
GND
36
GND
37
1.8V.I2C_CLK
38
1.8V.SYS_RESETz
39
1.8V.I2C_DATA
40
GND
41
VCC_1.8V
42
VCC_1.8V
43
GND
44
GND
45
VCC_3.3V
46
VCC_3.3V
47
GND
48
GND
49
VCC_5V
50
VCC_5V
DM644x EVM Technical Reference
Spectrum Digital, Inc
3.7.6 DC6, SD Interface Connector
Table 35: DC6, SD Interface Connector
Pin #
Signal
Pin #
Signal
1
SD_CLK
2
SD_CMD
3
GND
4
GND
5
SD_DATA0
6
SD_DATA1
7
SD_DATA2
8
SD_DATA3
9
GND
10
GND
3.7.7 DC7, Power Connector
Table 36: DC7, Power Connector
Pin #
Signal
Pin #
Signal
1
VDDIMX_EN
2
GND
3
DSP_CORE_SUPPLY
4
DSP_CORE_SUPPLY
5
GND
6
GND
7
VCC_1.8V
8
VCC_1.8V
9
GND
10
GND
3-33
Spectrum Digital, Inc
3.8 Test Points
The EVM has 63 test points. All test points appear on the top of the board. The
following figure identifies the position of each test point. the next table list each test
point and the signal appearing on that test point.
TP47
TP46 TP40
TP39 TP38
TP45
TP20 TP17
TP18
TP53
TP1
TP54
TP6
TP68
TP8
TP55
TP7
TP61
TP59
TP19
TP60
TP9
TP30
TP10
TP42
TP21
TP48
TP11
TP49
TP22
TP41
TP32
TP62
TP31
TP63
TP34
TP64
TP33
TP56
TP43
TP57
TP3
TP69
TP25
TP65
TP27
TP66
TP14
TP67
TP26
TP58
TP15
TP44
TP28
TP35
TP4
TP37
TP29
TP36
TP16
TP70
TP2
Figure 3-20, DM644x EVM, Test Points
3-34
TP5
DM644x EVM Technical Reference
Spectrum Digital, Inc
Table 37: DM644x EVM Test Points
Test Point
#
Signal
Schematic
Page
Test Point
#
TP1
GND
4,34
TP36
1.8 Volt Supply
35
TP2
GND
34
TP37
U27,U38,PIN 4,VCC_3.3V
35
Signal
Schematic
Page
TP3
GND
34
TP38
GND
4
TP4
U4,P24,P1.3/TA2
28
TP39
U28A,DDR_VSS.DLLVCC_1
.8V
4
TP5
VCC_5V
34
TP40
VCC_1.8V
4
TP6
GND
4
TP41
DSP_CORE_VDD
9
TP7
U28A,DDR_AMUX.DLL
TP42
U28D,VDD.10
DSP_CORE_VDD
9
TP8
U28E,PLLPWR18
VCC_1.8V
TP43
DSP_CORE_VDD
35
35
8
TP9
GND
8
TP44
DSP Core Supply
TP10
U28E,AMUX
8
TP45
GND
TP11
U28D,VDDS1.14
VCC_1.8V
9
TP46
U28H,
USB_VDDA1P8PHY
VCC_1.8V
7
TP14
+3.3V
34
TP47
VCC_1.8V
7
TP48
VCC_3.3V
7
3V3_PWR_OK
34
TP49
U28H,
USB_VDDA3P3PHY
VCC_3.3V
7
TP17
GND
4
TP53
VCC_1.8V
5
TP18
U28E,APLLREFV
DSP_CORE_VDD
8
TP54
U28G,VDDA18V
VCC_1.8V
5
TP19
VCC_1.8V
8
TP55
U28G,VDDA11
DSP_CORE_VDD
5
TP20
DSP_CORE_VDD
8
TP56
U51,Pin 36
24
TP21
VCC_1.8V
9
TP57
U51,Pin 37
24
TP22
U28D,VDDSHV.4
VCC_3.3V
9
TP58
U58,PIN 64,MDINT
22
TP25
DSP_CORE_VDDIMX
35
TP59
USB FD
21
TP26
VCC_1.8V
35
TP60
USB VBUS
21
TP15
TP16
TP27
GND
34
TP61
DSP_CORE_VDD
5
TP28
JP1,Pin 28, ATA_CSEL
18
TP62
U51,Pin 30
24
TP29
1.8 Volt Supply
35
TP63
U52,A8,MPF2
26
TP30
U28D,VDDIMX.11
DSP_CORE_VDDIMX
9
TP64
U52,A9,MPF3
26
TP31
DSP_CORE_VDDIMX
9
TP65
U52,C8,SCL
26
TP32
VCC_3.3V
9
TP66
U28I,GIO45/PWM0
VCC_1.8V
5
TP33
JP1, Pin 34
18
TP67
VIN, U54,PIN 3
5
TP68
GND
34
TP69
U52,J9,GPIO1
26
TP70
GND
34
TP34
TP35
DSP Core Supply
35
3-35
Spectrum Digital, Inc
3-36
DM644x EVM Technical Reference
Appendix A
Schematics
This appendix contains the schematics for the DaVinci EVM.
A-1
A-2
A
B
C
D
5
CAPACTITANCE VALUES IN MICROFARADS.
REFERENCE DESIGNATORS USED:
2.
3.
4
BOARD PROPERTIES
6.
32
12
E
21
E
11
E
1
SH
REV
SH
REV
SH
2
E
22
E
E
E
31
3
E
13
E
23
E
33
E
4
E
5
14
E
24
E
34
E
5
E
15
E
25
E
35
E
16
6
7
E
E
17
E
E
27
E
26
E
REVISION STATUS OF SHEETS
TOP - SIGNAL ROUTING
GROUND PLANE
INNER1 - SIGNAL ROUTING
VCC3 PLANE (3.3V BOARD)
INNER2 - SIGNAL ROUTING
INNER3 - SIGNAL ROUTING
VCC PLANE 2
INNER4 - SIGNAL ROUTING
GROUND PLANE
BOTTOM - SIGNAL ROUTING
E
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
8
E
18
E
28
E
9
E
19
E
29
E
10
E
20
E
30
E
OUTER LAYERS 0.5 OZ CU /W 0.5 OZ AU PLATING
INNER LAYERS 1.0 OZ CU
FR4 BOARD MATERIAL
MINIMUM TRACE WIDTH/SPACING 4 MILS
MINIMUM VIA SIZE 10/19 MIL
LAYER STACKUP:
REV
C.
D.
E.
F.
G.
H.
APPLICATION
NEXT ASSY
A. ROUTE TO WITHIN 10% OF MANHATTAN DISTANCE
B1. General layers 50 +/- 5 OHM MATCHED IMPEDANCE
B2. USB layer 90 ohm differential
OBSERVE THE FOLLOWING LAYOUT NOTES:
5.
4
RLSE
MFG
QA
ENGR-MGR
ENGR
CHK
R.R.P.
R.R.P.
C.M.D.
R.R.P.
R.R.P.
T.W.K.
DATE
02/17/2005
DATE
02/17/2005
DATE
02/17/2005
DATE
02/17/2005
DATE
03/01/2004
DATE
02/17/2005
DATE
02/17/2005
3
EMAC/GIO & McBSP/SPI & SD CONNECTORS
VLYNQ CONNECTOR
DAVINCI EMULATION HEADER
POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC
POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONNECTOR
31
32
33
34
35
R.R.P.
USB 2.0 INTERFACE
ETHERNET INTERFACE
TVP5146 LEVEL SHIFTER
TVP5416 VIDEO DECODER
VIDEO OUT
AIC33 AUDIO INTERFACE
SPDIF OUTPUTS & USER LEDS
MSP430 & IR INTERFACE
EMIF EXPANSION CONNECTOR
VIDEO INPUT/OUTPUT CONNECTORS
21
22
23
24
25
26
27
28
29
30
TVP5146
IO EXPANDER 0
IO EXPANDER 1
IO EXPANDER 2
MSP430
0x5D
0x38
0x39
0x3A
0x23
2
AIC33
0x1B
28
28
28
28
24
26
6
02/18/07
DWG NO
1
508162-0001
Title Block
Sheet
1
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
(USB/CD_RESET)
(PLL/USER_SW)
(LED)
I2C ADDRESS TABLE
I2C ROM
0x50
BASE
Production Update - DM6446 symbol updated to current Data Sheet
DDR2 MEMORY
SRAM/NAND FLASH
NOR FLASH
EMIF LEVEL SHIFTER
EMIF CPLD MULTIPLEXER
SD/MMC/MS CONNECTOR
SM/xD CONNECTOR
ATA INTERFACE
COMPACT FLASH CONNECTOR
RS232 INTERFACE
EVM TITLE SHEET
EVM BLOCK DIAGRAM
EMIF INTERFACE
DDR INTERFACE
VIDEO INTERFACE
I/O INTERFACE
USB & SD/MMC/MS CONTROLLER
EMULATION & CLOCKS
POWER PINS
CONFIGURATION CONTROL/BOOT OPTIONS
E
02/18/06
Production Release
D
09/27/05
10/28/05
SHEET
DATE
02/17/05
1
Gamma Release
Beta Release
Initial schematic ready for layout - Alpha Release
11
12
13
14
15
16
17
18
19
20
DWN
2
DESCRIPTION
C
B
A
REV
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
DAVINCI
SCHEMATIC CONTENTS
3
01
02
03
04
05
06
07
08
09
10
USED ON
4. ALL 0.1 uF AND 0.01uF CAPACITORS ARE DECOUPLING CAPS UNLESS
OTHERWISE NOTED. THEY ARE SHOWN ON THE PAGE WITH THE INTEGRATED
CIRCUITS THEY SHOULD BE PLACED NEAR.
RESISTANCE VALUES IN OHMS.
1.
NOTES, UNLESS OTHERWISE SPECIFIED:
of
35
Revision:
E
RRP
RRP
RRP
RRP
RRP
APPROVED
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
5
S H:31
SH:20
4
EEPROM
SH:6
SH:27
4
SH:18
ATA Connector
SH:28
SH:8
SH:6
I2C
SH:3
UART1
SH:6
UART0
SH:6
EMAC/
GPIOs
SH:5
Image In
SH:7
USB 2.0
SH:4
DDR2 IF
S H:9
Power Pins
SH:3-9
DaVinci
S H:3
EMIF/VLYNQ
S H:12
S H:32
Switch
VLYNQ Connector
S H:14
2
Switch
SH:19
SH:16
SH:7
2
SH:30
3
DC #4 Connector
SH:5
SH:31
DC #3 Connector
SH:5
SH:7
1
DWG NO
1
508162-0001
Sheet
DAVINCI BLOCK DIAGRAM
2
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
SH:26
Stereo Codec
(AIC33)
SH:27
SPDIF Outputs
S H:31
DC #3 Connector
PWM [2:1]
SH:6
SPI
SH:8
Timer In
SH:5
PWM0
SH:7
McBSP
S H:30
SH:5
S H:25
DC #5 Connector
SH:5
Video Out
(4) DAC Video Outputs
(4) DACs
S H:31
DC #6 Connector
SD/MMC/MS Connector
SD/MMC/MS
VCXO/PLL
(Audio & Video
Clock Generation)
SH:13
NOR Flash (16MB)
SH:12
NAND Flash (64MB)
S H:17
SMC/xD Connector
Compact Flash Connector
3
SRAM (4MB)
SH:14,15
1.8V to 3.3V
Level Shifters
Emulator
SH:8
PLLs
SH:29
DC #1 Connector
Resistor
Pop Option
(8) LEDs
SH:28
MSP430
IR/RTC/SC
UART
(Debug Term)
S H:22
DC #2 Connector
Switch
S H:22
SH:23
Level Shifter
& Switch
SH:21
USB 2.0 IF
SH:11
DDR2 SDRAM (256MB)
SH:33
Emulator Header
SH:8
Crystal/Osc
Ethernet IF
S H:30
DC #4 Connector
SH:24
Video Decoder
(TVP5146)
SH:10
Config Control &
EM_CS2 Select
S H:35
Power Supply (1.8V & DSP Core)
& DC #7 Connector
S H:34
Power Supply (3.3V)
& System Reset Logic
5
of
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-3
A-4
A
B
C
D
5
15,29 INTRQ_EM_RNW
15,29 W AIT/BUSY
5
R161
1K
VCC_1.8V
RPACK8-10
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
RPACK8-10
R171
243
VCC_1.8V
1
2
3
4
5
6
7
8
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
RN9
1
2
3
4
5
6
7
8
RN3
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
4
4
F1
F3
E2
G5
G4
D1
F2
H5
E1
E5
D3
F5
E3
E4
D2
F4
C1
EM_D[0:15] 12,13,14,29
3
TMS320DM6446
3
DMARQ/UART_RXD1
DMACK/UART_TXD1
EM_WEn/WEn/IOWRn/DIOWn/HDS2n
EM_OEn/REn/IORDn/DIORn/HDS1n
EMRWn/INTRQ/HRWn
GPIO51/ATA_CS1
GPIO52/ATA_CS0
EM_CS5n/GPIO8/VLYNQ_CLOCK
EM_CS4n/GPIO9/VLYNQ_SCRUN
EM_CS3n
EM_CS2n/HCSn
EM_BA1/DA1/GPIO52
EM_BA0/DA0/HINTn
EM_A0/DA2/HCNTL1/GPIO53
EM_A1/(ALE)/HHWIL
EM_A5/GPIO26
EM_A4/GPIO27
EM_A3/GPIO28
EM_A2/(CLE)/HCNTL0
EM_A13/GPIO18
EM_A12/GPIO19
EM_A11/GPIO20
EM_A10/GPIO21
EM_A9/GPIO22
EM_A8/GPIO23
EM_A7/GPIO24
EM_A6/GPIO25
EM_A21/GPIO10/VLYNQ_TXD0
EM_A20/GPIO11/VLYNQ_RXD0
EM_A19/GPIO12/VLYNQ_TXD1
EM_A18/GPIO13/VLYNQ_RXD1
EM_A17/GPIO14/VLYNQ_TXD2
EM_A16/GPIO15/VLYNQ_RXD2
EM_A15/GPIO16/VLYNQ_TXD3
EM_A14/GPIO17/VLYNQ_RXD3
EM_WAIT/(RDY_BUSYn)/IORDYn/HRDYn
EM_D08/DD08/HD08
EM_D09/DD09/HD09
EM_D10/DD10/HD10
EM_D11/DD11/HD11
EM_D12/DD12/HD12
EM_D13/DD13/HD13
EM_D14/DD14/HD14
EM_D15/DD15/HD15
EM_D00/DD00/HD00
EM_D01/DD01/HD01
EM_D02/DD02/HD02
EM_D03/DD03/HD03
EM_D04/DD04/HD04
EM_D05/DD05/HD05
EM_D06/DD06/HD06
EM_D07/DD07/HD07
U28B
G1
H3
G2
H4
G3
H1
J5
T1
T2
B1
C2
H2
J3
J4
J2
CPU.VLYNQ_CLK
RN8
RPACK8-10
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
K3
K4
K2
J1
16
15
14
13
12
11
10
9
RPACK8-10
RPACK8-10
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
RN2
RN7
N4
R1
P2
P1
M4
N3
N2
N1
T3
R3
R4
P5
R2
R5
P3
P4
22
22
R175
R174
R173
R172
C171
2
22
22
22
22
22
22
VLYNQ_ SCRUN
NO-POP
22
22
22
R170
R168
R203
R179
R394
NO-POP
R180
R167
R169
EM_A5
EM_A4
EM_A3
EM_A13
EM_A12
EM_A11
EM_A10
EM_A9
EM_A8
EM_A7
EM_A6
EM_A21
EM_A20
EM_A19
EM_A18
EM_A17
EM_A16
EM_A15
EM_A14
2
15,29
15,29
DWG NO
1
508162-0001
Sheet
DAVINCI EMIF INTERFACE
3
TMS320DM6446 EVALUATION MODULE
of
UART_RXD1/DMARQ 15
UART_TXD1/DMACK 15
WRITE_WE 12,13,15,29
READ_OE 12,13,15,29
INTRQ_EM_RNW 15,29
ATA_CS1
ATA_CS0
VLYNQ_SCRUN 32
EM_CS3
29
EM_CS2
10,15
VLYNQ_CLK 32
35
Revision:
E
CLE_EM_A2 12,13,15,29
ALE_EM_A1 12,13,15,29
ATA2_EM_A0 12,13,15,29
ATA1_EM_BA1 12,13,15,29
ATA0_EM_BA0 15,29
SPECTRUM DIGITAL INCORPORATED
NO-POP
C170
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
VLYNQ_CLK
1
EM_A[3:21] 12,13,14,29
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
5
11 DDR_D[0:31]
11 VREF_STL
W14
V14
W15
V15
U15
W16
V16
T17
V17
U17
U18
W17
V18
W18
V19
U19
D DR_D16
D DR_D17
D DR_D18
D DR_D19
D DR_D20
D DR_D21
D DR_D22
D DR_D23
D DR_D24
D DR_D25
D DR_D26
D DR_D27
D DR_D28
D DR_D29
D DR_D30
D DR_D31
C216
0.22uF
T15
V4
W4
U5
V5
W5
V6
W6
V7
DDR _D8
DDR _D9
D DR_D10
D DR_D11
D DR_D12
D DR_D13
D DR_D14
D DR_D15
VREF_STL
U1
U2
V1
V2
W2
U3
V3
W3
DDR _D0
DDR _D1
DDR _D2
DDR _D3
DDR _D4
DDR _D5
DDR _D6
DDR _D7
4
TMS320DM6446
DDR_VREF
DDR_D24
DDR_D25
DDR_D26
DDR_D27
DDR_D28
DDR_D29
DDR_D30
DDR_D31
DDR_D16
DDR_D17
DDR_D18
DDR_D19
DDR_D20
DDR_D21
DDR_D22
DDR_D23
DDR_D08
DDR_D09
DDR_D010
DDR_D11
DDR_D12
DDR_D13
DDR_D14
DDR_D15
DDR_D00
DDR_D01
DDR_D02
DDR_D03
DDR_D04
DDR_D05
DDR_D06
DDR_D07
U28A
TP6
1
TP45
TP17
1
1
TP38
1
R218
1
T11
R8
3
200
R204
T12
TP7
200
R219
T13
0
R33
R32
R51
R52
BDDR_DQM0
BDDR_DQM1
BDDR_DQM2
BDDR_DQM3
T4
T6
T14
T16
T10
R181
R182
R220
R221
BDDR_DQS0
BDDR_DQS1
BDDR_DQS2
BDDR_DQS3
BDDR_WE
BDDR_RAS
BDDR_CAS
BDDR_CKE
BDDR_CLK
R206
BDDR_CLK_N R205
U4
U6
U14
U16
T8
T7
U7
V8
W7
W8
R41
BDDR_CS
T9
R N10
4
3
2
1
RN12
4
3
2
1
4
3
2
1
U8
V9
U9
BDDR _A0
BDDR _A1
BDDR _A2
BDDR _A3
BDDR _A4
BDDR _A5
BDDR _A6
BDDR _A7
BDDR _A8
BDDR _A9
BDDR_A10
BDDR_A11
BDDR_A12 RN11 4
BDDR_BS00
3
BDDR_BS01
2
BDDR_BS02
1
W13
U13
V13
U12
V12
W12
W11
V11
V10
U11
U10
W10
W9
SURFACE MOUNT TEST POINT PADS
USED FOR VERIFYING DDR TIMINGS
RSV7
DDR_VSSDLL
DDR_VDDDLL
DDR_ZN
DDR_ZP
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_WEn
DDR_CASn
DDR_RASn
DDR_CKE
DDR_CLK0
DDR_CLK0n
DDR_CSn
DDR_BS00
DDR_BS01
DDR_BS02
DDR_A00
DDR_A01
DDR_A02
DDR_A03
DDR_A04
DDR_A05
DDR_A06
DDR_A07
DDR_A08
DDR_A09
DDR_A10
DDR_A11
DDR_A12
R N17
3
DDR_A0
DDR_A1
DDR_A2
DDR_A3
47
47
47
47
47
47
47
47
47
47
47
C189
0.1uF
DD R_DQM0
DD R_DQM1
DD R_DQM2
DD R_DQM3
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
RPACK4-47
5
6
7
8
11
11
11
11
DDR_DQM0
DDR_DQM1
DDR_DQM2
DDR_DQM3
C190
1uF
R53
TP40
0.22
11
11
11
11
DDR_DQS0
DDR_DQS1
DDR_DQS2
DDR_DQS3
DDR_CKE
DDR_WE
DDR_RAS
DDR_CAS
DDR_CLK 11
DDR_CLK_N 11
11
DDR_BS00 11
DDR_BS01 11
DDR_BS02 11
DDR_CS
2
1
2
11
11
11
11
VCC_1.8V
1
DWG NO
1
508162-0001
Sheet
DAVINCI DDR INTERFACE
4
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
PLACE RESISTOR BY DATA TERMINATOR PINS
BALANCE LINE LENGTHS WITH DATA BYTES LENGTHS
ROUTE CLOCK DIFFERENTIAL WITH 15 MIL SPACING BETWEEN
2
BLM21PG221SN1D
L10
DDR_CKE
DDR_WE
DDR_RAS
DDR_CAS
DDR_A[0:12] 11
TP39
RN13
4
3
2
1
D DR_CLK
DDR_CLK_N
DDR_ CS
RPACK4-47
5 DDR_A4
6 DDR_A5
7 DDR_A6
8 DDR_A7
RPACK4-47
5 DDR_A8
6 DDR_A9
7 DDR_A10
8 DDR_A11
RPACK4-47
5 DDR_A12
6 DDR_BS00
7 DDR_BS01
8 DDR_BS02
5
6
7
8
RPACK4-47
1
4
1
5
of
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-5
A
B
HD
VD
PCLK
YI7
YI6
YI5
YI4
YI3
YI2
YI1
YI0
C65
10uF
0.22
R62
5
C66
10uF
0.22
+
TP55
+
TP61
L21
BLM21PG221SN1D
DSP_CORE_VDD
R63
TP53
TP54
L22
BLM21PG221SN1D
VCC_1.8V
23,30
1
2
C
23,30
23,30
23,30
23,30
23,30
23,30
23,30
23,30
23,30
23,30
1
1
2
D
CI7
CI6
CI5
CI4
CI3
CI2
CI1
CI0
1
30
30
30
30
30
30
30
30
1
1
M18
L19
M19
L18
L17
L16
L15
K19
K18
K17
K16
N19
N18
N17
N16
N15
M17
M16
M15
C230
.1uF
C232
.1uF
HD
VD
PCLK
R18
T18
C231
.001uF
P16
P17
C233
.001uF
YI7/CCD07
YI6/CCD06
YI5/CCD05
YI4/CCD04
YI3/CCD03
YI2/CCD02
YI1/CCD01
YI0/CCD00
VSSA_1P1V
VDDA_1P1V
VSSA_1P8V
4
DAC_RBIAS
DAC_VREF
DAC_IOUT_D
DAC_IOUT_C
DAC_IOUT_B
DAC_IOUT_A
U28G
PWM2
R303 100K
R16
R17
R239
3
R240
4.99K
R241
7.5K
DAC_IOUTD 25
T19
DAC_IOUTB 25
DAC_IOUTA 25
Q1
2N3904
R304
2.2K
VCC_3.3V
DAC_IOUTC 25
4.02K
TP66 100pF
30
30
27 3V3.DC_PCLK
C234
.1uF
22.1K 1%
PWM1
C273
R305
VREF_0.5V
1
R307
1K
30
30
30
R296
10K
C272
0.1uF
TP67
VREF_1.24V
1
R301
NO-POP
R299
10K
VCC_3.3V
28
PLL.SR
28
PLL.FS2
28
PLL.FS1
30
30
28 PLL.CSEL
30
30
10,30
10,30
10,30
10,30
30
30
30
10,30
10,30
10,30
10,30
10,30
VPBECLK 30
HSYNC
VSYNC
VCLK
COUT7
COUT6
COUT5
COUT4
COUT3
COUT2
COUT1
COUT0
YOUT7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
3
R19
P18
P19
22
R194
VCC_1.8V
22
R216
A15
B15
C15
22
R234
22
R232
C17
C19
22
RPACK8-33
22
9
10
11
12
13
14
15
16
RPACK8-33
9
10
11
12
13
14
15
16
R233
RN18
R236
8
7
6
5
4
3
2
1
RN21
8
7
6
5
4
3
2
1
C18
D19
C16
B19
B18
A18
B17
A17
B16
A16
E18
E17
E16
E15
D18
D17
D16
D15
TMS320DM6446
TMS320DM6446
PWM0/GPIO45
PWM1/R2/GPIO46
PWM2/B2/GPIO47
VPBECLK
HSYNC
VSYNC
VCLK
COUT7/G4
COUT6/G3
COUT5/G2
COUT4/B7
COUT3/B6/DSP_BT
COUT2/B5/EM_WIDTH
COUT1/B4/BTSEL1
COUT0/B3/BT_SEL0
YOUT7/R7
YOUT6/R6
YOUT5/R5
YOUT4/R4/AEAW4
YOUT3/R3/AEAW3
YOUT2/G7/AEAW2
YOUT1/G6/AEAW1
YOUT0/G5/AEAW0
VDDA_1P8V
CI7/CCD15/UART_RXD2
CI6/CCD14/UART_TXD2
CI5/CCD13/UART_CTS2
CI4/CCD12/UART_RTS2
CI3/CCD11
CI2/CCD10
CI1/CCD09
CI0/CCD08
4
C235
1uF
R302
0
R298
10K
PLL1705
XT2
XT1
CSEL
SR
FS2
FS1
U55
27MHz
8
7
6
5
C312
10pF
9
8
15
14
3
2
19
18
17
16
4
20
13
1
2
TLV431ADBV
U39
C269
R294
R292
R293
R295
0.1uF
33
R366
33
2
R290
0.1uF
C266
33
DWG NO
1
508162-0001
Sheet
DAVINCI VIDEO INTERFACE
5
TMS320DM6446 EVALUATION MODULE
of
30
35
Revision:
E
AUDIO_CLK 26,31
VID_CLK
33
SPECTRUM DIGITAL INCORPORATED
CPLD_TIMER_IN 15
U57
SN74AUC1G125
4
4 R291
0.1uF
C265
1
U56
SN74AUC1G125
Date: Wednesday, March 14, 2007
Size:B
2
VCC_1.8V
VCC_1.8V
C71
10 uF
Page Contents:
Title:
33
R365
C311
0.1uF
VCC_3.3V
0.1uF
C270
+
NO-POP
33
NO-POP
NO-POP
VCC_3.3V
VCC_3.3V
R297
VREF =1.24 VOLTS
R242
1K
VCC_3.3V
PI6CX100-27W
4
AGND
VCC
MCKO2
MCKO1
SCKO3
SCKO2
SCKO1
SCKO0
DGND3
DGND2
DGND1
VDD3
VDD2
VDD1
C268
0.1uF
C267
0.1uF
C310
NO-POP
X1
X2
NC1
NC2
VIN
VDD
GND CLKOUT
U54
R244
NO-POP
R243
0
1
2
3
4
C271
NO-POP
Y5
11
10
12
7
6
5
R300
10K
2
5
3
1
U28I
3
5
3
1
A-6
5
5
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
5
15 1V8.MSP430_INT
5
GPIOV33_16/MDC
GPIOV33_12/RXDV
GPIOV33_13/RXER
GPIOV33_14/CRS
GPIOV33_15/MDIO
GPIOV33_8/RXD1
GPIOV33_9/RXD2
GPIOV33_10/RXD3
GPIOV33_11/RXCLK
GPIOV33_4/TXD1
GPIOV33_5/TXD2
GPIOV33_6/TXD3
GPIOV33_7/RXD0
GPIOV33_0/TXEN
GPIOV33_1/TXCLK
GPIOV33_2/COL
GPIOV33_3/TXD0
R424
10K
VCC_1.8V
GPIO7
SPI_EN1/HDDIR/GPIO42
SPI_EN0/GPIO37
SPI_CLK/GPIO39
SPI_DO/GPIO41
SPI_DI/GPIO40
SCL/GPIO43
SDA/GPIO44
UART_RXD0/GPIO35
UART_TXD0/GPIO36
GPIO0/LCD_OE
GPIO1/C_WEn
GPIO2/G0
GPIO3/B0/LCD_FIELD
GPIO4/R0/C_FIELD
GPIO5/G1
GPIO6/B1
GPIO38/R1
TMS320DM6446
U28C
C3
B2
A4
A3
A2
B3
C4
B4
D5
C5
UART_RXD0
UART_TXD0
22
22
22
RPACK4-22
8
7
6
5
1V8.MSP430_INT
R198
R201
RN14
1
2
3
4
R197
4
GIO0
GIO1
GIO2
GIO3
GIO4
GIO5
GIO6
GIO38
C13
E13
D13
C14
B14
E14
A14
D14
R410
10K
SPI_CLK
SPI_DO
SPI_DI
SPI_EN0
31
31
31
31
SPI_EN1
ATA_DIR
UART_RXD0 20
UART_TXD0 20
30
30
30
30
30
30
30
30
GIOV33_16 22,31
B10
22,31
22,31
22,31
22,31
GIOV33_12
GIOV33_13
GIOV33_14
GIOV33_15
D11
D10
C10
E10
22,31
22,31
22,31
22,31
22,31
22,31
22,31
22,31
GIOV33_8 22,31
GIOV33_9 22,31
GIOV33_10 22,31
GIOV33_11 22,31
GIOV33_4
GIOV33_5
GIOV33_6
GIOV33_7
GIOV33_0
GIOV33_1
GIOV33_2
GIOV33_3
C11
B11
E11
A10
D12
A11
C12
E12
B13
A13
A12
B12
4
31
15
VCC
WP
SCL
SDA
24WC256
A0
A1
NC
VSS
U34
R214
2.2K
8
7
6
5
VCC_3.3V
I2C_DATA
I2C_CLK
C195
0.1uF
3
SCL1
1
GND
4 SDA1
3
2 VREF1
U33
PCA9306
R212
2.2K
VCC_3.3V
1V8.I2C_DATA 26,30,31
1V8.I2C_CLK 26,30,31
C162
0.1uF
VCC_1.8V
EEPROM ( 32KBytes )
1
2
3
4
R215
2.2K
VCC_1.8V
3
R211
2.2K
ENABLE
SDA2
SCL2
VREF2
2
8
5
6
7
2
R213
100K
VCC_3.3V
3 V3.I2C_CLK
DWG NO
1
508162-0001
Sheet
DAVINCI I/O INTERFACE
6
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
3V3.I2C_DATA 24,27,28
3V3.I2C_CLK 24,27,28
SPECTRUM DIGITAL INCORPORATED
3V3.I2C_DATA
Title:
C194
0.1uF
1
of
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-7
A
B
C
L13
+
C59
10uF
+
C206
1uF
C209
0.1uF
C212
0.1uF
C8
RN16
5
8
7
6
5
C207
0.01uF
G17
G18
H16
H17
J18
J19
4
USB_VSSREF
USB_R1
USB_DM
USB_DP
USB_ID
USB_VBUS
U28H
TMS320DM6446
USB_VSSA1P2LDO
USB_VDDA1P2LDO
USB_VSS1P8
USB_VDD1P8
USB_VSSA3P3.2
USB_VDDA3P3.1
22
R195
A9
C211
0.01uF
22
R196
RPACK4-22
RN15
B9
C9
D9
E9
1
2
3
4
22
R199
D8
22
R200
5
6
7
8
RPACK4-22
A8
4
3
2
1
4
B8
A7
B7
C7
U28F
Place C206 as close to device as possible, between 2 to 5 millimeters
R60
0.22
C60
10uF
0.22
TP49
TP46
R61
SD_CLK
SD_CMD
SD_DATA3
SD_DATA2
SD_DATA1
SD_DATA0
CLKR/GPIO30
CLKX/GPIO29
DR/GPIO34
DX/GPIO33
FSR/GPIO32
FSX/GPIO31
TMS320DM6446
TP47
1
2
BLM21PG221SN1D
VCC_1.8V
1
2
BLM21PG221SN1D
VCC_3.3V L15
TP48
1
1
1
A-8
1
D
5
16,31,32
16,31,32
16,31,32
16,31,32
G16
H18
H19
G19
J16
J17
SD_CLK
R217
10K
16,31,32
SD_CMD 16,31,32
SD_DATA0
SD_DATA1
SD_DATA2
SD_DATA3
21
21
21
31 McBSP_EN
R309
360
3
Place R217 as close to device as possible
USB_DM
USB_DP
USB_ID
USB_VBUS 21
3
R308
10K
19
1
2
3
4
5
6
7
8
9
GND
VCC
B1
B2
B3
B4
B5
B6
B7
B8
10
20
18
17
16
15
14
13
12
11
74CBTLV3245
31
31
31
31
27,31
31
0.1uF
C274
VCC_3.3V
B_FSX
B_FSR
B_DX
B_DR
B_CLKX
B_CLKR
26
26
26
26
26
26
2
1
Date: Wednesday, March 14, 2007
1
508162-0001
Sheet
7
of
35
Revision:
E
DAVINCI USB & SD/MMC/MMC CONTROLLER
DWG NO
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
Title:
SPECTRUM DIGITAL INCORPORATED
U53 is a switch used for DC3 to allow the McBSP
to be disconnected from on-board circuitry.
Signal levels are at 1.8 Volt logic levels on both
sides of switch
G
NC
A1
A2
A3
A4
A5
A6
A7
A8
U53
CLKR
CLKX
FSX
FSR
DX
DR
2
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
NO-POP
L5
DSP_CORE_VDD
1
L6
2
0.22
NO-POP
TP18
C148
NO-POP
C147
1uF
33 DSP_EMU0
33 DSP_EMU1
TP20
R34
R35
TP8
TP19
33
C138
0.1uF
C137
1000pF
TP10
C142
NO-POP
C140
NO-POP
TP9
1
1
L3
M3
M2
D6
C6
B5
D7
33 DSP_TRST#
33 DSP_TDO
E6
33 DSP_TMS
A5
A6
33 DSP_TCK
DSP_TDI
B6
L4
33 DSP_RTCK
1
1
2
BLM21PG221SN1D
VCC_1.8V
1
13,15,26,29,30,31,34 1.8V.SYS_RESETz
1
1
MXVSS
MXI/CLKIN
MXO
M24VSS
M24XI
M24XO
CLK_OUT0/GPIO48
CLK_OUT1/TIM_IN/GPIO49
TMS320DM6446
RSV6
RSV24
PLLVDD18
EMU0
EMU1
TDO
TDI
TRSTn
TMS
TCK
RTCK
RESETn
U28E
15 TIMER_IN
L2
L1
M1
F17
F18
F19
K1
E19
R177
R176
NO-POP
VCC_1.8V
R237
R238
NO-POP
VCC_1.8V
0
0
C139
Y2
27MHz
C144
C229
24MHz
Y3
C228
CLKOUT0 29
18pF
18pF
18pF
18 pF
EIA0402
NO-POP
C141
.1uF
EIA0402
U40
GND
EN
1
2
VCC
U12
EN
1
DWG NO
508162-0001
Sheet
8
DAVINCI EMULATION & CLOCKS
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size: B
Page Contents:
SPECTRUM DIGITAL INCORPORATED
OUT GND 2
NO-POP/27 MHz
3
4
NO-POP/24 MHz
OUT
VCC
Title:
3
4
CRYSTAL AND CAPS REMOVED WHEN
OSCILLATOR IS USED
1
2
BLM21PG221SN1D
L2
NO-POP
VCC_1.8V
R178
R235
L14
1
2
BLM21PG221SN1D
C227
.1uF
VCC_1.8V
OPTIONAL OSCILLATOR POPULATION
of
35
Revision:
E
Spectrum Digital, Inc
A-9
A
B
C
D
VCC_1.8V
DSP_CORE_VDDIMX
DSP_CORE_VDD
VCC_3.3V
5
+
C125
NO-POP
R37
0.025
TP11
C130
NO-POP
0.025
TP31
0.025
TP42
0.025
TP22
TP21
+
C132
NO-POP
R42
TP30
+
C127
NO-POP
R54
TP41
+
R36
TP32
1
1
1
1
1
1
1
A-10
1
5
CPU_VCC_1.8V
CPU_VCC_1.8V
F16
L5
N5
M14
M6
L13
L7
K14
K6
J15
J7
H14
H6
G15
G9
G7
F14
F8
F6
E7
T5
R15
R13
R11
R9
P14
P12
P10
P8
P6
N13
N11
N9
N7
K11
K9
K8
J13
J11
J10
J9
H12
H11
H10
H8
CPU_DSP_CORE_VDDIMX
F13
F12
F11
F10
D4
M12
M10
M8
L11
L10
L9
L8
K12
K10
F15
4
0
CPU_DSP_CORE_VDD
CPU_VCC_3.3V
R202
4
TMS320DM6446
M24VDD
MXVDD
DVDD18.18
DVDD18.17
DVDD18.16
DVDD18.15
DVDD18.14
DVDD18.13
DVDD18.12
DVDD18.11
DVDD18.10
DVDD18.9
DVDD18.8
DVDD18.7
DVDD18.6
DVDD18.5
DVDD18.4
DVDD18.3
DVDD18.2
DVDD18.1
DVDDR2.14
DVDDR2.13
DVDDR2.12
DVDDR2.11
DVDDR2.10
DVDDR2.9
DVDDR2.8
DVDDR2.7
DVDDR2.6
DVDDR2.5
DVDDR2.4
DVDDR2.3
DVDDR2.2
DVDDR2.1
CVDDDSP.11
CVDDDSP.10
CVDDDSP.9
CVDDDSP.8
CVDDDSP.7
CVDDDSP.6
CVDDDSP.5
CVDDDSP.4
CVDDDSP.3
CVDDDSP.2
CVDDDSP.1
CVDD.10
CVDD.9
CVDD.8
CVDD.7
CVDD.6
CVDD.5
CVDD.4
CVDD.3
CVDD.2
CVDD.1
DVDD33.4
DVDD33.3
DVDD33.2
DVDD33.1
RSV5
U28D
VSS.45
VSS.44
VSS.43
VSS.42
VSS.41
VSS.40
VSS.39
VSS.38
VSS.37
VSS.36
VSS.35
VSS.34
VSS.33
VSS.32
VSS.31
VSS.30
VSS.29
VSS.28
VSS.27
VSS.26
VSS.25
VSS.24
VSS.23
VSS.22
VSS.21
VSS.20
VSS.19
VSS.18
VSS.17
VSS.16
VSS.15
VSS.14
VSS.13
VSS.12
VSS.11
VSS.10
VSS.9
VSS.8
VSS.7
VSS.6
VSS.5
VSS.4
VSS.3
VSS.2
VSS.1
RSV4
RSV2
RSV3
RSV1
R14
R12
R10
R7
R6
P15
P13
P11
P9
P7
N14
N12
N10
N8
N6
M13
M11
M9
M7
M5
L14
L12
L6
K15
K13
K7
K5
J14
J12
J8
J6
H15
H13
H9
H7
G14
G13
G12
G11
G10
G8
G6
F9
F7
E8
W19
A19
W1
A1
3
3
+
C49
22uF
C31
22uF
C58
22uF
+
C27
22uF
+
+
C47
22uF
C28
22uF
C40
22uF
CPU_VCC_1.8V
+
CPU_VCC_1.8V
+
CPU_VCC_1.8V
+
CPU_DSP_CORE_VDDIMX
CPU_DSP_CORE_VDD
+
+
0.1uF
C202
0.1uF
C113
0.1uF
2
0.1uF
C143
0.1uF
C145
0.1uF
0.1uF
C146
0.1uF
C135
0.1uF
0.1uF
C205
0.1uF
0.1uF
C175
0.1uF
C188
0.1uF
C183
0.1uF
C115
0.1uF
C134
DWG NO
1
508162-0001
DAVINCI POWER PINS
Sheet
9
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size:B
0.1uF
C136
0.1uF
C179
0.1uF
C168
0.1uF
C200
1
SPECTRUM DIGITAL INCORPORATED
0.1uF
C178
0.1uF
C204
0.1uF
C182
0.1uF
C199
Page Contents:
0.1uF
C176
0.1uF
C111
Title:
0.1uF
C203
0.1uF
C181
0.1uF
C184
0.1uF
C201
0.1uF
C174
C210
0.1uF
C167
0.1uF
C208
0.1uF
C180
C213
0.1uF
C186
0.1uF
C185
0.1uF
C177
C214
0.1uF
C169
0.1uF
C187
C30
22uF
C215
C29
22uF
C48
22uF
+
CPU_VCC_3.3V
2
of
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
AEAW [4:0]
YOUT[4:0]
5
DSP_BT
8_16
BTSEL[1:0]
MODE
COUT3
COUT2
COUT[1:0]
PINS
S1-2=XXX S1-1=XXX
S1-2=XXX S1-1=XXX
10 = Boot from ROM (HPI)
11 = Boot from ROM (UART)
4
S1-2=XXX S1-1=XXX
S1-3=XXX
1 = 16-bit
ALL ADDRESS LINES GPIO
S1-9=XXX
S1-8=XXX
S1-7=XXX
S1-6=XXX
S1-5=XXX
S1-4=XXX
1 = GEM Self-Boots
Address Bus Width
S1-4=XXX
0 = ARM boots GEM
DSP BOOT
S1-3=XXX
0 = 8-bit
Selects AEM IF CS2 Bus Width
S1-2=XXX S1-1=XXX
01 = Boot from AEM IF
SWITCH S1
00 = Boot from ROM (NAND)
Non-secure device
Selects ARM Boot Mode
FUNCTION
BOOT CONFIGURATION SWITCH
4
1
2
3
4
5
6
7
8
1K
1K
10
9
8
7
6
5
4
3
2
1
S3
20
19
18
17
16
15
14
13
12
11
J4
CONN 4x2
1
3
5
7
2
4
6
8
DIP_SWITCH-10
1
2
3
4
5
6
7
8
9
10
RN28
RPACK8-NO-POP
SPARE SWITCH
3
2
COUT0
COUT1
COUT2
COUT3
YOUT4
YOUT3
YOUT2
YOUT1
YOUT0
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
Date: Wednesday, March 14, 2007
1
508162-0001
Sheet
10 o f
35
Revision:
E
DAVINCI CONFIGURATION CONTROL/BOOT OPTIONS
DWG NO
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
1
Title:
USER_SW 28
R227
10K
FLASH_CEz 13
SRAM_CEz 12
NAND_CEz 12
DC_EM_CS2 29
R228
NO-POP
2
ONLY ONE DEVICE CAN BE SELECTED
AT A TIME AT POWER UP.
TO RECONFIGURE BOARD
POWER DOWN EVM,
CHANGE JUMPER TO DESIRED DEVICE.
16
15
14
13
12
11
10
9
RPACK8-1K
3,15 EM_CS2
R229
R230
RN29
VCC_1.8V
3
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
5
A
B
C
D
Spectrum Digital, Inc
A-11
A-12
A
B
C
D
5
5
T8
T2
R7
R3
R8
P1
P3
P2
DDR_A4
DDR_A3
DDR_A2
DDR_A1
DDR_A0
DDR_DQM1
DDR_DQM0
DDR_DQS0
E3
J3
D8
E7
H8
J7
M8
N8
D DR_CLK
DDR_CLK_N
DDR_DQS1
P8
P7
N7
N3
N2
DDR_CS
DDR_CAS
DDR_RAS
DDR_WE
DDR_CKE
V3
V7
N9
AA9
AA8
AA2
AA1
D2
V8
A9
A8
A2
A1
H2
V2
U7
R2
U3
U8
U2
T7
T3
DDR _A12
DDR _A11
DDR _A10
DDR_A9
DDR_A8
DDR_A7
DDR_A6
DDR_A5
R151
0
DDR_BS02
DDR_BS01
DDR_BS00
4 DDR_D[0:31]
4 DDR_DQM1
4 DDR_DQM0
4 DDR_DQS0
4 DDR_DQS1
4 DDR_CLK
4 DDR_CLK_N
4 DDR_CS
4 DDR_CAS
4 DDR_RAS
4 DDR_WE
4 DDR_CKE
4 DDR_BS02
4 DDR_BS01
4 DDR_BS00
4 DDR_A[0:12]
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSSQ.1
VSSQ.2
VSSQ.3
VSSQ.4
VSSQ.5
VSSQ.6
VSSQ.7
VSSQ.8
VSSQ.9
VSSQ.10
VSSDL
DQ3
DQ2
DQ1
DQ0
DQ7
DQ6
DQ5
DQ4
DQ11
DQ10
DQ9
DQ8
DQ15
DQ14
DQ13
DQ12
VREF
VDDL
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
VDDQ.5
VDDQ.6
VDDQ.7
VDDQ.8
VDDQ.9
VDDQ.10
C155
BDDR_D3
BDDR_D2
BDDR_D1
BDDR_D0
L3
L7
K2
K8
4
RN5
BDDR_D4
BDDR_D6
BDDR_D3
BDDR_D1
BDDR_D7
BDDR_D6
BDDR_D5
BDDR_D4
J9
J1
L9
L1
U9
T1
H3
D3
M3
G8
J8
D7
J2
E2
L8
L2
E8
H7
G2
M7
BDDR_D5
BDDR_D7
BDDR_D0
BDDR_D2
RN27
RN6
BDDR_D12
BDDR_D14
BDDR_D11
BDDR_D9
BDDR_D11
BDDR_D10
BDDR_D9
BDDR_D8
G3
G7
F2
F8
BDDR_D[0:15]
RN26
BDDR_D13
BDDR_D15
BDDR_D8
BDDR_D10
0.1uF
0.1uF
1
2
3
4
1
2
3
4
1
2
3
4
1
2
3
4
0.1uF
C152
0.1uF
0.1uF
C156
C150
C224
BDDR_D15
BDDR_D14
BDDR_D13
BDDR_D12
VREF_STL
VCC_1.8V
E9
E1
G9
G1
M2
M1
M9
H1
R9
D1
V1
F3
F7
K1
K3
K7
K9
D9
F1
F9
H9
128 MEGABYTES
MT47H64M16BT
UDM
LDM
UDQS#/NU
UDQS
LDQS#/NU
LDQS
CK
CK#
CS#
CAS#
RAS#
WE#
CKE
RFU.1
RFU.2
ODT
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
A4
A3
A2
A1
A0
BA2
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
U20
4
0.1uF
C154
RPACK4-47
8DDR _D4
7DDR _D6
6DDR _D3
5DDR _D1
8DDR _D5
7DDR _D7
6DDR _D0
5DDR _D2
RPACK4-47
RPACK4-47
8D DR_D12
7D DR_D14
6D DR_D11
5DDR _D9
RPACK4-47
8D DR_D13
7D DR_D15
6DDR _D8
5D DR_D10
C153
0.1uF
0.1uF
C157
0.1uF
C151
4 DDR_DQM3
4 DDR_DQM2
4 DDR_DQS2
DDR_DQM3
DDR_DQM2
DDR_DQS2
DDR_DQS3
DDR_CLK
DDR_CLK_N
DDR_ CS
DD R_CAS
DD R_RAS
DDR_WE
DD R_CKE
4 DDR_DQS3
3
DDR_A4
DDR_A3
DDR_A2
DDR_A1
DDR_A0
DDR_A12
DDR_A11
DDR_A10
DDR_A9
DDR_A8
DDR_A7
DDR_A6
DDR_A5
R152
0
DDR_BS02
DDR_BS01
DDR_BS00
22 uF
+ C18
3
VSS.1
VSS.2
VSS.3
VSS.4
VSS.5
VSSQ.1
VSSQ.2
VSSQ.3
VSSQ.4
VSSQ.5
VSSQ.6
VSSQ.7
VSSQ.8
VSSQ.9
VSSQ.10
VSSDL
DQ3
DQ2
DQ1
DQ0
DQ7
DQ6
DQ5
DQ4
DQ11
DQ10
DQ9
DQ8
DQ15
DQ14
DQ13
DQ12
VREF
VDDL
VDD.1
VDD.2
VDD.3
VDD.4
VDD.5
VDDQ.1
VDDQ.2
VDDQ.3
VDDQ.4
VDDQ.5
VDDQ.6
VDDQ.7
VDDQ.8
VDDQ.9
VDDQ.10
MT47H64M16BT
UDM
LDM
UDQS#/NU
UDQS
LDQS#/NU
LDQS
CK
CK#
CS#
CAS#
RAS#
WE#
CKE
RFU.1
RFU.2
ODT
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
A4
A3
A2
A1
A0
BA2
BA1
BA0
A12
A11
A10
A9
A8
A7
A6
A5
U32
U9
T1
H3
D3
M3
G8
J8
D7
J2
E2
L8
L2
E8
H7
G2
M7
L3
L7
K2
K8
J9
J1
L9
L1
G3
G7
F2
F8
E9
E1
G9
G1
M2
M1
M9
H1
R9
D1
V1
F3
F7
K1
K3
K7
K9
D9
F1
F9
H9
BDDR_D19
BDDR_D18
BDDR_D17
BDDR_D16
BDDR_D23
BDDR_D22
BDDR_D21
BDDR_D20
BDDR_D27
BDDR_D26
BDDR_D25
BDDR_D24
BDDR_D31
BDDR_D30
BDDR_D29
BDDR_D28
VCC_1.8V
2
128 MEGABYTES
E3
J3
D8
E7
H8
J7
M8
N8
P8
P7
N7
N3
N2
V3
V7
N9
AA9
AA8
AA2
AA1
D2
V8
A9
A8
A2
A1
H2
T8
T2
R7
R3
R8
P1
P3
P2
V2
U7
R2
U3
U8
U2
T7
T3
2
C217
0.1uF
C221
0.1uF
0.1uF
C149
1
2
3
4
1
2
3
4
1
2
3
4
C220
0.1uF
C57
22 uF
DDR_D19
DDR_D17
DDR_D22
DDR_D20
RPACK4-47
8
7
6
5
8 DDR_D28
7 DDR_D30
6 DDR_D25
5 DDR_D27
RPACK4-47
RPACK4-47
8 DDR_D23
7 DDR_D18
6 DDR_D16
5 DDR_D21
+
R207
1K 1%
DWG NO
1
508162-0001
DDR2 MEMORY
Sheet
11 o f
35
Revision:
E
VREF_STL 4
R208
1K 1%
VCC_1.8V
C102
NO-POP
TMS320DM6446 EVALUATION MODULE
Date: Thursday, March 08, 2007
Size:B
Page Contents:
Title:
RN31
BDDR_D19
BDDR_D17
BDDR_D22
BDDR_D20
BDDR_D28
BDDR_D30
BDDR_D25
BDDR_D27
RN30
RN19
BDDR_D23
BDDR_D18
BDDR_D16
BDDR_D21
+
RPACK4-47
8 DDR_D26
7 DDR_D29
6 DDR_D24
5 DDR_D31
C218
0.1uF
C225
0.1uF
SPECTRUM DIGITAL INCORPORATED
C219
0.1uF
RN20
BDDR_D26 1
BDDR_D29 2
BDDR_D24 3
BDDR_D31 4
BDDR_D[16:31]
VREF_STL
C223
0.1uF
C222
0.1uF
1
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
5
10 NAND_CEz
R139
NO-POP
R140
10K
VCC_1.8V
15 NAND_BUSY
3,13,15,29 WRITE_WE
3,13,15,29 READ_OE
10 SRAM_CEz
3,13,15,29 CLE_EM_A2
3,13,15,29 ALE_EM_A1
3,13,15,29 ATA2_EM_A0
3,13,15,29 ATA1_EM_BA1
R137
10K
A5
WRITE_WE
E6
A1
A2
ALE_EM_A1
A4
B2
A6
B3
R113
NO-POP
R141
10K
VCC_1.8V
WRITE_WE
READ_OE
LOCKPRE
WP
WE
ALE
CLE
CE
RE
R/B
U6
R134
0
SRAM_CE2
B.EM_A19
B.EM_A18
B.EM_A17
B.EM_A16
B.EM_A15
B.EM_A14
B.EM_A13
B.EM_A12
B.EM_A11
B.EM_A10
R136
0
EM_A9
EM_A8
EM_A7
EM_A6
EM_A5
EM_A4
EM_A3
CLE_EM_A2
ALE_EM_A1
ATA2_EM_A0
ATA1_EM_BA1
CLE_EM_A2
READ_OE
R135
10K
VCC_1.8V
R138
10K
VCC_1.8V
3,13,14,29 EM_A[3:21]
13,14,29 B.EM_A[10:21]
4
B2
A1
G5
A2
B5
A6
H6
G2
H1
D3
E4
F4
F3
G4
G3
H5
H4
H3
H2
D4
C4
C3
B4
B3
A5
A4
A3
UB
LB
WE
OE
CS1
CS2
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
VCC_1.8V
D6
E1
VCC.1
VCC.2
VSS.1
VSS.2
D1
E6
U7
4
SAMSUNG K9K1208/Q/D/U/0C
A3
H1
H6
G6
H5
G5
H4
H3
H2
G2
F2
C93
.1uF
3
2
2
NAND FLASH ( 64MBytes )
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
C92
.1uF
VCC_1.8V
K9K1G08 supports 128 MEGABYTES
VSS.1
VSS.2
VSS.3
I/O07
I/O06
I/O05
I/O04
I/O03
I/O02
I/O01
I/O00
VCC.1
VCC.2
F6
G4
SAMSUNG->K1S3216BCD
E3
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
B1
C1
C2
D2
E2
F2
F1
G1
C91
0.1uF
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
C90
0.1uF
B6
C5
C6
D5
E5
F5
F6
G6
3
SRAM ( 4MBytes )
NC.1
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
NC.12
NC.13
NC.14
NC.15
NC.16
NC.17
NC.18
NC.19
NC.20
NC.21
NC.22
NC.23
NC.24
NC.25
NC.26
NC.27
B1
B4
B5
B6
C1
C2
C3
C4
C5
C6
D1
D2
D3
D4
D5
D6
E1
E2
E3
E4
E5
F1
F3
F4
F5
G1
G3
5
DWG NO
1
508162-0001
SRAM/NAND FLASH
Sheet
12 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
EM_D[0:15] 3,13,14,29
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-13
A-14
A
B
C
D
3,12,14,29 EM_A[3:21]
10 FLASH_CEz
3,12,15,29 READ_OE
3,12,15,29 WRITE_WE
12,14,29 B.EM_A[10:21]
5
R116
NO-POP
R114
10K
VCC_1.8V
8,15,26,29,30,31,34 1.8V.SYS_RESETz
5
R115
10K
VCC_1.8V
R142
10K
VCC_1.8V
4
3,12,15,29 ATA1_EM_BA1
3,12,15,29 ATA2_EM_A0
3,12,15,29 ALE_EM_A1
3,12,15,29 CLE_EM_A2
4
EM_A3
EM_A4
EM_A5
EM_A6
EM_A7
EM_A8
EM_A9
WP/ACC
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
B6
F6
E6
C6
D4
B4
F8
EM_WPn
NC1
NC2
NC3
NC4
NC5
VSS2
VSS1
VCC
VIO
RY/BY
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
VSS.1
VSS.2
VSS.3
VSS.4
VCC.1
VCC.2
VCCQ.1
VCCQ.2
VCCQ.3
VPP
WAIT
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
27
28
30
55
56
52
33
43
29
17
35
37
39
41
44
46
48
50
36
38
40
42
45
47
49
51
3
RFU.1
RFU.2
ADV
RFU.3
RFU.4
RFU.5
PC28F128P30T85
CLK
WPn
RSTn
WE
CE
OE
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
NC/A24
NC/A25
UX13
16 MBytes
G8
1.8V.SYS_RESETz
3
NO-POP/AM29LV256M
RESET
CE
OE
WE
BYTE
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
WRITE_WE
16
14
32
34
13
53
31
26
25
24
23
22
21
20
10
9
8
7
6
5
4
3
54
19
18
11
12
15
2
1
FLASH_CEz
READ_OE
ATA1_EM_BA1
ATA2_EM_A0
ALE_EM_A1
CLE_EM_A2
EM_A3
EM_A4
EM_A5
EM_A6
EM_A7
EM_A8
EM_A9
B.EM_A10
B.EM_A11
B.EM_A12
B.EM_A13
B.EM_A14
B.EM_A15
B.EM_A16
B.EM_A17
B.EM_A18
B.EM_A19
B.EM_A20
B.EM_A21
EM_WPn
1.8V.SYS_RESETz
FLASH_CEz
READ_OE
WRITE_WE
B.EM_A10
B.EM_A11
B.EM_A12
B.EM_A13
B.EM_A14
B.EM_A15
B.EM_A16
B.EM_A17
B.EM_A18
B.EM_A19
B.EM_A20
B.EM_A21
ATA1_EM_BA1
ATA2_EM_A0
ALE_EM_A1
CLE_EM_A2
U13
F1
H1
G2
B8
E8
B2
H4
H2
H6
H3
A6
D5
G4
D6
A4
F7
F2
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
F4
F5
H5
G7
E7
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
EM_D0
EM_D1
EM_D2
EM_D3
EM_D4
EM_D5
EM_D6
EM_D7
EM_D8
EM_D9
EM_D10
EM_D11
EM_D12
EM_D13
EM_D14
EM_D15
C166
.1uF
C173
.1uF
VCC_1.8V
2
C165
.1uF
2
C172
.1uF
C94
.1 uF
VCC_3.3V
C120
.1uF
VCC_1.8V
R143
10K
VCC_1.8V
EM_D[0:15] 3,12,14,29
DWG NO
1
508162-0001
NOR FLASH
Sheet
13 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
5
4
28 VLYNQ_ONz
3,12,13,29 EM_A[3:21]
5
15 1V8.EM_DATA_BUF_DIR
15 1V8.EM_DATA_BUF_EN
3,12,13,29 EM_D[0:15]
VCC_3.3V
32
32
32
32
EM_A21
EM_A19
EM_A17
EM_A15
EM_A20
EM_A18
EM_A16
EM_A14
EM_A13
EM_A12
EM_A11
EM_A10
R144
L
A TO B1
NC.1
NC.2
NC.3
NC.4
NC.5
NC.6
NC.7
NC.8
NC.9
NC.10
NC.11
NC.12
NC.13
NC.14
1A
2A
3A
4A
5A
6A
7A
8A
9A
10A
11A
12A
S
4
24
25
1
48
13
14
16
17
19
20
22
23
EM_D7
EM_D6
EM_D5
EM_D4
EM_D3
EM_D2
EM_D1
EM_D0
7
18
2
3
5
6
8
9
11
12
C106
0.1uF
VCC_1.8V
VLYNQ_RXD0
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD3
GND
GND
GND
GND
GND
GND
GND
GND
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
VCCA
VCCA
U8
4
10
15
21
45
39
34
28
36
35
33
32
30
29
27
26
47
46
44
43
41
40
38
37
42
31
1B2
2B2
3B2
4B2
5B2
6B2
7B2
8B2
9B2
10B2
11B2
12B2
1B1
2B1
3B1
4B1
5B1
6B1
7B1
8B1
9B1
10B1
11B1
12B1
U11
SN74AVCB164245VR
2DIR
2OEn
1DIR
1OEn
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
VCCB
VCCB
SN74CBTLV16292DGGR
3
5
7
10
12
14
16
20
22
24
26
28
55
56
2
4
6
9
11
13
15
18
21
23
25
27
1
EM_D15
EM_D14
EM_D13
EM_D12
EM_D11
EM_D10
EM_D9
EM_D8
C89
0.1uF
VLYNQ_RXD0
VLYNQ_RXD1
VLYNQ_RXD2
VLYNQ_RXD3
10K
17
VCC.1
GND.1
GND.2
GND.3
GND.4
8
19
38
49
U11 is a switch used to enable Vlynq functions.
Signal levels are at 1.8 Volt logic levels on both
sides of switch
BUS
B->A
B<-A
3
C105
0.1uF
3V3.EM_D7
3V3.EM_D6
3V3.EM_D5
3V3.EM_D4
3V3.EM_D3
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
DIR
L
H
3
C373
560pF
C88
0.1uF
B.EM_A21
B.EM_A19
B.EM_A17
B.EM_A15
B.EM_A20
B.EM_A18
B.EM_A16
B.EM_A14
B.EM_A13
B.EM_A12
B.EM_A11
B.EM_A10
B.VLNQ_TXD0
B.VLNQ_TXD1
B.VLNQ_TXD2
B.VLNQ_TXD3
3V3.EM_D15
3V3.EM_D14
3V3.EM_D13
3V3.EM_D12
3V3.EM_D11
3V3.EM_D10
3V3.EM_D9
3V3.EM_D8
VCC_3.3V
53
51
48
46
44
42
40
37
35
33
31
29
54
52
50
47
45
43
41
39
36
34
32
30
C121
0.1uF
VCC_3.3V
NO-POP
C118
22
22
22
22
R416
R417
R418
R419
R392
NO-POP
22
22
22
22
R412
R413
R414
R415
3V3.EM_D[0:15] 17,18,19
C119
NO-POP
R393
NO-POP
C116
5.6pF
2
2
C117
5.6pF
DWG NO
1
508162-0001
EMIF LEVEL SHIFTER
Sheet
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
WLAN_INTR 32
SLP_CLK_EN 32
ELP_REQ/WAKEUP 32
PM_EN
32
32
32
32
32
B.EM_A[10:21] 12,13,29
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD3
Page Contents:
Title:
VLYNQ_TXD0
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD3
1
14 o f
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-15
A
B
C
D
8
TIMER_IN
VCC_1.8V
NO-POP
33
3,29 W AIT/BUSY
3,29 INTRQ_EM_RNW
6 1V8.MSP430_INT
R368
1
2
3
4
5
8
7
6
5
RPACK4-10K
RN24
8,13,26,29,30,31,34 1.8V.SYS_RESETz
31 TIMER_IN_DC3
ATA_DIR
R369
ISR_TDI
ISR_TCK
ISR_TDO
ISR_TMS
ISR_TMS
ISR_TDO
ISR_TCK
3,29 ATA0_EM_BA0
6
3,10 EM_CS2
3,29 ATA_CS1
3,29 ATA_CS0
3 UART_TXD1/DMACK
3 UART_RXD1/DMARQ
3,12,13,29 WRITE_WE
3,12,13,29 READ_OE
14 1V8.EM_DATA_BUF_DIR
14 1V8.EM_DATA_BUF_EN
12 NAND_BUSY
3,12,13,29 CLE_EM_A2
3,12,13,29 ALE_EM_A1
3,12,13,29 ATA2_EM_A0
3,12,13,29 ATA1_EM_BA1
C131
0.1uF
EPM240GTC100
TCK.B1
TMS.B1
TDI.B1
TDO.B1
B1.GCLK0
B1.GCLK1
B1.DEV_OE
B1.DEV_CLRn
B1.PIN38
B1.PIN39
B1.PIN40
B1.PIN41
B1.PIN42
B1.PIN47
B1.PIN48
B1.PIN49
B1.PIN50
B1.PIN51
B1.PIN28
B1.PIN29
B1.PIN30
B1.PIN33
B1.PIN34
B1.PIN35
B1.PIN36
B1.PIN37
B1.PIN16
B1.PIN17
B1.PIN18
B1.PIN19
B1.PIN20
B1.PIN21
B1.PIN26
B1.PIN27
B1.PIN2
B1.PIN3
B1.PIN4
B1.PIN5
B1.PIN6
B1.PIN7
B1.PIN8
B1.PIN15
2
4
6
8
10
4
SMT FEMALE HEADER 5X2
1
3
5
7
9
J17
24
22
23
25
12
14
43
44
38
39
40
41
42
47
48
49
50
51
28
29
30
33
34
35
36
37
16
17
18
19
20
21
26
27
2
3
4
5
6
7
8
15
C129
0.1uF
VCC_1.8V
CPLD REVISION 508163-0001B
ISR_TCK
ISR_TMS
ISR_TDI
ISR_TDO
DLOOP5
DLOOP4
DLOOP3
DLOOP2
DLOOP1
C128
0.1uF
45
31
9
B1.VCCIO1C
B1.VCCIO1B
B1.VCCIO1A
VCC_1.8V
63
13
VCCINT2
VCCINT1
4
B2.GCLK2
B2.GCLK3
B2.PIN92
B2.PIN95
B2.PIN96
B2.PIN97
B2.PIN98
B2.PIN99
B2.PIN100
B2.PIN1
B2.PIN84
B2.PIN85
B2.PIN86
B2.PIN87
B2.PIN88
B2.PIN89
B2.PIN90
B2.PIN91
B2.PIN74
B2.PIN75
B2.PIN76
B2.PIN77
B2.PIN78
B2.PIN81
B2.PIN82
B2.PIN83
B2.PIN66
B2.PIN67
B2.PIN68
B2.PIN69
B2.PIN70
B2.PIN71
B2.PIN72
B2.PIN73
19,28 3V3.CF_PWR_ON
3
U14
3V3.ATA_BUFF_DIR 18
3V3.ATA_BUFF_ENz 18
SPAREIO3 28
3V3.UART_RXD1 28,31
3V3.UART_TXD1 28,31
SPAREIO2 28
SPAREIO1 28
3V3.CF.INTRQ_EM_RNW 19
3V3.ATA.CS1 18
3V3.ATA.DA2 18
3V3.ATA.DMACK 18
3V3.ATA.DA1 18
3V3.ATA.DA0 18
3V3.ATA.DIOR 18
3V3.ATA.DIOW 18
3V3.ATA_RESETn 18
3V3.ATA.DMARQ 18
3V3.ATA.INTRQ_EM_RNW 18
3V3.ATA.WAIT/BUSY 18
3V3.ATA.CS0 18
62
64
R406
10K
VCC_3.3V
R43
10K
R3
10K
2
R191
10K
DWG NO
1
508162-0001
Sheet
15 o f
EMIF DATA BUS LEVEL SHIFTER
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size:B
MSP430_INT 28
1
SPECTRUM DIGITAL INCORPORATED
VCC_3.3V
Page Contents:
Title:
CPLD_TIMER_IN 5
3V3.SM.ALE_EM_A1 17
3V3.SM.CLE_EM_A2 17
3V3.SM.WRITE_WE 17
3V3.SM.READ_OE 17
3V3.SM.SM_CEz 17
3V3.SM.WAIT/BUSY 17
VCC_3.3V
0
0
VCC_1.8V
3V3.SYS_RESETz 22,24,28,31
BLM41P750SPT
L63
NO-POP
92
95
96
97
98
99
100
1
VCC_3.3V
R165
R192
C104
0.1uF
VCC_3.3V
3V3.CF.WAIT/BUSY 19
3V3.CF.WRITE_WE 19
3V3.CF.READ_OE 19
3V3.CF.ATA_CS0 19
3V3.CF.ATA_CS1 19
3V3.CF.ATA0_EM_BA0 19
3V3.CF.ATA1_EM_BA1 19
3V3.CF.ATA2_EM_A0 19
C109
0.1uF
C126
0.1uF
L62
2
84
85
86
87
88
89
90
91
74
75
76
77
78
81
82
83
66
67
68
69
70
71
72
73
52
53
54
55
56
57
58
61
C108
0.1uF
B2.PIN52
B2.PIN53
B2.PIN54
B2.PIN55
B2.PIN56
B2.PIN57
B2.PIN58
B2.PIN61
C107
0.1uF
3
28 3V3.SM_CEz
28 CFn_SEL
28 ATA_SEL
VCC_3.3V
94
80
59
GNDIO6
GNDIO5
GNDIO4
GNDIO3
GNDIO2
GNDIO1
93
79
60
46
32
10
B2.VCCIO1C
B2.VCCIO1B
B2.VCCIO1A
GNDINTB
GNDINTA
A-16
65
11
5
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
5
7,31,32 SD_DATA0
7,31,32 SD_DATA1
7,31,32 SD_CLK
7,31,32 SD_DATA2
7,31,32 SD_DATA3
7,31,32 SD_CMD
2
U5
R124
51K
R127
0.1uF
C95
R122
51K
0
WHEN USING DAT3 CARD DETECTION
PULL DOWN IS POPULATED WITH 470K OHM
RESISTOR AND PULL UP IN NOT POPULATED
R123
51K
4
VCC_3.3V
SN74LVC1G125
SELECTS TERMINATION FOR SD/MMC/MS
HEADER 3
SD CARD
1
2
3
MMC CARD
1-2
VCC_3.3V
MEMORY STICK PRO
1-2
J5
MEMORY STICK
2-3
5
3
1
J5 TERMINATION
4
R119
NO-POP
R120
51K
R125
NO-POP
R126
51K
VCC_3.3V
R118
NO-POP
R117
51K
3
R73
51K
VCC_3.3V
SD_DATA0
SD_DATA1
SD_CLK
SD_DATA2
SD_DATA3
SD_CMD
10uF
+ C10
VCC_3.3V
.1uF
C78
MS.DATA1
MS.DATA0
MS.DATA2
MS.DATA3
MS.CLK
9
1
2
3
4
5
6
7
8
SD.DAT2
SD.DAT3
SD.CMD
SD.VSS1
SD.VDD
SD.CLK
SD.VSS2
SD.DAT0
SD.DAT1
2
R99
0
MS.VSS2
MS.VCC
MS.SCLK
MS.DATA3
MS.XINS
MS.DATA2
MS.SDIO/DATA0
MS.DATA1
MS.BS
MS.VSS1
J3
SCDB2A101
2
WP
20
1-2
3
COM
22
4
23
GND.1
INS
21
5
MS.INS
SD/MMC.WP 28
SD/MMC.INS 28
MS.DATA2
MS.DATA0
MS.DATA1
MS.CMD.BS
MS.CLK
MS.DATA3
28
W ednesday, March 14, 2007
Date:
1
508162-0001
DWG NO
Size:B
Sheet
SD/MMC/MS CONNECTOR
16 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
R108
51K
VCC_3.3V
Page Contents:
Title:
19
18
17
16
15
14
13
12
11
10
R121
100K
VCC_3.3V
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-17
A
B
C
D
5
15 3V3.SM.WAIT/BUSY
15 3V3.SM.READ_OE
15 3V3.SM.SM_CEz
15 3V3.SM.CLE_EM_A2
15 3V3.SM.ALE_EM_A1
15 3V3.SM.WRITE_WE
14,18,19 3V3.EM_D[0:15]
4
3V3.WAIT/BUSY
3V3.READ_OE
3V3.SM_CEz
3V3.CLE_EM_A2
3V3.ALE_EM_A1
3V3.WRITE_WE
3V3.EM_D0
3V3.EM_D1
3V3.EM_D2
3V3.EM_D3
3V3.EM_D4
3V3.EM_D5
3V3.EM_D6
3V3.EM_D7
RN23
RN22
SMC6
SMC7
SMC8
SMC9
SMC13
SMC14
SMC15
SMC16
100K
R106
10K
SMC2
SMC3
SMC4
SM.xD.WP SMC5
SMC19
SMC20
SMC21
SMC11
SMC18
R77
NO-POP
100K
1
2
3
4
8
7
6
5
4
3
2
1
5
6
7
8
SM.CLE
SM.ALE
SM.WE
SM.WP
SM.R/B
SM.RE
SM.CE
SM.CD
SM.OPTION
SM.I/O1
SM.I/O2
SM.I/O3
SM.I/O4
SM.I/O5
SM.I/O6
SM.I/O7
SM.I/O8
J15
VCC_3.3V
+
SMC17
4
SMC12
SMC22
SM.LVD
SMCWP2
SMCWP1
SMC1
SMC10
SM.26
SM.25
SM.VSS1
SM.VSS2
SM.VCC1
SM.VCC2
SM.SENS.1
SM.SENS.2
A-18
SMCSW1
SMCSW2
5
3
3
xD.VCC1
xD.VCC2
xD.CD
xD.R/B
xD.RE
xD.CE
xD.CLE
xD.ALE
xD.WE
xD.WP
xD.VSS1
xD.I/O0
xD.I/O1
xD.I/O2
xD.I/O3
xD.I/O4
xD.I/O5
xD.I/O6
xD.I/O7
xD.VSS2
R78
10K
VCC_3.3V
R107
10K
VCC_3.3V
3V3.EM_D0
3V3.EM_D1
3V3.EM_D2
3V3.EM_D3
3V3.EM_D4
3V3.EM_D5
3V3.EM_D6
3V3.EM_D7
28
SM.xD.WP 28
SM.CD
2
R76
10K
VCC_3.3V
3V3.W AIT/BUSY
3V3.READ_OE
3V3.SM_CEz
3V3.CLE_EM_A2
3V3.ALE_EM_A1
3V3.WRITE_WE
SM.xD.WP
Chant Sincere SM/xD Connector
XD18
XD20
XD1
XD2
XD3
XD4
XD5
XD6
XD7
XD8
XD9
XD10
XD11
XD12
XD13
XD14
XD15
XD16
XD17
XD19
VCC_3.3V
SM/xD_CONNECTOR
C9
10uF
2
28
DWG NO
1
508162-0001
SM/xD CONNECTOR
Sheet
17 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
xD.CD
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
C86
.1uF
5
15 3V3.ATA_BUFF_ENz
VCC_3.3V
28
34
39
45
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
7
18
GND
GND
GND
GND
1OE
1DIR
2OE
2DIR
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
Vcc
Vcc
4
10
15
21
48
1
25
24
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
42
31
15 3V3.ATA.CS0
15 3V3.ATA.CS1
15 3V3.ATA.DIOR
15 3V3.ATA.DIOW
4
ATA.CS0
ATA.CS1
ATA.DIOR
ATA.DIOW
ATA.DA0
ATA.DA1
ATA.DA2
ATA.DMACK
DIR
L
H
BUS
B->A
B<-A
ATA.DD15
ATA.DD14
ATA.DD13
ATA.DD12
ATA.DD11
ATA.DD10
ATA.DD9
ATA.DD8
ATA.DD7
ATA.DD6
ATA.DD5
ATA.DD4
ATA.DD3
ATA.DD2
ATA.DD1
ATA.DD0
C103
.1uF
C87
.1uF
VCC_3.3V
ATA_RESETn
4
SN74LVT16245B/SN74CB3Q16245
GND
GND
GND
GND
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
Vcc
Vcc
U9
15 3V3.ATA.DA0
15 3V3.ATA.DA1
15 3V3.ATA.DA2
15 3V3.ATA.DMACK
3V3.EM_D15
3V3.EM_D14
3V3.EM_D13
3V3.EM_D12
3V3.EM_D11
3V3.EM_D10
3V3.EM_D9
3V3.EM_D8
3V3.EM_D7
3V3.EM_D6
3V3.EM_D5
3V3.EM_D4
3V3.EM_D3
3V3.EM_D2
3V3.EM_D1
3V3.EM_D0
C101
.1uF
15 3V3.ATA_RESETn
15 3V3.ATA_BUFF_DIR
14,17,19 3V3.EM_D[0:15]
5
LED,GRN
DS10
R223
2K
VCC_3.3V
1
2
3
4
5
6
7
8
3
ATA.DMARQ
ATA.DIOW
ATA.DIOR
ATA.I ORDY
ATA.DMACK
ATA.INTRQ
ATA.DA1
ATA.DA0
ATA.CS0
ATA_DASPn
RN4
22
33
33
33
R46
R48
R58
R57
ATA.INTRQ
ATA.IORDY
ATA.DMARQ
VCC_5V
22
22
R47
R45
33
R153
R154
10K
VCC_5V
R157
R155
1K
R150
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
82
82
82
HEADER 22X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
JP1
ATA.DD[0:15]
R148
5.6K
VCC_5V
RPACK8-33
16
15
14
13
12
11
10
9
R156
R158
20K
VCC_3.3V
ATA_RESETn
ATA.DD7
ATA.DD6
ATA.DD5
ATA.DD4
ATA.DD3
ATA.DD2
ATA.DD1
ATA.DD0
R112
10K
3
RN1
2
3V3.ATA.INTRQ_EM_RNW 15
3V3.ATA.WAIT/BUSY 15
33
33
TP33
TEST POINT
R44
0
1
R401
NO-POP
1
1
TP34
TEST POINT
Z9
Z8
DWG NO
1
508162-0001
ATA INTERFACE
Sheet
18 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
1
Z7
1
1
Z6
MOUNTING HOLES
1
VCC_3.3V
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
ATA.DA2
ATA.CS1
RPACK8-33
ATA.DD8
16
ATA.DD9
15
ATA.DD10
14
ATA.DD11
13
ATA.DD12
12
ATA.DD13
11
ATA.DD14
10
ATA.DD15
9
ATA_CSEL
1
2
3
4
5
6
7
8
3V3.ATA.DMARQ 15
NC
R55
R56
IOCS16
KEY
2
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-19
A-20
A
B
C
D
5
5
15,28 3V3.CF_PWR_ON
6
5
4
15 3V3.CF.ATA_CS1
15 3V3.CF.ATA_CS0
15 3V3.CF.READ_OE
15 3V3.CF.WRITE_WE
28 3V3.CF_RESETz
R2
VOUT
VOUT
VCC_3.3V
FDC6331L
R1/C1
ON/OFF
VIN
U10
R111 NO-POP
15 3V3.CF.INTRQ_EM_RNW
15 3V3.CF.WAIT/BUSY
R109
100K
VCC_3.3V
1
2
3
R23
10K
4
R22
1K
R110
2K
4
R25
10K
R26
20K
20K
R21
15 3V3.CF.ATA0_EM_BA0
15 3V3.CF.ATA1_EM_BA1
15 3V3.CF.ATA2_EM_A0
+
CF_ A0
CF_ A1
CF_ A2
R400
NO-POP
VCC_3.3V
C16
10uF
3
C15
.1uF
3
R24
0
R27
0
C17
.1uF
1
50
43
41
37
42
24
39
7
32
9
36
34
35
44
20
19
18
17
16
15
14
12
11
10
8
38
13
BVD2
BVD1
VS1
VS2
CD1
CD2
D00
D01
D02
D03
D04
D05
D06
D07
D08
D09
D10
D11
D12
D13
D14
D15
45
46
33
40
26
25
21
22
23
2
3
4
5
6
47
48
49
27
28
29
30
31
Compact Flash Connector
GND
GND
INPACK#
RESET
RDY/BSY
WAIT
WP
CSEL
CE1
CE2
OE
WE
IORD
IOWR
REG
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
VCC
VCC
P1
2
R28
100K
VCC_3.3V
3V3.EM_D0
3V3.EM_D1
3V3.EM_D2
3V3.EM_D3
3V3.EM_D4
3V3.EM_D5
3V3.EM_D6
3V3.EM_D7
3V3.EM_D8
3V3.EM_D9
3V3.EM_D10
3V3.EM_D11
3V3.EM_D12
3V3.EM_D13
3V3.EM_D14
3V3.EM_D15
2
R20
100K
DWG NO
1
508162-0001
Sheet
COMPACT FLASH CONNECTOR
19 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
3V3.CF_CD1 28
3V3.CF_CD2 28
3V3.EM_D[0:15] 14,17,18
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
6 UART_RXD0
6 UART_TXD0
5
UART_RXD0
UART_TXD0
.1uF
C243
.1uF
C245
VCC_1.8V
VCC_1.8V
2
4
6
2
4
6
A1
VCCA
U43
DIR
A1
B-->A
A-->B
H
FUNCTION
L
DIR
GND1
DIR
SN74AVC1T45
B1
VCCB
U42
VCCA
SN74AVC1T45
GND1
B1
VCCB
4
5
3
1
5
3
1
C246
.1uF
C244
.1uF
VCC_3.3V
3V3.UART_TXD0
3V3.UART_RXD0
VCC_3.3V
VCC_3.3V
10
R357
R356
+
3
+
+
C299
1uF
C301
.1uF
C302
1uF
0
U64
V+
C1-
C1+
ENABLE
ROUT
INVALID
DIN
47uF
C77
3
4
2
1
9
10
11
V-
C2-
C2+
RIN
FORCEON
FORCEOFF
DOUT
MAX3221
VCC
15
3
GND
14
7
6
5
8
12
16
13
+
2
C296
1uF
C298
1uF
R355
10K
R354
10K
VCC_3.3V VCC_3.3V
2
1
6
2
7
3
8
4
9
5
2
DSUB9-Male
BLM21PG221SN1D
2
BLM21PG221SN1D
L55
DWG NO
1
508162-0001
RS232 INTERFACE
Sheet
20 o f
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
1
1
L54
S_A_TXD
S_A_RXD
P6
SPECTRUM DIGITAL INCORPORATED
10pF
10pF
Title:
C295
C294
S_A_RXD
10pF
L47
C297
10pF
1uH
1uH
C300
L46
1
11
10
4
+
5
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-21
A
B
C
22,31
GIOV33_16
28 USB.DRVVBUSz
1
5
1
TP72 TP71
1K
R379
2
1
R430
10K
5
3
4
C374
0.1uF
USB_ID
4
C351
.1uF
R166
C133
100uF
USB_DM
USB_DP
10K
U59
SN74AHC1G08
R377
100K
VCC_5V
4
For Peripheral or OTG the
Capacitancer should be 4.7 uF
so remove R132 thus C69 provides capacitance
For host mode Capacitor Minimum Capacitance
is 100uF, this design uses 104.7uF
both C133 and C69 installed.
7
7 USB_VBUS
7 USB_DM
7
USB_DP
2
1
R378
1K
VCC_5V
U15
SN74LVC1G07
VCC_3.3V VCC_3.3V
5
3
D
4
+
R132
C69
4.7uF
1uF
C197
G
Q2
0
D
S
+
100nF
C293
IRLML6401
D6
R133
1
1
C350
.1uF
TP59
3
HEADER 3
J7
TP60
NO-POP
0
VCC_5V
1
2
3
1
1
2
BLM21PG221SN1D
2
BLM21PG221SN1D
L53
L52
R337
1.5K
TP74
1
Selects Termination
for Host/Client
configurations
VCC_3.3V
22,31 GIOV33_15
3
TP76
1
R427
NO-POP
Q3
NO-POP
R428
NO-POP
TP75
1
TP71-TP74
R425-R429
Q3
TP73
1
2
2
NO-POP
R429
SHIELD2
SHIELD1
2
1
GND
DD+
SHIELD4
SHIELD3
VBUS-A
J10C
MINI A-B CONNECTOR
4
3
1
508162-0001
USB 2.0 INTERFACE
Sheet
21 o f
35
Revision:
E
USB_SHIELD
USB_SHIELD
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
FULL SIZE A CONNECTOR
DWG NO
USB_SHIELD
USB_SHIELD
USB-miniAB/A/B connector
USB-miniAB/A/B connector
4A
2A
3A
1A
GND
ID
D+
D-
VBUS
J10A
FULL SIZE B CONNECTOR
GND
DD+
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
USB_SHIELD
5AB
4AB
3AB
2AB
1AB
J10B
ATTACH
USB-miniAB/A/B connector
4B
2B
3B
1B
THESE FOOTPRINTS ARE OVERLAYED
ONLY 1 OF 3 IS POPULATED AT 1 TIME
1
SHIELD5
SHIELD6
SHIELD7
SHIELD8
A-22
5
6
7
8
5
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
C262
.1uF
C247
.1uF
5
TP58
MDINT
1
2
3
4
5
6
7
8
VCC_3.3V
TDI
TDO
TMS
TCK
TRST#
RX_DV
RX_ER
MDDIS
MDC
MDIO
MDINT#
RESET#
TxSLEW0
TxSLEW1
PAUSE
SLEEP
COL
CRS
RX_CLK
RXD0
RXD1
RXD2
RXD3
TX_EN
TX_ER
TX_CLK
TXD0
TXD1
TXD2
TXD3
22
22
LXT971ALE
REFCLK/XI
XO
SD/TP#
VCCA
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
GND
TEST0
TEST1
PWRDWN
RBIAS
LED/CFG3
LED/CFG2
LED/CFG1
N/C1
N/C2
N/C3
TPFIP
TPFIN
TPFOP
TPFON
1
2
26
22
12
13
14
15
16
25
34
35
39
17
36
37
38
9
10
44
23
24
19
20
AVCC3.3
4
0
0
RPACK8-33
16
15
14
13
12
11
10
9
EIA0402
EIA0402
4
3V3.SYS_RESETz 15,24,28,31
Place terminations
close to PHY source
pins.
R262
R261
RN34
R274
R257
27
28
29
30
31
49
53
3
43
42
64
4
5
6
33
32
MII_RXDV
MII_RXER
XSPCLK_MDCLK
XSPDO_MDIO
MDINT_TP
SYS_RSTz
TXSLEW0
TXSLEW1
PAUSE
SLEEP
62
63
52
48
47
46
45
56
54
MTXEN
R280
1.5k
MII_COL
MII_CRS
MII_RCLK
MII_RXD0
MII_RXD1
MII_RDX2
MII_RXD3
55
57
58
59
60
U58
MII_TXCLK
MTXD0
MTXD1
MTXD2
MTXD3
C258
.1uF
BLM41P750SPT
51
VCCD
L32
21
VCCA
AVCC3.3
8
40
VCCIO1
VCCIO2
GND1
GND2
GND3
GND4
GND5
GND6
7
11
18
41
50
61
R284
0
R287
10k
LXT_RDP_c
LXT_RDM_c
PWRDWN
R276
100
COLLISION/
DUPLEX
STATUS
R289
RBIAS
C261
.1uF
Y6
25MHz
C264
10pF
C248
10pF
VCC_3.3V
22.1k
R277
100
LINK/
ACTIVITY
LINKLED-
LED1-
R259
R288
49.9
3
MTXD0
MTXD1
MTXD2
MTXD3
MTXEN
360
35
34
33
31
30
29
28
27
26
25
46
45
44
43
42
40
39
38
37
36
1
U41
CBTLV16210DGGR
.1uF
C259
R358
49.9
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2B10
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
1B10
NC
.1uF
C303
LXT_RDM
C263
0.01uF
LXT_RDP
LXT_TDM
LXT_TDP
Route pairs together,
pairs are (3 and 6) and
(1 and 2).
AVCC3.3
270pF
C304
270pF
C260
R275
100
SPEED
3
LXT_TDCT
1
2
5
GND
GND
GND
GND
41
32
17
8
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
2A10
2OE
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
1A10
1OE
C257
0.01uF
13
14
16
18
19
20
21
22
23
24
360
2
GIOV33_13 6,31
GIOV33_12 6,31
GIOV33_10 6,31
GIOV33_9 6,31
GIOV33_8 6,31
GIOV33_7 6,31
GIOV33_11 6,31
GIOV33_14 6,31
GIOV33_2 6,31
GIOV33_1 6,31
R222
ENET_ENABLEz
47
GIOV33_3 6,31
GIOV33_4 6,31
GIOV33_5 6,31
GIOV33_6 6,31
GIOV33_0 6,31
GIOV33_15 6,31
GIOV33_16 6,31
ENET_ENABLEz
RXD+
RXD-CT
RXD-
TXD+
TXD-CT
TXD-
NC1
GND
LED2LED2+
LED1LED1+
RJ45 HALO HFJ11-2450E-L21
P2
2
3
4
5
6
7
9
10
11
12
48
.1uF
C226
3
5
6
1
4
2
7
8
12
11
10
9
2
VCC_3.3V
VCC_3.3V
L31
EXC-3BB102H
LED1-
LINKLED-
15
VCC
S1
S0
1
1
1
2
NO POP
10k
NO POP
10k
10k
10k
DWG NO
1
508162-0001
ETHERNET INTERFACE
Sheet
35
Revision:
E
VCC_3.3V
22 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
R260
R283
R286
R285
R278
R279
NO POP
10k
BLM21PG221SN1D
2
BLM21PG221SN1D
L57
L56
R281
R282
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
ENET_ENABLEz 31
R407
10K
TXSLEW0
TXSLEW1
SLEEP
PAUSE
PWRDWN
R258
NO-POP
VCC_3.3V
13
14
VCC_3.3V
A
B
C
D
Spectrum Digital, Inc
A-23
A-24
A
B
C
D
5
5
24 TVP5146VIDEO[0:7]
C68
0.1uF
R64
360
TVP5146VIDEO0
TVP5146VIDEO1
TVP5146VIDEO2
TVP5146VIDEO3
TVP5146VIDEO4
TVP5146VIDEO5
TVP5146VIDEO6
TVP5146VIDEO7
C67
0.1uF
VCC_3.3V
4
10
15
21
45
39
34
28
36
35
33
32
30
29
27
26
47
46
44
43
41
40
38
37
42
31
2DIR
2OEn
1DIR
1OEn
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
VCCB
VCCB
4
3
DIR
L
H
BUS
B->A
B<-A
3
SN74AVCB164245VR
GND
GND
GND
GND
GND
GND
GND
GND
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
VCCA
VCCA
U66
U66 is a tri-stateable logic translator used for DC4
to allow the TVP5146 to be disconnected
from on-board circuitry.Signal levels are at 1.8V logic
levels on B side and 3.3V on A sides of translator.
30 CAPTURE_EN
24 TVP5146PCLK
24 TVP5146VSYNC
24 TVP5146HSYNC
4
7
18
24
25
1
48
13
14
16
17
19
20
22
23
2
3
5
6
8
9
11
12
R264
10K
RN32
4
3
2
1
5
6
7
8
1
2
3
4
5
6
7
8
RN33
C61
0.1uF
R231
0
VCC_1.8V
RPACK4-33
C62
0.1uF
RPACK8-33
B. YI0
16
B. YI1
15
B. YI2
14
B. YI3
13
B. YI4
12
B. YI5
11
B. YI6
10
B. YI7
9
VCC_1.8V
R226
Y I0
Y I1
Y I2
Y I3
Y I4
Y I5
Y I6
Y I7
0
PCLK
VD
HD
YI0
YI1
YI2
YI3
YI4
YI5
YI6
YI7
2
2
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
5,30
DWG NO
1
508162-0001
Sheet
TVP5146 LEVEL SHIFTER
23 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
1.8V_DC3_PCLK 31
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
VCC_1.8V
VCC_1.8V
DDEC_GND
1
1
L23
1
L37
RCA JACK
J12
1.8VA_DDEC
5
2
BLM41P750SPT
1.8VD_DDEC
C332
330pF
1
L28
1
L38
C286
0.1uF
C334
0.1uF
C333
3.3VA_DDEC
DDEC_GND
75
R374 .1uF
DDEC_GND
2
BLM41P750SPT
3.3VD_DDEC
C250
2K
R329
NO POP
R328
3.3VD_DDEC
.1uF
C328
DDEC_GND
C335
0.1uF
DDEC_GND
DDEC_GND
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
DDEC_GND
0.1uF
DDEC_GND
C330
0.1uF
DDEC_GND
0.1uF
C347
C345
DDEC_GND
0.1uF
C348
6,27,28 3V3.I2C_CLK
6,27,28 3V3.I2C_DATA
15,22,28,31 3V3.SYS_RESETz
C343
4
0.1uF
C288
DDEC_GND
0.1uF
C291
0.1uF
.1uF
R376
75
C339
.1uF
R375
75
2
BLM41P750SPT
330pF
0.1uF
C336
.1uF
C289
DDEC_GND
DDEC_GND
C342
330pF
2.7uH
C338
DDEC_GND
2.7uH
DDEC_GND
VCC_3.3V
L40
0.1uF
C284
C344
680pF
DDEC_GND
VCC_3.3V
C325
680pF
L44 2.7uH
DDEC_GND
2
BLM41P750SPT
DDEC_GND
C326
330pF
L43 2.7uH
DDEC_GND
680pF
330pF
L41
C340
2.7uH
DDEC_GND
330pF
2.7uH
0.1uF
C341
1.8VA_DDEC
C368
L39
0.1uF
C285
C367
L42
DDEC_GND
DDEC_GND
2
1
6
4
3
5
749181-1
0.1uF
0.1uF
LUMA
J11
C287
C290
3.3VD_DDEC
DDEC_GND
0.1uF
C283
0.1uF
0.1uF
0.1uF
0.1uF
1.8VD_DDEC
C346
C337
C327
C329
3.3VA_DDEC
DDEC_GND
0.1uF
C331
81
23
18
17
16
9
8
7
2
1
80
28
29
34
33
35
THERMAL
VI_4_A
VI_3_C
VI_3_B
VI_3_A
VI_2_C
VI_2_B
VI_2_A
VI_1_C
VI_1_B
VI_1_A
SCL
SDA
RESETB
PWRDWN
FSS/GPIO
U51
TVP5146
XTAL2
XTAL1
INTREQ
DATACLK
AVID/GPIO
GLCO/12CA
FID/GPIO
VS/VBLK/GPIO
HS/CS/GPIO
C9
C8
C7
C6
C5
C4
C3
C2
C1
C0
Y9
Y8
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
12
3
DDEC_GND
75
74
30
100K
R336
R332
0
Y4
22
4.7K
1
508162-0001
Sheet
TVP5146 VIDEO DECODER
DWG NO
24 o f
35
Revision:
E
TVP5146PCLK 23
TVP5146VSYNC 23
TVP5146HSYNC 23
R333
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
TVP5146VIDEO[0:7] 23
3.3VD_DDEC
1
SPECTRUM DIGITAL INCORPORATED
33pF
Title:
C292
33pF
R266
TP56
C349
14.31818mhz
2.2K
1
36
40
1
37
TP57
22
R331
71
22
R335
1
R334
NO POP
2K
TP62
R327
4.7K
R265
3.3VD_DDEC
TVP5146VIDEO7
TVP5146VIDEO6
TVP5146VIDEO5
TVP5146VIDEO4
TVP5146VIDEO3
TVP5146VIDEO2
TVP5146VIDEO1
TVP5146VIDEO0
R330
RN35
RPACK8-33
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
72
2
2
73
57
58
59
60
63
64
65
66
69
70
43
44
45
46
47
50
51
52
53
54
3.3VD_DDEC
76
PLL_A18VDD
A18VDD_REF
3.3VA_DDEC 1.8VD_DDEC
11
14
25
78
CH2_A18VDD
CH3_A18VDD
CH4_A18VDD
CH1_A18VDD
1.8VA_DDEC
3
4
5
20
21
CH1_A33VDD
CH2_A33VDD
CH3_A33VDD
CH4_A33VDD
CH2_A18GND
CH3_A18GND
CH4_A18GND
CH1_A18GND
CH1_A33GND
CH2_A33GND
CH3_A33GND
CH4_A33GND
AGND
A18GND_REF
PLL_A18GND
4
31
41
55
67
DVDD1
DVDD2
DVDD3
DVDD4
10
15
24
79
3
6
19
22
26
13
77
2
38
48
61
IOVDD1
IOVDD2
IOVDD3
DGND1
DGND2
DGND3
DGND4
DGND5
IOGND1
IOGND2
IOGND3
27
32
42
56
68
39
49
62
5
A
B
C
D
Spectrum Digital, Inc
A-25
A
B
C
D
5 DAC_IOUTD
5 DAC_IOUTC
5 DAC_IOUTB
5 DAC_IOUTA
L12
5
R269
1K
R270
1K
R272
1K
12uH
27pF
C251
12uH
12uH
12uH
12uH
27pF
C253
R344
1K
R352
1K
DENC_GND
R348
1K
DENC_GND
1812LS-273XJB
L25
DENC_GND
27pF
C254
R340
1K
DENC_GND
1812LS-273XJB
L24
27pF
4
220uF
4
R353
267 1%
R349
267 1%
DAC_3V3
DENC_GND
DENC_GND
R343
4 -
3 +
DENC_GND
4 -
3 +
R351
4 -
3 +
DENC_GND
DENC_GND
C355
0.1uF
1
DENC_GND
C359
0.1uF
C358
0.1uF
VOUT_ON
10K
3
DAC_3V3
3
DENC_GND
R381 NO-POP
OPA357AIDBV
R380
1
DENC_GND
1130 1%
OPA357AIDBV
VOUT_ON
U47
1130 1%
OPA357AIDBV
VOUT_ON
1
DENC_GND
1130 1%
U49
C352
0.1uF
OPA357AIDBV
1
VOUT_ON
U50
1130 1%
U48
DENC_GND
R347
DAC_3V3
R345
267 1%
DENC_GND
4 -
3 +
DAC_3V3
R341
267 1%
DENC_GND
R339
DAC_3V3
DAC_3V3
+ C64
DENC_GND
BLM41P750SPT
DENC_GND
1812LS-273XJB
L26
C252
DENC_GND
1812LS-273XJB
L18
R271
1K
DENC_GND
12uH
1812LS-273XJB
L17
DENC_GND
12uH
L16
C255
0.01uF
1812LS-273XJB
L27
C256
0.1uF
DENC_GND
1812LS-273XJB
L19
DENC_GND
12uH
1812LS-273XJB
L20
DENC_GND
10uF
+ C63
3V3A_VOUT
DENC_GND
BLM41P750SPT
5
6
2
5
6
2
5
6
2
5
6
2
5
A-26
R346
R350
R342
75
6
DENC_GND
DENC_GND
2
2
1
J9
4
5
749181-1
3
75
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
75
75
R338
2
1uH
DENC_GND
10pF
C361
L34
DENC_GND
10pF
C363
L33
10pF
C362
DENC_GND
10pF
C360
DENC_GND
J8
DENC_GND
6
5
1
DWG NO
1
508162-0001
VIDEO OUTPUT
Sheet
25 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
DUAL RCA JACK
3
2
4
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
1uH
10pF
DENC_GND
10pF
DENC_GND
C356
C357
L35
10pF
DENC_GND
C353
DENC_GND
1uH
1uH
10pF
C354
L36
1
VCC_3.3V
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
1U
1L
5U
4U
R370
47K
2
5
1
3
4
6
C321
.1uF
R373
10K
R371
330
B_CLKR
B_FSX
B_FSR
B_DX
B_DR
7
7
7
7
7
5,31 AUDIO_CLK
B_CLKX
7
10
R315
R312
10
10
R317
10
10
R316
R320
10
R314
R372
330
C319
.1uF
VCC_1.8V
5.6K
5.6K
BLM21PG221SN1D
L45
R388
R385
8,13,15,29,30,31,34 1.8V.SYS_RESETz
C317
220pF
MIC_IN
P3
5L
4L
Dual-Stereo
LINE_IN
C249
.1uF
R387
5.6K
R386
5.6K
C279
.1uF
C366
220pF
R319
20K
R321
6,30,31 1V8.I2C_CLK
6,30,31 1V8.I2C_DATA
R318
10K
1
1
R323
C278
.1uF
TP63
TP64
.1uF
10K
NO-POP
NO-POP
10K
.1uF
C320
.1uF
C281
.1uF
C282
C280
.1uF
C323
C324 .1uF
C365
220pF
C322 .1uF
C70
10uF
R324
R326
R325
R322
+
0
R310
10
0
G8
G9
F9
E9
F8
E8
B8
B9
A8
A9
H8
A2
A1
B3
B2
A4
B5
B4
A3
A6
A5
B7
B6
H9
C9
D9
U52
1uF
C276
SCL
SDA
GPIO1
GPIO2
LEFT_LO+
LEFT_LORIGHT_LO+
RIGHT_LO-
MONO_LO+
MONO_LO-
HPLOUT
HPLCOM
DRVSS.1
DRVSS.2
HPRCOM
HPROUT
DRVDD.1
DRVDD.2
AVDD_ADC
AVSS_ADC.1
AVSS_ADC.2
AVDD_DAC
AVSS_DAC.1
AVSS_DAC.2
ISOLATE GROUNDS
AND CONNECT AT
SINGLE LOCATION
IN THE GROUND PLANE
TVL320AIC33IZQE
MCLK
BCLK
WCLK
DIN
DOUT
SELECT
MFP0
MFP1
MPF2
MFP3
RESET
MICBIAS
MIC3R
MIC3L
MICDET
LINE2L+
LINE2LLINE2R+
LINE2R-
LINE1L+
LINE1LLINE1R+
LINE1R-
DVDD
IOVDD
DVSS
.1uF
C277
VCC_1.8V
C8
D8
J9
J8
J4
J5
J6
J7
J2
J3
D1
E1
E2
F2
F1
G1
C1
H1
B1
C2
D2
J1
G2
H2
TP65
C73
C72
C315
.1uF
R311
20K
L49
10uF,6.3V
C76
L48
L51
L50
C316
.1uF
10uF,6.3V
C75
33uF,6.3V
33uF,6.3V
C314
.1uF
+
+
L29
+
+
1
BLM21PG221SN1D
C74
10uF
L30
C318
.1uF
R313
20K
TP69
R384
20K
.1uF
P4
3
2
P5
Headphone Out
3
1
2
4
DWG NO
508162-0001
Sheet
AIC33 AUDIO INTERFACE
26 o f
TMS320DM6446 EVALUATION MODULE
35
Revision:
E
DUAL RCA JACK
C275
SPECTRUM DIGITAL INCORPORATED
R382
20K
R367
20K
R383
20K
BEAD M2301
Date: Wednesday, March 14, 2007
Size: B
Page Contents:
Title:
BLM21PG221SN1D
BLM21PG221SN1D
BLM21PG221SN1D
BLM21PG221SN1D
+
VCC_3.3V
1
VCC_1.8V
Spectrum Digital, Inc
A-27
1
A
B
C
7,31
DX
6,24,28 3V3.I2C_DATA
6,24,28 3V3.I2C_CLK
5
30 1V8.DC_PCLK
C79
.1uF
16
15
14
13
12
11
10
9
VCC_3.3V
R362
100K
DIR
L
H
U2
U62
GND1
A2
A1
VCCA
1
2
3
4
5
6
7
8
FUNCTION
B-->A
A-->B
SN74AVC2T45
DIR
B2
B1
VCCB
VDD
A0
SDA
A1
SCL
A2
INT
P0
P7
P1
P6
P2
P5
P3
P4
GND
PCF8574A
5
6
7
8
4
3
2
1
4
R363
VCC_3.3V
LED
DS8
R65
330
VCC_3.3V
33
C307
.1uF
LED
DS7
R66
330
LED
DS6
3
R68
330
LED
DS5
SN74LVC1G125
R67
330
3V3.DC_PCLK 5
2
U61
4
R361
R364
4
VCC_3.3V
SN74LVC1G125
2
U63
5
3
1
LED
DS4
R69
330
0.1uF
C309
0
R360 220
LED
DS3
R70
330
0.1uF
C364
0.1uF
VCC_3.3V
0
C305
0.1uF
C306
LED
DS2
R71
330
3
2
1
2
U65
IN
VCC
GND
R359
100
1
J13RCA JACK
2
2
VCC_3.3V
5
3
1
C308
.1uF
VCC_1.8V
3
LED
DS1
R72
330
MP2
D
4
MP1
5
A-28
4
5
1
508162-0001
W ednesday, March 14, 2007
Date:
Sheet
27 o f
SPDIF OUTPUTS & USER LEDS
DWG NO
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
Title:
SPECTRUM DIGITAL INCORPORATED
USER CONTROLLED LEDS
TOTX141P
OPTICAL SPDIF OUT
SPDIF OUT
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
16 SD/MMC.WP
17 SM.xD.WP
5
C193
.1uF
VCC_3.3V
16
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
A0
A1
A2
P0
P1
P2
P3
GND
PCF8574A
VDD
SDA
SCL
INT
P7
P6
P5
P4
U35
A0
A1
A2
P0
P1
P2
P3
GND
U18
PCF8574A
VDD
SDA
SCL
INT
P7
P6
P5
P4
15,22,24,31 3V3.SYS_RESETz
VCC_3.3V
VCC_3.3V
6,24,27 3V3.I2C_DATA
6,24,27 3V3.I2C_CLK
10 USER_SW
15 SPAREIO3
15 SPAREIO2
15 SPAREIO1
6,24,27 3V3.I2C_DATA
6,24,27 3V3.I2C_CLK
C100
.1uF
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
4
0
PLL.CSEL
PLL.SR
PLL.FS1
PLL.FS2
R101
10K
5
5
5
5
VCC_3.3V
32.768KHz
R104
47K
MSP430_3V3
R105
100K
8
9
10
VCC_3.3V
VCC_3.3V
USB.DRVVBUSz 21
VDDIMX_EN 35
VLYNQ_ONz 14
3V3.CF_RESETz 19
R224
10K
NO-POP
R96
3
NO-POP
R97
Y1
5
6
7
11
12
13
14
15
16
17
18
R273
R102
NO-POP
L1
BLM41P750SPT
15 3V3.SM_CEz
17
SM.CD
17
xD.CD
15,19 3V3.CF_PWR_ON
16 SD/MMC.INS
16
MS.INS
C84
.1uF
VCC_3.3V
3
19
20
3
C83
.1uF
4
19 3V3.CF_CD1
19 3V3.CF_CD2
BA2032SM
BHT1
RN25
RPACK4-10K
1
2
D3
BAT17
D4
BAT17
5
8
7
6
5
1
2
3
4
P1.0/TACLK
P1.1/TA0
P1.2/TA1
+
XOUT
XIN
2
1
RST/NMI
P3.0/STE0/A5
P3.1/SIMO0
P3.2/SOMI0
P3.3/UCLK0
P3.4/UTXD0
P3.5/URXD0
P3.6/A6
P3.7/A7
430_TDO
28
4
0.1uF
C163
R422
10K
VCC_1.8V
U30
SN74LVC1G06
VCC_3.3V
3V3.UART_RXD1 15,31
2
CFn_SEL
2
15
ATA_SEL 15
R421
NO-POP
VCC_3.3V
MSP430F1232IPW
430_TEST/VPP
430_TDI
27
1
430_TMS
26
3V3.UART_TXD1 15,31
TEST
P1.7/TA2/TDO
P1.6/TA1/TDI
P1.5/TA0/TMS
430_TCK
0.1uF
C85
25
24
21
22
23
C13
10uF 6.3V
P2.3/CA0/TA1
P1.3/TA2
P2.4/CA1/TA2
P2.5/ROSC
P1.4/SMCLK/TCK
P2.0/ACLK
P2.1/INCLK
P2.2/CAOUT/TA0
U4
2
VCC
VSS
4
5
3
VCC_3.3V
430_TCK
430_TMS
430_TDI
430_TDO
1
13
11
9
7
5
3
1
0
0
MSP430_3V3
430_TEST/VPP
3V3.I2C_CLK 6,24,27
MSP430_INT 15
DWG NO
1
508162-0001
Sheet
MSP430 & IR INTERFACE
28 o f
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size:B
TSOP34840
U3
3V3.I2C_DATA 6,24,27
3
1
2
SPECTRUM DIGITAL INCORPORATED
14
12
10
8
6
4
2
C1
10uF 6.3V
HEADER 7X2
Page Contents:
Title:
J2
+
R75
100
NC1
TCLKEN
RST/NMI
ACLKEN
GND
ACLK
TCK
TEST/VPP
TMS
XOUT
TDI/VPP VCC_MSP
TDO/TDI
NC2
1V8.WLAN_RESETz 32
TP4
R98
R103
R74
10K
VCC_3.3V
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-29
A-30
A
B
C
D
5
3
EM_CS3
8,13,15,26,30,31,34 1.8V.SYS_RESETz
3,15 ATA_CS1
3,12,13,15 ATA1_EM_BA1
3,12,13,15 WRITE_WE
3,15 W AIT/BUSY
3,12,13,14 EM_D[0:15]
3,12,13,14 EM_A[3:21]
12,13,14 B.EM_A[10:21]
5
EM_D3
EM_D1
EM_D9
EM_D7
EM_D5
EM_D15
EM_D13
EM_D11
VCC_5V
4
VCC_3.3V
3,12,13,15 ALE_EM_A1
4
EM_A5
EM_A3
B.EM_A13
B.EM_A11
EM_A9
EM_A7
B.EM_A21
B.EM_A19
B.EM_A17
B.EM_A15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
DC1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
EMIF CONNECTOR
HEADER 35x2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
EM_A4
3
EM_D2
EM_D0
EM_D8
EM_D6
EM_D4
EM_D14
EM_D12
EM_D10
B.EM_A12
B.EM_A10
EM_A8
EM_A6
B.EM_A20
B.EM_A18
B.EM_A16
B.EM_A14
3
VCC_1.8V
VCC_3.3V
CLE_EM_A2 3,12,13,15
ATA2_EM_A0 3,12,13,15
2
DC_EM_CS2 10
CLKOUT0 8
ATA_CS0 3,15
ATA0_EM_BA0 3,15
READ_OE 3,12,13,15
INTRQ_EM_RNW 3,15
2
DWG NO
1
508162-0001
Sheet
EMIF EXPANSION CONNECTOR
29 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
5
27 1V8.DC_PCLK
5
COUT0
COUT2
COUT4
COUT6
5,10
5,10
5
5
YOUT0
YOUT2
YOUT4
YOUT6
6,26,31 1V8.I2C_CLK
6,26,31 1V8.I2C_DATA
5,10
5,10
5,10
5
VPBECLK
VID_CLK
VCLK
GIO0
GIO3
GIO6
5
5
5
CI0
CI2
CI4
CI6
PCLK
4
VCC_5V
VCC_3.3V
VCC_1.8V
R268
R267
VCC_5V
VCC_3.3V
VCC_1.8V
6,26,31 1V8.I2C_CLK
5
5
5
5
5,23
6
6
6
NO-POP
R225
YI0
YI2
YI4
YI6
PWM1
5
5,23
5,23
5,23
5,23
GIO1
6
8,13,15,26,29,31,34 1.8V.SYS_RESETz
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
HEADER 25X2
DC4
NO-POP
NO-POP
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
HEADER 25X2
DC5
3
VIDEO OUTPUT CONNECTOR
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
VIDEO INPUT CONNECTOR
3
VCC_3.3V
VCC_1.8V
VCC_5V
VCC_3.3V
VCC_1.8V
VCC_5V
5
5
5
5
5,23
5,23
5,23
5,23
5,23
5,23
5
6
2
1.8V.SYS_RESETz 8,13,15,26,29,31,34
5,10
5,10
5
5
5
YOUT1
YOUT3
YOUT5
YOUT7
5
VSYNC
5,10
5,10
5
5
6
6
6
HSYNC
COUT1
COUT3
COUT5
COUT7
GIO2
GIO5
GIO38
1V8.I2C_DATA 6,26,31
CI1
CI3
CI5
CI7
HD
VD
YI1
YI3
YI5
YI7
PWM2
GIO4
CAPTURE_EN 23
2
Date: Wednesday, March 14, 2007
1
508162-0001
Sheet
30 o f
VIDEO INPUT/OUTPUT CONNECTORS
DWG NO
Page Contents:
Size:B
TMS320DM6446 EVALUATION MODULE
Title:
SPECTRUM DIGITAL INCORPORATED
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-31
A-32
A
B
C
D
5
5
DR
CLKR
FSR
7
7
7
8,13,15,26,29,30,34 1.8V.SYS_RESETz
7 McBSP_EN
5,26 AUDIO_CLK
SPI_EN1
SPI_DI
SPI_CLK
6
6
6
22 ENET_ENABLEz
7,16,32 SD_CLK
VCC_5V
VCC_3.3V
R263
VCC_5V
VCC_3.3V
VCC_1.8V
4
7,16,32 SD_DATA0
7,16,32 SD_DATA2
6,22 GIOV33_12
6,22 GIOV33_14
6,22 GIOV33_16
6,22 GIOV33_6
6,22 GIOV33_8
6,22 GIOV33_10
6,22 GIOV33_0
6,22 GIOV33_2
6,22 GIOV33_4
4
NO-POP
DC2
DC6
HEADER 5X2
1
3
5
7
9
DC3
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
2
4
6
8
10
HEADER 15X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
HEADER 20X2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
7,27
7
7
VCC_1.8V
VCC_3.3V
1.8V_DC3_PCLK 23
1V8.I2C_CLK 6,26,30
1V8.I2C_DATA 6,26,30
DX
CLKX
FSX
SD_DATA1 7,16,32
SD_DATA3 7,16,32
3
3V3.UART_RXD1 15,28
3V3.UART_TXD1 15,28
3V3.SYS_RESETz 15,22,24,28
GIOV33_13 6,22
GIOV33_15 6,22
GIOV33_7 6,22
GIOV33_9 6,22
GIOV33_11 6,22
GIOV33_1 6,22
GIOV33_3 6,22
GIOV33_5 6,22
SPI_EN0 6
SPI_DO 6
TIMER_IN_DC3 15
VCC_5V
VCC_3.3V
SD_CMD 7,16,32
3
2
2
DWG NO
1
508162-0001
Sheet
31 o f
EMAC/GIO & McBSP/SPI & SD CONNECTORS
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
D
14 VLYNQ_TXD2
14 VLYNQ_TXD3
BLM41P750SPT
+
C5
33uF
L61
5
14 VLYNQ_RXD2
14 VLYNQ_RXD3
28 1V8.WLAN_RESETz
VCC_3.3V
0.1uF
0.1uF
0.1uF
C12
0.1uF
C11
0.1uF
0
R10
C7
NO-POP
R13
R6
VLYNQ_TXD2
NO-POP
NO-POP
VLYNQ_RXD2
VLYNQ_RXD3
R12
R11
NO-POP
NO-POP
Resistors are only populated for modules
requiring the upper VLYNQ data pairs
R7
VLYNQ_TXD3
Resistors are only populated for modules
requiring the upper VLYNQ data pairs
C6
C4
3 VLYNQ_SCRUN
7,16,31 SD_DATA0
4
4
20
26
25
29
30
34
48
56
61
64
66
65
68
67
72
71
86
73
59
45
96
99
94
95
92
91
90
87
85
84
81
80
79
78
75
76
60
57
58
53
54
51
52
47
46
41
44
39
42
35
38
33
11
13
12
14
INTA
RST
CLK
REQ
GNT
PME
IDSEL
PAR
IRDY
FRAME
TRDY
CLKRUN
STOP
SERR
DEVSEL
PERR
C/BE0
C/BE1
C/BE2
C/BE3
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
LED1_GRNP
LED1_GRNN
LED2_YELP
LED2_YELN
J16
89
88
63
40
31
28
19
70
EMC1
EMC2
EMC3
EMC4
INTB
RESERVED_A
RESERVED_B
RESERVED_C
RESERVED_E
RESERVED_F
RESERVED_G
RESERVED_H
RESERVED_I
RESERVED_J
RESERVED_K
8PMJ-3
8PMJ-1
8PMJ-6
8PMJ-2
8PMJ-7
8PMJ-4
8PMJ-8
8PMJ-5
TIP
RING
AC_SYNC
M66EN
AC_SDATA_IN
AC_SDATA_OUT
AC_BIT_CLK
AC_CODEC_ID0#
AC_CODEC_ID1#
AC_RESET#
MOD_AUDIO_MON
AUDIO_GND
SYS_AUDIO_OUT
SYS_AUDIO_IN
SYS_AUDIO_OUT.GND
SYS_AUDIO_IN.GND
AUDIO_GND.1
AUDIO_GND.3
MPCIACT
VCC5VA
+3.3V.1
+3.3V.2
+3.3V.3
+3.3V.4
+3.3V.5
+3.3V.6
+3.3V.7
+3.3V.8
97
18
+5V.1
+5V.2
124
24
+3.3VAUX.1
+3.3VAUX.2
GND.1
GND.2
GND.3
GND.4
GND.5
GND.6
GND.7
GND.8
GND.9
GND.10
GND.11
GND.12
GND.13
GND.14
GND.15
GND.16
CH8GND
114
102
101
83
82
77
69
62
55
50
49
37
32
27
23
74
15
5
EMC1
EMC2
EMC3
EMC4
17
16
21
22
36
43
93
98
100
112
121
3
4
5
6
7
8
9
10
1
2
103
104
105
106
107
108
109
110
111
113
115
116
117
118
119
120
122
123
3
mPCI
3
R397
1K
C110
33uF
C2
33uF
+
VCC_1.8V
NO-POP
2
R408
10K
VCC_1.8V
0
NO-POP
0
NO-POP
0
R14
R15
R16
R8
R9
2
R5
0
NO-POP
NO-POP
R19
R4
0
NO-POP
R17
R18
7,16,31
DWG NO
1
508162-0001
VLYNQ INTERFACE
Sheet
32 o f
TMS320DM6446 EVALUATION MODULE
Date: Wednesday, March 14, 2007
Size:B
1
SPECTRUM DIGITAL INCORPORATED
VLYNQ_TXD1 14
SD_DATA1 7,16,31
VLYNQ_TXD0 14
SD_DATA2 7,16,31
VLYNQ_RXD1 14
SD_DATA3 7,16,31
VLYNQ_RXD0 14
SD_CMD 7,16,31
VLYNQ_CLK 3
SD_CLK
Page Contents:
Title:
SLP_CLK_EN 14
ELP_REQ/WAKEUP 14
PM_EN
14
WLAN_INTR 14
VCC_1.8V
VCC_5V
VCC_3.3V
BLM41P750SPT
R399
NO-POP
10K
R409
10K
0.1uF
C114
0.1uF
L60
BLM41P750SPT
C8
R391
R398
1K
VCC_1.8V
0.1uF
C112
0.1uF
C3
R390
+
L59
NO-POP
L58
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
A-33
A-34
A
B
C
D
R79
VCC_1.8V
10K
R80
10K
S1 4-5
5
34 POR_RSTz
S1 1-2
5
C80
3
4
5
RESET
VDD
6
1
R81
2.2K
VCC_1.8V
R90
R91
MR
GND 2
TPS3808G09DBVR
CT
SENSE1
U1
TI COMPATABLE EMULATOR
8 DSP_TDO
8 DSP_RTCK
S2 4-5
NO-POP
S2 1-2
S2/S1 SETTINGS
4
1
2
3
R82
10K
4
5
6
C81
0.1uF
0
0
CASD20TB
S2
VCC_3.3V
4
C82
NO-POP
3
CTI_TCK
CTI_EMU0
R92
R89
0
4
5
6
1
3
5
7
9
11
13
15
17
19
R83
2.2K
R86
NO-POP
TRSTn
TDIS
KEY
GND.1
GND.2
GND.3
EMU1
GND.4
EMU3
GND.5
J1
R93
R94
2
4
6
8
10
12
14
16
18
20
33
R95
NO-POP
39
39
8
DSP_TMS 8
DSP_TDI
DSP_TRST# 8
DSP_TCK 8
2
2
CTI_EMU1
EMULATOR_RSTn 34
20 PIN CTI INTERFACE
TMS
TDI
TVD
TDO
TCKRTN
TCLK
EMU0
SRST
EMU2
EMU4
CASD20TB
R84
2.2K
1
2
3
S1
R85
NO-POP
VCC_1.8V
VCC_1.8V
3
DWG NO
1
508162-0001
Sheet
DAVINCI EMULATION HEADER
33 o f
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
Date: Wednesday, March 14, 2007
Size:B
Page Contents:
Title:
R88
0
R87
NO-POP
VCC_1.8V
DSP_EMU1 8
DSP_EMU0 8
1
35
Revision:
E
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
A
B
C
3
1
2
A
AA
S4
B
BB
Z4
1
Z2
1
5
PUSHBUTTON SW
Z3
Z5
1
1
1
Z1
2
D7
SMCJ6A
no-pop
F_4.0A
BOX MOUNTING HOLES
HEADER 2
J6
1
CENTER
SHUNT
SLEEVE
2.5 MM JACK
RASM712
J14
6
R389
4
1
33
R245
+
C14
47uF
C236
1uF
PBSW_RSTz
R246
10K
VCC_3.3V
GREEN
DS9
R100
220
VCC_5V
U45
GND
RESET
VDD
MR
CT
SENSE1
U46
GND
RESET
VDD
2
1
2
1
6
3
33 EMULATOR_RSTn
R249
10K
VCC_3.3V
R252
10K
VCC_3.3V
X5
X4
X3
X2
X1
2
R29
R256
TP15
C98
1000pF
R255
1K
CASE SHIELDING TABS FOR POWER SUPPLY
SENSE THRESHOLD FOR TPS3808G09 IS 0.840 VOLTS
+
VCC_1.8V
R129
C369
100uF 4V
10K 1%
C240
0.1uF
C238
0.1uF
VCC_3.3V
VCC_3.3V
+
C242
0.1uF
C20
100uF 4V
3.3 uH
L3
2
3300pF 107 1%
C23
R128
Sets
Voltage
C97
8200pF
VCC_3.3V
BAS16-7
2
1
6
C21
6
TPS3808G09DBVR
MR
CT
SENSE1
D5
TPS3808G09DBVR
TP70
4
GND
RESET
TPS3808G09DBVR
MR
CT
VDD
0.047uF
SENSE1
U44
6
7
8
9
10
1
2
3
4
5
C22
470pF
R130
2K 1%
R30
3.74K 1%
SENSE THRESHOLD FOR TPS3808G01 IS 0.405 VOLTS
3
4
5
4
3
TP27
NO-POP
C237
NO-POP
C239
5
3
4
5
TP1
R247
10K
R250
10K
NO-POP
C241
TPS54310PWP
TP68
0
10K
R253
10K
13
12
11
16
15
14
POWERPAD
RT
AGND
SYNC
VSENSE
SS/ENA
COMP
VBIAS
PWRGD
BOOT
VIN3
VIN2
VIN1
PH1
PH2
PGND3
PH3
PGND2
PH4
PGND1
PH5
TP2
R248
DSP_CORE_VDD
R251
VCC_3.3V
R254
10K
0.1uF
VCC_1.8V
C39
+
10uF LESR
C24
21
20
19
18
17
U19
AGND
3.3 sq in AGND,
min thermal pad
TP3
C96
0.1uF
BLM41P750SPT
L4
0.039uF
0.1uF
71.5K 1%
R31
1
POWER INPUT
C26
C25
1
F1
R160
NO-POP
1
R159
NO-POP
1
1
1
D
33
1V2_PWR_OK
1
TP5
33
1V8_PWR_OK
1
2
5
7
1
8
3
1
SW1
SWITCH
Connect
at pin 1
1
1
4
1
0.025
0
TP16
+
100 uF
C19
1
3.3V @1.5Amp Max
TP14
3V3_PWR_OK 35
1.8V.SYS_RESETz 8,13,15,26,29,30,31
1
1
DWG NO
1
508162-0001
Date: Wednesday, March 14, 2007
Size:B
Sheet
34 o f
35
Revision:
E
Page Contents: POWER SUPPLY ( 3.3V ) & SYSTEM RESET LOGIC
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
POR_RSTz 33
NO-POP
R131
10K
VCC_5V
VCC_3.3V C99
TP28
Title:
1
5
A
B
C
D
Spectrum Digital, Inc
A-35
A
B
C
D
5
R163
L7
0.039uF
0.1uF
L9
C56
0.1uF
10uF LESR
VCC_1.8V
R210
NO-POP
R189
DSP_CORE_SUPPLY
4
13
12
11
16
15
14
21
20
19
18
17
6
4
13
12
11
16
15
14
21
20
19
18
17
3.3 sq in AGND,
min thermal pad
AGND
0
DC7
2
4
6
8
10
DTR1E
DTR1B
DTR2E
HEADER 5X2
1
3
5
7
9
UMC2N
DTR1C/DTR2B
DTR2C
U37
TPS54310PWP
POWERPAD
RT
AGND
SYNC
VSENSE
SS/ENA
COMP
VBIAS
PWRGD
BOOT
VIN3
VIN2
VIN1
PH1
PH2
PGND3
PH3
PGND2
PH4
PGND1
PH5
U38
AGND
3.3 sq in AGND, min
thermal pad
TPS54310PWP
POWERPAD
RT
AGND
SYNC
VSENSE
SS/ENA
COMP
VBIAS
PWRGD
BOOT
VIN3
VIN2
VIN1
PH1
PH2
PGND3
PH3
PGND2
PH4
PGND1
PH5
U27
Connect at pin 1
71.5K
+
C54
0.039uF
C46
VCC_5V
0.1uF
BLM41P750SPT
C158
0.1uF
NO-POP
NO-POP
C55
0.1uF
R50
C45
+
71.5K 1%
R40
10uF LESR
C44
C38
C37
BLM41P750SPT
C122
0.1uF
NO-POP
0
28 VDDIMX_EN
R187
NO-POP
R2
10K
VCC_3.3V
R164
1V8_PWR_OK
R162
R423
3V3_PWR_OK
1V2_PWR_OK
3V3_PWR_OK
28 VDDIMX_EN
VCC_5V
34 3V3_PWR_OK
1
2
3
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
C53
C42
560pF
2.7 uH
DSP_CORE_SUPPLY
3
+
TP29
0.025
TP36
R1
10K
R209
C52
100uF 4V
R183
107 1%
R59
R184
10K 1%
C43
3300pF
1.2V -> 28.0K 1%
1.05V -> 56.0K 1%
0.95V -> 150K 1%
TP35
R188
100K
VCC_5V
VCC_1.8V
2
100 uF
C51
2
U31
AO3404
U36
AO3404
+
DSP_CORE_SUPPLY
1000pF
C161
TP44
C192
NO-POP
10K
C191
1000pF
0.025
CORE VOLTAGE SUPPORT FOR 0.95 TO 1.2 VOLTS
1000pF
C124
R38
107 1%
R145
R146
100uF 4V
C41
VCC_5V
+
L11
L8
10K 1%
3300pF
C36
VCC_1.8V
2.7 uH
C159
0.01uF
R49
28.0K 1%
R185
1.65K 1%
C34
VCC_5V
0.047uF
0.047uF
C35
470pF
C123
8200pF
R39
10.2K 1%
R147
2K 1%
1
Sets
Voltage
1
3
1
Connect
at pin
1
1
4
10K
R395
TP37
1
1V2_PWR_OK 35
C50
100 uF
100 uF
1
1
TP25
TP43
TMS320DM6446 EVALUATION MODULE
SPECTRUM DIGITAL INCORPORATED
+
C32
DSP_CORE_VDDIMX
+
DSP_CORE_VDD
1V2_PWR_OK
TP12
TP26
1V8_PWR_OK 35
1
DWG NO
1
508162-0001
Date: Wednesday, March 14, 2007
Size:B
Sheet
35 o f
35
Revision:
E
Page Contents: POWER SUPPLY ( 1.8V & DSP_CORE) & EVM POWER CONN
Title:
1
1V8_PWR_OK
100 uF
1
+
C33
C160
NO-POP
C196
10K
R186
NO-POP
VCC_5V
S
S
D
D
D
D
G
G
G
S
S
A-36
G
5
A
B
C
D
Spectrum Digital, Inc
DM644x EVM Technical Reference
Appendix B
Mechanical Information
This appendix contains the mechanical information about the DM644x
EVM produced by Spectrum Digital.
B-1
THIS DRAWING IS NOT TO SCALE
Spectrum Digital, Inc
B-2
DM644x EVM Technical Reference
Spectrum Digital, Inc
B-3
Spectrum Digital, Inc
B-4
DM644x EVM Technical Reference
Printed in U.S.A., March 2007
508165-0001 Rev E